1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #ifndef __ASSEMBLY__ 9 #ifdef CONFIG_MMU 10 11 #include <linux/mm_types.h> 12 #include <linux/bug.h> 13 #include <linux/errno.h> 14 #include <asm-generic/pgtable_uffd.h> 15 #include <linux/page_table_check.h> 16 17 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 18 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 19 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 20 #endif 21 22 /* 23 * On almost all architectures and configurations, 0 can be used as the 24 * upper ceiling to free_pgtables(): on many architectures it has the same 25 * effect as using TASK_SIZE. However, there is one configuration which 26 * must impose a more careful limit, to avoid freeing kernel pgtables. 27 */ 28 #ifndef USER_PGTABLES_CEILING 29 #define USER_PGTABLES_CEILING 0UL 30 #endif 31 32 /* 33 * This defines the first usable user address. Platforms 34 * can override its value with custom FIRST_USER_ADDRESS 35 * defined in their respective <asm/pgtable.h>. 36 */ 37 #ifndef FIRST_USER_ADDRESS 38 #define FIRST_USER_ADDRESS 0UL 39 #endif 40 41 /* 42 * This defines the generic helper for accessing PMD page 43 * table page. Although platforms can still override this 44 * via their respective <asm/pgtable.h>. 45 */ 46 #ifndef pmd_pgtable 47 #define pmd_pgtable(pmd) pmd_page(pmd) 48 #endif 49 50 /* 51 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 52 * 53 * The pXx_index() functions return the index of the entry in the page 54 * table page which would control the given virtual address 55 * 56 * As these functions may be used by the same code for different levels of 57 * the page table folding, they are always available, regardless of 58 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 59 * because in such cases PTRS_PER_PxD equals 1. 60 */ 61 62 static inline unsigned long pte_index(unsigned long address) 63 { 64 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 65 } 66 #define pte_index pte_index 67 68 #ifndef pmd_index 69 static inline unsigned long pmd_index(unsigned long address) 70 { 71 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 72 } 73 #define pmd_index pmd_index 74 #endif 75 76 #ifndef pud_index 77 static inline unsigned long pud_index(unsigned long address) 78 { 79 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 80 } 81 #define pud_index pud_index 82 #endif 83 84 #ifndef pgd_index 85 /* Must be a compile-time constant, so implement it as a macro */ 86 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 87 #endif 88 89 #ifndef pte_offset_kernel 90 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 91 { 92 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 93 } 94 #define pte_offset_kernel pte_offset_kernel 95 #endif 96 97 #if defined(CONFIG_HIGHPTE) 98 #define pte_offset_map(dir, address) \ 99 ((pte_t *)kmap_atomic(pmd_page(*(dir))) + \ 100 pte_index((address))) 101 #define pte_unmap(pte) kunmap_atomic((pte)) 102 #else 103 #define pte_offset_map(dir, address) pte_offset_kernel((dir), (address)) 104 #define pte_unmap(pte) ((void)(pte)) /* NOP */ 105 #endif 106 107 /* Find an entry in the second-level page table.. */ 108 #ifndef pmd_offset 109 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 110 { 111 return pud_pgtable(*pud) + pmd_index(address); 112 } 113 #define pmd_offset pmd_offset 114 #endif 115 116 #ifndef pud_offset 117 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 118 { 119 return p4d_pgtable(*p4d) + pud_index(address); 120 } 121 #define pud_offset pud_offset 122 #endif 123 124 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 125 { 126 return (pgd + pgd_index(address)); 127 }; 128 129 /* 130 * a shortcut to get a pgd_t in a given mm 131 */ 132 #ifndef pgd_offset 133 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 134 #endif 135 136 /* 137 * a shortcut which implies the use of the kernel's pgd, instead 138 * of a process's 139 */ 140 #ifndef pgd_offset_k 141 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 142 #endif 143 144 /* 145 * In many cases it is known that a virtual address is mapped at PMD or PTE 146 * level, so instead of traversing all the page table levels, we can get a 147 * pointer to the PMD entry in user or kernel page table or translate a virtual 148 * address to the pointer in the PTE in the kernel page tables with simple 149 * helpers. 150 */ 151 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 152 { 153 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 154 } 155 156 static inline pmd_t *pmd_off_k(unsigned long va) 157 { 158 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 159 } 160 161 static inline pte_t *virt_to_kpte(unsigned long vaddr) 162 { 163 pmd_t *pmd = pmd_off_k(vaddr); 164 165 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 166 } 167 168 #ifndef pmd_young 169 static inline int pmd_young(pmd_t pmd) 170 { 171 return 0; 172 } 173 #endif 174 175 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 176 extern int ptep_set_access_flags(struct vm_area_struct *vma, 177 unsigned long address, pte_t *ptep, 178 pte_t entry, int dirty); 179 #endif 180 181 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 182 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 183 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 184 unsigned long address, pmd_t *pmdp, 185 pmd_t entry, int dirty); 186 extern int pudp_set_access_flags(struct vm_area_struct *vma, 187 unsigned long address, pud_t *pudp, 188 pud_t entry, int dirty); 189 #else 190 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 191 unsigned long address, pmd_t *pmdp, 192 pmd_t entry, int dirty) 193 { 194 BUILD_BUG(); 195 return 0; 196 } 197 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 198 unsigned long address, pud_t *pudp, 199 pud_t entry, int dirty) 200 { 201 BUILD_BUG(); 202 return 0; 203 } 204 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 205 #endif 206 207 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 208 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 209 unsigned long address, 210 pte_t *ptep) 211 { 212 pte_t pte = *ptep; 213 int r = 1; 214 if (!pte_young(pte)) 215 r = 0; 216 else 217 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 218 return r; 219 } 220 #endif 221 222 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 223 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 224 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 225 unsigned long address, 226 pmd_t *pmdp) 227 { 228 pmd_t pmd = *pmdp; 229 int r = 1; 230 if (!pmd_young(pmd)) 231 r = 0; 232 else 233 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 234 return r; 235 } 236 #else 237 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 238 unsigned long address, 239 pmd_t *pmdp) 240 { 241 BUILD_BUG(); 242 return 0; 243 } 244 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 245 #endif 246 247 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 248 int ptep_clear_flush_young(struct vm_area_struct *vma, 249 unsigned long address, pte_t *ptep); 250 #endif 251 252 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 253 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 254 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 255 unsigned long address, pmd_t *pmdp); 256 #else 257 /* 258 * Despite relevant to THP only, this API is called from generic rmap code 259 * under PageTransHuge(), hence needs a dummy implementation for !THP 260 */ 261 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 262 unsigned long address, pmd_t *pmdp) 263 { 264 BUILD_BUG(); 265 return 0; 266 } 267 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 268 #endif 269 270 #ifndef arch_has_hw_nonleaf_pmd_young 271 /* 272 * Return whether the accessed bit in non-leaf PMD entries is supported on the 273 * local CPU. 274 */ 275 static inline bool arch_has_hw_nonleaf_pmd_young(void) 276 { 277 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 278 } 279 #endif 280 281 #ifndef arch_has_hw_pte_young 282 /* 283 * Return whether the accessed bit is supported on the local CPU. 284 * 285 * This stub assumes accessing through an old PTE triggers a page fault. 286 * Architectures that automatically set the access bit should overwrite it. 287 */ 288 static inline bool arch_has_hw_pte_young(void) 289 { 290 return false; 291 } 292 #endif 293 294 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 295 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 296 unsigned long address, 297 pte_t *ptep) 298 { 299 pte_t pte = *ptep; 300 pte_clear(mm, address, ptep); 301 page_table_check_pte_clear(mm, address, pte); 302 return pte; 303 } 304 #endif 305 306 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 307 pte_t *ptep) 308 { 309 ptep_get_and_clear(mm, addr, ptep); 310 } 311 312 #ifndef __HAVE_ARCH_PTEP_GET 313 static inline pte_t ptep_get(pte_t *ptep) 314 { 315 return READ_ONCE(*ptep); 316 } 317 #endif 318 319 #ifdef CONFIG_GUP_GET_PTE_LOW_HIGH 320 /* 321 * WARNING: only to be used in the get_user_pages_fast() implementation. 322 * 323 * With get_user_pages_fast(), we walk down the pagetables without taking any 324 * locks. For this we would like to load the pointers atomically, but sometimes 325 * that is not possible (e.g. without expensive cmpxchg8b on x86_32 PAE). What 326 * we do have is the guarantee that a PTE will only either go from not present 327 * to present, or present to not present or both -- it will not switch to a 328 * completely different present page without a TLB flush in between; something 329 * that we are blocking by holding interrupts off. 330 * 331 * Setting ptes from not present to present goes: 332 * 333 * ptep->pte_high = h; 334 * smp_wmb(); 335 * ptep->pte_low = l; 336 * 337 * And present to not present goes: 338 * 339 * ptep->pte_low = 0; 340 * smp_wmb(); 341 * ptep->pte_high = 0; 342 * 343 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 344 * We load pte_high *after* loading pte_low, which ensures we don't see an older 345 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 346 * picked up a changed pte high. We might have gotten rubbish values from 347 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 348 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 349 * operates on present ptes we're safe. 350 */ 351 static inline pte_t ptep_get_lockless(pte_t *ptep) 352 { 353 pte_t pte; 354 355 do { 356 pte.pte_low = ptep->pte_low; 357 smp_rmb(); 358 pte.pte_high = ptep->pte_high; 359 smp_rmb(); 360 } while (unlikely(pte.pte_low != ptep->pte_low)); 361 362 return pte; 363 } 364 #else /* CONFIG_GUP_GET_PTE_LOW_HIGH */ 365 /* 366 * We require that the PTE can be read atomically. 367 */ 368 static inline pte_t ptep_get_lockless(pte_t *ptep) 369 { 370 return ptep_get(ptep); 371 } 372 #endif /* CONFIG_GUP_GET_PTE_LOW_HIGH */ 373 374 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 375 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 376 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 377 unsigned long address, 378 pmd_t *pmdp) 379 { 380 pmd_t pmd = *pmdp; 381 382 pmd_clear(pmdp); 383 page_table_check_pmd_clear(mm, address, pmd); 384 385 return pmd; 386 } 387 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 388 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 389 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 390 unsigned long address, 391 pud_t *pudp) 392 { 393 pud_t pud = *pudp; 394 395 pud_clear(pudp); 396 page_table_check_pud_clear(mm, address, pud); 397 398 return pud; 399 } 400 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 401 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 402 403 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 404 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 405 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 406 unsigned long address, pmd_t *pmdp, 407 int full) 408 { 409 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 410 } 411 #endif 412 413 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 414 static inline pud_t pudp_huge_get_and_clear_full(struct mm_struct *mm, 415 unsigned long address, pud_t *pudp, 416 int full) 417 { 418 return pudp_huge_get_and_clear(mm, address, pudp); 419 } 420 #endif 421 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 422 423 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 424 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 425 unsigned long address, pte_t *ptep, 426 int full) 427 { 428 return ptep_get_and_clear(mm, address, ptep); 429 } 430 #endif 431 432 433 /* 434 * If two threads concurrently fault at the same page, the thread that 435 * won the race updates the PTE and its local TLB/Cache. The other thread 436 * gives up, simply does nothing, and continues; on architectures where 437 * software can update TLB, local TLB can be updated here to avoid next page 438 * fault. This function updates TLB only, do nothing with cache or others. 439 * It is the difference with function update_mmu_cache. 440 */ 441 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 442 static inline void update_mmu_tlb(struct vm_area_struct *vma, 443 unsigned long address, pte_t *ptep) 444 { 445 } 446 #define __HAVE_ARCH_UPDATE_MMU_TLB 447 #endif 448 449 /* 450 * Some architectures may be able to avoid expensive synchronization 451 * primitives when modifications are made to PTE's which are already 452 * not present, or in the process of an address space destruction. 453 */ 454 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 455 static inline void pte_clear_not_present_full(struct mm_struct *mm, 456 unsigned long address, 457 pte_t *ptep, 458 int full) 459 { 460 pte_clear(mm, address, ptep); 461 } 462 #endif 463 464 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 465 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 466 unsigned long address, 467 pte_t *ptep); 468 #endif 469 470 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 471 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 472 unsigned long address, 473 pmd_t *pmdp); 474 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 475 unsigned long address, 476 pud_t *pudp); 477 #endif 478 479 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 480 struct mm_struct; 481 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 482 { 483 pte_t old_pte = *ptep; 484 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 485 } 486 #endif 487 488 /* 489 * On some architectures hardware does not set page access bit when accessing 490 * memory page, it is responsibility of software setting this bit. It brings 491 * out extra page fault penalty to track page access bit. For optimization page 492 * access bit can be set during all page fault flow on these arches. 493 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 494 * where software maintains page access bit. 495 */ 496 #ifndef pte_sw_mkyoung 497 static inline pte_t pte_sw_mkyoung(pte_t pte) 498 { 499 return pte; 500 } 501 #define pte_sw_mkyoung pte_sw_mkyoung 502 #endif 503 504 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 505 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 506 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 507 unsigned long address, pmd_t *pmdp) 508 { 509 pmd_t old_pmd = *pmdp; 510 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 511 } 512 #else 513 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 514 unsigned long address, pmd_t *pmdp) 515 { 516 BUILD_BUG(); 517 } 518 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 519 #endif 520 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 521 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 522 static inline void pudp_set_wrprotect(struct mm_struct *mm, 523 unsigned long address, pud_t *pudp) 524 { 525 pud_t old_pud = *pudp; 526 527 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 528 } 529 #else 530 static inline void pudp_set_wrprotect(struct mm_struct *mm, 531 unsigned long address, pud_t *pudp) 532 { 533 BUILD_BUG(); 534 } 535 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 536 #endif 537 538 #ifndef pmdp_collapse_flush 539 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 540 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 541 unsigned long address, pmd_t *pmdp); 542 #else 543 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 544 unsigned long address, 545 pmd_t *pmdp) 546 { 547 BUILD_BUG(); 548 return *pmdp; 549 } 550 #define pmdp_collapse_flush pmdp_collapse_flush 551 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 552 #endif 553 554 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 555 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 556 pgtable_t pgtable); 557 #endif 558 559 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 560 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 561 #endif 562 563 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 564 /* 565 * This is an implementation of pmdp_establish() that is only suitable for an 566 * architecture that doesn't have hardware dirty/accessed bits. In this case we 567 * can't race with CPU which sets these bits and non-atomic approach is fine. 568 */ 569 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 570 unsigned long address, pmd_t *pmdp, pmd_t pmd) 571 { 572 pmd_t old_pmd = *pmdp; 573 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 574 return old_pmd; 575 } 576 #endif 577 578 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 579 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 580 pmd_t *pmdp); 581 #endif 582 583 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 584 585 /* 586 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 587 * hugepage mapping in the page tables. This function is similar to 588 * pmdp_invalidate(), but should only be used if the access and dirty bits would 589 * not be cleared by the software in the new PMD value. The function ensures 590 * that hardware changes of the access and dirty bits updates would not be lost. 591 * 592 * Doing so can allow in certain architectures to avoid a TLB flush in most 593 * cases. Yet, another TLB flush might be necessary later if the PMD update 594 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 595 * even when a TLB flush is needed because of the update, the caller may be able 596 * to batch these TLB flushing operations, so fewer TLB flush operations are 597 * needed. 598 */ 599 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 600 unsigned long address, pmd_t *pmdp); 601 #endif 602 603 #ifndef __HAVE_ARCH_PTE_SAME 604 static inline int pte_same(pte_t pte_a, pte_t pte_b) 605 { 606 return pte_val(pte_a) == pte_val(pte_b); 607 } 608 #endif 609 610 #ifndef __HAVE_ARCH_PTE_UNUSED 611 /* 612 * Some architectures provide facilities to virtualization guests 613 * so that they can flag allocated pages as unused. This allows the 614 * host to transparently reclaim unused pages. This function returns 615 * whether the pte's page is unused. 616 */ 617 static inline int pte_unused(pte_t pte) 618 { 619 return 0; 620 } 621 #endif 622 623 #ifndef pte_access_permitted 624 #define pte_access_permitted(pte, write) \ 625 (pte_present(pte) && (!(write) || pte_write(pte))) 626 #endif 627 628 #ifndef pmd_access_permitted 629 #define pmd_access_permitted(pmd, write) \ 630 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 631 #endif 632 633 #ifndef pud_access_permitted 634 #define pud_access_permitted(pud, write) \ 635 (pud_present(pud) && (!(write) || pud_write(pud))) 636 #endif 637 638 #ifndef p4d_access_permitted 639 #define p4d_access_permitted(p4d, write) \ 640 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 641 #endif 642 643 #ifndef pgd_access_permitted 644 #define pgd_access_permitted(pgd, write) \ 645 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 646 #endif 647 648 #ifndef __HAVE_ARCH_PMD_SAME 649 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 650 { 651 return pmd_val(pmd_a) == pmd_val(pmd_b); 652 } 653 654 static inline int pud_same(pud_t pud_a, pud_t pud_b) 655 { 656 return pud_val(pud_a) == pud_val(pud_b); 657 } 658 #endif 659 660 #ifndef __HAVE_ARCH_P4D_SAME 661 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 662 { 663 return p4d_val(p4d_a) == p4d_val(p4d_b); 664 } 665 #endif 666 667 #ifndef __HAVE_ARCH_PGD_SAME 668 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 669 { 670 return pgd_val(pgd_a) == pgd_val(pgd_b); 671 } 672 #endif 673 674 /* 675 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 676 * TLB flush will be required as a result of the "set". For example, use 677 * in scenarios where it is known ahead of time that the routine is 678 * setting non-present entries, or re-setting an existing entry to the 679 * same value. Otherwise, use the typical "set" helpers and flush the 680 * TLB. 681 */ 682 #define set_pte_safe(ptep, pte) \ 683 ({ \ 684 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 685 set_pte(ptep, pte); \ 686 }) 687 688 #define set_pmd_safe(pmdp, pmd) \ 689 ({ \ 690 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 691 set_pmd(pmdp, pmd); \ 692 }) 693 694 #define set_pud_safe(pudp, pud) \ 695 ({ \ 696 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 697 set_pud(pudp, pud); \ 698 }) 699 700 #define set_p4d_safe(p4dp, p4d) \ 701 ({ \ 702 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 703 set_p4d(p4dp, p4d); \ 704 }) 705 706 #define set_pgd_safe(pgdp, pgd) \ 707 ({ \ 708 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 709 set_pgd(pgdp, pgd); \ 710 }) 711 712 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 713 /* 714 * Some architectures support metadata associated with a page. When a 715 * page is being swapped out, this metadata must be saved so it can be 716 * restored when the page is swapped back in. SPARC M7 and newer 717 * processors support an ADI (Application Data Integrity) tag for the 718 * page as metadata for the page. arch_do_swap_page() can restore this 719 * metadata when a page is swapped back in. 720 */ 721 static inline void arch_do_swap_page(struct mm_struct *mm, 722 struct vm_area_struct *vma, 723 unsigned long addr, 724 pte_t pte, pte_t oldpte) 725 { 726 727 } 728 #endif 729 730 #ifndef __HAVE_ARCH_UNMAP_ONE 731 /* 732 * Some architectures support metadata associated with a page. When a 733 * page is being swapped out, this metadata must be saved so it can be 734 * restored when the page is swapped back in. SPARC M7 and newer 735 * processors support an ADI (Application Data Integrity) tag for the 736 * page as metadata for the page. arch_unmap_one() can save this 737 * metadata on a swap-out of a page. 738 */ 739 static inline int arch_unmap_one(struct mm_struct *mm, 740 struct vm_area_struct *vma, 741 unsigned long addr, 742 pte_t orig_pte) 743 { 744 return 0; 745 } 746 #endif 747 748 /* 749 * Allow architectures to preserve additional metadata associated with 750 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 751 * prototypes must be defined in the arch-specific asm/pgtable.h file. 752 */ 753 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 754 static inline int arch_prepare_to_swap(struct page *page) 755 { 756 return 0; 757 } 758 #endif 759 760 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 761 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 762 { 763 } 764 765 static inline void arch_swap_invalidate_area(int type) 766 { 767 } 768 #endif 769 770 #ifndef __HAVE_ARCH_SWAP_RESTORE 771 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 772 { 773 } 774 #endif 775 776 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 777 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 778 #endif 779 780 #ifndef __HAVE_ARCH_MOVE_PTE 781 #define move_pte(pte, prot, old_addr, new_addr) (pte) 782 #endif 783 784 #ifndef pte_accessible 785 # define pte_accessible(mm, pte) ((void)(pte), 1) 786 #endif 787 788 #ifndef flush_tlb_fix_spurious_fault 789 #define flush_tlb_fix_spurious_fault(vma, address) flush_tlb_page(vma, address) 790 #endif 791 792 /* 793 * When walking page tables, get the address of the next boundary, 794 * or the end address of the range if that comes earlier. Although no 795 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 796 */ 797 798 #define pgd_addr_end(addr, end) \ 799 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 800 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 801 }) 802 803 #ifndef p4d_addr_end 804 #define p4d_addr_end(addr, end) \ 805 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 806 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 807 }) 808 #endif 809 810 #ifndef pud_addr_end 811 #define pud_addr_end(addr, end) \ 812 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 813 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 814 }) 815 #endif 816 817 #ifndef pmd_addr_end 818 #define pmd_addr_end(addr, end) \ 819 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 820 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 821 }) 822 #endif 823 824 /* 825 * When walking page tables, we usually want to skip any p?d_none entries; 826 * and any p?d_bad entries - reporting the error before resetting to none. 827 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 828 */ 829 void pgd_clear_bad(pgd_t *); 830 831 #ifndef __PAGETABLE_P4D_FOLDED 832 void p4d_clear_bad(p4d_t *); 833 #else 834 #define p4d_clear_bad(p4d) do { } while (0) 835 #endif 836 837 #ifndef __PAGETABLE_PUD_FOLDED 838 void pud_clear_bad(pud_t *); 839 #else 840 #define pud_clear_bad(p4d) do { } while (0) 841 #endif 842 843 void pmd_clear_bad(pmd_t *); 844 845 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 846 { 847 if (pgd_none(*pgd)) 848 return 1; 849 if (unlikely(pgd_bad(*pgd))) { 850 pgd_clear_bad(pgd); 851 return 1; 852 } 853 return 0; 854 } 855 856 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 857 { 858 if (p4d_none(*p4d)) 859 return 1; 860 if (unlikely(p4d_bad(*p4d))) { 861 p4d_clear_bad(p4d); 862 return 1; 863 } 864 return 0; 865 } 866 867 static inline int pud_none_or_clear_bad(pud_t *pud) 868 { 869 if (pud_none(*pud)) 870 return 1; 871 if (unlikely(pud_bad(*pud))) { 872 pud_clear_bad(pud); 873 return 1; 874 } 875 return 0; 876 } 877 878 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 879 { 880 if (pmd_none(*pmd)) 881 return 1; 882 if (unlikely(pmd_bad(*pmd))) { 883 pmd_clear_bad(pmd); 884 return 1; 885 } 886 return 0; 887 } 888 889 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 890 unsigned long addr, 891 pte_t *ptep) 892 { 893 /* 894 * Get the current pte state, but zero it out to make it 895 * non-present, preventing the hardware from asynchronously 896 * updating it. 897 */ 898 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 899 } 900 901 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 902 unsigned long addr, 903 pte_t *ptep, pte_t pte) 904 { 905 /* 906 * The pte is non-present, so there's no hardware state to 907 * preserve. 908 */ 909 set_pte_at(vma->vm_mm, addr, ptep, pte); 910 } 911 912 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 913 /* 914 * Start a pte protection read-modify-write transaction, which 915 * protects against asynchronous hardware modifications to the pte. 916 * The intention is not to prevent the hardware from making pte 917 * updates, but to prevent any updates it may make from being lost. 918 * 919 * This does not protect against other software modifications of the 920 * pte; the appropriate pte lock must be held over the transaction. 921 * 922 * Note that this interface is intended to be batchable, meaning that 923 * ptep_modify_prot_commit may not actually update the pte, but merely 924 * queue the update to be done at some later time. The update must be 925 * actually committed before the pte lock is released, however. 926 */ 927 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 928 unsigned long addr, 929 pte_t *ptep) 930 { 931 return __ptep_modify_prot_start(vma, addr, ptep); 932 } 933 934 /* 935 * Commit an update to a pte, leaving any hardware-controlled bits in 936 * the PTE unmodified. 937 */ 938 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 939 unsigned long addr, 940 pte_t *ptep, pte_t old_pte, pte_t pte) 941 { 942 __ptep_modify_prot_commit(vma, addr, ptep, pte); 943 } 944 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 945 #endif /* CONFIG_MMU */ 946 947 /* 948 * No-op macros that just return the current protection value. Defined here 949 * because these macros can be used even if CONFIG_MMU is not defined. 950 */ 951 952 #ifndef pgprot_nx 953 #define pgprot_nx(prot) (prot) 954 #endif 955 956 #ifndef pgprot_noncached 957 #define pgprot_noncached(prot) (prot) 958 #endif 959 960 #ifndef pgprot_writecombine 961 #define pgprot_writecombine pgprot_noncached 962 #endif 963 964 #ifndef pgprot_writethrough 965 #define pgprot_writethrough pgprot_noncached 966 #endif 967 968 #ifndef pgprot_device 969 #define pgprot_device pgprot_noncached 970 #endif 971 972 #ifndef pgprot_mhp 973 #define pgprot_mhp(prot) (prot) 974 #endif 975 976 #ifdef CONFIG_MMU 977 #ifndef pgprot_modify 978 #define pgprot_modify pgprot_modify 979 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 980 { 981 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 982 newprot = pgprot_noncached(newprot); 983 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 984 newprot = pgprot_writecombine(newprot); 985 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 986 newprot = pgprot_device(newprot); 987 return newprot; 988 } 989 #endif 990 #endif /* CONFIG_MMU */ 991 992 #ifndef pgprot_encrypted 993 #define pgprot_encrypted(prot) (prot) 994 #endif 995 996 #ifndef pgprot_decrypted 997 #define pgprot_decrypted(prot) (prot) 998 #endif 999 1000 /* 1001 * A facility to provide lazy MMU batching. This allows PTE updates and 1002 * page invalidations to be delayed until a call to leave lazy MMU mode 1003 * is issued. Some architectures may benefit from doing this, and it is 1004 * beneficial for both shadow and direct mode hypervisors, which may batch 1005 * the PTE updates which happen during this window. Note that using this 1006 * interface requires that read hazards be removed from the code. A read 1007 * hazard could result in the direct mode hypervisor case, since the actual 1008 * write to the page tables may not yet have taken place, so reads though 1009 * a raw PTE pointer after it has been modified are not guaranteed to be 1010 * up to date. This mode can only be entered and left under the protection of 1011 * the page table locks for all page tables which may be modified. In the UP 1012 * case, this is required so that preemption is disabled, and in the SMP case, 1013 * it must synchronize the delayed page table writes properly on other CPUs. 1014 */ 1015 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 1016 #define arch_enter_lazy_mmu_mode() do {} while (0) 1017 #define arch_leave_lazy_mmu_mode() do {} while (0) 1018 #define arch_flush_lazy_mmu_mode() do {} while (0) 1019 #endif 1020 1021 /* 1022 * A facility to provide batching of the reload of page tables and 1023 * other process state with the actual context switch code for 1024 * paravirtualized guests. By convention, only one of the batched 1025 * update (lazy) modes (CPU, MMU) should be active at any given time, 1026 * entry should never be nested, and entry and exits should always be 1027 * paired. This is for sanity of maintaining and reasoning about the 1028 * kernel code. In this case, the exit (end of the context switch) is 1029 * in architecture-specific code, and so doesn't need a generic 1030 * definition. 1031 */ 1032 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1033 #define arch_start_context_switch(prev) do {} while (0) 1034 #endif 1035 1036 /* 1037 * When replacing an anonymous page by a real (!non) swap entry, we clear 1038 * PG_anon_exclusive from the page and instead remember whether the flag was 1039 * set in the swp pte. During fork(), we have to mark the entry as !exclusive 1040 * (possibly shared). On swapin, we use that information to restore 1041 * PG_anon_exclusive, which is very helpful in cases where we might have 1042 * additional (e.g., FOLL_GET) references on a page and wouldn't be able to 1043 * detect exclusivity. 1044 * 1045 * These functions don't apply to non-swap entries (e.g., migration, hwpoison, 1046 * ...). 1047 */ 1048 #ifndef __HAVE_ARCH_PTE_SWP_EXCLUSIVE 1049 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1050 { 1051 return pte; 1052 } 1053 1054 static inline int pte_swp_exclusive(pte_t pte) 1055 { 1056 return false; 1057 } 1058 1059 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1060 { 1061 return pte; 1062 } 1063 #endif 1064 1065 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1066 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1067 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1068 { 1069 return pmd; 1070 } 1071 1072 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1073 { 1074 return 0; 1075 } 1076 1077 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1078 { 1079 return pmd; 1080 } 1081 #endif 1082 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1083 static inline int pte_soft_dirty(pte_t pte) 1084 { 1085 return 0; 1086 } 1087 1088 static inline int pmd_soft_dirty(pmd_t pmd) 1089 { 1090 return 0; 1091 } 1092 1093 static inline pte_t pte_mksoft_dirty(pte_t pte) 1094 { 1095 return pte; 1096 } 1097 1098 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1099 { 1100 return pmd; 1101 } 1102 1103 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1104 { 1105 return pte; 1106 } 1107 1108 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1109 { 1110 return pmd; 1111 } 1112 1113 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1114 { 1115 return pte; 1116 } 1117 1118 static inline int pte_swp_soft_dirty(pte_t pte) 1119 { 1120 return 0; 1121 } 1122 1123 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1124 { 1125 return pte; 1126 } 1127 1128 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1129 { 1130 return pmd; 1131 } 1132 1133 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1134 { 1135 return 0; 1136 } 1137 1138 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1139 { 1140 return pmd; 1141 } 1142 #endif 1143 1144 #ifndef __HAVE_PFNMAP_TRACKING 1145 /* 1146 * Interfaces that can be used by architecture code to keep track of 1147 * memory type of pfn mappings specified by the remap_pfn_range, 1148 * vmf_insert_pfn. 1149 */ 1150 1151 /* 1152 * track_pfn_remap is called when a _new_ pfn mapping is being established 1153 * by remap_pfn_range() for physical range indicated by pfn and size. 1154 */ 1155 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1156 unsigned long pfn, unsigned long addr, 1157 unsigned long size) 1158 { 1159 return 0; 1160 } 1161 1162 /* 1163 * track_pfn_insert is called when a _new_ single pfn is established 1164 * by vmf_insert_pfn(). 1165 */ 1166 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1167 pfn_t pfn) 1168 { 1169 } 1170 1171 /* 1172 * track_pfn_copy is called when vma that is covering the pfnmap gets 1173 * copied through copy_page_range(). 1174 */ 1175 static inline int track_pfn_copy(struct vm_area_struct *vma) 1176 { 1177 return 0; 1178 } 1179 1180 /* 1181 * untrack_pfn is called while unmapping a pfnmap for a region. 1182 * untrack can be called for a specific region indicated by pfn and size or 1183 * can be for the entire vma (in which case pfn, size are zero). 1184 */ 1185 static inline void untrack_pfn(struct vm_area_struct *vma, 1186 unsigned long pfn, unsigned long size) 1187 { 1188 } 1189 1190 /* 1191 * untrack_pfn_moved is called while mremapping a pfnmap for a new region. 1192 */ 1193 static inline void untrack_pfn_moved(struct vm_area_struct *vma) 1194 { 1195 } 1196 #else 1197 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1198 unsigned long pfn, unsigned long addr, 1199 unsigned long size); 1200 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1201 pfn_t pfn); 1202 extern int track_pfn_copy(struct vm_area_struct *vma); 1203 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1204 unsigned long size); 1205 extern void untrack_pfn_moved(struct vm_area_struct *vma); 1206 #endif 1207 1208 #ifdef CONFIG_MMU 1209 #ifdef __HAVE_COLOR_ZERO_PAGE 1210 static inline int is_zero_pfn(unsigned long pfn) 1211 { 1212 extern unsigned long zero_pfn; 1213 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1214 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1215 } 1216 1217 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1218 1219 #else 1220 static inline int is_zero_pfn(unsigned long pfn) 1221 { 1222 extern unsigned long zero_pfn; 1223 return pfn == zero_pfn; 1224 } 1225 1226 static inline unsigned long my_zero_pfn(unsigned long addr) 1227 { 1228 extern unsigned long zero_pfn; 1229 return zero_pfn; 1230 } 1231 #endif 1232 #else 1233 static inline int is_zero_pfn(unsigned long pfn) 1234 { 1235 return 0; 1236 } 1237 1238 static inline unsigned long my_zero_pfn(unsigned long addr) 1239 { 1240 return 0; 1241 } 1242 #endif /* CONFIG_MMU */ 1243 1244 #ifdef CONFIG_MMU 1245 1246 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1247 static inline int pmd_trans_huge(pmd_t pmd) 1248 { 1249 return 0; 1250 } 1251 #ifndef pmd_write 1252 static inline int pmd_write(pmd_t pmd) 1253 { 1254 BUG(); 1255 return 0; 1256 } 1257 #endif /* pmd_write */ 1258 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1259 1260 #ifndef pud_write 1261 static inline int pud_write(pud_t pud) 1262 { 1263 BUG(); 1264 return 0; 1265 } 1266 #endif /* pud_write */ 1267 1268 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1269 static inline int pmd_devmap(pmd_t pmd) 1270 { 1271 return 0; 1272 } 1273 static inline int pud_devmap(pud_t pud) 1274 { 1275 return 0; 1276 } 1277 static inline int pgd_devmap(pgd_t pgd) 1278 { 1279 return 0; 1280 } 1281 #endif 1282 1283 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1284 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1285 static inline int pud_trans_huge(pud_t pud) 1286 { 1287 return 0; 1288 } 1289 #endif 1290 1291 /* See pmd_none_or_trans_huge_or_clear_bad for discussion. */ 1292 static inline int pud_none_or_trans_huge_or_dev_or_clear_bad(pud_t *pud) 1293 { 1294 pud_t pudval = READ_ONCE(*pud); 1295 1296 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1297 return 1; 1298 if (unlikely(pud_bad(pudval))) { 1299 pud_clear_bad(pud); 1300 return 1; 1301 } 1302 return 0; 1303 } 1304 1305 /* See pmd_trans_unstable for discussion. */ 1306 static inline int pud_trans_unstable(pud_t *pud) 1307 { 1308 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1309 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1310 return pud_none_or_trans_huge_or_dev_or_clear_bad(pud); 1311 #else 1312 return 0; 1313 #endif 1314 } 1315 1316 #ifndef pmd_read_atomic 1317 static inline pmd_t pmd_read_atomic(pmd_t *pmdp) 1318 { 1319 /* 1320 * Depend on compiler for an atomic pmd read. NOTE: this is 1321 * only going to work, if the pmdval_t isn't larger than 1322 * an unsigned long. 1323 */ 1324 return *pmdp; 1325 } 1326 #endif 1327 1328 #ifndef arch_needs_pgtable_deposit 1329 #define arch_needs_pgtable_deposit() (false) 1330 #endif 1331 /* 1332 * This function is meant to be used by sites walking pagetables with 1333 * the mmap_lock held in read mode to protect against MADV_DONTNEED and 1334 * transhuge page faults. MADV_DONTNEED can convert a transhuge pmd 1335 * into a null pmd and the transhuge page fault can convert a null pmd 1336 * into an hugepmd or into a regular pmd (if the hugepage allocation 1337 * fails). While holding the mmap_lock in read mode the pmd becomes 1338 * stable and stops changing under us only if it's not null and not a 1339 * transhuge pmd. When those races occurs and this function makes a 1340 * difference vs the standard pmd_none_or_clear_bad, the result is 1341 * undefined so behaving like if the pmd was none is safe (because it 1342 * can return none anyway). The compiler level barrier() is critically 1343 * important to compute the two checks atomically on the same pmdval. 1344 * 1345 * For 32bit kernels with a 64bit large pmd_t this automatically takes 1346 * care of reading the pmd atomically to avoid SMP race conditions 1347 * against pmd_populate() when the mmap_lock is hold for reading by the 1348 * caller (a special atomic read not done by "gcc" as in the generic 1349 * version above, is also needed when THP is disabled because the page 1350 * fault can populate the pmd from under us). 1351 */ 1352 static inline int pmd_none_or_trans_huge_or_clear_bad(pmd_t *pmd) 1353 { 1354 pmd_t pmdval = pmd_read_atomic(pmd); 1355 /* 1356 * The barrier will stabilize the pmdval in a register or on 1357 * the stack so that it will stop changing under the code. 1358 * 1359 * When CONFIG_TRANSPARENT_HUGEPAGE=y on x86 32bit PAE, 1360 * pmd_read_atomic is allowed to return a not atomic pmdval 1361 * (for example pointing to an hugepage that has never been 1362 * mapped in the pmd). The below checks will only care about 1363 * the low part of the pmd with 32bit PAE x86 anyway, with the 1364 * exception of pmd_none(). So the important thing is that if 1365 * the low part of the pmd is found null, the high part will 1366 * be also null or the pmd_none() check below would be 1367 * confused. 1368 */ 1369 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1370 barrier(); 1371 #endif 1372 /* 1373 * !pmd_present() checks for pmd migration entries 1374 * 1375 * The complete check uses is_pmd_migration_entry() in linux/swapops.h 1376 * But using that requires moving current function and pmd_trans_unstable() 1377 * to linux/swapops.h to resolve dependency, which is too much code move. 1378 * 1379 * !pmd_present() is equivalent to is_pmd_migration_entry() currently, 1380 * because !pmd_present() pages can only be under migration not swapped 1381 * out. 1382 * 1383 * pmd_none() is preserved for future condition checks on pmd migration 1384 * entries and not confusing with this function name, although it is 1385 * redundant with !pmd_present(). 1386 */ 1387 if (pmd_none(pmdval) || pmd_trans_huge(pmdval) || 1388 (IS_ENABLED(CONFIG_ARCH_ENABLE_THP_MIGRATION) && !pmd_present(pmdval))) 1389 return 1; 1390 if (unlikely(pmd_bad(pmdval))) { 1391 pmd_clear_bad(pmd); 1392 return 1; 1393 } 1394 return 0; 1395 } 1396 1397 /* 1398 * This is a noop if Transparent Hugepage Support is not built into 1399 * the kernel. Otherwise it is equivalent to 1400 * pmd_none_or_trans_huge_or_clear_bad(), and shall only be called in 1401 * places that already verified the pmd is not none and they want to 1402 * walk ptes while holding the mmap sem in read mode (write mode don't 1403 * need this). If THP is not enabled, the pmd can't go away under the 1404 * code even if MADV_DONTNEED runs, but if THP is enabled we need to 1405 * run a pmd_trans_unstable before walking the ptes after 1406 * split_huge_pmd returns (because it may have run when the pmd become 1407 * null, but then a page fault can map in a THP and not a regular page). 1408 */ 1409 static inline int pmd_trans_unstable(pmd_t *pmd) 1410 { 1411 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1412 return pmd_none_or_trans_huge_or_clear_bad(pmd); 1413 #else 1414 return 0; 1415 #endif 1416 } 1417 1418 /* 1419 * the ordering of these checks is important for pmds with _page_devmap set. 1420 * if we check pmd_trans_unstable() first we will trip the bad_pmd() check 1421 * inside of pmd_none_or_trans_huge_or_clear_bad(). this will end up correctly 1422 * returning 1 but not before it spams dmesg with the pmd_clear_bad() output. 1423 */ 1424 static inline int pmd_devmap_trans_unstable(pmd_t *pmd) 1425 { 1426 return pmd_devmap(*pmd) || pmd_trans_unstable(pmd); 1427 } 1428 1429 #ifndef CONFIG_NUMA_BALANCING 1430 /* 1431 * Technically a PTE can be PROTNONE even when not doing NUMA balancing but 1432 * the only case the kernel cares is for NUMA balancing and is only ever set 1433 * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked 1434 * _PAGE_PROTNONE so by default, implement the helper as "always no". It 1435 * is the responsibility of the caller to distinguish between PROT_NONE 1436 * protections and NUMA hinting fault protections. 1437 */ 1438 static inline int pte_protnone(pte_t pte) 1439 { 1440 return 0; 1441 } 1442 1443 static inline int pmd_protnone(pmd_t pmd) 1444 { 1445 return 0; 1446 } 1447 #endif /* CONFIG_NUMA_BALANCING */ 1448 1449 #endif /* CONFIG_MMU */ 1450 1451 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1452 1453 #ifndef __PAGETABLE_P4D_FOLDED 1454 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1455 void p4d_clear_huge(p4d_t *p4d); 1456 #else 1457 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1458 { 1459 return 0; 1460 } 1461 static inline void p4d_clear_huge(p4d_t *p4d) { } 1462 #endif /* !__PAGETABLE_P4D_FOLDED */ 1463 1464 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1465 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1466 int pud_clear_huge(pud_t *pud); 1467 int pmd_clear_huge(pmd_t *pmd); 1468 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1469 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1470 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1471 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1472 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1473 { 1474 return 0; 1475 } 1476 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1477 { 1478 return 0; 1479 } 1480 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1481 { 1482 return 0; 1483 } 1484 static inline void p4d_clear_huge(p4d_t *p4d) { } 1485 static inline int pud_clear_huge(pud_t *pud) 1486 { 1487 return 0; 1488 } 1489 static inline int pmd_clear_huge(pmd_t *pmd) 1490 { 1491 return 0; 1492 } 1493 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1494 { 1495 return 0; 1496 } 1497 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1498 { 1499 return 0; 1500 } 1501 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1502 { 1503 return 0; 1504 } 1505 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1506 1507 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1508 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1509 /* 1510 * ARCHes with special requirements for evicting THP backing TLB entries can 1511 * implement this. Otherwise also, it can help optimize normal TLB flush in 1512 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1513 * entire TLB if flush span is greater than a threshold, which will 1514 * likely be true for a single huge page. Thus a single THP flush will 1515 * invalidate the entire TLB which is not desirable. 1516 * e.g. see arch/arc: flush_pmd_tlb_range 1517 */ 1518 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1519 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1520 #else 1521 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1522 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1523 #endif 1524 #endif 1525 1526 struct file; 1527 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1528 unsigned long size, pgprot_t *vma_prot); 1529 1530 #ifndef CONFIG_X86_ESPFIX64 1531 static inline void init_espfix_bsp(void) { } 1532 #endif 1533 1534 extern void __init pgtable_cache_init(void); 1535 1536 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1537 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1538 { 1539 return true; 1540 } 1541 1542 static inline bool arch_has_pfn_modify_check(void) 1543 { 1544 return false; 1545 } 1546 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1547 1548 /* 1549 * Architecture PAGE_KERNEL_* fallbacks 1550 * 1551 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1552 * because they really don't support them, or the port needs to be updated to 1553 * reflect the required functionality. Below are a set of relatively safe 1554 * fallbacks, as best effort, which we can count on in lieu of the architectures 1555 * not defining them on their own yet. 1556 */ 1557 1558 #ifndef PAGE_KERNEL_RO 1559 # define PAGE_KERNEL_RO PAGE_KERNEL 1560 #endif 1561 1562 #ifndef PAGE_KERNEL_EXEC 1563 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1564 #endif 1565 1566 /* 1567 * Page Table Modification bits for pgtbl_mod_mask. 1568 * 1569 * These are used by the p?d_alloc_track*() set of functions an in the generic 1570 * vmalloc/ioremap code to track at which page-table levels entries have been 1571 * modified. Based on that the code can better decide when vmalloc and ioremap 1572 * mapping changes need to be synchronized to other page-tables in the system. 1573 */ 1574 #define __PGTBL_PGD_MODIFIED 0 1575 #define __PGTBL_P4D_MODIFIED 1 1576 #define __PGTBL_PUD_MODIFIED 2 1577 #define __PGTBL_PMD_MODIFIED 3 1578 #define __PGTBL_PTE_MODIFIED 4 1579 1580 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1581 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1582 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1583 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1584 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1585 1586 /* Page-Table Modification Mask */ 1587 typedef unsigned int pgtbl_mod_mask; 1588 1589 #endif /* !__ASSEMBLY__ */ 1590 1591 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1592 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1593 /* 1594 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1595 * with physical address space extension, but falls back to 1596 * BITS_PER_LONG otherwise. 1597 */ 1598 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1599 #else 1600 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1601 #endif 1602 #endif 1603 1604 #ifndef has_transparent_hugepage 1605 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1606 #endif 1607 1608 /* 1609 * On some architectures it depends on the mm if the p4d/pud or pmd 1610 * layer of the page table hierarchy is folded or not. 1611 */ 1612 #ifndef mm_p4d_folded 1613 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1614 #endif 1615 1616 #ifndef mm_pud_folded 1617 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1618 #endif 1619 1620 #ifndef mm_pmd_folded 1621 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1622 #endif 1623 1624 #ifndef p4d_offset_lockless 1625 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1626 #endif 1627 #ifndef pud_offset_lockless 1628 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1629 #endif 1630 #ifndef pmd_offset_lockless 1631 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1632 #endif 1633 1634 /* 1635 * p?d_leaf() - true if this entry is a final mapping to a physical address. 1636 * This differs from p?d_huge() by the fact that they are always available (if 1637 * the architecture supports large pages at the appropriate level) even 1638 * if CONFIG_HUGETLB_PAGE is not defined. 1639 * Only meaningful when called on a valid entry. 1640 */ 1641 #ifndef pgd_leaf 1642 #define pgd_leaf(x) 0 1643 #endif 1644 #ifndef p4d_leaf 1645 #define p4d_leaf(x) 0 1646 #endif 1647 #ifndef pud_leaf 1648 #define pud_leaf(x) 0 1649 #endif 1650 #ifndef pmd_leaf 1651 #define pmd_leaf(x) 0 1652 #endif 1653 1654 #ifndef pgd_leaf_size 1655 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1656 #endif 1657 #ifndef p4d_leaf_size 1658 #define p4d_leaf_size(x) P4D_SIZE 1659 #endif 1660 #ifndef pud_leaf_size 1661 #define pud_leaf_size(x) PUD_SIZE 1662 #endif 1663 #ifndef pmd_leaf_size 1664 #define pmd_leaf_size(x) PMD_SIZE 1665 #endif 1666 #ifndef pte_leaf_size 1667 #define pte_leaf_size(x) PAGE_SIZE 1668 #endif 1669 1670 /* 1671 * Some architectures have MMUs that are configurable or selectable at boot 1672 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1673 * helps to have a static maximum value. 1674 */ 1675 1676 #ifndef MAX_PTRS_PER_PTE 1677 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1678 #endif 1679 1680 #ifndef MAX_PTRS_PER_PMD 1681 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1682 #endif 1683 1684 #ifndef MAX_PTRS_PER_PUD 1685 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1686 #endif 1687 1688 #ifndef MAX_PTRS_PER_P4D 1689 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1690 #endif 1691 1692 /* description of effects of mapping type and prot in current implementation. 1693 * this is due to the limited x86 page protection hardware. The expected 1694 * behavior is in parens: 1695 * 1696 * map_type prot 1697 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1698 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1699 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1700 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1701 * 1702 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1703 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1704 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1705 * 1706 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1707 * MAP_PRIVATE (with Enhanced PAN supported): 1708 * r: (no) no 1709 * w: (no) no 1710 * x: (yes) yes 1711 */ 1712 #define DECLARE_VM_GET_PAGE_PROT \ 1713 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1714 { \ 1715 return protection_map[vm_flags & \ 1716 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1717 } \ 1718 EXPORT_SYMBOL(vm_get_page_prot); 1719 1720 #endif /* _LINUX_PGTABLE_H */ 1721