1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT) 9 #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT) 10 11 #ifndef __ASSEMBLY__ 12 #ifdef CONFIG_MMU 13 14 #include <linux/mm_types.h> 15 #include <linux/bug.h> 16 #include <linux/errno.h> 17 #include <asm-generic/pgtable_uffd.h> 18 #include <linux/page_table_check.h> 19 20 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 22 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 23 #endif 24 25 /* 26 * On almost all architectures and configurations, 0 can be used as the 27 * upper ceiling to free_pgtables(): on many architectures it has the same 28 * effect as using TASK_SIZE. However, there is one configuration which 29 * must impose a more careful limit, to avoid freeing kernel pgtables. 30 */ 31 #ifndef USER_PGTABLES_CEILING 32 #define USER_PGTABLES_CEILING 0UL 33 #endif 34 35 /* 36 * This defines the first usable user address. Platforms 37 * can override its value with custom FIRST_USER_ADDRESS 38 * defined in their respective <asm/pgtable.h>. 39 */ 40 #ifndef FIRST_USER_ADDRESS 41 #define FIRST_USER_ADDRESS 0UL 42 #endif 43 44 /* 45 * This defines the generic helper for accessing PMD page 46 * table page. Although platforms can still override this 47 * via their respective <asm/pgtable.h>. 48 */ 49 #ifndef pmd_pgtable 50 #define pmd_pgtable(pmd) pmd_page(pmd) 51 #endif 52 53 /* 54 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 55 * 56 * The pXx_index() functions return the index of the entry in the page 57 * table page which would control the given virtual address 58 * 59 * As these functions may be used by the same code for different levels of 60 * the page table folding, they are always available, regardless of 61 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 62 * because in such cases PTRS_PER_PxD equals 1. 63 */ 64 65 static inline unsigned long pte_index(unsigned long address) 66 { 67 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 68 } 69 70 #ifndef pmd_index 71 static inline unsigned long pmd_index(unsigned long address) 72 { 73 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 74 } 75 #define pmd_index pmd_index 76 #endif 77 78 #ifndef pud_index 79 static inline unsigned long pud_index(unsigned long address) 80 { 81 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 82 } 83 #define pud_index pud_index 84 #endif 85 86 #ifndef pgd_index 87 /* Must be a compile-time constant, so implement it as a macro */ 88 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 89 #endif 90 91 #ifndef pte_offset_kernel 92 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 93 { 94 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 95 } 96 #define pte_offset_kernel pte_offset_kernel 97 #endif 98 99 #ifdef CONFIG_HIGHPTE 100 #define __pte_map(pmd, address) \ 101 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address))) 102 #define pte_unmap(pte) do { \ 103 kunmap_local((pte)); \ 104 rcu_read_unlock(); \ 105 } while (0) 106 #else 107 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address) 108 { 109 return pte_offset_kernel(pmd, address); 110 } 111 static inline void pte_unmap(pte_t *pte) 112 { 113 rcu_read_unlock(); 114 } 115 #endif 116 117 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable); 118 119 /* Find an entry in the second-level page table.. */ 120 #ifndef pmd_offset 121 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 122 { 123 return pud_pgtable(*pud) + pmd_index(address); 124 } 125 #define pmd_offset pmd_offset 126 #endif 127 128 #ifndef pud_offset 129 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 130 { 131 return p4d_pgtable(*p4d) + pud_index(address); 132 } 133 #define pud_offset pud_offset 134 #endif 135 136 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 137 { 138 return (pgd + pgd_index(address)); 139 }; 140 141 /* 142 * a shortcut to get a pgd_t in a given mm 143 */ 144 #ifndef pgd_offset 145 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 146 #endif 147 148 /* 149 * a shortcut which implies the use of the kernel's pgd, instead 150 * of a process's 151 */ 152 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 153 154 /* 155 * In many cases it is known that a virtual address is mapped at PMD or PTE 156 * level, so instead of traversing all the page table levels, we can get a 157 * pointer to the PMD entry in user or kernel page table or translate a virtual 158 * address to the pointer in the PTE in the kernel page tables with simple 159 * helpers. 160 */ 161 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 162 { 163 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 164 } 165 166 static inline pmd_t *pmd_off_k(unsigned long va) 167 { 168 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 169 } 170 171 static inline pte_t *virt_to_kpte(unsigned long vaddr) 172 { 173 pmd_t *pmd = pmd_off_k(vaddr); 174 175 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 176 } 177 178 #ifndef pmd_young 179 static inline int pmd_young(pmd_t pmd) 180 { 181 return 0; 182 } 183 #endif 184 185 #ifndef pmd_dirty 186 static inline int pmd_dirty(pmd_t pmd) 187 { 188 return 0; 189 } 190 #endif 191 192 /* 193 * A facility to provide lazy MMU batching. This allows PTE updates and 194 * page invalidations to be delayed until a call to leave lazy MMU mode 195 * is issued. Some architectures may benefit from doing this, and it is 196 * beneficial for both shadow and direct mode hypervisors, which may batch 197 * the PTE updates which happen during this window. Note that using this 198 * interface requires that read hazards be removed from the code. A read 199 * hazard could result in the direct mode hypervisor case, since the actual 200 * write to the page tables may not yet have taken place, so reads though 201 * a raw PTE pointer after it has been modified are not guaranteed to be 202 * up to date. This mode can only be entered and left under the protection of 203 * the page table locks for all page tables which may be modified. In the UP 204 * case, this is required so that preemption is disabled, and in the SMP case, 205 * it must synchronize the delayed page table writes properly on other CPUs. 206 */ 207 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 208 #define arch_enter_lazy_mmu_mode() do {} while (0) 209 #define arch_leave_lazy_mmu_mode() do {} while (0) 210 #define arch_flush_lazy_mmu_mode() do {} while (0) 211 #endif 212 213 #ifndef pte_batch_hint 214 /** 215 * pte_batch_hint - Number of pages that can be added to batch without scanning. 216 * @ptep: Page table pointer for the entry. 217 * @pte: Page table entry. 218 * 219 * Some architectures know that a set of contiguous ptes all map the same 220 * contiguous memory with the same permissions. In this case, it can provide a 221 * hint to aid pte batching without the core code needing to scan every pte. 222 * 223 * An architecture implementation may ignore the PTE accessed state. Further, 224 * the dirty state must apply atomically to all the PTEs described by the hint. 225 * 226 * May be overridden by the architecture, else pte_batch_hint is always 1. 227 */ 228 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 229 { 230 return 1; 231 } 232 #endif 233 234 #ifndef pte_advance_pfn 235 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 236 { 237 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 238 } 239 #endif 240 241 #define pte_next_pfn(pte) pte_advance_pfn(pte, 1) 242 243 #ifndef set_ptes 244 /** 245 * set_ptes - Map consecutive pages to a contiguous range of addresses. 246 * @mm: Address space to map the pages into. 247 * @addr: Address to map the first page at. 248 * @ptep: Page table pointer for the first entry. 249 * @pte: Page table entry for the first page. 250 * @nr: Number of pages to map. 251 * 252 * When nr==1, initial state of pte may be present or not present, and new state 253 * may be present or not present. When nr>1, initial state of all ptes must be 254 * not present, and new state must be present. 255 * 256 * May be overridden by the architecture, or the architecture can define 257 * set_pte() and PFN_PTE_SHIFT. 258 * 259 * Context: The caller holds the page table lock. The pages all belong 260 * to the same folio. The PTEs are all in the same PMD. 261 */ 262 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 263 pte_t *ptep, pte_t pte, unsigned int nr) 264 { 265 page_table_check_ptes_set(mm, ptep, pte, nr); 266 267 arch_enter_lazy_mmu_mode(); 268 for (;;) { 269 set_pte(ptep, pte); 270 if (--nr == 0) 271 break; 272 ptep++; 273 pte = pte_next_pfn(pte); 274 } 275 arch_leave_lazy_mmu_mode(); 276 } 277 #endif 278 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) 279 280 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 281 extern int ptep_set_access_flags(struct vm_area_struct *vma, 282 unsigned long address, pte_t *ptep, 283 pte_t entry, int dirty); 284 #endif 285 286 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 287 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 288 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 289 unsigned long address, pmd_t *pmdp, 290 pmd_t entry, int dirty); 291 extern int pudp_set_access_flags(struct vm_area_struct *vma, 292 unsigned long address, pud_t *pudp, 293 pud_t entry, int dirty); 294 #else 295 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 296 unsigned long address, pmd_t *pmdp, 297 pmd_t entry, int dirty) 298 { 299 BUILD_BUG(); 300 return 0; 301 } 302 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 303 unsigned long address, pud_t *pudp, 304 pud_t entry, int dirty) 305 { 306 BUILD_BUG(); 307 return 0; 308 } 309 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 310 #endif 311 312 #ifndef ptep_get 313 static inline pte_t ptep_get(pte_t *ptep) 314 { 315 return READ_ONCE(*ptep); 316 } 317 #endif 318 319 #ifndef pmdp_get 320 static inline pmd_t pmdp_get(pmd_t *pmdp) 321 { 322 return READ_ONCE(*pmdp); 323 } 324 #endif 325 326 #ifndef pudp_get 327 static inline pud_t pudp_get(pud_t *pudp) 328 { 329 return READ_ONCE(*pudp); 330 } 331 #endif 332 333 #ifndef p4dp_get 334 static inline p4d_t p4dp_get(p4d_t *p4dp) 335 { 336 return READ_ONCE(*p4dp); 337 } 338 #endif 339 340 #ifndef pgdp_get 341 static inline pgd_t pgdp_get(pgd_t *pgdp) 342 { 343 return READ_ONCE(*pgdp); 344 } 345 #endif 346 347 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 348 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 349 unsigned long address, 350 pte_t *ptep) 351 { 352 pte_t pte = ptep_get(ptep); 353 int r = 1; 354 if (!pte_young(pte)) 355 r = 0; 356 else 357 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 358 return r; 359 } 360 #endif 361 362 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 363 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 364 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 365 unsigned long address, 366 pmd_t *pmdp) 367 { 368 pmd_t pmd = *pmdp; 369 int r = 1; 370 if (!pmd_young(pmd)) 371 r = 0; 372 else 373 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 374 return r; 375 } 376 #else 377 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 378 unsigned long address, 379 pmd_t *pmdp) 380 { 381 BUILD_BUG(); 382 return 0; 383 } 384 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 385 #endif 386 387 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 388 int ptep_clear_flush_young(struct vm_area_struct *vma, 389 unsigned long address, pte_t *ptep); 390 #endif 391 392 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 393 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 394 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 395 unsigned long address, pmd_t *pmdp); 396 #else 397 /* 398 * Despite relevant to THP only, this API is called from generic rmap code 399 * under PageTransHuge(), hence needs a dummy implementation for !THP 400 */ 401 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 402 unsigned long address, pmd_t *pmdp) 403 { 404 BUILD_BUG(); 405 return 0; 406 } 407 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 408 #endif 409 410 #ifndef arch_has_hw_nonleaf_pmd_young 411 /* 412 * Return whether the accessed bit in non-leaf PMD entries is supported on the 413 * local CPU. 414 */ 415 static inline bool arch_has_hw_nonleaf_pmd_young(void) 416 { 417 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 418 } 419 #endif 420 421 #ifndef arch_has_hw_pte_young 422 /* 423 * Return whether the accessed bit is supported on the local CPU. 424 * 425 * This stub assumes accessing through an old PTE triggers a page fault. 426 * Architectures that automatically set the access bit should overwrite it. 427 */ 428 static inline bool arch_has_hw_pte_young(void) 429 { 430 return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG); 431 } 432 #endif 433 434 #ifndef arch_check_zapped_pte 435 static inline void arch_check_zapped_pte(struct vm_area_struct *vma, 436 pte_t pte) 437 { 438 } 439 #endif 440 441 #ifndef arch_check_zapped_pmd 442 static inline void arch_check_zapped_pmd(struct vm_area_struct *vma, 443 pmd_t pmd) 444 { 445 } 446 #endif 447 448 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 449 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 450 unsigned long address, 451 pte_t *ptep) 452 { 453 pte_t pte = ptep_get(ptep); 454 pte_clear(mm, address, ptep); 455 page_table_check_pte_clear(mm, pte); 456 return pte; 457 } 458 #endif 459 460 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 461 pte_t *ptep) 462 { 463 ptep_get_and_clear(mm, addr, ptep); 464 } 465 466 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH 467 /* 468 * For walking the pagetables without holding any locks. Some architectures 469 * (eg x86-32 PAE) cannot load the entries atomically without using expensive 470 * instructions. We are guaranteed that a PTE will only either go from not 471 * present to present, or present to not present -- it will not switch to a 472 * completely different present page without a TLB flush inbetween; which we 473 * are blocking by holding interrupts off. 474 * 475 * Setting ptes from not present to present goes: 476 * 477 * ptep->pte_high = h; 478 * smp_wmb(); 479 * ptep->pte_low = l; 480 * 481 * And present to not present goes: 482 * 483 * ptep->pte_low = 0; 484 * smp_wmb(); 485 * ptep->pte_high = 0; 486 * 487 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 488 * We load pte_high *after* loading pte_low, which ensures we don't see an older 489 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 490 * picked up a changed pte high. We might have gotten rubbish values from 491 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 492 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 493 * operates on present ptes we're safe. 494 */ 495 static inline pte_t ptep_get_lockless(pte_t *ptep) 496 { 497 pte_t pte; 498 499 do { 500 pte.pte_low = ptep->pte_low; 501 smp_rmb(); 502 pte.pte_high = ptep->pte_high; 503 smp_rmb(); 504 } while (unlikely(pte.pte_low != ptep->pte_low)); 505 506 return pte; 507 } 508 #define ptep_get_lockless ptep_get_lockless 509 510 #if CONFIG_PGTABLE_LEVELS > 2 511 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 512 { 513 pmd_t pmd; 514 515 do { 516 pmd.pmd_low = pmdp->pmd_low; 517 smp_rmb(); 518 pmd.pmd_high = pmdp->pmd_high; 519 smp_rmb(); 520 } while (unlikely(pmd.pmd_low != pmdp->pmd_low)); 521 522 return pmd; 523 } 524 #define pmdp_get_lockless pmdp_get_lockless 525 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one() 526 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 527 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */ 528 529 /* 530 * We require that the PTE can be read atomically. 531 */ 532 #ifndef ptep_get_lockless 533 static inline pte_t ptep_get_lockless(pte_t *ptep) 534 { 535 return ptep_get(ptep); 536 } 537 #endif 538 539 #ifndef pmdp_get_lockless 540 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 541 { 542 return pmdp_get(pmdp); 543 } 544 static inline void pmdp_get_lockless_sync(void) 545 { 546 } 547 #endif 548 549 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 550 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 551 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 552 unsigned long address, 553 pmd_t *pmdp) 554 { 555 pmd_t pmd = *pmdp; 556 557 pmd_clear(pmdp); 558 page_table_check_pmd_clear(mm, pmd); 559 560 return pmd; 561 } 562 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 563 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 564 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 565 unsigned long address, 566 pud_t *pudp) 567 { 568 pud_t pud = *pudp; 569 570 pud_clear(pudp); 571 page_table_check_pud_clear(mm, pud); 572 573 return pud; 574 } 575 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 576 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 577 578 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 579 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 580 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 581 unsigned long address, pmd_t *pmdp, 582 int full) 583 { 584 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 585 } 586 #endif 587 588 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 589 static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 590 unsigned long address, pud_t *pudp, 591 int full) 592 { 593 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp); 594 } 595 #endif 596 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 597 598 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 599 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 600 unsigned long address, pte_t *ptep, 601 int full) 602 { 603 return ptep_get_and_clear(mm, address, ptep); 604 } 605 #endif 606 607 #ifndef get_and_clear_full_ptes 608 /** 609 * get_and_clear_full_ptes - Clear present PTEs that map consecutive pages of 610 * the same folio, collecting dirty/accessed bits. 611 * @mm: Address space the pages are mapped into. 612 * @addr: Address the first page is mapped at. 613 * @ptep: Page table pointer for the first entry. 614 * @nr: Number of entries to clear. 615 * @full: Whether we are clearing a full mm. 616 * 617 * May be overridden by the architecture; otherwise, implemented as a simple 618 * loop over ptep_get_and_clear_full(), merging dirty/accessed bits into the 619 * returned PTE. 620 * 621 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 622 * some PTEs might be write-protected. 623 * 624 * Context: The caller holds the page table lock. The PTEs map consecutive 625 * pages that belong to the same folio. The PTEs are all in the same PMD. 626 */ 627 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 628 unsigned long addr, pte_t *ptep, unsigned int nr, int full) 629 { 630 pte_t pte, tmp_pte; 631 632 pte = ptep_get_and_clear_full(mm, addr, ptep, full); 633 while (--nr) { 634 ptep++; 635 addr += PAGE_SIZE; 636 tmp_pte = ptep_get_and_clear_full(mm, addr, ptep, full); 637 if (pte_dirty(tmp_pte)) 638 pte = pte_mkdirty(pte); 639 if (pte_young(tmp_pte)) 640 pte = pte_mkyoung(pte); 641 } 642 return pte; 643 } 644 #endif 645 646 #ifndef clear_full_ptes 647 /** 648 * clear_full_ptes - Clear present PTEs that map consecutive pages of the same 649 * folio. 650 * @mm: Address space the pages are mapped into. 651 * @addr: Address the first page is mapped at. 652 * @ptep: Page table pointer for the first entry. 653 * @nr: Number of entries to clear. 654 * @full: Whether we are clearing a full mm. 655 * 656 * May be overridden by the architecture; otherwise, implemented as a simple 657 * loop over ptep_get_and_clear_full(). 658 * 659 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 660 * some PTEs might be write-protected. 661 * 662 * Context: The caller holds the page table lock. The PTEs map consecutive 663 * pages that belong to the same folio. The PTEs are all in the same PMD. 664 */ 665 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 666 pte_t *ptep, unsigned int nr, int full) 667 { 668 for (;;) { 669 ptep_get_and_clear_full(mm, addr, ptep, full); 670 if (--nr == 0) 671 break; 672 ptep++; 673 addr += PAGE_SIZE; 674 } 675 } 676 #endif 677 678 /* 679 * If two threads concurrently fault at the same page, the thread that 680 * won the race updates the PTE and its local TLB/Cache. The other thread 681 * gives up, simply does nothing, and continues; on architectures where 682 * software can update TLB, local TLB can be updated here to avoid next page 683 * fault. This function updates TLB only, do nothing with cache or others. 684 * It is the difference with function update_mmu_cache. 685 */ 686 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 687 static inline void update_mmu_tlb(struct vm_area_struct *vma, 688 unsigned long address, pte_t *ptep) 689 { 690 } 691 #define __HAVE_ARCH_UPDATE_MMU_TLB 692 #endif 693 694 /* 695 * Some architectures may be able to avoid expensive synchronization 696 * primitives when modifications are made to PTE's which are already 697 * not present, or in the process of an address space destruction. 698 */ 699 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 700 static inline void pte_clear_not_present_full(struct mm_struct *mm, 701 unsigned long address, 702 pte_t *ptep, 703 int full) 704 { 705 pte_clear(mm, address, ptep); 706 } 707 #endif 708 709 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 710 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 711 unsigned long address, 712 pte_t *ptep); 713 #endif 714 715 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 716 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 717 unsigned long address, 718 pmd_t *pmdp); 719 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 720 unsigned long address, 721 pud_t *pudp); 722 #endif 723 724 #ifndef pte_mkwrite 725 static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma) 726 { 727 return pte_mkwrite_novma(pte); 728 } 729 #endif 730 731 #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite) 732 static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma) 733 { 734 return pmd_mkwrite_novma(pmd); 735 } 736 #endif 737 738 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 739 struct mm_struct; 740 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 741 { 742 pte_t old_pte = ptep_get(ptep); 743 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 744 } 745 #endif 746 747 #ifndef wrprotect_ptes 748 /** 749 * wrprotect_ptes - Write-protect PTEs that map consecutive pages of the same 750 * folio. 751 * @mm: Address space the pages are mapped into. 752 * @addr: Address the first page is mapped at. 753 * @ptep: Page table pointer for the first entry. 754 * @nr: Number of entries to write-protect. 755 * 756 * May be overridden by the architecture; otherwise, implemented as a simple 757 * loop over ptep_set_wrprotect(). 758 * 759 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 760 * some PTEs might be write-protected. 761 * 762 * Context: The caller holds the page table lock. The PTEs map consecutive 763 * pages that belong to the same folio. The PTEs are all in the same PMD. 764 */ 765 static inline void wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 766 pte_t *ptep, unsigned int nr) 767 { 768 for (;;) { 769 ptep_set_wrprotect(mm, addr, ptep); 770 if (--nr == 0) 771 break; 772 ptep++; 773 addr += PAGE_SIZE; 774 } 775 } 776 #endif 777 778 /* 779 * On some architectures hardware does not set page access bit when accessing 780 * memory page, it is responsibility of software setting this bit. It brings 781 * out extra page fault penalty to track page access bit. For optimization page 782 * access bit can be set during all page fault flow on these arches. 783 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 784 * where software maintains page access bit. 785 */ 786 #ifndef pte_sw_mkyoung 787 static inline pte_t pte_sw_mkyoung(pte_t pte) 788 { 789 return pte; 790 } 791 #define pte_sw_mkyoung pte_sw_mkyoung 792 #endif 793 794 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 795 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 796 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 797 unsigned long address, pmd_t *pmdp) 798 { 799 pmd_t old_pmd = *pmdp; 800 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 801 } 802 #else 803 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 804 unsigned long address, pmd_t *pmdp) 805 { 806 BUILD_BUG(); 807 } 808 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 809 #endif 810 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 811 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 812 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 813 static inline void pudp_set_wrprotect(struct mm_struct *mm, 814 unsigned long address, pud_t *pudp) 815 { 816 pud_t old_pud = *pudp; 817 818 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 819 } 820 #else 821 static inline void pudp_set_wrprotect(struct mm_struct *mm, 822 unsigned long address, pud_t *pudp) 823 { 824 BUILD_BUG(); 825 } 826 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 827 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 828 #endif 829 830 #ifndef pmdp_collapse_flush 831 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 832 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 833 unsigned long address, pmd_t *pmdp); 834 #else 835 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 836 unsigned long address, 837 pmd_t *pmdp) 838 { 839 BUILD_BUG(); 840 return *pmdp; 841 } 842 #define pmdp_collapse_flush pmdp_collapse_flush 843 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 844 #endif 845 846 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 847 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 848 pgtable_t pgtable); 849 #endif 850 851 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 852 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 853 #endif 854 855 #ifndef arch_needs_pgtable_deposit 856 #define arch_needs_pgtable_deposit() (false) 857 #endif 858 859 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 860 /* 861 * This is an implementation of pmdp_establish() that is only suitable for an 862 * architecture that doesn't have hardware dirty/accessed bits. In this case we 863 * can't race with CPU which sets these bits and non-atomic approach is fine. 864 */ 865 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 866 unsigned long address, pmd_t *pmdp, pmd_t pmd) 867 { 868 pmd_t old_pmd = *pmdp; 869 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 870 return old_pmd; 871 } 872 #endif 873 874 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 875 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 876 pmd_t *pmdp); 877 #endif 878 879 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 880 881 /* 882 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 883 * hugepage mapping in the page tables. This function is similar to 884 * pmdp_invalidate(), but should only be used if the access and dirty bits would 885 * not be cleared by the software in the new PMD value. The function ensures 886 * that hardware changes of the access and dirty bits updates would not be lost. 887 * 888 * Doing so can allow in certain architectures to avoid a TLB flush in most 889 * cases. Yet, another TLB flush might be necessary later if the PMD update 890 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 891 * even when a TLB flush is needed because of the update, the caller may be able 892 * to batch these TLB flushing operations, so fewer TLB flush operations are 893 * needed. 894 */ 895 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 896 unsigned long address, pmd_t *pmdp); 897 #endif 898 899 #ifndef __HAVE_ARCH_PTE_SAME 900 static inline int pte_same(pte_t pte_a, pte_t pte_b) 901 { 902 return pte_val(pte_a) == pte_val(pte_b); 903 } 904 #endif 905 906 #ifndef __HAVE_ARCH_PTE_UNUSED 907 /* 908 * Some architectures provide facilities to virtualization guests 909 * so that they can flag allocated pages as unused. This allows the 910 * host to transparently reclaim unused pages. This function returns 911 * whether the pte's page is unused. 912 */ 913 static inline int pte_unused(pte_t pte) 914 { 915 return 0; 916 } 917 #endif 918 919 #ifndef pte_access_permitted 920 #define pte_access_permitted(pte, write) \ 921 (pte_present(pte) && (!(write) || pte_write(pte))) 922 #endif 923 924 #ifndef pmd_access_permitted 925 #define pmd_access_permitted(pmd, write) \ 926 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 927 #endif 928 929 #ifndef pud_access_permitted 930 #define pud_access_permitted(pud, write) \ 931 (pud_present(pud) && (!(write) || pud_write(pud))) 932 #endif 933 934 #ifndef p4d_access_permitted 935 #define p4d_access_permitted(p4d, write) \ 936 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 937 #endif 938 939 #ifndef pgd_access_permitted 940 #define pgd_access_permitted(pgd, write) \ 941 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 942 #endif 943 944 #ifndef __HAVE_ARCH_PMD_SAME 945 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 946 { 947 return pmd_val(pmd_a) == pmd_val(pmd_b); 948 } 949 #endif 950 951 #ifndef pud_same 952 static inline int pud_same(pud_t pud_a, pud_t pud_b) 953 { 954 return pud_val(pud_a) == pud_val(pud_b); 955 } 956 #define pud_same pud_same 957 #endif 958 959 #ifndef __HAVE_ARCH_P4D_SAME 960 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 961 { 962 return p4d_val(p4d_a) == p4d_val(p4d_b); 963 } 964 #endif 965 966 #ifndef __HAVE_ARCH_PGD_SAME 967 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 968 { 969 return pgd_val(pgd_a) == pgd_val(pgd_b); 970 } 971 #endif 972 973 /* 974 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 975 * TLB flush will be required as a result of the "set". For example, use 976 * in scenarios where it is known ahead of time that the routine is 977 * setting non-present entries, or re-setting an existing entry to the 978 * same value. Otherwise, use the typical "set" helpers and flush the 979 * TLB. 980 */ 981 #define set_pte_safe(ptep, pte) \ 982 ({ \ 983 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 984 set_pte(ptep, pte); \ 985 }) 986 987 #define set_pmd_safe(pmdp, pmd) \ 988 ({ \ 989 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 990 set_pmd(pmdp, pmd); \ 991 }) 992 993 #define set_pud_safe(pudp, pud) \ 994 ({ \ 995 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 996 set_pud(pudp, pud); \ 997 }) 998 999 #define set_p4d_safe(p4dp, p4d) \ 1000 ({ \ 1001 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1002 set_p4d(p4dp, p4d); \ 1003 }) 1004 1005 #define set_pgd_safe(pgdp, pgd) \ 1006 ({ \ 1007 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1008 set_pgd(pgdp, pgd); \ 1009 }) 1010 1011 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 1012 /* 1013 * Some architectures support metadata associated with a page. When a 1014 * page is being swapped out, this metadata must be saved so it can be 1015 * restored when the page is swapped back in. SPARC M7 and newer 1016 * processors support an ADI (Application Data Integrity) tag for the 1017 * page as metadata for the page. arch_do_swap_page() can restore this 1018 * metadata when a page is swapped back in. 1019 */ 1020 static inline void arch_do_swap_page(struct mm_struct *mm, 1021 struct vm_area_struct *vma, 1022 unsigned long addr, 1023 pte_t pte, pte_t oldpte) 1024 { 1025 1026 } 1027 #endif 1028 1029 #ifndef __HAVE_ARCH_UNMAP_ONE 1030 /* 1031 * Some architectures support metadata associated with a page. When a 1032 * page is being swapped out, this metadata must be saved so it can be 1033 * restored when the page is swapped back in. SPARC M7 and newer 1034 * processors support an ADI (Application Data Integrity) tag for the 1035 * page as metadata for the page. arch_unmap_one() can save this 1036 * metadata on a swap-out of a page. 1037 */ 1038 static inline int arch_unmap_one(struct mm_struct *mm, 1039 struct vm_area_struct *vma, 1040 unsigned long addr, 1041 pte_t orig_pte) 1042 { 1043 return 0; 1044 } 1045 #endif 1046 1047 /* 1048 * Allow architectures to preserve additional metadata associated with 1049 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 1050 * prototypes must be defined in the arch-specific asm/pgtable.h file. 1051 */ 1052 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 1053 static inline int arch_prepare_to_swap(struct page *page) 1054 { 1055 return 0; 1056 } 1057 #endif 1058 1059 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 1060 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1061 { 1062 } 1063 1064 static inline void arch_swap_invalidate_area(int type) 1065 { 1066 } 1067 #endif 1068 1069 #ifndef __HAVE_ARCH_SWAP_RESTORE 1070 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1071 { 1072 } 1073 #endif 1074 1075 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 1076 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 1077 #endif 1078 1079 #ifndef __HAVE_ARCH_MOVE_PTE 1080 #define move_pte(pte, prot, old_addr, new_addr) (pte) 1081 #endif 1082 1083 #ifndef pte_accessible 1084 # define pte_accessible(mm, pte) ((void)(pte), 1) 1085 #endif 1086 1087 #ifndef flush_tlb_fix_spurious_fault 1088 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address) 1089 #endif 1090 1091 /* 1092 * When walking page tables, get the address of the next boundary, 1093 * or the end address of the range if that comes earlier. Although no 1094 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 1095 */ 1096 1097 #define pgd_addr_end(addr, end) \ 1098 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 1099 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1100 }) 1101 1102 #ifndef p4d_addr_end 1103 #define p4d_addr_end(addr, end) \ 1104 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 1105 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1106 }) 1107 #endif 1108 1109 #ifndef pud_addr_end 1110 #define pud_addr_end(addr, end) \ 1111 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 1112 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1113 }) 1114 #endif 1115 1116 #ifndef pmd_addr_end 1117 #define pmd_addr_end(addr, end) \ 1118 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 1119 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1120 }) 1121 #endif 1122 1123 /* 1124 * When walking page tables, we usually want to skip any p?d_none entries; 1125 * and any p?d_bad entries - reporting the error before resetting to none. 1126 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 1127 */ 1128 void pgd_clear_bad(pgd_t *); 1129 1130 #ifndef __PAGETABLE_P4D_FOLDED 1131 void p4d_clear_bad(p4d_t *); 1132 #else 1133 #define p4d_clear_bad(p4d) do { } while (0) 1134 #endif 1135 1136 #ifndef __PAGETABLE_PUD_FOLDED 1137 void pud_clear_bad(pud_t *); 1138 #else 1139 #define pud_clear_bad(p4d) do { } while (0) 1140 #endif 1141 1142 void pmd_clear_bad(pmd_t *); 1143 1144 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 1145 { 1146 if (pgd_none(*pgd)) 1147 return 1; 1148 if (unlikely(pgd_bad(*pgd))) { 1149 pgd_clear_bad(pgd); 1150 return 1; 1151 } 1152 return 0; 1153 } 1154 1155 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 1156 { 1157 if (p4d_none(*p4d)) 1158 return 1; 1159 if (unlikely(p4d_bad(*p4d))) { 1160 p4d_clear_bad(p4d); 1161 return 1; 1162 } 1163 return 0; 1164 } 1165 1166 static inline int pud_none_or_clear_bad(pud_t *pud) 1167 { 1168 if (pud_none(*pud)) 1169 return 1; 1170 if (unlikely(pud_bad(*pud))) { 1171 pud_clear_bad(pud); 1172 return 1; 1173 } 1174 return 0; 1175 } 1176 1177 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 1178 { 1179 if (pmd_none(*pmd)) 1180 return 1; 1181 if (unlikely(pmd_bad(*pmd))) { 1182 pmd_clear_bad(pmd); 1183 return 1; 1184 } 1185 return 0; 1186 } 1187 1188 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 1189 unsigned long addr, 1190 pte_t *ptep) 1191 { 1192 /* 1193 * Get the current pte state, but zero it out to make it 1194 * non-present, preventing the hardware from asynchronously 1195 * updating it. 1196 */ 1197 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 1198 } 1199 1200 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 1201 unsigned long addr, 1202 pte_t *ptep, pte_t pte) 1203 { 1204 /* 1205 * The pte is non-present, so there's no hardware state to 1206 * preserve. 1207 */ 1208 set_pte_at(vma->vm_mm, addr, ptep, pte); 1209 } 1210 1211 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1212 /* 1213 * Start a pte protection read-modify-write transaction, which 1214 * protects against asynchronous hardware modifications to the pte. 1215 * The intention is not to prevent the hardware from making pte 1216 * updates, but to prevent any updates it may make from being lost. 1217 * 1218 * This does not protect against other software modifications of the 1219 * pte; the appropriate pte lock must be held over the transaction. 1220 * 1221 * Note that this interface is intended to be batchable, meaning that 1222 * ptep_modify_prot_commit may not actually update the pte, but merely 1223 * queue the update to be done at some later time. The update must be 1224 * actually committed before the pte lock is released, however. 1225 */ 1226 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1227 unsigned long addr, 1228 pte_t *ptep) 1229 { 1230 return __ptep_modify_prot_start(vma, addr, ptep); 1231 } 1232 1233 /* 1234 * Commit an update to a pte, leaving any hardware-controlled bits in 1235 * the PTE unmodified. 1236 */ 1237 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 1238 unsigned long addr, 1239 pte_t *ptep, pte_t old_pte, pte_t pte) 1240 { 1241 __ptep_modify_prot_commit(vma, addr, ptep, pte); 1242 } 1243 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 1244 #endif /* CONFIG_MMU */ 1245 1246 /* 1247 * No-op macros that just return the current protection value. Defined here 1248 * because these macros can be used even if CONFIG_MMU is not defined. 1249 */ 1250 1251 #ifndef pgprot_nx 1252 #define pgprot_nx(prot) (prot) 1253 #endif 1254 1255 #ifndef pgprot_noncached 1256 #define pgprot_noncached(prot) (prot) 1257 #endif 1258 1259 #ifndef pgprot_writecombine 1260 #define pgprot_writecombine pgprot_noncached 1261 #endif 1262 1263 #ifndef pgprot_writethrough 1264 #define pgprot_writethrough pgprot_noncached 1265 #endif 1266 1267 #ifndef pgprot_device 1268 #define pgprot_device pgprot_noncached 1269 #endif 1270 1271 #ifndef pgprot_mhp 1272 #define pgprot_mhp(prot) (prot) 1273 #endif 1274 1275 #ifdef CONFIG_MMU 1276 #ifndef pgprot_modify 1277 #define pgprot_modify pgprot_modify 1278 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 1279 { 1280 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 1281 newprot = pgprot_noncached(newprot); 1282 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 1283 newprot = pgprot_writecombine(newprot); 1284 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 1285 newprot = pgprot_device(newprot); 1286 return newprot; 1287 } 1288 #endif 1289 #endif /* CONFIG_MMU */ 1290 1291 #ifndef pgprot_encrypted 1292 #define pgprot_encrypted(prot) (prot) 1293 #endif 1294 1295 #ifndef pgprot_decrypted 1296 #define pgprot_decrypted(prot) (prot) 1297 #endif 1298 1299 /* 1300 * A facility to provide batching of the reload of page tables and 1301 * other process state with the actual context switch code for 1302 * paravirtualized guests. By convention, only one of the batched 1303 * update (lazy) modes (CPU, MMU) should be active at any given time, 1304 * entry should never be nested, and entry and exits should always be 1305 * paired. This is for sanity of maintaining and reasoning about the 1306 * kernel code. In this case, the exit (end of the context switch) is 1307 * in architecture-specific code, and so doesn't need a generic 1308 * definition. 1309 */ 1310 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1311 #define arch_start_context_switch(prev) do {} while (0) 1312 #endif 1313 1314 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1315 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1316 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1317 { 1318 return pmd; 1319 } 1320 1321 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1322 { 1323 return 0; 1324 } 1325 1326 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1327 { 1328 return pmd; 1329 } 1330 #endif 1331 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1332 static inline int pte_soft_dirty(pte_t pte) 1333 { 1334 return 0; 1335 } 1336 1337 static inline int pmd_soft_dirty(pmd_t pmd) 1338 { 1339 return 0; 1340 } 1341 1342 static inline pte_t pte_mksoft_dirty(pte_t pte) 1343 { 1344 return pte; 1345 } 1346 1347 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1348 { 1349 return pmd; 1350 } 1351 1352 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1353 { 1354 return pte; 1355 } 1356 1357 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1358 { 1359 return pmd; 1360 } 1361 1362 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1363 { 1364 return pte; 1365 } 1366 1367 static inline int pte_swp_soft_dirty(pte_t pte) 1368 { 1369 return 0; 1370 } 1371 1372 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1373 { 1374 return pte; 1375 } 1376 1377 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1378 { 1379 return pmd; 1380 } 1381 1382 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1383 { 1384 return 0; 1385 } 1386 1387 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1388 { 1389 return pmd; 1390 } 1391 #endif 1392 1393 #ifndef __HAVE_PFNMAP_TRACKING 1394 /* 1395 * Interfaces that can be used by architecture code to keep track of 1396 * memory type of pfn mappings specified by the remap_pfn_range, 1397 * vmf_insert_pfn. 1398 */ 1399 1400 /* 1401 * track_pfn_remap is called when a _new_ pfn mapping is being established 1402 * by remap_pfn_range() for physical range indicated by pfn and size. 1403 */ 1404 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1405 unsigned long pfn, unsigned long addr, 1406 unsigned long size) 1407 { 1408 return 0; 1409 } 1410 1411 /* 1412 * track_pfn_insert is called when a _new_ single pfn is established 1413 * by vmf_insert_pfn(). 1414 */ 1415 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1416 pfn_t pfn) 1417 { 1418 } 1419 1420 /* 1421 * track_pfn_copy is called when vma that is covering the pfnmap gets 1422 * copied through copy_page_range(). 1423 */ 1424 static inline int track_pfn_copy(struct vm_area_struct *vma) 1425 { 1426 return 0; 1427 } 1428 1429 /* 1430 * untrack_pfn is called while unmapping a pfnmap for a region. 1431 * untrack can be called for a specific region indicated by pfn and size or 1432 * can be for the entire vma (in which case pfn, size are zero). 1433 */ 1434 static inline void untrack_pfn(struct vm_area_struct *vma, 1435 unsigned long pfn, unsigned long size, 1436 bool mm_wr_locked) 1437 { 1438 } 1439 1440 /* 1441 * untrack_pfn_clear is called while mremapping a pfnmap for a new region 1442 * or fails to copy pgtable during duplicate vm area. 1443 */ 1444 static inline void untrack_pfn_clear(struct vm_area_struct *vma) 1445 { 1446 } 1447 #else 1448 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1449 unsigned long pfn, unsigned long addr, 1450 unsigned long size); 1451 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1452 pfn_t pfn); 1453 extern int track_pfn_copy(struct vm_area_struct *vma); 1454 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1455 unsigned long size, bool mm_wr_locked); 1456 extern void untrack_pfn_clear(struct vm_area_struct *vma); 1457 #endif 1458 1459 #ifdef CONFIG_MMU 1460 #ifdef __HAVE_COLOR_ZERO_PAGE 1461 static inline int is_zero_pfn(unsigned long pfn) 1462 { 1463 extern unsigned long zero_pfn; 1464 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1465 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1466 } 1467 1468 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1469 1470 #else 1471 static inline int is_zero_pfn(unsigned long pfn) 1472 { 1473 extern unsigned long zero_pfn; 1474 return pfn == zero_pfn; 1475 } 1476 1477 static inline unsigned long my_zero_pfn(unsigned long addr) 1478 { 1479 extern unsigned long zero_pfn; 1480 return zero_pfn; 1481 } 1482 #endif 1483 #else 1484 static inline int is_zero_pfn(unsigned long pfn) 1485 { 1486 return 0; 1487 } 1488 1489 static inline unsigned long my_zero_pfn(unsigned long addr) 1490 { 1491 return 0; 1492 } 1493 #endif /* CONFIG_MMU */ 1494 1495 #ifdef CONFIG_MMU 1496 1497 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1498 static inline int pmd_trans_huge(pmd_t pmd) 1499 { 1500 return 0; 1501 } 1502 #ifndef pmd_write 1503 static inline int pmd_write(pmd_t pmd) 1504 { 1505 BUG(); 1506 return 0; 1507 } 1508 #endif /* pmd_write */ 1509 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1510 1511 #ifndef pud_write 1512 static inline int pud_write(pud_t pud) 1513 { 1514 BUG(); 1515 return 0; 1516 } 1517 #endif /* pud_write */ 1518 1519 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1520 static inline int pmd_devmap(pmd_t pmd) 1521 { 1522 return 0; 1523 } 1524 static inline int pud_devmap(pud_t pud) 1525 { 1526 return 0; 1527 } 1528 static inline int pgd_devmap(pgd_t pgd) 1529 { 1530 return 0; 1531 } 1532 #endif 1533 1534 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1535 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1536 static inline int pud_trans_huge(pud_t pud) 1537 { 1538 return 0; 1539 } 1540 #endif 1541 1542 static inline int pud_trans_unstable(pud_t *pud) 1543 { 1544 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1545 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1546 pud_t pudval = READ_ONCE(*pud); 1547 1548 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1549 return 1; 1550 if (unlikely(pud_bad(pudval))) { 1551 pud_clear_bad(pud); 1552 return 1; 1553 } 1554 #endif 1555 return 0; 1556 } 1557 1558 #ifndef CONFIG_NUMA_BALANCING 1559 /* 1560 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is 1561 * perfectly valid to indicate "no" in that case, which is why our default 1562 * implementation defaults to "always no". 1563 * 1564 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE 1565 * page protection due to NUMA hinting. NUMA hinting faults only apply in 1566 * accessible VMAs. 1567 * 1568 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault, 1569 * looking at the VMA accessibility is sufficient. 1570 */ 1571 static inline int pte_protnone(pte_t pte) 1572 { 1573 return 0; 1574 } 1575 1576 static inline int pmd_protnone(pmd_t pmd) 1577 { 1578 return 0; 1579 } 1580 #endif /* CONFIG_NUMA_BALANCING */ 1581 1582 #endif /* CONFIG_MMU */ 1583 1584 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1585 1586 #ifndef __PAGETABLE_P4D_FOLDED 1587 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1588 void p4d_clear_huge(p4d_t *p4d); 1589 #else 1590 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1591 { 1592 return 0; 1593 } 1594 static inline void p4d_clear_huge(p4d_t *p4d) { } 1595 #endif /* !__PAGETABLE_P4D_FOLDED */ 1596 1597 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1598 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1599 int pud_clear_huge(pud_t *pud); 1600 int pmd_clear_huge(pmd_t *pmd); 1601 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1602 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1603 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1604 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1605 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1606 { 1607 return 0; 1608 } 1609 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1610 { 1611 return 0; 1612 } 1613 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1614 { 1615 return 0; 1616 } 1617 static inline void p4d_clear_huge(p4d_t *p4d) { } 1618 static inline int pud_clear_huge(pud_t *pud) 1619 { 1620 return 0; 1621 } 1622 static inline int pmd_clear_huge(pmd_t *pmd) 1623 { 1624 return 0; 1625 } 1626 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1627 { 1628 return 0; 1629 } 1630 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1631 { 1632 return 0; 1633 } 1634 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1635 { 1636 return 0; 1637 } 1638 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1639 1640 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1641 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1642 /* 1643 * ARCHes with special requirements for evicting THP backing TLB entries can 1644 * implement this. Otherwise also, it can help optimize normal TLB flush in 1645 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1646 * entire TLB if flush span is greater than a threshold, which will 1647 * likely be true for a single huge page. Thus a single THP flush will 1648 * invalidate the entire TLB which is not desirable. 1649 * e.g. see arch/arc: flush_pmd_tlb_range 1650 */ 1651 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1652 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1653 #else 1654 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1655 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1656 #endif 1657 #endif 1658 1659 struct file; 1660 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1661 unsigned long size, pgprot_t *vma_prot); 1662 1663 #ifndef CONFIG_X86_ESPFIX64 1664 static inline void init_espfix_bsp(void) { } 1665 #endif 1666 1667 extern void __init pgtable_cache_init(void); 1668 1669 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1670 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1671 { 1672 return true; 1673 } 1674 1675 static inline bool arch_has_pfn_modify_check(void) 1676 { 1677 return false; 1678 } 1679 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1680 1681 /* 1682 * Architecture PAGE_KERNEL_* fallbacks 1683 * 1684 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1685 * because they really don't support them, or the port needs to be updated to 1686 * reflect the required functionality. Below are a set of relatively safe 1687 * fallbacks, as best effort, which we can count on in lieu of the architectures 1688 * not defining them on their own yet. 1689 */ 1690 1691 #ifndef PAGE_KERNEL_RO 1692 # define PAGE_KERNEL_RO PAGE_KERNEL 1693 #endif 1694 1695 #ifndef PAGE_KERNEL_EXEC 1696 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1697 #endif 1698 1699 /* 1700 * Page Table Modification bits for pgtbl_mod_mask. 1701 * 1702 * These are used by the p?d_alloc_track*() set of functions an in the generic 1703 * vmalloc/ioremap code to track at which page-table levels entries have been 1704 * modified. Based on that the code can better decide when vmalloc and ioremap 1705 * mapping changes need to be synchronized to other page-tables in the system. 1706 */ 1707 #define __PGTBL_PGD_MODIFIED 0 1708 #define __PGTBL_P4D_MODIFIED 1 1709 #define __PGTBL_PUD_MODIFIED 2 1710 #define __PGTBL_PMD_MODIFIED 3 1711 #define __PGTBL_PTE_MODIFIED 4 1712 1713 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1714 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1715 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1716 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1717 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1718 1719 /* Page-Table Modification Mask */ 1720 typedef unsigned int pgtbl_mod_mask; 1721 1722 #endif /* !__ASSEMBLY__ */ 1723 1724 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1725 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1726 /* 1727 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1728 * with physical address space extension, but falls back to 1729 * BITS_PER_LONG otherwise. 1730 */ 1731 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1732 #else 1733 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1734 #endif 1735 #endif 1736 1737 #ifndef has_transparent_hugepage 1738 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1739 #endif 1740 1741 #ifndef has_transparent_pud_hugepage 1742 #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1743 #endif 1744 /* 1745 * On some architectures it depends on the mm if the p4d/pud or pmd 1746 * layer of the page table hierarchy is folded or not. 1747 */ 1748 #ifndef mm_p4d_folded 1749 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1750 #endif 1751 1752 #ifndef mm_pud_folded 1753 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1754 #endif 1755 1756 #ifndef mm_pmd_folded 1757 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1758 #endif 1759 1760 #ifndef p4d_offset_lockless 1761 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1762 #endif 1763 #ifndef pud_offset_lockless 1764 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1765 #endif 1766 #ifndef pmd_offset_lockless 1767 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1768 #endif 1769 1770 /* 1771 * p?d_leaf() - true if this entry is a final mapping to a physical address. 1772 * This differs from p?d_huge() by the fact that they are always available (if 1773 * the architecture supports large pages at the appropriate level) even 1774 * if CONFIG_HUGETLB_PAGE is not defined. 1775 * Only meaningful when called on a valid entry. 1776 */ 1777 #ifndef pgd_leaf 1778 #define pgd_leaf(x) false 1779 #endif 1780 #ifndef p4d_leaf 1781 #define p4d_leaf(x) false 1782 #endif 1783 #ifndef pud_leaf 1784 #define pud_leaf(x) false 1785 #endif 1786 #ifndef pmd_leaf 1787 #define pmd_leaf(x) false 1788 #endif 1789 1790 #ifndef pgd_leaf_size 1791 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1792 #endif 1793 #ifndef p4d_leaf_size 1794 #define p4d_leaf_size(x) P4D_SIZE 1795 #endif 1796 #ifndef pud_leaf_size 1797 #define pud_leaf_size(x) PUD_SIZE 1798 #endif 1799 #ifndef pmd_leaf_size 1800 #define pmd_leaf_size(x) PMD_SIZE 1801 #endif 1802 #ifndef pte_leaf_size 1803 #define pte_leaf_size(x) PAGE_SIZE 1804 #endif 1805 1806 /* 1807 * Some architectures have MMUs that are configurable or selectable at boot 1808 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1809 * helps to have a static maximum value. 1810 */ 1811 1812 #ifndef MAX_PTRS_PER_PTE 1813 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1814 #endif 1815 1816 #ifndef MAX_PTRS_PER_PMD 1817 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1818 #endif 1819 1820 #ifndef MAX_PTRS_PER_PUD 1821 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1822 #endif 1823 1824 #ifndef MAX_PTRS_PER_P4D 1825 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1826 #endif 1827 1828 /* description of effects of mapping type and prot in current implementation. 1829 * this is due to the limited x86 page protection hardware. The expected 1830 * behavior is in parens: 1831 * 1832 * map_type prot 1833 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1834 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1835 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1836 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1837 * 1838 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1839 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1840 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1841 * 1842 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1843 * MAP_PRIVATE (with Enhanced PAN supported): 1844 * r: (no) no 1845 * w: (no) no 1846 * x: (yes) yes 1847 */ 1848 #define DECLARE_VM_GET_PAGE_PROT \ 1849 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1850 { \ 1851 return protection_map[vm_flags & \ 1852 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1853 } \ 1854 EXPORT_SYMBOL(vm_get_page_prot); 1855 1856 #endif /* _LINUX_PGTABLE_H */ 1857