1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT) 9 #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT) 10 11 #ifndef __ASSEMBLY__ 12 #ifdef CONFIG_MMU 13 14 #include <linux/mm_types.h> 15 #include <linux/bug.h> 16 #include <linux/errno.h> 17 #include <asm-generic/pgtable_uffd.h> 18 #include <linux/page_table_check.h> 19 20 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 22 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 23 #endif 24 25 /* 26 * On almost all architectures and configurations, 0 can be used as the 27 * upper ceiling to free_pgtables(): on many architectures it has the same 28 * effect as using TASK_SIZE. However, there is one configuration which 29 * must impose a more careful limit, to avoid freeing kernel pgtables. 30 */ 31 #ifndef USER_PGTABLES_CEILING 32 #define USER_PGTABLES_CEILING 0UL 33 #endif 34 35 /* 36 * This defines the first usable user address. Platforms 37 * can override its value with custom FIRST_USER_ADDRESS 38 * defined in their respective <asm/pgtable.h>. 39 */ 40 #ifndef FIRST_USER_ADDRESS 41 #define FIRST_USER_ADDRESS 0UL 42 #endif 43 44 /* 45 * This defines the generic helper for accessing PMD page 46 * table page. Although platforms can still override this 47 * via their respective <asm/pgtable.h>. 48 */ 49 #ifndef pmd_pgtable 50 #define pmd_pgtable(pmd) pmd_page(pmd) 51 #endif 52 53 /* 54 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 55 * 56 * The pXx_index() functions return the index of the entry in the page 57 * table page which would control the given virtual address 58 * 59 * As these functions may be used by the same code for different levels of 60 * the page table folding, they are always available, regardless of 61 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 62 * because in such cases PTRS_PER_PxD equals 1. 63 */ 64 65 static inline unsigned long pte_index(unsigned long address) 66 { 67 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 68 } 69 70 #ifndef pmd_index 71 static inline unsigned long pmd_index(unsigned long address) 72 { 73 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 74 } 75 #define pmd_index pmd_index 76 #endif 77 78 #ifndef pud_index 79 static inline unsigned long pud_index(unsigned long address) 80 { 81 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 82 } 83 #define pud_index pud_index 84 #endif 85 86 #ifndef pgd_index 87 /* Must be a compile-time constant, so implement it as a macro */ 88 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 89 #endif 90 91 #ifndef pte_offset_kernel 92 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 93 { 94 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 95 } 96 #define pte_offset_kernel pte_offset_kernel 97 #endif 98 99 #ifdef CONFIG_HIGHPTE 100 #define __pte_map(pmd, address) \ 101 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address))) 102 #define pte_unmap(pte) do { \ 103 kunmap_local((pte)); \ 104 rcu_read_unlock(); \ 105 } while (0) 106 #else 107 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address) 108 { 109 return pte_offset_kernel(pmd, address); 110 } 111 static inline void pte_unmap(pte_t *pte) 112 { 113 rcu_read_unlock(); 114 } 115 #endif 116 117 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable); 118 119 /* Find an entry in the second-level page table.. */ 120 #ifndef pmd_offset 121 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 122 { 123 return pud_pgtable(*pud) + pmd_index(address); 124 } 125 #define pmd_offset pmd_offset 126 #endif 127 128 #ifndef pud_offset 129 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 130 { 131 return p4d_pgtable(*p4d) + pud_index(address); 132 } 133 #define pud_offset pud_offset 134 #endif 135 136 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 137 { 138 return (pgd + pgd_index(address)); 139 }; 140 141 /* 142 * a shortcut to get a pgd_t in a given mm 143 */ 144 #ifndef pgd_offset 145 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 146 #endif 147 148 /* 149 * a shortcut which implies the use of the kernel's pgd, instead 150 * of a process's 151 */ 152 #ifndef pgd_offset_k 153 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 154 #endif 155 156 /* 157 * In many cases it is known that a virtual address is mapped at PMD or PTE 158 * level, so instead of traversing all the page table levels, we can get a 159 * pointer to the PMD entry in user or kernel page table or translate a virtual 160 * address to the pointer in the PTE in the kernel page tables with simple 161 * helpers. 162 */ 163 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 164 { 165 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 166 } 167 168 static inline pmd_t *pmd_off_k(unsigned long va) 169 { 170 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 171 } 172 173 static inline pte_t *virt_to_kpte(unsigned long vaddr) 174 { 175 pmd_t *pmd = pmd_off_k(vaddr); 176 177 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 178 } 179 180 #ifndef pmd_young 181 static inline int pmd_young(pmd_t pmd) 182 { 183 return 0; 184 } 185 #endif 186 187 #ifndef pmd_dirty 188 static inline int pmd_dirty(pmd_t pmd) 189 { 190 return 0; 191 } 192 #endif 193 194 /* 195 * A facility to provide lazy MMU batching. This allows PTE updates and 196 * page invalidations to be delayed until a call to leave lazy MMU mode 197 * is issued. Some architectures may benefit from doing this, and it is 198 * beneficial for both shadow and direct mode hypervisors, which may batch 199 * the PTE updates which happen during this window. Note that using this 200 * interface requires that read hazards be removed from the code. A read 201 * hazard could result in the direct mode hypervisor case, since the actual 202 * write to the page tables may not yet have taken place, so reads though 203 * a raw PTE pointer after it has been modified are not guaranteed to be 204 * up to date. This mode can only be entered and left under the protection of 205 * the page table locks for all page tables which may be modified. In the UP 206 * case, this is required so that preemption is disabled, and in the SMP case, 207 * it must synchronize the delayed page table writes properly on other CPUs. 208 */ 209 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 210 #define arch_enter_lazy_mmu_mode() do {} while (0) 211 #define arch_leave_lazy_mmu_mode() do {} while (0) 212 #define arch_flush_lazy_mmu_mode() do {} while (0) 213 #endif 214 215 #ifndef pte_next_pfn 216 #ifndef pte_advance_pfn 217 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 218 { 219 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 220 } 221 #endif 222 223 #define pte_next_pfn(pte) pte_advance_pfn(pte, 1) 224 #endif 225 226 #ifndef set_ptes 227 /** 228 * set_ptes - Map consecutive pages to a contiguous range of addresses. 229 * @mm: Address space to map the pages into. 230 * @addr: Address to map the first page at. 231 * @ptep: Page table pointer for the first entry. 232 * @pte: Page table entry for the first page. 233 * @nr: Number of pages to map. 234 * 235 * When nr==1, initial state of pte may be present or not present, and new state 236 * may be present or not present. When nr>1, initial state of all ptes must be 237 * not present, and new state must be present. 238 * 239 * May be overridden by the architecture, or the architecture can define 240 * set_pte() and PFN_PTE_SHIFT. 241 * 242 * Context: The caller holds the page table lock. The pages all belong 243 * to the same folio. The PTEs are all in the same PMD. 244 */ 245 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 246 pte_t *ptep, pte_t pte, unsigned int nr) 247 { 248 page_table_check_ptes_set(mm, ptep, pte, nr); 249 250 arch_enter_lazy_mmu_mode(); 251 for (;;) { 252 set_pte(ptep, pte); 253 if (--nr == 0) 254 break; 255 ptep++; 256 pte = pte_next_pfn(pte); 257 } 258 arch_leave_lazy_mmu_mode(); 259 } 260 #endif 261 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) 262 263 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 264 extern int ptep_set_access_flags(struct vm_area_struct *vma, 265 unsigned long address, pte_t *ptep, 266 pte_t entry, int dirty); 267 #endif 268 269 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 270 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 271 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 272 unsigned long address, pmd_t *pmdp, 273 pmd_t entry, int dirty); 274 extern int pudp_set_access_flags(struct vm_area_struct *vma, 275 unsigned long address, pud_t *pudp, 276 pud_t entry, int dirty); 277 #else 278 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 279 unsigned long address, pmd_t *pmdp, 280 pmd_t entry, int dirty) 281 { 282 BUILD_BUG(); 283 return 0; 284 } 285 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 286 unsigned long address, pud_t *pudp, 287 pud_t entry, int dirty) 288 { 289 BUILD_BUG(); 290 return 0; 291 } 292 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 293 #endif 294 295 #ifndef ptep_get 296 static inline pte_t ptep_get(pte_t *ptep) 297 { 298 return READ_ONCE(*ptep); 299 } 300 #endif 301 302 #ifndef pmdp_get 303 static inline pmd_t pmdp_get(pmd_t *pmdp) 304 { 305 return READ_ONCE(*pmdp); 306 } 307 #endif 308 309 #ifndef pudp_get 310 static inline pud_t pudp_get(pud_t *pudp) 311 { 312 return READ_ONCE(*pudp); 313 } 314 #endif 315 316 #ifndef p4dp_get 317 static inline p4d_t p4dp_get(p4d_t *p4dp) 318 { 319 return READ_ONCE(*p4dp); 320 } 321 #endif 322 323 #ifndef pgdp_get 324 static inline pgd_t pgdp_get(pgd_t *pgdp) 325 { 326 return READ_ONCE(*pgdp); 327 } 328 #endif 329 330 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 331 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 332 unsigned long address, 333 pte_t *ptep) 334 { 335 pte_t pte = ptep_get(ptep); 336 int r = 1; 337 if (!pte_young(pte)) 338 r = 0; 339 else 340 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 341 return r; 342 } 343 #endif 344 345 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 346 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 347 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 348 unsigned long address, 349 pmd_t *pmdp) 350 { 351 pmd_t pmd = *pmdp; 352 int r = 1; 353 if (!pmd_young(pmd)) 354 r = 0; 355 else 356 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 357 return r; 358 } 359 #else 360 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 361 unsigned long address, 362 pmd_t *pmdp) 363 { 364 BUILD_BUG(); 365 return 0; 366 } 367 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 368 #endif 369 370 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 371 int ptep_clear_flush_young(struct vm_area_struct *vma, 372 unsigned long address, pte_t *ptep); 373 #endif 374 375 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 376 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 377 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 378 unsigned long address, pmd_t *pmdp); 379 #else 380 /* 381 * Despite relevant to THP only, this API is called from generic rmap code 382 * under PageTransHuge(), hence needs a dummy implementation for !THP 383 */ 384 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 385 unsigned long address, pmd_t *pmdp) 386 { 387 BUILD_BUG(); 388 return 0; 389 } 390 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 391 #endif 392 393 #ifndef arch_has_hw_nonleaf_pmd_young 394 /* 395 * Return whether the accessed bit in non-leaf PMD entries is supported on the 396 * local CPU. 397 */ 398 static inline bool arch_has_hw_nonleaf_pmd_young(void) 399 { 400 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 401 } 402 #endif 403 404 #ifndef arch_has_hw_pte_young 405 /* 406 * Return whether the accessed bit is supported on the local CPU. 407 * 408 * This stub assumes accessing through an old PTE triggers a page fault. 409 * Architectures that automatically set the access bit should overwrite it. 410 */ 411 static inline bool arch_has_hw_pte_young(void) 412 { 413 return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG); 414 } 415 #endif 416 417 #ifndef arch_check_zapped_pte 418 static inline void arch_check_zapped_pte(struct vm_area_struct *vma, 419 pte_t pte) 420 { 421 } 422 #endif 423 424 #ifndef arch_check_zapped_pmd 425 static inline void arch_check_zapped_pmd(struct vm_area_struct *vma, 426 pmd_t pmd) 427 { 428 } 429 #endif 430 431 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 432 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 433 unsigned long address, 434 pte_t *ptep) 435 { 436 pte_t pte = ptep_get(ptep); 437 pte_clear(mm, address, ptep); 438 page_table_check_pte_clear(mm, pte); 439 return pte; 440 } 441 #endif 442 443 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 444 pte_t *ptep) 445 { 446 ptep_get_and_clear(mm, addr, ptep); 447 } 448 449 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH 450 /* 451 * For walking the pagetables without holding any locks. Some architectures 452 * (eg x86-32 PAE) cannot load the entries atomically without using expensive 453 * instructions. We are guaranteed that a PTE will only either go from not 454 * present to present, or present to not present -- it will not switch to a 455 * completely different present page without a TLB flush inbetween; which we 456 * are blocking by holding interrupts off. 457 * 458 * Setting ptes from not present to present goes: 459 * 460 * ptep->pte_high = h; 461 * smp_wmb(); 462 * ptep->pte_low = l; 463 * 464 * And present to not present goes: 465 * 466 * ptep->pte_low = 0; 467 * smp_wmb(); 468 * ptep->pte_high = 0; 469 * 470 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 471 * We load pte_high *after* loading pte_low, which ensures we don't see an older 472 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 473 * picked up a changed pte high. We might have gotten rubbish values from 474 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 475 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 476 * operates on present ptes we're safe. 477 */ 478 static inline pte_t ptep_get_lockless(pte_t *ptep) 479 { 480 pte_t pte; 481 482 do { 483 pte.pte_low = ptep->pte_low; 484 smp_rmb(); 485 pte.pte_high = ptep->pte_high; 486 smp_rmb(); 487 } while (unlikely(pte.pte_low != ptep->pte_low)); 488 489 return pte; 490 } 491 #define ptep_get_lockless ptep_get_lockless 492 493 #if CONFIG_PGTABLE_LEVELS > 2 494 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 495 { 496 pmd_t pmd; 497 498 do { 499 pmd.pmd_low = pmdp->pmd_low; 500 smp_rmb(); 501 pmd.pmd_high = pmdp->pmd_high; 502 smp_rmb(); 503 } while (unlikely(pmd.pmd_low != pmdp->pmd_low)); 504 505 return pmd; 506 } 507 #define pmdp_get_lockless pmdp_get_lockless 508 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one() 509 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 510 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */ 511 512 /* 513 * We require that the PTE can be read atomically. 514 */ 515 #ifndef ptep_get_lockless 516 static inline pte_t ptep_get_lockless(pte_t *ptep) 517 { 518 return ptep_get(ptep); 519 } 520 #endif 521 522 #ifndef pmdp_get_lockless 523 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 524 { 525 return pmdp_get(pmdp); 526 } 527 static inline void pmdp_get_lockless_sync(void) 528 { 529 } 530 #endif 531 532 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 533 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 534 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 535 unsigned long address, 536 pmd_t *pmdp) 537 { 538 pmd_t pmd = *pmdp; 539 540 pmd_clear(pmdp); 541 page_table_check_pmd_clear(mm, pmd); 542 543 return pmd; 544 } 545 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 546 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 547 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 548 unsigned long address, 549 pud_t *pudp) 550 { 551 pud_t pud = *pudp; 552 553 pud_clear(pudp); 554 page_table_check_pud_clear(mm, pud); 555 556 return pud; 557 } 558 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 559 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 560 561 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 562 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 563 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 564 unsigned long address, pmd_t *pmdp, 565 int full) 566 { 567 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 568 } 569 #endif 570 571 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 572 static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 573 unsigned long address, pud_t *pudp, 574 int full) 575 { 576 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp); 577 } 578 #endif 579 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 580 581 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 582 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 583 unsigned long address, pte_t *ptep, 584 int full) 585 { 586 return ptep_get_and_clear(mm, address, ptep); 587 } 588 #endif 589 590 #ifndef get_and_clear_full_ptes 591 /** 592 * get_and_clear_full_ptes - Clear present PTEs that map consecutive pages of 593 * the same folio, collecting dirty/accessed bits. 594 * @mm: Address space the pages are mapped into. 595 * @addr: Address the first page is mapped at. 596 * @ptep: Page table pointer for the first entry. 597 * @nr: Number of entries to clear. 598 * @full: Whether we are clearing a full mm. 599 * 600 * May be overridden by the architecture; otherwise, implemented as a simple 601 * loop over ptep_get_and_clear_full(), merging dirty/accessed bits into the 602 * returned PTE. 603 * 604 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 605 * some PTEs might be write-protected. 606 * 607 * Context: The caller holds the page table lock. The PTEs map consecutive 608 * pages that belong to the same folio. The PTEs are all in the same PMD. 609 */ 610 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 611 unsigned long addr, pte_t *ptep, unsigned int nr, int full) 612 { 613 pte_t pte, tmp_pte; 614 615 pte = ptep_get_and_clear_full(mm, addr, ptep, full); 616 while (--nr) { 617 ptep++; 618 addr += PAGE_SIZE; 619 tmp_pte = ptep_get_and_clear_full(mm, addr, ptep, full); 620 if (pte_dirty(tmp_pte)) 621 pte = pte_mkdirty(pte); 622 if (pte_young(tmp_pte)) 623 pte = pte_mkyoung(pte); 624 } 625 return pte; 626 } 627 #endif 628 629 #ifndef clear_full_ptes 630 /** 631 * clear_full_ptes - Clear present PTEs that map consecutive pages of the same 632 * folio. 633 * @mm: Address space the pages are mapped into. 634 * @addr: Address the first page is mapped at. 635 * @ptep: Page table pointer for the first entry. 636 * @nr: Number of entries to clear. 637 * @full: Whether we are clearing a full mm. 638 * 639 * May be overridden by the architecture; otherwise, implemented as a simple 640 * loop over ptep_get_and_clear_full(). 641 * 642 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 643 * some PTEs might be write-protected. 644 * 645 * Context: The caller holds the page table lock. The PTEs map consecutive 646 * pages that belong to the same folio. The PTEs are all in the same PMD. 647 */ 648 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 649 pte_t *ptep, unsigned int nr, int full) 650 { 651 for (;;) { 652 ptep_get_and_clear_full(mm, addr, ptep, full); 653 if (--nr == 0) 654 break; 655 ptep++; 656 addr += PAGE_SIZE; 657 } 658 } 659 #endif 660 661 /* 662 * If two threads concurrently fault at the same page, the thread that 663 * won the race updates the PTE and its local TLB/Cache. The other thread 664 * gives up, simply does nothing, and continues; on architectures where 665 * software can update TLB, local TLB can be updated here to avoid next page 666 * fault. This function updates TLB only, do nothing with cache or others. 667 * It is the difference with function update_mmu_cache. 668 */ 669 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 670 static inline void update_mmu_tlb(struct vm_area_struct *vma, 671 unsigned long address, pte_t *ptep) 672 { 673 } 674 #define __HAVE_ARCH_UPDATE_MMU_TLB 675 #endif 676 677 /* 678 * Some architectures may be able to avoid expensive synchronization 679 * primitives when modifications are made to PTE's which are already 680 * not present, or in the process of an address space destruction. 681 */ 682 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 683 static inline void pte_clear_not_present_full(struct mm_struct *mm, 684 unsigned long address, 685 pte_t *ptep, 686 int full) 687 { 688 pte_clear(mm, address, ptep); 689 } 690 #endif 691 692 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 693 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 694 unsigned long address, 695 pte_t *ptep); 696 #endif 697 698 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 699 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 700 unsigned long address, 701 pmd_t *pmdp); 702 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 703 unsigned long address, 704 pud_t *pudp); 705 #endif 706 707 #ifndef pte_mkwrite 708 static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma) 709 { 710 return pte_mkwrite_novma(pte); 711 } 712 #endif 713 714 #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite) 715 static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma) 716 { 717 return pmd_mkwrite_novma(pmd); 718 } 719 #endif 720 721 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 722 struct mm_struct; 723 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 724 { 725 pte_t old_pte = ptep_get(ptep); 726 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 727 } 728 #endif 729 730 #ifndef wrprotect_ptes 731 /** 732 * wrprotect_ptes - Write-protect PTEs that map consecutive pages of the same 733 * folio. 734 * @mm: Address space the pages are mapped into. 735 * @addr: Address the first page is mapped at. 736 * @ptep: Page table pointer for the first entry. 737 * @nr: Number of entries to write-protect. 738 * 739 * May be overridden by the architecture; otherwise, implemented as a simple 740 * loop over ptep_set_wrprotect(). 741 * 742 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 743 * some PTEs might be write-protected. 744 * 745 * Context: The caller holds the page table lock. The PTEs map consecutive 746 * pages that belong to the same folio. The PTEs are all in the same PMD. 747 */ 748 static inline void wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 749 pte_t *ptep, unsigned int nr) 750 { 751 for (;;) { 752 ptep_set_wrprotect(mm, addr, ptep); 753 if (--nr == 0) 754 break; 755 ptep++; 756 addr += PAGE_SIZE; 757 } 758 } 759 #endif 760 761 /* 762 * On some architectures hardware does not set page access bit when accessing 763 * memory page, it is responsibility of software setting this bit. It brings 764 * out extra page fault penalty to track page access bit. For optimization page 765 * access bit can be set during all page fault flow on these arches. 766 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 767 * where software maintains page access bit. 768 */ 769 #ifndef pte_sw_mkyoung 770 static inline pte_t pte_sw_mkyoung(pte_t pte) 771 { 772 return pte; 773 } 774 #define pte_sw_mkyoung pte_sw_mkyoung 775 #endif 776 777 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 778 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 779 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 780 unsigned long address, pmd_t *pmdp) 781 { 782 pmd_t old_pmd = *pmdp; 783 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 784 } 785 #else 786 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 787 unsigned long address, pmd_t *pmdp) 788 { 789 BUILD_BUG(); 790 } 791 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 792 #endif 793 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 794 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 795 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 796 static inline void pudp_set_wrprotect(struct mm_struct *mm, 797 unsigned long address, pud_t *pudp) 798 { 799 pud_t old_pud = *pudp; 800 801 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 802 } 803 #else 804 static inline void pudp_set_wrprotect(struct mm_struct *mm, 805 unsigned long address, pud_t *pudp) 806 { 807 BUILD_BUG(); 808 } 809 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 810 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 811 #endif 812 813 #ifndef pmdp_collapse_flush 814 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 815 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 816 unsigned long address, pmd_t *pmdp); 817 #else 818 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 819 unsigned long address, 820 pmd_t *pmdp) 821 { 822 BUILD_BUG(); 823 return *pmdp; 824 } 825 #define pmdp_collapse_flush pmdp_collapse_flush 826 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 827 #endif 828 829 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 830 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 831 pgtable_t pgtable); 832 #endif 833 834 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 835 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 836 #endif 837 838 #ifndef arch_needs_pgtable_deposit 839 #define arch_needs_pgtable_deposit() (false) 840 #endif 841 842 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 843 /* 844 * This is an implementation of pmdp_establish() that is only suitable for an 845 * architecture that doesn't have hardware dirty/accessed bits. In this case we 846 * can't race with CPU which sets these bits and non-atomic approach is fine. 847 */ 848 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 849 unsigned long address, pmd_t *pmdp, pmd_t pmd) 850 { 851 pmd_t old_pmd = *pmdp; 852 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 853 return old_pmd; 854 } 855 #endif 856 857 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 858 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 859 pmd_t *pmdp); 860 #endif 861 862 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 863 864 /* 865 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 866 * hugepage mapping in the page tables. This function is similar to 867 * pmdp_invalidate(), but should only be used if the access and dirty bits would 868 * not be cleared by the software in the new PMD value. The function ensures 869 * that hardware changes of the access and dirty bits updates would not be lost. 870 * 871 * Doing so can allow in certain architectures to avoid a TLB flush in most 872 * cases. Yet, another TLB flush might be necessary later if the PMD update 873 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 874 * even when a TLB flush is needed because of the update, the caller may be able 875 * to batch these TLB flushing operations, so fewer TLB flush operations are 876 * needed. 877 */ 878 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 879 unsigned long address, pmd_t *pmdp); 880 #endif 881 882 #ifndef __HAVE_ARCH_PTE_SAME 883 static inline int pte_same(pte_t pte_a, pte_t pte_b) 884 { 885 return pte_val(pte_a) == pte_val(pte_b); 886 } 887 #endif 888 889 #ifndef __HAVE_ARCH_PTE_UNUSED 890 /* 891 * Some architectures provide facilities to virtualization guests 892 * so that they can flag allocated pages as unused. This allows the 893 * host to transparently reclaim unused pages. This function returns 894 * whether the pte's page is unused. 895 */ 896 static inline int pte_unused(pte_t pte) 897 { 898 return 0; 899 } 900 #endif 901 902 #ifndef pte_access_permitted 903 #define pte_access_permitted(pte, write) \ 904 (pte_present(pte) && (!(write) || pte_write(pte))) 905 #endif 906 907 #ifndef pmd_access_permitted 908 #define pmd_access_permitted(pmd, write) \ 909 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 910 #endif 911 912 #ifndef pud_access_permitted 913 #define pud_access_permitted(pud, write) \ 914 (pud_present(pud) && (!(write) || pud_write(pud))) 915 #endif 916 917 #ifndef p4d_access_permitted 918 #define p4d_access_permitted(p4d, write) \ 919 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 920 #endif 921 922 #ifndef pgd_access_permitted 923 #define pgd_access_permitted(pgd, write) \ 924 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 925 #endif 926 927 #ifndef __HAVE_ARCH_PMD_SAME 928 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 929 { 930 return pmd_val(pmd_a) == pmd_val(pmd_b); 931 } 932 #endif 933 934 #ifndef pud_same 935 static inline int pud_same(pud_t pud_a, pud_t pud_b) 936 { 937 return pud_val(pud_a) == pud_val(pud_b); 938 } 939 #define pud_same pud_same 940 #endif 941 942 #ifndef __HAVE_ARCH_P4D_SAME 943 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 944 { 945 return p4d_val(p4d_a) == p4d_val(p4d_b); 946 } 947 #endif 948 949 #ifndef __HAVE_ARCH_PGD_SAME 950 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 951 { 952 return pgd_val(pgd_a) == pgd_val(pgd_b); 953 } 954 #endif 955 956 /* 957 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 958 * TLB flush will be required as a result of the "set". For example, use 959 * in scenarios where it is known ahead of time that the routine is 960 * setting non-present entries, or re-setting an existing entry to the 961 * same value. Otherwise, use the typical "set" helpers and flush the 962 * TLB. 963 */ 964 #define set_pte_safe(ptep, pte) \ 965 ({ \ 966 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 967 set_pte(ptep, pte); \ 968 }) 969 970 #define set_pmd_safe(pmdp, pmd) \ 971 ({ \ 972 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 973 set_pmd(pmdp, pmd); \ 974 }) 975 976 #define set_pud_safe(pudp, pud) \ 977 ({ \ 978 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 979 set_pud(pudp, pud); \ 980 }) 981 982 #define set_p4d_safe(p4dp, p4d) \ 983 ({ \ 984 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 985 set_p4d(p4dp, p4d); \ 986 }) 987 988 #define set_pgd_safe(pgdp, pgd) \ 989 ({ \ 990 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 991 set_pgd(pgdp, pgd); \ 992 }) 993 994 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 995 /* 996 * Some architectures support metadata associated with a page. When a 997 * page is being swapped out, this metadata must be saved so it can be 998 * restored when the page is swapped back in. SPARC M7 and newer 999 * processors support an ADI (Application Data Integrity) tag for the 1000 * page as metadata for the page. arch_do_swap_page() can restore this 1001 * metadata when a page is swapped back in. 1002 */ 1003 static inline void arch_do_swap_page(struct mm_struct *mm, 1004 struct vm_area_struct *vma, 1005 unsigned long addr, 1006 pte_t pte, pte_t oldpte) 1007 { 1008 1009 } 1010 #endif 1011 1012 #ifndef __HAVE_ARCH_UNMAP_ONE 1013 /* 1014 * Some architectures support metadata associated with a page. When a 1015 * page is being swapped out, this metadata must be saved so it can be 1016 * restored when the page is swapped back in. SPARC M7 and newer 1017 * processors support an ADI (Application Data Integrity) tag for the 1018 * page as metadata for the page. arch_unmap_one() can save this 1019 * metadata on a swap-out of a page. 1020 */ 1021 static inline int arch_unmap_one(struct mm_struct *mm, 1022 struct vm_area_struct *vma, 1023 unsigned long addr, 1024 pte_t orig_pte) 1025 { 1026 return 0; 1027 } 1028 #endif 1029 1030 /* 1031 * Allow architectures to preserve additional metadata associated with 1032 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 1033 * prototypes must be defined in the arch-specific asm/pgtable.h file. 1034 */ 1035 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 1036 static inline int arch_prepare_to_swap(struct page *page) 1037 { 1038 return 0; 1039 } 1040 #endif 1041 1042 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 1043 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1044 { 1045 } 1046 1047 static inline void arch_swap_invalidate_area(int type) 1048 { 1049 } 1050 #endif 1051 1052 #ifndef __HAVE_ARCH_SWAP_RESTORE 1053 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1054 { 1055 } 1056 #endif 1057 1058 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 1059 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 1060 #endif 1061 1062 #ifndef __HAVE_ARCH_MOVE_PTE 1063 #define move_pte(pte, prot, old_addr, new_addr) (pte) 1064 #endif 1065 1066 #ifndef pte_accessible 1067 # define pte_accessible(mm, pte) ((void)(pte), 1) 1068 #endif 1069 1070 #ifndef flush_tlb_fix_spurious_fault 1071 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address) 1072 #endif 1073 1074 /* 1075 * When walking page tables, get the address of the next boundary, 1076 * or the end address of the range if that comes earlier. Although no 1077 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 1078 */ 1079 1080 #define pgd_addr_end(addr, end) \ 1081 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 1082 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1083 }) 1084 1085 #ifndef p4d_addr_end 1086 #define p4d_addr_end(addr, end) \ 1087 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 1088 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1089 }) 1090 #endif 1091 1092 #ifndef pud_addr_end 1093 #define pud_addr_end(addr, end) \ 1094 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 1095 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1096 }) 1097 #endif 1098 1099 #ifndef pmd_addr_end 1100 #define pmd_addr_end(addr, end) \ 1101 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 1102 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1103 }) 1104 #endif 1105 1106 /* 1107 * When walking page tables, we usually want to skip any p?d_none entries; 1108 * and any p?d_bad entries - reporting the error before resetting to none. 1109 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 1110 */ 1111 void pgd_clear_bad(pgd_t *); 1112 1113 #ifndef __PAGETABLE_P4D_FOLDED 1114 void p4d_clear_bad(p4d_t *); 1115 #else 1116 #define p4d_clear_bad(p4d) do { } while (0) 1117 #endif 1118 1119 #ifndef __PAGETABLE_PUD_FOLDED 1120 void pud_clear_bad(pud_t *); 1121 #else 1122 #define pud_clear_bad(p4d) do { } while (0) 1123 #endif 1124 1125 void pmd_clear_bad(pmd_t *); 1126 1127 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 1128 { 1129 if (pgd_none(*pgd)) 1130 return 1; 1131 if (unlikely(pgd_bad(*pgd))) { 1132 pgd_clear_bad(pgd); 1133 return 1; 1134 } 1135 return 0; 1136 } 1137 1138 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 1139 { 1140 if (p4d_none(*p4d)) 1141 return 1; 1142 if (unlikely(p4d_bad(*p4d))) { 1143 p4d_clear_bad(p4d); 1144 return 1; 1145 } 1146 return 0; 1147 } 1148 1149 static inline int pud_none_or_clear_bad(pud_t *pud) 1150 { 1151 if (pud_none(*pud)) 1152 return 1; 1153 if (unlikely(pud_bad(*pud))) { 1154 pud_clear_bad(pud); 1155 return 1; 1156 } 1157 return 0; 1158 } 1159 1160 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 1161 { 1162 if (pmd_none(*pmd)) 1163 return 1; 1164 if (unlikely(pmd_bad(*pmd))) { 1165 pmd_clear_bad(pmd); 1166 return 1; 1167 } 1168 return 0; 1169 } 1170 1171 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 1172 unsigned long addr, 1173 pte_t *ptep) 1174 { 1175 /* 1176 * Get the current pte state, but zero it out to make it 1177 * non-present, preventing the hardware from asynchronously 1178 * updating it. 1179 */ 1180 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 1181 } 1182 1183 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 1184 unsigned long addr, 1185 pte_t *ptep, pte_t pte) 1186 { 1187 /* 1188 * The pte is non-present, so there's no hardware state to 1189 * preserve. 1190 */ 1191 set_pte_at(vma->vm_mm, addr, ptep, pte); 1192 } 1193 1194 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1195 /* 1196 * Start a pte protection read-modify-write transaction, which 1197 * protects against asynchronous hardware modifications to the pte. 1198 * The intention is not to prevent the hardware from making pte 1199 * updates, but to prevent any updates it may make from being lost. 1200 * 1201 * This does not protect against other software modifications of the 1202 * pte; the appropriate pte lock must be held over the transaction. 1203 * 1204 * Note that this interface is intended to be batchable, meaning that 1205 * ptep_modify_prot_commit may not actually update the pte, but merely 1206 * queue the update to be done at some later time. The update must be 1207 * actually committed before the pte lock is released, however. 1208 */ 1209 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1210 unsigned long addr, 1211 pte_t *ptep) 1212 { 1213 return __ptep_modify_prot_start(vma, addr, ptep); 1214 } 1215 1216 /* 1217 * Commit an update to a pte, leaving any hardware-controlled bits in 1218 * the PTE unmodified. 1219 */ 1220 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 1221 unsigned long addr, 1222 pte_t *ptep, pte_t old_pte, pte_t pte) 1223 { 1224 __ptep_modify_prot_commit(vma, addr, ptep, pte); 1225 } 1226 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 1227 #endif /* CONFIG_MMU */ 1228 1229 /* 1230 * No-op macros that just return the current protection value. Defined here 1231 * because these macros can be used even if CONFIG_MMU is not defined. 1232 */ 1233 1234 #ifndef pgprot_nx 1235 #define pgprot_nx(prot) (prot) 1236 #endif 1237 1238 #ifndef pgprot_noncached 1239 #define pgprot_noncached(prot) (prot) 1240 #endif 1241 1242 #ifndef pgprot_writecombine 1243 #define pgprot_writecombine pgprot_noncached 1244 #endif 1245 1246 #ifndef pgprot_writethrough 1247 #define pgprot_writethrough pgprot_noncached 1248 #endif 1249 1250 #ifndef pgprot_device 1251 #define pgprot_device pgprot_noncached 1252 #endif 1253 1254 #ifndef pgprot_mhp 1255 #define pgprot_mhp(prot) (prot) 1256 #endif 1257 1258 #ifdef CONFIG_MMU 1259 #ifndef pgprot_modify 1260 #define pgprot_modify pgprot_modify 1261 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 1262 { 1263 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 1264 newprot = pgprot_noncached(newprot); 1265 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 1266 newprot = pgprot_writecombine(newprot); 1267 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 1268 newprot = pgprot_device(newprot); 1269 return newprot; 1270 } 1271 #endif 1272 #endif /* CONFIG_MMU */ 1273 1274 #ifndef pgprot_encrypted 1275 #define pgprot_encrypted(prot) (prot) 1276 #endif 1277 1278 #ifndef pgprot_decrypted 1279 #define pgprot_decrypted(prot) (prot) 1280 #endif 1281 1282 /* 1283 * A facility to provide batching of the reload of page tables and 1284 * other process state with the actual context switch code for 1285 * paravirtualized guests. By convention, only one of the batched 1286 * update (lazy) modes (CPU, MMU) should be active at any given time, 1287 * entry should never be nested, and entry and exits should always be 1288 * paired. This is for sanity of maintaining and reasoning about the 1289 * kernel code. In this case, the exit (end of the context switch) is 1290 * in architecture-specific code, and so doesn't need a generic 1291 * definition. 1292 */ 1293 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1294 #define arch_start_context_switch(prev) do {} while (0) 1295 #endif 1296 1297 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1298 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1299 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1300 { 1301 return pmd; 1302 } 1303 1304 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1305 { 1306 return 0; 1307 } 1308 1309 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1310 { 1311 return pmd; 1312 } 1313 #endif 1314 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1315 static inline int pte_soft_dirty(pte_t pte) 1316 { 1317 return 0; 1318 } 1319 1320 static inline int pmd_soft_dirty(pmd_t pmd) 1321 { 1322 return 0; 1323 } 1324 1325 static inline pte_t pte_mksoft_dirty(pte_t pte) 1326 { 1327 return pte; 1328 } 1329 1330 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1331 { 1332 return pmd; 1333 } 1334 1335 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1336 { 1337 return pte; 1338 } 1339 1340 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1341 { 1342 return pmd; 1343 } 1344 1345 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1346 { 1347 return pte; 1348 } 1349 1350 static inline int pte_swp_soft_dirty(pte_t pte) 1351 { 1352 return 0; 1353 } 1354 1355 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1356 { 1357 return pte; 1358 } 1359 1360 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1361 { 1362 return pmd; 1363 } 1364 1365 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1366 { 1367 return 0; 1368 } 1369 1370 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1371 { 1372 return pmd; 1373 } 1374 #endif 1375 1376 #ifndef __HAVE_PFNMAP_TRACKING 1377 /* 1378 * Interfaces that can be used by architecture code to keep track of 1379 * memory type of pfn mappings specified by the remap_pfn_range, 1380 * vmf_insert_pfn. 1381 */ 1382 1383 /* 1384 * track_pfn_remap is called when a _new_ pfn mapping is being established 1385 * by remap_pfn_range() for physical range indicated by pfn and size. 1386 */ 1387 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1388 unsigned long pfn, unsigned long addr, 1389 unsigned long size) 1390 { 1391 return 0; 1392 } 1393 1394 /* 1395 * track_pfn_insert is called when a _new_ single pfn is established 1396 * by vmf_insert_pfn(). 1397 */ 1398 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1399 pfn_t pfn) 1400 { 1401 } 1402 1403 /* 1404 * track_pfn_copy is called when vma that is covering the pfnmap gets 1405 * copied through copy_page_range(). 1406 */ 1407 static inline int track_pfn_copy(struct vm_area_struct *vma) 1408 { 1409 return 0; 1410 } 1411 1412 /* 1413 * untrack_pfn is called while unmapping a pfnmap for a region. 1414 * untrack can be called for a specific region indicated by pfn and size or 1415 * can be for the entire vma (in which case pfn, size are zero). 1416 */ 1417 static inline void untrack_pfn(struct vm_area_struct *vma, 1418 unsigned long pfn, unsigned long size, 1419 bool mm_wr_locked) 1420 { 1421 } 1422 1423 /* 1424 * untrack_pfn_clear is called while mremapping a pfnmap for a new region 1425 * or fails to copy pgtable during duplicate vm area. 1426 */ 1427 static inline void untrack_pfn_clear(struct vm_area_struct *vma) 1428 { 1429 } 1430 #else 1431 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1432 unsigned long pfn, unsigned long addr, 1433 unsigned long size); 1434 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1435 pfn_t pfn); 1436 extern int track_pfn_copy(struct vm_area_struct *vma); 1437 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1438 unsigned long size, bool mm_wr_locked); 1439 extern void untrack_pfn_clear(struct vm_area_struct *vma); 1440 #endif 1441 1442 #ifdef CONFIG_MMU 1443 #ifdef __HAVE_COLOR_ZERO_PAGE 1444 static inline int is_zero_pfn(unsigned long pfn) 1445 { 1446 extern unsigned long zero_pfn; 1447 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1448 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1449 } 1450 1451 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1452 1453 #else 1454 static inline int is_zero_pfn(unsigned long pfn) 1455 { 1456 extern unsigned long zero_pfn; 1457 return pfn == zero_pfn; 1458 } 1459 1460 static inline unsigned long my_zero_pfn(unsigned long addr) 1461 { 1462 extern unsigned long zero_pfn; 1463 return zero_pfn; 1464 } 1465 #endif 1466 #else 1467 static inline int is_zero_pfn(unsigned long pfn) 1468 { 1469 return 0; 1470 } 1471 1472 static inline unsigned long my_zero_pfn(unsigned long addr) 1473 { 1474 return 0; 1475 } 1476 #endif /* CONFIG_MMU */ 1477 1478 #ifdef CONFIG_MMU 1479 1480 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1481 static inline int pmd_trans_huge(pmd_t pmd) 1482 { 1483 return 0; 1484 } 1485 #ifndef pmd_write 1486 static inline int pmd_write(pmd_t pmd) 1487 { 1488 BUG(); 1489 return 0; 1490 } 1491 #endif /* pmd_write */ 1492 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1493 1494 #ifndef pud_write 1495 static inline int pud_write(pud_t pud) 1496 { 1497 BUG(); 1498 return 0; 1499 } 1500 #endif /* pud_write */ 1501 1502 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1503 static inline int pmd_devmap(pmd_t pmd) 1504 { 1505 return 0; 1506 } 1507 static inline int pud_devmap(pud_t pud) 1508 { 1509 return 0; 1510 } 1511 static inline int pgd_devmap(pgd_t pgd) 1512 { 1513 return 0; 1514 } 1515 #endif 1516 1517 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1518 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1519 static inline int pud_trans_huge(pud_t pud) 1520 { 1521 return 0; 1522 } 1523 #endif 1524 1525 static inline int pud_trans_unstable(pud_t *pud) 1526 { 1527 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1528 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1529 pud_t pudval = READ_ONCE(*pud); 1530 1531 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1532 return 1; 1533 if (unlikely(pud_bad(pudval))) { 1534 pud_clear_bad(pud); 1535 return 1; 1536 } 1537 #endif 1538 return 0; 1539 } 1540 1541 #ifndef CONFIG_NUMA_BALANCING 1542 /* 1543 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is 1544 * perfectly valid to indicate "no" in that case, which is why our default 1545 * implementation defaults to "always no". 1546 * 1547 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE 1548 * page protection due to NUMA hinting. NUMA hinting faults only apply in 1549 * accessible VMAs. 1550 * 1551 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault, 1552 * looking at the VMA accessibility is sufficient. 1553 */ 1554 static inline int pte_protnone(pte_t pte) 1555 { 1556 return 0; 1557 } 1558 1559 static inline int pmd_protnone(pmd_t pmd) 1560 { 1561 return 0; 1562 } 1563 #endif /* CONFIG_NUMA_BALANCING */ 1564 1565 #endif /* CONFIG_MMU */ 1566 1567 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1568 1569 #ifndef __PAGETABLE_P4D_FOLDED 1570 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1571 void p4d_clear_huge(p4d_t *p4d); 1572 #else 1573 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1574 { 1575 return 0; 1576 } 1577 static inline void p4d_clear_huge(p4d_t *p4d) { } 1578 #endif /* !__PAGETABLE_P4D_FOLDED */ 1579 1580 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1581 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1582 int pud_clear_huge(pud_t *pud); 1583 int pmd_clear_huge(pmd_t *pmd); 1584 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1585 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1586 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1587 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1588 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1589 { 1590 return 0; 1591 } 1592 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1593 { 1594 return 0; 1595 } 1596 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1597 { 1598 return 0; 1599 } 1600 static inline void p4d_clear_huge(p4d_t *p4d) { } 1601 static inline int pud_clear_huge(pud_t *pud) 1602 { 1603 return 0; 1604 } 1605 static inline int pmd_clear_huge(pmd_t *pmd) 1606 { 1607 return 0; 1608 } 1609 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1610 { 1611 return 0; 1612 } 1613 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1614 { 1615 return 0; 1616 } 1617 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1618 { 1619 return 0; 1620 } 1621 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1622 1623 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1624 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1625 /* 1626 * ARCHes with special requirements for evicting THP backing TLB entries can 1627 * implement this. Otherwise also, it can help optimize normal TLB flush in 1628 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1629 * entire TLB if flush span is greater than a threshold, which will 1630 * likely be true for a single huge page. Thus a single THP flush will 1631 * invalidate the entire TLB which is not desirable. 1632 * e.g. see arch/arc: flush_pmd_tlb_range 1633 */ 1634 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1635 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1636 #else 1637 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1638 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1639 #endif 1640 #endif 1641 1642 struct file; 1643 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1644 unsigned long size, pgprot_t *vma_prot); 1645 1646 #ifndef CONFIG_X86_ESPFIX64 1647 static inline void init_espfix_bsp(void) { } 1648 #endif 1649 1650 extern void __init pgtable_cache_init(void); 1651 1652 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1653 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1654 { 1655 return true; 1656 } 1657 1658 static inline bool arch_has_pfn_modify_check(void) 1659 { 1660 return false; 1661 } 1662 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1663 1664 /* 1665 * Architecture PAGE_KERNEL_* fallbacks 1666 * 1667 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1668 * because they really don't support them, or the port needs to be updated to 1669 * reflect the required functionality. Below are a set of relatively safe 1670 * fallbacks, as best effort, which we can count on in lieu of the architectures 1671 * not defining them on their own yet. 1672 */ 1673 1674 #ifndef PAGE_KERNEL_RO 1675 # define PAGE_KERNEL_RO PAGE_KERNEL 1676 #endif 1677 1678 #ifndef PAGE_KERNEL_EXEC 1679 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1680 #endif 1681 1682 /* 1683 * Page Table Modification bits for pgtbl_mod_mask. 1684 * 1685 * These are used by the p?d_alloc_track*() set of functions an in the generic 1686 * vmalloc/ioremap code to track at which page-table levels entries have been 1687 * modified. Based on that the code can better decide when vmalloc and ioremap 1688 * mapping changes need to be synchronized to other page-tables in the system. 1689 */ 1690 #define __PGTBL_PGD_MODIFIED 0 1691 #define __PGTBL_P4D_MODIFIED 1 1692 #define __PGTBL_PUD_MODIFIED 2 1693 #define __PGTBL_PMD_MODIFIED 3 1694 #define __PGTBL_PTE_MODIFIED 4 1695 1696 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1697 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1698 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1699 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1700 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1701 1702 /* Page-Table Modification Mask */ 1703 typedef unsigned int pgtbl_mod_mask; 1704 1705 #endif /* !__ASSEMBLY__ */ 1706 1707 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1708 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1709 /* 1710 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1711 * with physical address space extension, but falls back to 1712 * BITS_PER_LONG otherwise. 1713 */ 1714 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1715 #else 1716 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1717 #endif 1718 #endif 1719 1720 #ifndef has_transparent_hugepage 1721 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1722 #endif 1723 1724 #ifndef has_transparent_pud_hugepage 1725 #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1726 #endif 1727 /* 1728 * On some architectures it depends on the mm if the p4d/pud or pmd 1729 * layer of the page table hierarchy is folded or not. 1730 */ 1731 #ifndef mm_p4d_folded 1732 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1733 #endif 1734 1735 #ifndef mm_pud_folded 1736 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1737 #endif 1738 1739 #ifndef mm_pmd_folded 1740 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1741 #endif 1742 1743 #ifndef p4d_offset_lockless 1744 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1745 #endif 1746 #ifndef pud_offset_lockless 1747 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1748 #endif 1749 #ifndef pmd_offset_lockless 1750 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1751 #endif 1752 1753 /* 1754 * p?d_leaf() - true if this entry is a final mapping to a physical address. 1755 * This differs from p?d_huge() by the fact that they are always available (if 1756 * the architecture supports large pages at the appropriate level) even 1757 * if CONFIG_HUGETLB_PAGE is not defined. 1758 * Only meaningful when called on a valid entry. 1759 */ 1760 #ifndef pgd_leaf 1761 #define pgd_leaf(x) 0 1762 #endif 1763 #ifndef p4d_leaf 1764 #define p4d_leaf(x) 0 1765 #endif 1766 #ifndef pud_leaf 1767 #define pud_leaf(x) 0 1768 #endif 1769 #ifndef pmd_leaf 1770 #define pmd_leaf(x) 0 1771 #endif 1772 1773 #ifndef pgd_leaf_size 1774 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1775 #endif 1776 #ifndef p4d_leaf_size 1777 #define p4d_leaf_size(x) P4D_SIZE 1778 #endif 1779 #ifndef pud_leaf_size 1780 #define pud_leaf_size(x) PUD_SIZE 1781 #endif 1782 #ifndef pmd_leaf_size 1783 #define pmd_leaf_size(x) PMD_SIZE 1784 #endif 1785 #ifndef pte_leaf_size 1786 #define pte_leaf_size(x) PAGE_SIZE 1787 #endif 1788 1789 /* 1790 * Some architectures have MMUs that are configurable or selectable at boot 1791 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1792 * helps to have a static maximum value. 1793 */ 1794 1795 #ifndef MAX_PTRS_PER_PTE 1796 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1797 #endif 1798 1799 #ifndef MAX_PTRS_PER_PMD 1800 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1801 #endif 1802 1803 #ifndef MAX_PTRS_PER_PUD 1804 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1805 #endif 1806 1807 #ifndef MAX_PTRS_PER_P4D 1808 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1809 #endif 1810 1811 /* description of effects of mapping type and prot in current implementation. 1812 * this is due to the limited x86 page protection hardware. The expected 1813 * behavior is in parens: 1814 * 1815 * map_type prot 1816 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1817 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1818 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1819 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1820 * 1821 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1822 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1823 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1824 * 1825 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1826 * MAP_PRIVATE (with Enhanced PAN supported): 1827 * r: (no) no 1828 * w: (no) no 1829 * x: (yes) yes 1830 */ 1831 #define DECLARE_VM_GET_PAGE_PROT \ 1832 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1833 { \ 1834 return protection_map[vm_flags & \ 1835 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1836 } \ 1837 EXPORT_SYMBOL(vm_get_page_prot); 1838 1839 #endif /* _LINUX_PGTABLE_H */ 1840