1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #ifndef __ASSEMBLY__ 9 #ifdef CONFIG_MMU 10 11 #include <linux/mm_types.h> 12 #include <linux/bug.h> 13 #include <linux/errno.h> 14 #include <asm-generic/pgtable_uffd.h> 15 16 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 17 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 18 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 19 #endif 20 21 /* 22 * On almost all architectures and configurations, 0 can be used as the 23 * upper ceiling to free_pgtables(): on many architectures it has the same 24 * effect as using TASK_SIZE. However, there is one configuration which 25 * must impose a more careful limit, to avoid freeing kernel pgtables. 26 */ 27 #ifndef USER_PGTABLES_CEILING 28 #define USER_PGTABLES_CEILING 0UL 29 #endif 30 31 /* 32 * This defines the first usable user address. Platforms 33 * can override its value with custom FIRST_USER_ADDRESS 34 * defined in their respective <asm/pgtable.h>. 35 */ 36 #ifndef FIRST_USER_ADDRESS 37 #define FIRST_USER_ADDRESS 0UL 38 #endif 39 40 /* 41 * This defines the generic helper for accessing PMD page 42 * table page. Although platforms can still override this 43 * via their respective <asm/pgtable.h>. 44 */ 45 #ifndef pmd_pgtable 46 #define pmd_pgtable(pmd) pmd_page(pmd) 47 #endif 48 49 /* 50 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 51 * 52 * The pXx_index() functions return the index of the entry in the page 53 * table page which would control the given virtual address 54 * 55 * As these functions may be used by the same code for different levels of 56 * the page table folding, they are always available, regardless of 57 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 58 * because in such cases PTRS_PER_PxD equals 1. 59 */ 60 61 static inline unsigned long pte_index(unsigned long address) 62 { 63 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 64 } 65 #define pte_index pte_index 66 67 #ifndef pmd_index 68 static inline unsigned long pmd_index(unsigned long address) 69 { 70 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 71 } 72 #define pmd_index pmd_index 73 #endif 74 75 #ifndef pud_index 76 static inline unsigned long pud_index(unsigned long address) 77 { 78 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 79 } 80 #define pud_index pud_index 81 #endif 82 83 #ifndef pgd_index 84 /* Must be a compile-time constant, so implement it as a macro */ 85 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 86 #endif 87 88 #ifndef pte_offset_kernel 89 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 90 { 91 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 92 } 93 #define pte_offset_kernel pte_offset_kernel 94 #endif 95 96 #if defined(CONFIG_HIGHPTE) 97 #define pte_offset_map(dir, address) \ 98 ((pte_t *)kmap_atomic(pmd_page(*(dir))) + \ 99 pte_index((address))) 100 #define pte_unmap(pte) kunmap_atomic((pte)) 101 #else 102 #define pte_offset_map(dir, address) pte_offset_kernel((dir), (address)) 103 #define pte_unmap(pte) ((void)(pte)) /* NOP */ 104 #endif 105 106 /* Find an entry in the second-level page table.. */ 107 #ifndef pmd_offset 108 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 109 { 110 return pud_pgtable(*pud) + pmd_index(address); 111 } 112 #define pmd_offset pmd_offset 113 #endif 114 115 #ifndef pud_offset 116 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 117 { 118 return p4d_pgtable(*p4d) + pud_index(address); 119 } 120 #define pud_offset pud_offset 121 #endif 122 123 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 124 { 125 return (pgd + pgd_index(address)); 126 }; 127 128 /* 129 * a shortcut to get a pgd_t in a given mm 130 */ 131 #ifndef pgd_offset 132 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 133 #endif 134 135 /* 136 * a shortcut which implies the use of the kernel's pgd, instead 137 * of a process's 138 */ 139 #ifndef pgd_offset_k 140 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 141 #endif 142 143 /* 144 * In many cases it is known that a virtual address is mapped at PMD or PTE 145 * level, so instead of traversing all the page table levels, we can get a 146 * pointer to the PMD entry in user or kernel page table or translate a virtual 147 * address to the pointer in the PTE in the kernel page tables with simple 148 * helpers. 149 */ 150 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 151 { 152 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 153 } 154 155 static inline pmd_t *pmd_off_k(unsigned long va) 156 { 157 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 158 } 159 160 static inline pte_t *virt_to_kpte(unsigned long vaddr) 161 { 162 pmd_t *pmd = pmd_off_k(vaddr); 163 164 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 165 } 166 167 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 168 extern int ptep_set_access_flags(struct vm_area_struct *vma, 169 unsigned long address, pte_t *ptep, 170 pte_t entry, int dirty); 171 #endif 172 173 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 174 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 175 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 176 unsigned long address, pmd_t *pmdp, 177 pmd_t entry, int dirty); 178 extern int pudp_set_access_flags(struct vm_area_struct *vma, 179 unsigned long address, pud_t *pudp, 180 pud_t entry, int dirty); 181 #else 182 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 183 unsigned long address, pmd_t *pmdp, 184 pmd_t entry, int dirty) 185 { 186 BUILD_BUG(); 187 return 0; 188 } 189 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 190 unsigned long address, pud_t *pudp, 191 pud_t entry, int dirty) 192 { 193 BUILD_BUG(); 194 return 0; 195 } 196 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 197 #endif 198 199 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 200 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 201 unsigned long address, 202 pte_t *ptep) 203 { 204 pte_t pte = *ptep; 205 int r = 1; 206 if (!pte_young(pte)) 207 r = 0; 208 else 209 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 210 return r; 211 } 212 #endif 213 214 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 215 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 216 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 217 unsigned long address, 218 pmd_t *pmdp) 219 { 220 pmd_t pmd = *pmdp; 221 int r = 1; 222 if (!pmd_young(pmd)) 223 r = 0; 224 else 225 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 226 return r; 227 } 228 #else 229 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 230 unsigned long address, 231 pmd_t *pmdp) 232 { 233 BUILD_BUG(); 234 return 0; 235 } 236 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 237 #endif 238 239 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 240 int ptep_clear_flush_young(struct vm_area_struct *vma, 241 unsigned long address, pte_t *ptep); 242 #endif 243 244 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 245 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 246 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 247 unsigned long address, pmd_t *pmdp); 248 #else 249 /* 250 * Despite relevant to THP only, this API is called from generic rmap code 251 * under PageTransHuge(), hence needs a dummy implementation for !THP 252 */ 253 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 254 unsigned long address, pmd_t *pmdp) 255 { 256 BUILD_BUG(); 257 return 0; 258 } 259 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 260 #endif 261 262 #ifndef __HAVE_ARCH_PTEP_CLEAR 263 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 264 pte_t *ptep) 265 { 266 pte_clear(mm, addr, ptep); 267 } 268 #endif 269 270 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 271 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 272 unsigned long address, 273 pte_t *ptep) 274 { 275 pte_t pte = *ptep; 276 pte_clear(mm, address, ptep); 277 return pte; 278 } 279 #endif 280 281 #ifndef __HAVE_ARCH_PTEP_GET 282 static inline pte_t ptep_get(pte_t *ptep) 283 { 284 return READ_ONCE(*ptep); 285 } 286 #endif 287 288 #ifdef CONFIG_GUP_GET_PTE_LOW_HIGH 289 /* 290 * WARNING: only to be used in the get_user_pages_fast() implementation. 291 * 292 * With get_user_pages_fast(), we walk down the pagetables without taking any 293 * locks. For this we would like to load the pointers atomically, but sometimes 294 * that is not possible (e.g. without expensive cmpxchg8b on x86_32 PAE). What 295 * we do have is the guarantee that a PTE will only either go from not present 296 * to present, or present to not present or both -- it will not switch to a 297 * completely different present page without a TLB flush in between; something 298 * that we are blocking by holding interrupts off. 299 * 300 * Setting ptes from not present to present goes: 301 * 302 * ptep->pte_high = h; 303 * smp_wmb(); 304 * ptep->pte_low = l; 305 * 306 * And present to not present goes: 307 * 308 * ptep->pte_low = 0; 309 * smp_wmb(); 310 * ptep->pte_high = 0; 311 * 312 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 313 * We load pte_high *after* loading pte_low, which ensures we don't see an older 314 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 315 * picked up a changed pte high. We might have gotten rubbish values from 316 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 317 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 318 * operates on present ptes we're safe. 319 */ 320 static inline pte_t ptep_get_lockless(pte_t *ptep) 321 { 322 pte_t pte; 323 324 do { 325 pte.pte_low = ptep->pte_low; 326 smp_rmb(); 327 pte.pte_high = ptep->pte_high; 328 smp_rmb(); 329 } while (unlikely(pte.pte_low != ptep->pte_low)); 330 331 return pte; 332 } 333 #else /* CONFIG_GUP_GET_PTE_LOW_HIGH */ 334 /* 335 * We require that the PTE can be read atomically. 336 */ 337 static inline pte_t ptep_get_lockless(pte_t *ptep) 338 { 339 return ptep_get(ptep); 340 } 341 #endif /* CONFIG_GUP_GET_PTE_LOW_HIGH */ 342 343 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 344 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 345 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 346 unsigned long address, 347 pmd_t *pmdp) 348 { 349 pmd_t pmd = *pmdp; 350 pmd_clear(pmdp); 351 return pmd; 352 } 353 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 354 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 355 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 356 unsigned long address, 357 pud_t *pudp) 358 { 359 pud_t pud = *pudp; 360 361 pud_clear(pudp); 362 return pud; 363 } 364 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 365 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 366 367 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 368 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 369 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 370 unsigned long address, pmd_t *pmdp, 371 int full) 372 { 373 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 374 } 375 #endif 376 377 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 378 static inline pud_t pudp_huge_get_and_clear_full(struct mm_struct *mm, 379 unsigned long address, pud_t *pudp, 380 int full) 381 { 382 return pudp_huge_get_and_clear(mm, address, pudp); 383 } 384 #endif 385 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 386 387 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 388 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 389 unsigned long address, pte_t *ptep, 390 int full) 391 { 392 pte_t pte; 393 pte = ptep_get_and_clear(mm, address, ptep); 394 return pte; 395 } 396 #endif 397 398 399 /* 400 * If two threads concurrently fault at the same page, the thread that 401 * won the race updates the PTE and its local TLB/Cache. The other thread 402 * gives up, simply does nothing, and continues; on architectures where 403 * software can update TLB, local TLB can be updated here to avoid next page 404 * fault. This function updates TLB only, do nothing with cache or others. 405 * It is the difference with function update_mmu_cache. 406 */ 407 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 408 static inline void update_mmu_tlb(struct vm_area_struct *vma, 409 unsigned long address, pte_t *ptep) 410 { 411 } 412 #define __HAVE_ARCH_UPDATE_MMU_TLB 413 #endif 414 415 /* 416 * Some architectures may be able to avoid expensive synchronization 417 * primitives when modifications are made to PTE's which are already 418 * not present, or in the process of an address space destruction. 419 */ 420 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 421 static inline void pte_clear_not_present_full(struct mm_struct *mm, 422 unsigned long address, 423 pte_t *ptep, 424 int full) 425 { 426 pte_clear(mm, address, ptep); 427 } 428 #endif 429 430 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 431 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 432 unsigned long address, 433 pte_t *ptep); 434 #endif 435 436 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 437 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 438 unsigned long address, 439 pmd_t *pmdp); 440 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 441 unsigned long address, 442 pud_t *pudp); 443 #endif 444 445 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 446 struct mm_struct; 447 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 448 { 449 pte_t old_pte = *ptep; 450 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 451 } 452 #endif 453 454 /* 455 * On some architectures hardware does not set page access bit when accessing 456 * memory page, it is responsibility of software setting this bit. It brings 457 * out extra page fault penalty to track page access bit. For optimization page 458 * access bit can be set during all page fault flow on these arches. 459 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 460 * where software maintains page access bit. 461 */ 462 #ifndef pte_sw_mkyoung 463 static inline pte_t pte_sw_mkyoung(pte_t pte) 464 { 465 return pte; 466 } 467 #define pte_sw_mkyoung pte_sw_mkyoung 468 #endif 469 470 #ifndef pte_savedwrite 471 #define pte_savedwrite pte_write 472 #endif 473 474 #ifndef pte_mk_savedwrite 475 #define pte_mk_savedwrite pte_mkwrite 476 #endif 477 478 #ifndef pte_clear_savedwrite 479 #define pte_clear_savedwrite pte_wrprotect 480 #endif 481 482 #ifndef pmd_savedwrite 483 #define pmd_savedwrite pmd_write 484 #endif 485 486 #ifndef pmd_mk_savedwrite 487 #define pmd_mk_savedwrite pmd_mkwrite 488 #endif 489 490 #ifndef pmd_clear_savedwrite 491 #define pmd_clear_savedwrite pmd_wrprotect 492 #endif 493 494 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 495 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 496 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 497 unsigned long address, pmd_t *pmdp) 498 { 499 pmd_t old_pmd = *pmdp; 500 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 501 } 502 #else 503 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 504 unsigned long address, pmd_t *pmdp) 505 { 506 BUILD_BUG(); 507 } 508 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 509 #endif 510 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 511 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 512 static inline void pudp_set_wrprotect(struct mm_struct *mm, 513 unsigned long address, pud_t *pudp) 514 { 515 pud_t old_pud = *pudp; 516 517 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 518 } 519 #else 520 static inline void pudp_set_wrprotect(struct mm_struct *mm, 521 unsigned long address, pud_t *pudp) 522 { 523 BUILD_BUG(); 524 } 525 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 526 #endif 527 528 #ifndef pmdp_collapse_flush 529 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 530 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 531 unsigned long address, pmd_t *pmdp); 532 #else 533 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 534 unsigned long address, 535 pmd_t *pmdp) 536 { 537 BUILD_BUG(); 538 return *pmdp; 539 } 540 #define pmdp_collapse_flush pmdp_collapse_flush 541 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 542 #endif 543 544 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 545 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 546 pgtable_t pgtable); 547 #endif 548 549 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 550 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 551 #endif 552 553 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 554 /* 555 * This is an implementation of pmdp_establish() that is only suitable for an 556 * architecture that doesn't have hardware dirty/accessed bits. In this case we 557 * can't race with CPU which sets these bits and non-atomic approach is fine. 558 */ 559 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 560 unsigned long address, pmd_t *pmdp, pmd_t pmd) 561 { 562 pmd_t old_pmd = *pmdp; 563 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 564 return old_pmd; 565 } 566 #endif 567 568 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 569 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 570 pmd_t *pmdp); 571 #endif 572 573 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 574 575 /* 576 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 577 * hugepage mapping in the page tables. This function is similar to 578 * pmdp_invalidate(), but should only be used if the access and dirty bits would 579 * not be cleared by the software in the new PMD value. The function ensures 580 * that hardware changes of the access and dirty bits updates would not be lost. 581 * 582 * Doing so can allow in certain architectures to avoid a TLB flush in most 583 * cases. Yet, another TLB flush might be necessary later if the PMD update 584 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 585 * even when a TLB flush is needed because of the update, the caller may be able 586 * to batch these TLB flushing operations, so fewer TLB flush operations are 587 * needed. 588 */ 589 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 590 unsigned long address, pmd_t *pmdp); 591 #endif 592 593 #ifndef __HAVE_ARCH_PTE_SAME 594 static inline int pte_same(pte_t pte_a, pte_t pte_b) 595 { 596 return pte_val(pte_a) == pte_val(pte_b); 597 } 598 #endif 599 600 #ifndef __HAVE_ARCH_PTE_UNUSED 601 /* 602 * Some architectures provide facilities to virtualization guests 603 * so that they can flag allocated pages as unused. This allows the 604 * host to transparently reclaim unused pages. This function returns 605 * whether the pte's page is unused. 606 */ 607 static inline int pte_unused(pte_t pte) 608 { 609 return 0; 610 } 611 #endif 612 613 #ifndef pte_access_permitted 614 #define pte_access_permitted(pte, write) \ 615 (pte_present(pte) && (!(write) || pte_write(pte))) 616 #endif 617 618 #ifndef pmd_access_permitted 619 #define pmd_access_permitted(pmd, write) \ 620 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 621 #endif 622 623 #ifndef pud_access_permitted 624 #define pud_access_permitted(pud, write) \ 625 (pud_present(pud) && (!(write) || pud_write(pud))) 626 #endif 627 628 #ifndef p4d_access_permitted 629 #define p4d_access_permitted(p4d, write) \ 630 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 631 #endif 632 633 #ifndef pgd_access_permitted 634 #define pgd_access_permitted(pgd, write) \ 635 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 636 #endif 637 638 #ifndef __HAVE_ARCH_PMD_SAME 639 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 640 { 641 return pmd_val(pmd_a) == pmd_val(pmd_b); 642 } 643 644 static inline int pud_same(pud_t pud_a, pud_t pud_b) 645 { 646 return pud_val(pud_a) == pud_val(pud_b); 647 } 648 #endif 649 650 #ifndef __HAVE_ARCH_P4D_SAME 651 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 652 { 653 return p4d_val(p4d_a) == p4d_val(p4d_b); 654 } 655 #endif 656 657 #ifndef __HAVE_ARCH_PGD_SAME 658 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 659 { 660 return pgd_val(pgd_a) == pgd_val(pgd_b); 661 } 662 #endif 663 664 /* 665 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 666 * TLB flush will be required as a result of the "set". For example, use 667 * in scenarios where it is known ahead of time that the routine is 668 * setting non-present entries, or re-setting an existing entry to the 669 * same value. Otherwise, use the typical "set" helpers and flush the 670 * TLB. 671 */ 672 #define set_pte_safe(ptep, pte) \ 673 ({ \ 674 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 675 set_pte(ptep, pte); \ 676 }) 677 678 #define set_pmd_safe(pmdp, pmd) \ 679 ({ \ 680 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 681 set_pmd(pmdp, pmd); \ 682 }) 683 684 #define set_pud_safe(pudp, pud) \ 685 ({ \ 686 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 687 set_pud(pudp, pud); \ 688 }) 689 690 #define set_p4d_safe(p4dp, p4d) \ 691 ({ \ 692 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 693 set_p4d(p4dp, p4d); \ 694 }) 695 696 #define set_pgd_safe(pgdp, pgd) \ 697 ({ \ 698 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 699 set_pgd(pgdp, pgd); \ 700 }) 701 702 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 703 /* 704 * Some architectures support metadata associated with a page. When a 705 * page is being swapped out, this metadata must be saved so it can be 706 * restored when the page is swapped back in. SPARC M7 and newer 707 * processors support an ADI (Application Data Integrity) tag for the 708 * page as metadata for the page. arch_do_swap_page() can restore this 709 * metadata when a page is swapped back in. 710 */ 711 static inline void arch_do_swap_page(struct mm_struct *mm, 712 struct vm_area_struct *vma, 713 unsigned long addr, 714 pte_t pte, pte_t oldpte) 715 { 716 717 } 718 #endif 719 720 #ifndef __HAVE_ARCH_UNMAP_ONE 721 /* 722 * Some architectures support metadata associated with a page. When a 723 * page is being swapped out, this metadata must be saved so it can be 724 * restored when the page is swapped back in. SPARC M7 and newer 725 * processors support an ADI (Application Data Integrity) tag for the 726 * page as metadata for the page. arch_unmap_one() can save this 727 * metadata on a swap-out of a page. 728 */ 729 static inline int arch_unmap_one(struct mm_struct *mm, 730 struct vm_area_struct *vma, 731 unsigned long addr, 732 pte_t orig_pte) 733 { 734 return 0; 735 } 736 #endif 737 738 /* 739 * Allow architectures to preserve additional metadata associated with 740 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 741 * prototypes must be defined in the arch-specific asm/pgtable.h file. 742 */ 743 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 744 static inline int arch_prepare_to_swap(struct page *page) 745 { 746 return 0; 747 } 748 #endif 749 750 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 751 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 752 { 753 } 754 755 static inline void arch_swap_invalidate_area(int type) 756 { 757 } 758 #endif 759 760 #ifndef __HAVE_ARCH_SWAP_RESTORE 761 static inline void arch_swap_restore(swp_entry_t entry, struct page *page) 762 { 763 } 764 #endif 765 766 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 767 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 768 #endif 769 770 #ifndef __HAVE_ARCH_MOVE_PTE 771 #define move_pte(pte, prot, old_addr, new_addr) (pte) 772 #endif 773 774 #ifndef pte_accessible 775 # define pte_accessible(mm, pte) ((void)(pte), 1) 776 #endif 777 778 #ifndef flush_tlb_fix_spurious_fault 779 #define flush_tlb_fix_spurious_fault(vma, address) flush_tlb_page(vma, address) 780 #endif 781 782 /* 783 * When walking page tables, get the address of the next boundary, 784 * or the end address of the range if that comes earlier. Although no 785 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 786 */ 787 788 #define pgd_addr_end(addr, end) \ 789 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 790 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 791 }) 792 793 #ifndef p4d_addr_end 794 #define p4d_addr_end(addr, end) \ 795 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 796 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 797 }) 798 #endif 799 800 #ifndef pud_addr_end 801 #define pud_addr_end(addr, end) \ 802 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 803 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 804 }) 805 #endif 806 807 #ifndef pmd_addr_end 808 #define pmd_addr_end(addr, end) \ 809 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 810 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 811 }) 812 #endif 813 814 /* 815 * When walking page tables, we usually want to skip any p?d_none entries; 816 * and any p?d_bad entries - reporting the error before resetting to none. 817 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 818 */ 819 void pgd_clear_bad(pgd_t *); 820 821 #ifndef __PAGETABLE_P4D_FOLDED 822 void p4d_clear_bad(p4d_t *); 823 #else 824 #define p4d_clear_bad(p4d) do { } while (0) 825 #endif 826 827 #ifndef __PAGETABLE_PUD_FOLDED 828 void pud_clear_bad(pud_t *); 829 #else 830 #define pud_clear_bad(p4d) do { } while (0) 831 #endif 832 833 void pmd_clear_bad(pmd_t *); 834 835 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 836 { 837 if (pgd_none(*pgd)) 838 return 1; 839 if (unlikely(pgd_bad(*pgd))) { 840 pgd_clear_bad(pgd); 841 return 1; 842 } 843 return 0; 844 } 845 846 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 847 { 848 if (p4d_none(*p4d)) 849 return 1; 850 if (unlikely(p4d_bad(*p4d))) { 851 p4d_clear_bad(p4d); 852 return 1; 853 } 854 return 0; 855 } 856 857 static inline int pud_none_or_clear_bad(pud_t *pud) 858 { 859 if (pud_none(*pud)) 860 return 1; 861 if (unlikely(pud_bad(*pud))) { 862 pud_clear_bad(pud); 863 return 1; 864 } 865 return 0; 866 } 867 868 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 869 { 870 if (pmd_none(*pmd)) 871 return 1; 872 if (unlikely(pmd_bad(*pmd))) { 873 pmd_clear_bad(pmd); 874 return 1; 875 } 876 return 0; 877 } 878 879 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 880 unsigned long addr, 881 pte_t *ptep) 882 { 883 /* 884 * Get the current pte state, but zero it out to make it 885 * non-present, preventing the hardware from asynchronously 886 * updating it. 887 */ 888 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 889 } 890 891 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 892 unsigned long addr, 893 pte_t *ptep, pte_t pte) 894 { 895 /* 896 * The pte is non-present, so there's no hardware state to 897 * preserve. 898 */ 899 set_pte_at(vma->vm_mm, addr, ptep, pte); 900 } 901 902 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 903 /* 904 * Start a pte protection read-modify-write transaction, which 905 * protects against asynchronous hardware modifications to the pte. 906 * The intention is not to prevent the hardware from making pte 907 * updates, but to prevent any updates it may make from being lost. 908 * 909 * This does not protect against other software modifications of the 910 * pte; the appropriate pte lock must be held over the transaction. 911 * 912 * Note that this interface is intended to be batchable, meaning that 913 * ptep_modify_prot_commit may not actually update the pte, but merely 914 * queue the update to be done at some later time. The update must be 915 * actually committed before the pte lock is released, however. 916 */ 917 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 918 unsigned long addr, 919 pte_t *ptep) 920 { 921 return __ptep_modify_prot_start(vma, addr, ptep); 922 } 923 924 /* 925 * Commit an update to a pte, leaving any hardware-controlled bits in 926 * the PTE unmodified. 927 */ 928 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 929 unsigned long addr, 930 pte_t *ptep, pte_t old_pte, pte_t pte) 931 { 932 __ptep_modify_prot_commit(vma, addr, ptep, pte); 933 } 934 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 935 #endif /* CONFIG_MMU */ 936 937 /* 938 * No-op macros that just return the current protection value. Defined here 939 * because these macros can be used even if CONFIG_MMU is not defined. 940 */ 941 942 #ifndef pgprot_nx 943 #define pgprot_nx(prot) (prot) 944 #endif 945 946 #ifndef pgprot_noncached 947 #define pgprot_noncached(prot) (prot) 948 #endif 949 950 #ifndef pgprot_writecombine 951 #define pgprot_writecombine pgprot_noncached 952 #endif 953 954 #ifndef pgprot_writethrough 955 #define pgprot_writethrough pgprot_noncached 956 #endif 957 958 #ifndef pgprot_device 959 #define pgprot_device pgprot_noncached 960 #endif 961 962 #ifndef pgprot_mhp 963 #define pgprot_mhp(prot) (prot) 964 #endif 965 966 #ifdef CONFIG_MMU 967 #ifndef pgprot_modify 968 #define pgprot_modify pgprot_modify 969 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 970 { 971 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 972 newprot = pgprot_noncached(newprot); 973 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 974 newprot = pgprot_writecombine(newprot); 975 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 976 newprot = pgprot_device(newprot); 977 return newprot; 978 } 979 #endif 980 #endif /* CONFIG_MMU */ 981 982 #ifndef pgprot_encrypted 983 #define pgprot_encrypted(prot) (prot) 984 #endif 985 986 #ifndef pgprot_decrypted 987 #define pgprot_decrypted(prot) (prot) 988 #endif 989 990 /* 991 * A facility to provide lazy MMU batching. This allows PTE updates and 992 * page invalidations to be delayed until a call to leave lazy MMU mode 993 * is issued. Some architectures may benefit from doing this, and it is 994 * beneficial for both shadow and direct mode hypervisors, which may batch 995 * the PTE updates which happen during this window. Note that using this 996 * interface requires that read hazards be removed from the code. A read 997 * hazard could result in the direct mode hypervisor case, since the actual 998 * write to the page tables may not yet have taken place, so reads though 999 * a raw PTE pointer after it has been modified are not guaranteed to be 1000 * up to date. This mode can only be entered and left under the protection of 1001 * the page table locks for all page tables which may be modified. In the UP 1002 * case, this is required so that preemption is disabled, and in the SMP case, 1003 * it must synchronize the delayed page table writes properly on other CPUs. 1004 */ 1005 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 1006 #define arch_enter_lazy_mmu_mode() do {} while (0) 1007 #define arch_leave_lazy_mmu_mode() do {} while (0) 1008 #define arch_flush_lazy_mmu_mode() do {} while (0) 1009 #endif 1010 1011 /* 1012 * A facility to provide batching of the reload of page tables and 1013 * other process state with the actual context switch code for 1014 * paravirtualized guests. By convention, only one of the batched 1015 * update (lazy) modes (CPU, MMU) should be active at any given time, 1016 * entry should never be nested, and entry and exits should always be 1017 * paired. This is for sanity of maintaining and reasoning about the 1018 * kernel code. In this case, the exit (end of the context switch) is 1019 * in architecture-specific code, and so doesn't need a generic 1020 * definition. 1021 */ 1022 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1023 #define arch_start_context_switch(prev) do {} while (0) 1024 #endif 1025 1026 /* 1027 * When replacing an anonymous page by a real (!non) swap entry, we clear 1028 * PG_anon_exclusive from the page and instead remember whether the flag was 1029 * set in the swp pte. During fork(), we have to mark the entry as !exclusive 1030 * (possibly shared). On swapin, we use that information to restore 1031 * PG_anon_exclusive, which is very helpful in cases where we might have 1032 * additional (e.g., FOLL_GET) references on a page and wouldn't be able to 1033 * detect exclusivity. 1034 * 1035 * These functions don't apply to non-swap entries (e.g., migration, hwpoison, 1036 * ...). 1037 */ 1038 #ifndef __HAVE_ARCH_PTE_SWP_EXCLUSIVE 1039 static inline pte_t pte_swp_mkexclusive(pte_t pte) 1040 { 1041 return pte; 1042 } 1043 1044 static inline int pte_swp_exclusive(pte_t pte) 1045 { 1046 return false; 1047 } 1048 1049 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 1050 { 1051 return pte; 1052 } 1053 #endif 1054 1055 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1056 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1057 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1058 { 1059 return pmd; 1060 } 1061 1062 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1063 { 1064 return 0; 1065 } 1066 1067 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1068 { 1069 return pmd; 1070 } 1071 #endif 1072 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1073 static inline int pte_soft_dirty(pte_t pte) 1074 { 1075 return 0; 1076 } 1077 1078 static inline int pmd_soft_dirty(pmd_t pmd) 1079 { 1080 return 0; 1081 } 1082 1083 static inline pte_t pte_mksoft_dirty(pte_t pte) 1084 { 1085 return pte; 1086 } 1087 1088 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1089 { 1090 return pmd; 1091 } 1092 1093 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1094 { 1095 return pte; 1096 } 1097 1098 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1099 { 1100 return pmd; 1101 } 1102 1103 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1104 { 1105 return pte; 1106 } 1107 1108 static inline int pte_swp_soft_dirty(pte_t pte) 1109 { 1110 return 0; 1111 } 1112 1113 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1114 { 1115 return pte; 1116 } 1117 1118 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1119 { 1120 return pmd; 1121 } 1122 1123 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1124 { 1125 return 0; 1126 } 1127 1128 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1129 { 1130 return pmd; 1131 } 1132 #endif 1133 1134 #ifndef __HAVE_PFNMAP_TRACKING 1135 /* 1136 * Interfaces that can be used by architecture code to keep track of 1137 * memory type of pfn mappings specified by the remap_pfn_range, 1138 * vmf_insert_pfn. 1139 */ 1140 1141 /* 1142 * track_pfn_remap is called when a _new_ pfn mapping is being established 1143 * by remap_pfn_range() for physical range indicated by pfn and size. 1144 */ 1145 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1146 unsigned long pfn, unsigned long addr, 1147 unsigned long size) 1148 { 1149 return 0; 1150 } 1151 1152 /* 1153 * track_pfn_insert is called when a _new_ single pfn is established 1154 * by vmf_insert_pfn(). 1155 */ 1156 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1157 pfn_t pfn) 1158 { 1159 } 1160 1161 /* 1162 * track_pfn_copy is called when vma that is covering the pfnmap gets 1163 * copied through copy_page_range(). 1164 */ 1165 static inline int track_pfn_copy(struct vm_area_struct *vma) 1166 { 1167 return 0; 1168 } 1169 1170 /* 1171 * untrack_pfn is called while unmapping a pfnmap for a region. 1172 * untrack can be called for a specific region indicated by pfn and size or 1173 * can be for the entire vma (in which case pfn, size are zero). 1174 */ 1175 static inline void untrack_pfn(struct vm_area_struct *vma, 1176 unsigned long pfn, unsigned long size) 1177 { 1178 } 1179 1180 /* 1181 * untrack_pfn_moved is called while mremapping a pfnmap for a new region. 1182 */ 1183 static inline void untrack_pfn_moved(struct vm_area_struct *vma) 1184 { 1185 } 1186 #else 1187 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1188 unsigned long pfn, unsigned long addr, 1189 unsigned long size); 1190 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1191 pfn_t pfn); 1192 extern int track_pfn_copy(struct vm_area_struct *vma); 1193 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1194 unsigned long size); 1195 extern void untrack_pfn_moved(struct vm_area_struct *vma); 1196 #endif 1197 1198 #ifdef CONFIG_MMU 1199 #ifdef __HAVE_COLOR_ZERO_PAGE 1200 static inline int is_zero_pfn(unsigned long pfn) 1201 { 1202 extern unsigned long zero_pfn; 1203 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1204 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1205 } 1206 1207 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1208 1209 #else 1210 static inline int is_zero_pfn(unsigned long pfn) 1211 { 1212 extern unsigned long zero_pfn; 1213 return pfn == zero_pfn; 1214 } 1215 1216 static inline unsigned long my_zero_pfn(unsigned long addr) 1217 { 1218 extern unsigned long zero_pfn; 1219 return zero_pfn; 1220 } 1221 #endif 1222 #else 1223 static inline int is_zero_pfn(unsigned long pfn) 1224 { 1225 return 0; 1226 } 1227 1228 static inline unsigned long my_zero_pfn(unsigned long addr) 1229 { 1230 return 0; 1231 } 1232 #endif /* CONFIG_MMU */ 1233 1234 #ifdef CONFIG_MMU 1235 1236 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1237 static inline int pmd_trans_huge(pmd_t pmd) 1238 { 1239 return 0; 1240 } 1241 #ifndef pmd_write 1242 static inline int pmd_write(pmd_t pmd) 1243 { 1244 BUG(); 1245 return 0; 1246 } 1247 #endif /* pmd_write */ 1248 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1249 1250 #ifndef pud_write 1251 static inline int pud_write(pud_t pud) 1252 { 1253 BUG(); 1254 return 0; 1255 } 1256 #endif /* pud_write */ 1257 1258 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1259 static inline int pmd_devmap(pmd_t pmd) 1260 { 1261 return 0; 1262 } 1263 static inline int pud_devmap(pud_t pud) 1264 { 1265 return 0; 1266 } 1267 static inline int pgd_devmap(pgd_t pgd) 1268 { 1269 return 0; 1270 } 1271 #endif 1272 1273 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1274 (defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1275 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)) 1276 static inline int pud_trans_huge(pud_t pud) 1277 { 1278 return 0; 1279 } 1280 #endif 1281 1282 /* See pmd_none_or_trans_huge_or_clear_bad for discussion. */ 1283 static inline int pud_none_or_trans_huge_or_dev_or_clear_bad(pud_t *pud) 1284 { 1285 pud_t pudval = READ_ONCE(*pud); 1286 1287 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1288 return 1; 1289 if (unlikely(pud_bad(pudval))) { 1290 pud_clear_bad(pud); 1291 return 1; 1292 } 1293 return 0; 1294 } 1295 1296 /* See pmd_trans_unstable for discussion. */ 1297 static inline int pud_trans_unstable(pud_t *pud) 1298 { 1299 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1300 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1301 return pud_none_or_trans_huge_or_dev_or_clear_bad(pud); 1302 #else 1303 return 0; 1304 #endif 1305 } 1306 1307 #ifndef pmd_read_atomic 1308 static inline pmd_t pmd_read_atomic(pmd_t *pmdp) 1309 { 1310 /* 1311 * Depend on compiler for an atomic pmd read. NOTE: this is 1312 * only going to work, if the pmdval_t isn't larger than 1313 * an unsigned long. 1314 */ 1315 return *pmdp; 1316 } 1317 #endif 1318 1319 #ifndef arch_needs_pgtable_deposit 1320 #define arch_needs_pgtable_deposit() (false) 1321 #endif 1322 /* 1323 * This function is meant to be used by sites walking pagetables with 1324 * the mmap_lock held in read mode to protect against MADV_DONTNEED and 1325 * transhuge page faults. MADV_DONTNEED can convert a transhuge pmd 1326 * into a null pmd and the transhuge page fault can convert a null pmd 1327 * into an hugepmd or into a regular pmd (if the hugepage allocation 1328 * fails). While holding the mmap_lock in read mode the pmd becomes 1329 * stable and stops changing under us only if it's not null and not a 1330 * transhuge pmd. When those races occurs and this function makes a 1331 * difference vs the standard pmd_none_or_clear_bad, the result is 1332 * undefined so behaving like if the pmd was none is safe (because it 1333 * can return none anyway). The compiler level barrier() is critically 1334 * important to compute the two checks atomically on the same pmdval. 1335 * 1336 * For 32bit kernels with a 64bit large pmd_t this automatically takes 1337 * care of reading the pmd atomically to avoid SMP race conditions 1338 * against pmd_populate() when the mmap_lock is hold for reading by the 1339 * caller (a special atomic read not done by "gcc" as in the generic 1340 * version above, is also needed when THP is disabled because the page 1341 * fault can populate the pmd from under us). 1342 */ 1343 static inline int pmd_none_or_trans_huge_or_clear_bad(pmd_t *pmd) 1344 { 1345 pmd_t pmdval = pmd_read_atomic(pmd); 1346 /* 1347 * The barrier will stabilize the pmdval in a register or on 1348 * the stack so that it will stop changing under the code. 1349 * 1350 * When CONFIG_TRANSPARENT_HUGEPAGE=y on x86 32bit PAE, 1351 * pmd_read_atomic is allowed to return a not atomic pmdval 1352 * (for example pointing to an hugepage that has never been 1353 * mapped in the pmd). The below checks will only care about 1354 * the low part of the pmd with 32bit PAE x86 anyway, with the 1355 * exception of pmd_none(). So the important thing is that if 1356 * the low part of the pmd is found null, the high part will 1357 * be also null or the pmd_none() check below would be 1358 * confused. 1359 */ 1360 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1361 barrier(); 1362 #endif 1363 /* 1364 * !pmd_present() checks for pmd migration entries 1365 * 1366 * The complete check uses is_pmd_migration_entry() in linux/swapops.h 1367 * But using that requires moving current function and pmd_trans_unstable() 1368 * to linux/swapops.h to resolve dependency, which is too much code move. 1369 * 1370 * !pmd_present() is equivalent to is_pmd_migration_entry() currently, 1371 * because !pmd_present() pages can only be under migration not swapped 1372 * out. 1373 * 1374 * pmd_none() is preserved for future condition checks on pmd migration 1375 * entries and not confusing with this function name, although it is 1376 * redundant with !pmd_present(). 1377 */ 1378 if (pmd_none(pmdval) || pmd_trans_huge(pmdval) || 1379 (IS_ENABLED(CONFIG_ARCH_ENABLE_THP_MIGRATION) && !pmd_present(pmdval))) 1380 return 1; 1381 if (unlikely(pmd_bad(pmdval))) { 1382 pmd_clear_bad(pmd); 1383 return 1; 1384 } 1385 return 0; 1386 } 1387 1388 /* 1389 * This is a noop if Transparent Hugepage Support is not built into 1390 * the kernel. Otherwise it is equivalent to 1391 * pmd_none_or_trans_huge_or_clear_bad(), and shall only be called in 1392 * places that already verified the pmd is not none and they want to 1393 * walk ptes while holding the mmap sem in read mode (write mode don't 1394 * need this). If THP is not enabled, the pmd can't go away under the 1395 * code even if MADV_DONTNEED runs, but if THP is enabled we need to 1396 * run a pmd_trans_unstable before walking the ptes after 1397 * split_huge_pmd returns (because it may have run when the pmd become 1398 * null, but then a page fault can map in a THP and not a regular page). 1399 */ 1400 static inline int pmd_trans_unstable(pmd_t *pmd) 1401 { 1402 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1403 return pmd_none_or_trans_huge_or_clear_bad(pmd); 1404 #else 1405 return 0; 1406 #endif 1407 } 1408 1409 /* 1410 * the ordering of these checks is important for pmds with _page_devmap set. 1411 * if we check pmd_trans_unstable() first we will trip the bad_pmd() check 1412 * inside of pmd_none_or_trans_huge_or_clear_bad(). this will end up correctly 1413 * returning 1 but not before it spams dmesg with the pmd_clear_bad() output. 1414 */ 1415 static inline int pmd_devmap_trans_unstable(pmd_t *pmd) 1416 { 1417 return pmd_devmap(*pmd) || pmd_trans_unstable(pmd); 1418 } 1419 1420 #ifndef CONFIG_NUMA_BALANCING 1421 /* 1422 * Technically a PTE can be PROTNONE even when not doing NUMA balancing but 1423 * the only case the kernel cares is for NUMA balancing and is only ever set 1424 * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked 1425 * _PAGE_PROTNONE so by default, implement the helper as "always no". It 1426 * is the responsibility of the caller to distinguish between PROT_NONE 1427 * protections and NUMA hinting fault protections. 1428 */ 1429 static inline int pte_protnone(pte_t pte) 1430 { 1431 return 0; 1432 } 1433 1434 static inline int pmd_protnone(pmd_t pmd) 1435 { 1436 return 0; 1437 } 1438 #endif /* CONFIG_NUMA_BALANCING */ 1439 1440 #endif /* CONFIG_MMU */ 1441 1442 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1443 1444 #ifndef __PAGETABLE_P4D_FOLDED 1445 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1446 int p4d_clear_huge(p4d_t *p4d); 1447 #else 1448 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1449 { 1450 return 0; 1451 } 1452 static inline int p4d_clear_huge(p4d_t *p4d) 1453 { 1454 return 0; 1455 } 1456 #endif /* !__PAGETABLE_P4D_FOLDED */ 1457 1458 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1459 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1460 int pud_clear_huge(pud_t *pud); 1461 int pmd_clear_huge(pmd_t *pmd); 1462 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1463 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1464 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1465 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1466 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1467 { 1468 return 0; 1469 } 1470 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1471 { 1472 return 0; 1473 } 1474 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1475 { 1476 return 0; 1477 } 1478 static inline int p4d_clear_huge(p4d_t *p4d) 1479 { 1480 return 0; 1481 } 1482 static inline int pud_clear_huge(pud_t *pud) 1483 { 1484 return 0; 1485 } 1486 static inline int pmd_clear_huge(pmd_t *pmd) 1487 { 1488 return 0; 1489 } 1490 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1491 { 1492 return 0; 1493 } 1494 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1495 { 1496 return 0; 1497 } 1498 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1499 { 1500 return 0; 1501 } 1502 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1503 1504 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1505 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1506 /* 1507 * ARCHes with special requirements for evicting THP backing TLB entries can 1508 * implement this. Otherwise also, it can help optimize normal TLB flush in 1509 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1510 * entire TLB if flush span is greater than a threshold, which will 1511 * likely be true for a single huge page. Thus a single THP flush will 1512 * invalidate the entire TLB which is not desirable. 1513 * e.g. see arch/arc: flush_pmd_tlb_range 1514 */ 1515 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1516 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1517 #else 1518 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1519 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1520 #endif 1521 #endif 1522 1523 struct file; 1524 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1525 unsigned long size, pgprot_t *vma_prot); 1526 1527 #ifndef CONFIG_X86_ESPFIX64 1528 static inline void init_espfix_bsp(void) { } 1529 #endif 1530 1531 extern void __init pgtable_cache_init(void); 1532 1533 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1534 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1535 { 1536 return true; 1537 } 1538 1539 static inline bool arch_has_pfn_modify_check(void) 1540 { 1541 return false; 1542 } 1543 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1544 1545 /* 1546 * Architecture PAGE_KERNEL_* fallbacks 1547 * 1548 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1549 * because they really don't support them, or the port needs to be updated to 1550 * reflect the required functionality. Below are a set of relatively safe 1551 * fallbacks, as best effort, which we can count on in lieu of the architectures 1552 * not defining them on their own yet. 1553 */ 1554 1555 #ifndef PAGE_KERNEL_RO 1556 # define PAGE_KERNEL_RO PAGE_KERNEL 1557 #endif 1558 1559 #ifndef PAGE_KERNEL_EXEC 1560 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1561 #endif 1562 1563 /* 1564 * Page Table Modification bits for pgtbl_mod_mask. 1565 * 1566 * These are used by the p?d_alloc_track*() set of functions an in the generic 1567 * vmalloc/ioremap code to track at which page-table levels entries have been 1568 * modified. Based on that the code can better decide when vmalloc and ioremap 1569 * mapping changes need to be synchronized to other page-tables in the system. 1570 */ 1571 #define __PGTBL_PGD_MODIFIED 0 1572 #define __PGTBL_P4D_MODIFIED 1 1573 #define __PGTBL_PUD_MODIFIED 2 1574 #define __PGTBL_PMD_MODIFIED 3 1575 #define __PGTBL_PTE_MODIFIED 4 1576 1577 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1578 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1579 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1580 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1581 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1582 1583 /* Page-Table Modification Mask */ 1584 typedef unsigned int pgtbl_mod_mask; 1585 1586 #endif /* !__ASSEMBLY__ */ 1587 1588 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1589 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1590 /* 1591 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1592 * with physical address space extension, but falls back to 1593 * BITS_PER_LONG otherwise. 1594 */ 1595 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1596 #else 1597 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1598 #endif 1599 #endif 1600 1601 #ifndef has_transparent_hugepage 1602 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1603 #define has_transparent_hugepage() 1 1604 #else 1605 #define has_transparent_hugepage() 0 1606 #endif 1607 #endif 1608 1609 /* 1610 * On some architectures it depends on the mm if the p4d/pud or pmd 1611 * layer of the page table hierarchy is folded or not. 1612 */ 1613 #ifndef mm_p4d_folded 1614 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1615 #endif 1616 1617 #ifndef mm_pud_folded 1618 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1619 #endif 1620 1621 #ifndef mm_pmd_folded 1622 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1623 #endif 1624 1625 #ifndef p4d_offset_lockless 1626 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1627 #endif 1628 #ifndef pud_offset_lockless 1629 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1630 #endif 1631 #ifndef pmd_offset_lockless 1632 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1633 #endif 1634 1635 /* 1636 * p?d_leaf() - true if this entry is a final mapping to a physical address. 1637 * This differs from p?d_huge() by the fact that they are always available (if 1638 * the architecture supports large pages at the appropriate level) even 1639 * if CONFIG_HUGETLB_PAGE is not defined. 1640 * Only meaningful when called on a valid entry. 1641 */ 1642 #ifndef pgd_leaf 1643 #define pgd_leaf(x) 0 1644 #endif 1645 #ifndef p4d_leaf 1646 #define p4d_leaf(x) 0 1647 #endif 1648 #ifndef pud_leaf 1649 #define pud_leaf(x) 0 1650 #endif 1651 #ifndef pmd_leaf 1652 #define pmd_leaf(x) 0 1653 #endif 1654 1655 #ifndef pgd_leaf_size 1656 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1657 #endif 1658 #ifndef p4d_leaf_size 1659 #define p4d_leaf_size(x) P4D_SIZE 1660 #endif 1661 #ifndef pud_leaf_size 1662 #define pud_leaf_size(x) PUD_SIZE 1663 #endif 1664 #ifndef pmd_leaf_size 1665 #define pmd_leaf_size(x) PMD_SIZE 1666 #endif 1667 #ifndef pte_leaf_size 1668 #define pte_leaf_size(x) PAGE_SIZE 1669 #endif 1670 1671 /* 1672 * Some architectures have MMUs that are configurable or selectable at boot 1673 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1674 * helps to have a static maximum value. 1675 */ 1676 1677 #ifndef MAX_PTRS_PER_PTE 1678 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1679 #endif 1680 1681 #ifndef MAX_PTRS_PER_PMD 1682 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1683 #endif 1684 1685 #ifndef MAX_PTRS_PER_PUD 1686 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1687 #endif 1688 1689 #ifndef MAX_PTRS_PER_P4D 1690 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1691 #endif 1692 1693 #endif /* _LINUX_PGTABLE_H */ 1694