1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #ifndef __ASSEMBLY__ 9 #ifdef CONFIG_MMU 10 11 #include <linux/mm_types.h> 12 #include <linux/bug.h> 13 #include <linux/errno.h> 14 #include <asm-generic/pgtable_uffd.h> 15 #include <linux/page_table_check.h> 16 17 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 18 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 19 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 20 #endif 21 22 /* 23 * On almost all architectures and configurations, 0 can be used as the 24 * upper ceiling to free_pgtables(): on many architectures it has the same 25 * effect as using TASK_SIZE. However, there is one configuration which 26 * must impose a more careful limit, to avoid freeing kernel pgtables. 27 */ 28 #ifndef USER_PGTABLES_CEILING 29 #define USER_PGTABLES_CEILING 0UL 30 #endif 31 32 /* 33 * This defines the first usable user address. Platforms 34 * can override its value with custom FIRST_USER_ADDRESS 35 * defined in their respective <asm/pgtable.h>. 36 */ 37 #ifndef FIRST_USER_ADDRESS 38 #define FIRST_USER_ADDRESS 0UL 39 #endif 40 41 /* 42 * This defines the generic helper for accessing PMD page 43 * table page. Although platforms can still override this 44 * via their respective <asm/pgtable.h>. 45 */ 46 #ifndef pmd_pgtable 47 #define pmd_pgtable(pmd) pmd_page(pmd) 48 #endif 49 50 /* 51 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 52 * 53 * The pXx_index() functions return the index of the entry in the page 54 * table page which would control the given virtual address 55 * 56 * As these functions may be used by the same code for different levels of 57 * the page table folding, they are always available, regardless of 58 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 59 * because in such cases PTRS_PER_PxD equals 1. 60 */ 61 62 static inline unsigned long pte_index(unsigned long address) 63 { 64 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 65 } 66 #define pte_index pte_index 67 68 #ifndef pmd_index 69 static inline unsigned long pmd_index(unsigned long address) 70 { 71 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 72 } 73 #define pmd_index pmd_index 74 #endif 75 76 #ifndef pud_index 77 static inline unsigned long pud_index(unsigned long address) 78 { 79 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 80 } 81 #define pud_index pud_index 82 #endif 83 84 #ifndef pgd_index 85 /* Must be a compile-time constant, so implement it as a macro */ 86 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 87 #endif 88 89 #ifndef pte_offset_kernel 90 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 91 { 92 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 93 } 94 #define pte_offset_kernel pte_offset_kernel 95 #endif 96 97 #ifdef CONFIG_HIGHPTE 98 #define __pte_map(pmd, address) \ 99 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address))) 100 #define pte_unmap(pte) do { \ 101 kunmap_local((pte)); \ 102 rcu_read_unlock(); \ 103 } while (0) 104 #else 105 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address) 106 { 107 return pte_offset_kernel(pmd, address); 108 } 109 static inline void pte_unmap(pte_t *pte) 110 { 111 rcu_read_unlock(); 112 } 113 #endif 114 115 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable); 116 117 /* Find an entry in the second-level page table.. */ 118 #ifndef pmd_offset 119 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 120 { 121 return pud_pgtable(*pud) + pmd_index(address); 122 } 123 #define pmd_offset pmd_offset 124 #endif 125 126 #ifndef pud_offset 127 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 128 { 129 return p4d_pgtable(*p4d) + pud_index(address); 130 } 131 #define pud_offset pud_offset 132 #endif 133 134 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 135 { 136 return (pgd + pgd_index(address)); 137 }; 138 139 /* 140 * a shortcut to get a pgd_t in a given mm 141 */ 142 #ifndef pgd_offset 143 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 144 #endif 145 146 /* 147 * a shortcut which implies the use of the kernel's pgd, instead 148 * of a process's 149 */ 150 #ifndef pgd_offset_k 151 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 152 #endif 153 154 /* 155 * In many cases it is known that a virtual address is mapped at PMD or PTE 156 * level, so instead of traversing all the page table levels, we can get a 157 * pointer to the PMD entry in user or kernel page table or translate a virtual 158 * address to the pointer in the PTE in the kernel page tables with simple 159 * helpers. 160 */ 161 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 162 { 163 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 164 } 165 166 static inline pmd_t *pmd_off_k(unsigned long va) 167 { 168 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 169 } 170 171 static inline pte_t *virt_to_kpte(unsigned long vaddr) 172 { 173 pmd_t *pmd = pmd_off_k(vaddr); 174 175 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 176 } 177 178 #ifndef pmd_young 179 static inline int pmd_young(pmd_t pmd) 180 { 181 return 0; 182 } 183 #endif 184 185 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 186 extern int ptep_set_access_flags(struct vm_area_struct *vma, 187 unsigned long address, pte_t *ptep, 188 pte_t entry, int dirty); 189 #endif 190 191 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 192 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 193 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 194 unsigned long address, pmd_t *pmdp, 195 pmd_t entry, int dirty); 196 extern int pudp_set_access_flags(struct vm_area_struct *vma, 197 unsigned long address, pud_t *pudp, 198 pud_t entry, int dirty); 199 #else 200 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 201 unsigned long address, pmd_t *pmdp, 202 pmd_t entry, int dirty) 203 { 204 BUILD_BUG(); 205 return 0; 206 } 207 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 208 unsigned long address, pud_t *pudp, 209 pud_t entry, int dirty) 210 { 211 BUILD_BUG(); 212 return 0; 213 } 214 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 215 #endif 216 217 #ifndef ptep_get 218 static inline pte_t ptep_get(pte_t *ptep) 219 { 220 return READ_ONCE(*ptep); 221 } 222 #endif 223 224 #ifndef pmdp_get 225 static inline pmd_t pmdp_get(pmd_t *pmdp) 226 { 227 return READ_ONCE(*pmdp); 228 } 229 #endif 230 231 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 232 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 233 unsigned long address, 234 pte_t *ptep) 235 { 236 pte_t pte = ptep_get(ptep); 237 int r = 1; 238 if (!pte_young(pte)) 239 r = 0; 240 else 241 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 242 return r; 243 } 244 #endif 245 246 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 247 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 248 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 249 unsigned long address, 250 pmd_t *pmdp) 251 { 252 pmd_t pmd = *pmdp; 253 int r = 1; 254 if (!pmd_young(pmd)) 255 r = 0; 256 else 257 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 258 return r; 259 } 260 #else 261 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 262 unsigned long address, 263 pmd_t *pmdp) 264 { 265 BUILD_BUG(); 266 return 0; 267 } 268 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 269 #endif 270 271 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 272 int ptep_clear_flush_young(struct vm_area_struct *vma, 273 unsigned long address, pte_t *ptep); 274 #endif 275 276 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 277 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 278 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 279 unsigned long address, pmd_t *pmdp); 280 #else 281 /* 282 * Despite relevant to THP only, this API is called from generic rmap code 283 * under PageTransHuge(), hence needs a dummy implementation for !THP 284 */ 285 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 286 unsigned long address, pmd_t *pmdp) 287 { 288 BUILD_BUG(); 289 return 0; 290 } 291 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 292 #endif 293 294 #ifndef arch_has_hw_nonleaf_pmd_young 295 /* 296 * Return whether the accessed bit in non-leaf PMD entries is supported on the 297 * local CPU. 298 */ 299 static inline bool arch_has_hw_nonleaf_pmd_young(void) 300 { 301 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 302 } 303 #endif 304 305 #ifndef arch_has_hw_pte_young 306 /* 307 * Return whether the accessed bit is supported on the local CPU. 308 * 309 * This stub assumes accessing through an old PTE triggers a page fault. 310 * Architectures that automatically set the access bit should overwrite it. 311 */ 312 static inline bool arch_has_hw_pte_young(void) 313 { 314 return false; 315 } 316 #endif 317 318 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 319 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 320 unsigned long address, 321 pte_t *ptep) 322 { 323 pte_t pte = ptep_get(ptep); 324 pte_clear(mm, address, ptep); 325 page_table_check_pte_clear(mm, pte); 326 return pte; 327 } 328 #endif 329 330 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 331 pte_t *ptep) 332 { 333 ptep_get_and_clear(mm, addr, ptep); 334 } 335 336 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH 337 /* 338 * For walking the pagetables without holding any locks. Some architectures 339 * (eg x86-32 PAE) cannot load the entries atomically without using expensive 340 * instructions. We are guaranteed that a PTE will only either go from not 341 * present to present, or present to not present -- it will not switch to a 342 * completely different present page without a TLB flush inbetween; which we 343 * are blocking by holding interrupts off. 344 * 345 * Setting ptes from not present to present goes: 346 * 347 * ptep->pte_high = h; 348 * smp_wmb(); 349 * ptep->pte_low = l; 350 * 351 * And present to not present goes: 352 * 353 * ptep->pte_low = 0; 354 * smp_wmb(); 355 * ptep->pte_high = 0; 356 * 357 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 358 * We load pte_high *after* loading pte_low, which ensures we don't see an older 359 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 360 * picked up a changed pte high. We might have gotten rubbish values from 361 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 362 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 363 * operates on present ptes we're safe. 364 */ 365 static inline pte_t ptep_get_lockless(pte_t *ptep) 366 { 367 pte_t pte; 368 369 do { 370 pte.pte_low = ptep->pte_low; 371 smp_rmb(); 372 pte.pte_high = ptep->pte_high; 373 smp_rmb(); 374 } while (unlikely(pte.pte_low != ptep->pte_low)); 375 376 return pte; 377 } 378 #define ptep_get_lockless ptep_get_lockless 379 380 #if CONFIG_PGTABLE_LEVELS > 2 381 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 382 { 383 pmd_t pmd; 384 385 do { 386 pmd.pmd_low = pmdp->pmd_low; 387 smp_rmb(); 388 pmd.pmd_high = pmdp->pmd_high; 389 smp_rmb(); 390 } while (unlikely(pmd.pmd_low != pmdp->pmd_low)); 391 392 return pmd; 393 } 394 #define pmdp_get_lockless pmdp_get_lockless 395 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one() 396 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 397 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */ 398 399 /* 400 * We require that the PTE can be read atomically. 401 */ 402 #ifndef ptep_get_lockless 403 static inline pte_t ptep_get_lockless(pte_t *ptep) 404 { 405 return ptep_get(ptep); 406 } 407 #endif 408 409 #ifndef pmdp_get_lockless 410 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 411 { 412 return pmdp_get(pmdp); 413 } 414 static inline void pmdp_get_lockless_sync(void) 415 { 416 } 417 #endif 418 419 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 420 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 421 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 422 unsigned long address, 423 pmd_t *pmdp) 424 { 425 pmd_t pmd = *pmdp; 426 427 pmd_clear(pmdp); 428 page_table_check_pmd_clear(mm, pmd); 429 430 return pmd; 431 } 432 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 433 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 434 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 435 unsigned long address, 436 pud_t *pudp) 437 { 438 pud_t pud = *pudp; 439 440 pud_clear(pudp); 441 page_table_check_pud_clear(mm, pud); 442 443 return pud; 444 } 445 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 446 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 447 448 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 449 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 450 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 451 unsigned long address, pmd_t *pmdp, 452 int full) 453 { 454 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 455 } 456 #endif 457 458 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 459 static inline pud_t pudp_huge_get_and_clear_full(struct mm_struct *mm, 460 unsigned long address, pud_t *pudp, 461 int full) 462 { 463 return pudp_huge_get_and_clear(mm, address, pudp); 464 } 465 #endif 466 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 467 468 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 469 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 470 unsigned long address, pte_t *ptep, 471 int full) 472 { 473 return ptep_get_and_clear(mm, address, ptep); 474 } 475 #endif 476 477 478 /* 479 * If two threads concurrently fault at the same page, the thread that 480 * won the race updates the PTE and its local TLB/Cache. The other thread 481 * gives up, simply does nothing, and continues; on architectures where 482 * software can update TLB, local TLB can be updated here to avoid next page 483 * fault. This function updates TLB only, do nothing with cache or others. 484 * It is the difference with function update_mmu_cache. 485 */ 486 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 487 static inline void update_mmu_tlb(struct vm_area_struct *vma, 488 unsigned long address, pte_t *ptep) 489 { 490 } 491 #define __HAVE_ARCH_UPDATE_MMU_TLB 492 #endif 493 494 /* 495 * Some architectures may be able to avoid expensive synchronization 496 * primitives when modifications are made to PTE's which are already 497 * not present, or in the process of an address space destruction. 498 */ 499 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 500 static inline void pte_clear_not_present_full(struct mm_struct *mm, 501 unsigned long address, 502 pte_t *ptep, 503 int full) 504 { 505 pte_clear(mm, address, ptep); 506 } 507 #endif 508 509 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 510 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 511 unsigned long address, 512 pte_t *ptep); 513 #endif 514 515 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 516 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 517 unsigned long address, 518 pmd_t *pmdp); 519 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 520 unsigned long address, 521 pud_t *pudp); 522 #endif 523 524 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 525 struct mm_struct; 526 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 527 { 528 pte_t old_pte = ptep_get(ptep); 529 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 530 } 531 #endif 532 533 /* 534 * On some architectures hardware does not set page access bit when accessing 535 * memory page, it is responsibility of software setting this bit. It brings 536 * out extra page fault penalty to track page access bit. For optimization page 537 * access bit can be set during all page fault flow on these arches. 538 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 539 * where software maintains page access bit. 540 */ 541 #ifndef pte_sw_mkyoung 542 static inline pte_t pte_sw_mkyoung(pte_t pte) 543 { 544 return pte; 545 } 546 #define pte_sw_mkyoung pte_sw_mkyoung 547 #endif 548 549 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 550 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 551 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 552 unsigned long address, pmd_t *pmdp) 553 { 554 pmd_t old_pmd = *pmdp; 555 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 556 } 557 #else 558 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 559 unsigned long address, pmd_t *pmdp) 560 { 561 BUILD_BUG(); 562 } 563 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 564 #endif 565 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 566 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 567 static inline void pudp_set_wrprotect(struct mm_struct *mm, 568 unsigned long address, pud_t *pudp) 569 { 570 pud_t old_pud = *pudp; 571 572 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 573 } 574 #else 575 static inline void pudp_set_wrprotect(struct mm_struct *mm, 576 unsigned long address, pud_t *pudp) 577 { 578 BUILD_BUG(); 579 } 580 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 581 #endif 582 583 #ifndef pmdp_collapse_flush 584 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 585 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 586 unsigned long address, pmd_t *pmdp); 587 #else 588 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 589 unsigned long address, 590 pmd_t *pmdp) 591 { 592 BUILD_BUG(); 593 return *pmdp; 594 } 595 #define pmdp_collapse_flush pmdp_collapse_flush 596 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 597 #endif 598 599 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 600 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 601 pgtable_t pgtable); 602 #endif 603 604 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 605 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 606 #endif 607 608 #ifndef arch_needs_pgtable_deposit 609 #define arch_needs_pgtable_deposit() (false) 610 #endif 611 612 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 613 /* 614 * This is an implementation of pmdp_establish() that is only suitable for an 615 * architecture that doesn't have hardware dirty/accessed bits. In this case we 616 * can't race with CPU which sets these bits and non-atomic approach is fine. 617 */ 618 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 619 unsigned long address, pmd_t *pmdp, pmd_t pmd) 620 { 621 pmd_t old_pmd = *pmdp; 622 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 623 return old_pmd; 624 } 625 #endif 626 627 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 628 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 629 pmd_t *pmdp); 630 #endif 631 632 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 633 634 /* 635 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 636 * hugepage mapping in the page tables. This function is similar to 637 * pmdp_invalidate(), but should only be used if the access and dirty bits would 638 * not be cleared by the software in the new PMD value. The function ensures 639 * that hardware changes of the access and dirty bits updates would not be lost. 640 * 641 * Doing so can allow in certain architectures to avoid a TLB flush in most 642 * cases. Yet, another TLB flush might be necessary later if the PMD update 643 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 644 * even when a TLB flush is needed because of the update, the caller may be able 645 * to batch these TLB flushing operations, so fewer TLB flush operations are 646 * needed. 647 */ 648 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 649 unsigned long address, pmd_t *pmdp); 650 #endif 651 652 #ifndef __HAVE_ARCH_PTE_SAME 653 static inline int pte_same(pte_t pte_a, pte_t pte_b) 654 { 655 return pte_val(pte_a) == pte_val(pte_b); 656 } 657 #endif 658 659 #ifndef __HAVE_ARCH_PTE_UNUSED 660 /* 661 * Some architectures provide facilities to virtualization guests 662 * so that they can flag allocated pages as unused. This allows the 663 * host to transparently reclaim unused pages. This function returns 664 * whether the pte's page is unused. 665 */ 666 static inline int pte_unused(pte_t pte) 667 { 668 return 0; 669 } 670 #endif 671 672 #ifndef pte_access_permitted 673 #define pte_access_permitted(pte, write) \ 674 (pte_present(pte) && (!(write) || pte_write(pte))) 675 #endif 676 677 #ifndef pmd_access_permitted 678 #define pmd_access_permitted(pmd, write) \ 679 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 680 #endif 681 682 #ifndef pud_access_permitted 683 #define pud_access_permitted(pud, write) \ 684 (pud_present(pud) && (!(write) || pud_write(pud))) 685 #endif 686 687 #ifndef p4d_access_permitted 688 #define p4d_access_permitted(p4d, write) \ 689 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 690 #endif 691 692 #ifndef pgd_access_permitted 693 #define pgd_access_permitted(pgd, write) \ 694 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 695 #endif 696 697 #ifndef __HAVE_ARCH_PMD_SAME 698 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 699 { 700 return pmd_val(pmd_a) == pmd_val(pmd_b); 701 } 702 703 static inline int pud_same(pud_t pud_a, pud_t pud_b) 704 { 705 return pud_val(pud_a) == pud_val(pud_b); 706 } 707 #endif 708 709 #ifndef __HAVE_ARCH_P4D_SAME 710 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 711 { 712 return p4d_val(p4d_a) == p4d_val(p4d_b); 713 } 714 #endif 715 716 #ifndef __HAVE_ARCH_PGD_SAME 717 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 718 { 719 return pgd_val(pgd_a) == pgd_val(pgd_b); 720 } 721 #endif 722 723 /* 724 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 725 * TLB flush will be required as a result of the "set". For example, use 726 * in scenarios where it is known ahead of time that the routine is 727 * setting non-present entries, or re-setting an existing entry to the 728 * same value. Otherwise, use the typical "set" helpers and flush the 729 * TLB. 730 */ 731 #define set_pte_safe(ptep, pte) \ 732 ({ \ 733 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 734 set_pte(ptep, pte); \ 735 }) 736 737 #define set_pmd_safe(pmdp, pmd) \ 738 ({ \ 739 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 740 set_pmd(pmdp, pmd); \ 741 }) 742 743 #define set_pud_safe(pudp, pud) \ 744 ({ \ 745 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 746 set_pud(pudp, pud); \ 747 }) 748 749 #define set_p4d_safe(p4dp, p4d) \ 750 ({ \ 751 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 752 set_p4d(p4dp, p4d); \ 753 }) 754 755 #define set_pgd_safe(pgdp, pgd) \ 756 ({ \ 757 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 758 set_pgd(pgdp, pgd); \ 759 }) 760 761 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 762 /* 763 * Some architectures support metadata associated with a page. When a 764 * page is being swapped out, this metadata must be saved so it can be 765 * restored when the page is swapped back in. SPARC M7 and newer 766 * processors support an ADI (Application Data Integrity) tag for the 767 * page as metadata for the page. arch_do_swap_page() can restore this 768 * metadata when a page is swapped back in. 769 */ 770 static inline void arch_do_swap_page(struct mm_struct *mm, 771 struct vm_area_struct *vma, 772 unsigned long addr, 773 pte_t pte, pte_t oldpte) 774 { 775 776 } 777 #endif 778 779 #ifndef __HAVE_ARCH_UNMAP_ONE 780 /* 781 * Some architectures support metadata associated with a page. When a 782 * page is being swapped out, this metadata must be saved so it can be 783 * restored when the page is swapped back in. SPARC M7 and newer 784 * processors support an ADI (Application Data Integrity) tag for the 785 * page as metadata for the page. arch_unmap_one() can save this 786 * metadata on a swap-out of a page. 787 */ 788 static inline int arch_unmap_one(struct mm_struct *mm, 789 struct vm_area_struct *vma, 790 unsigned long addr, 791 pte_t orig_pte) 792 { 793 return 0; 794 } 795 #endif 796 797 /* 798 * Allow architectures to preserve additional metadata associated with 799 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 800 * prototypes must be defined in the arch-specific asm/pgtable.h file. 801 */ 802 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 803 static inline int arch_prepare_to_swap(struct page *page) 804 { 805 return 0; 806 } 807 #endif 808 809 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 810 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 811 { 812 } 813 814 static inline void arch_swap_invalidate_area(int type) 815 { 816 } 817 #endif 818 819 #ifndef __HAVE_ARCH_SWAP_RESTORE 820 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 821 { 822 } 823 #endif 824 825 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 826 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 827 #endif 828 829 #ifndef __HAVE_ARCH_MOVE_PTE 830 #define move_pte(pte, prot, old_addr, new_addr) (pte) 831 #endif 832 833 #ifndef pte_accessible 834 # define pte_accessible(mm, pte) ((void)(pte), 1) 835 #endif 836 837 #ifndef flush_tlb_fix_spurious_fault 838 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address) 839 #endif 840 841 /* 842 * When walking page tables, get the address of the next boundary, 843 * or the end address of the range if that comes earlier. Although no 844 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 845 */ 846 847 #define pgd_addr_end(addr, end) \ 848 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 849 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 850 }) 851 852 #ifndef p4d_addr_end 853 #define p4d_addr_end(addr, end) \ 854 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 855 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 856 }) 857 #endif 858 859 #ifndef pud_addr_end 860 #define pud_addr_end(addr, end) \ 861 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 862 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 863 }) 864 #endif 865 866 #ifndef pmd_addr_end 867 #define pmd_addr_end(addr, end) \ 868 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 869 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 870 }) 871 #endif 872 873 /* 874 * When walking page tables, we usually want to skip any p?d_none entries; 875 * and any p?d_bad entries - reporting the error before resetting to none. 876 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 877 */ 878 void pgd_clear_bad(pgd_t *); 879 880 #ifndef __PAGETABLE_P4D_FOLDED 881 void p4d_clear_bad(p4d_t *); 882 #else 883 #define p4d_clear_bad(p4d) do { } while (0) 884 #endif 885 886 #ifndef __PAGETABLE_PUD_FOLDED 887 void pud_clear_bad(pud_t *); 888 #else 889 #define pud_clear_bad(p4d) do { } while (0) 890 #endif 891 892 void pmd_clear_bad(pmd_t *); 893 894 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 895 { 896 if (pgd_none(*pgd)) 897 return 1; 898 if (unlikely(pgd_bad(*pgd))) { 899 pgd_clear_bad(pgd); 900 return 1; 901 } 902 return 0; 903 } 904 905 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 906 { 907 if (p4d_none(*p4d)) 908 return 1; 909 if (unlikely(p4d_bad(*p4d))) { 910 p4d_clear_bad(p4d); 911 return 1; 912 } 913 return 0; 914 } 915 916 static inline int pud_none_or_clear_bad(pud_t *pud) 917 { 918 if (pud_none(*pud)) 919 return 1; 920 if (unlikely(pud_bad(*pud))) { 921 pud_clear_bad(pud); 922 return 1; 923 } 924 return 0; 925 } 926 927 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 928 { 929 if (pmd_none(*pmd)) 930 return 1; 931 if (unlikely(pmd_bad(*pmd))) { 932 pmd_clear_bad(pmd); 933 return 1; 934 } 935 return 0; 936 } 937 938 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 939 unsigned long addr, 940 pte_t *ptep) 941 { 942 /* 943 * Get the current pte state, but zero it out to make it 944 * non-present, preventing the hardware from asynchronously 945 * updating it. 946 */ 947 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 948 } 949 950 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 951 unsigned long addr, 952 pte_t *ptep, pte_t pte) 953 { 954 /* 955 * The pte is non-present, so there's no hardware state to 956 * preserve. 957 */ 958 set_pte_at(vma->vm_mm, addr, ptep, pte); 959 } 960 961 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 962 /* 963 * Start a pte protection read-modify-write transaction, which 964 * protects against asynchronous hardware modifications to the pte. 965 * The intention is not to prevent the hardware from making pte 966 * updates, but to prevent any updates it may make from being lost. 967 * 968 * This does not protect against other software modifications of the 969 * pte; the appropriate pte lock must be held over the transaction. 970 * 971 * Note that this interface is intended to be batchable, meaning that 972 * ptep_modify_prot_commit may not actually update the pte, but merely 973 * queue the update to be done at some later time. The update must be 974 * actually committed before the pte lock is released, however. 975 */ 976 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 977 unsigned long addr, 978 pte_t *ptep) 979 { 980 return __ptep_modify_prot_start(vma, addr, ptep); 981 } 982 983 /* 984 * Commit an update to a pte, leaving any hardware-controlled bits in 985 * the PTE unmodified. 986 */ 987 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 988 unsigned long addr, 989 pte_t *ptep, pte_t old_pte, pte_t pte) 990 { 991 __ptep_modify_prot_commit(vma, addr, ptep, pte); 992 } 993 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 994 #endif /* CONFIG_MMU */ 995 996 /* 997 * No-op macros that just return the current protection value. Defined here 998 * because these macros can be used even if CONFIG_MMU is not defined. 999 */ 1000 1001 #ifndef pgprot_nx 1002 #define pgprot_nx(prot) (prot) 1003 #endif 1004 1005 #ifndef pgprot_noncached 1006 #define pgprot_noncached(prot) (prot) 1007 #endif 1008 1009 #ifndef pgprot_writecombine 1010 #define pgprot_writecombine pgprot_noncached 1011 #endif 1012 1013 #ifndef pgprot_writethrough 1014 #define pgprot_writethrough pgprot_noncached 1015 #endif 1016 1017 #ifndef pgprot_device 1018 #define pgprot_device pgprot_noncached 1019 #endif 1020 1021 #ifndef pgprot_mhp 1022 #define pgprot_mhp(prot) (prot) 1023 #endif 1024 1025 #ifdef CONFIG_MMU 1026 #ifndef pgprot_modify 1027 #define pgprot_modify pgprot_modify 1028 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 1029 { 1030 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 1031 newprot = pgprot_noncached(newprot); 1032 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 1033 newprot = pgprot_writecombine(newprot); 1034 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 1035 newprot = pgprot_device(newprot); 1036 return newprot; 1037 } 1038 #endif 1039 #endif /* CONFIG_MMU */ 1040 1041 #ifndef pgprot_encrypted 1042 #define pgprot_encrypted(prot) (prot) 1043 #endif 1044 1045 #ifndef pgprot_decrypted 1046 #define pgprot_decrypted(prot) (prot) 1047 #endif 1048 1049 /* 1050 * A facility to provide lazy MMU batching. This allows PTE updates and 1051 * page invalidations to be delayed until a call to leave lazy MMU mode 1052 * is issued. Some architectures may benefit from doing this, and it is 1053 * beneficial for both shadow and direct mode hypervisors, which may batch 1054 * the PTE updates which happen during this window. Note that using this 1055 * interface requires that read hazards be removed from the code. A read 1056 * hazard could result in the direct mode hypervisor case, since the actual 1057 * write to the page tables may not yet have taken place, so reads though 1058 * a raw PTE pointer after it has been modified are not guaranteed to be 1059 * up to date. This mode can only be entered and left under the protection of 1060 * the page table locks for all page tables which may be modified. In the UP 1061 * case, this is required so that preemption is disabled, and in the SMP case, 1062 * it must synchronize the delayed page table writes properly on other CPUs. 1063 */ 1064 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 1065 #define arch_enter_lazy_mmu_mode() do {} while (0) 1066 #define arch_leave_lazy_mmu_mode() do {} while (0) 1067 #define arch_flush_lazy_mmu_mode() do {} while (0) 1068 #endif 1069 1070 /* 1071 * A facility to provide batching of the reload of page tables and 1072 * other process state with the actual context switch code for 1073 * paravirtualized guests. By convention, only one of the batched 1074 * update (lazy) modes (CPU, MMU) should be active at any given time, 1075 * entry should never be nested, and entry and exits should always be 1076 * paired. This is for sanity of maintaining and reasoning about the 1077 * kernel code. In this case, the exit (end of the context switch) is 1078 * in architecture-specific code, and so doesn't need a generic 1079 * definition. 1080 */ 1081 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1082 #define arch_start_context_switch(prev) do {} while (0) 1083 #endif 1084 1085 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1086 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1087 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1088 { 1089 return pmd; 1090 } 1091 1092 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1093 { 1094 return 0; 1095 } 1096 1097 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1098 { 1099 return pmd; 1100 } 1101 #endif 1102 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1103 static inline int pte_soft_dirty(pte_t pte) 1104 { 1105 return 0; 1106 } 1107 1108 static inline int pmd_soft_dirty(pmd_t pmd) 1109 { 1110 return 0; 1111 } 1112 1113 static inline pte_t pte_mksoft_dirty(pte_t pte) 1114 { 1115 return pte; 1116 } 1117 1118 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1119 { 1120 return pmd; 1121 } 1122 1123 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1124 { 1125 return pte; 1126 } 1127 1128 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1129 { 1130 return pmd; 1131 } 1132 1133 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1134 { 1135 return pte; 1136 } 1137 1138 static inline int pte_swp_soft_dirty(pte_t pte) 1139 { 1140 return 0; 1141 } 1142 1143 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1144 { 1145 return pte; 1146 } 1147 1148 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1149 { 1150 return pmd; 1151 } 1152 1153 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1154 { 1155 return 0; 1156 } 1157 1158 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1159 { 1160 return pmd; 1161 } 1162 #endif 1163 1164 #ifndef __HAVE_PFNMAP_TRACKING 1165 /* 1166 * Interfaces that can be used by architecture code to keep track of 1167 * memory type of pfn mappings specified by the remap_pfn_range, 1168 * vmf_insert_pfn. 1169 */ 1170 1171 /* 1172 * track_pfn_remap is called when a _new_ pfn mapping is being established 1173 * by remap_pfn_range() for physical range indicated by pfn and size. 1174 */ 1175 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1176 unsigned long pfn, unsigned long addr, 1177 unsigned long size) 1178 { 1179 return 0; 1180 } 1181 1182 /* 1183 * track_pfn_insert is called when a _new_ single pfn is established 1184 * by vmf_insert_pfn(). 1185 */ 1186 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1187 pfn_t pfn) 1188 { 1189 } 1190 1191 /* 1192 * track_pfn_copy is called when vma that is covering the pfnmap gets 1193 * copied through copy_page_range(). 1194 */ 1195 static inline int track_pfn_copy(struct vm_area_struct *vma) 1196 { 1197 return 0; 1198 } 1199 1200 /* 1201 * untrack_pfn is called while unmapping a pfnmap for a region. 1202 * untrack can be called for a specific region indicated by pfn and size or 1203 * can be for the entire vma (in which case pfn, size are zero). 1204 */ 1205 static inline void untrack_pfn(struct vm_area_struct *vma, 1206 unsigned long pfn, unsigned long size, 1207 bool mm_wr_locked) 1208 { 1209 } 1210 1211 /* 1212 * untrack_pfn_clear is called while mremapping a pfnmap for a new region 1213 * or fails to copy pgtable during duplicate vm area. 1214 */ 1215 static inline void untrack_pfn_clear(struct vm_area_struct *vma) 1216 { 1217 } 1218 #else 1219 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1220 unsigned long pfn, unsigned long addr, 1221 unsigned long size); 1222 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1223 pfn_t pfn); 1224 extern int track_pfn_copy(struct vm_area_struct *vma); 1225 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1226 unsigned long size, bool mm_wr_locked); 1227 extern void untrack_pfn_clear(struct vm_area_struct *vma); 1228 #endif 1229 1230 #ifdef CONFIG_MMU 1231 #ifdef __HAVE_COLOR_ZERO_PAGE 1232 static inline int is_zero_pfn(unsigned long pfn) 1233 { 1234 extern unsigned long zero_pfn; 1235 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1236 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1237 } 1238 1239 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1240 1241 #else 1242 static inline int is_zero_pfn(unsigned long pfn) 1243 { 1244 extern unsigned long zero_pfn; 1245 return pfn == zero_pfn; 1246 } 1247 1248 static inline unsigned long my_zero_pfn(unsigned long addr) 1249 { 1250 extern unsigned long zero_pfn; 1251 return zero_pfn; 1252 } 1253 #endif 1254 #else 1255 static inline int is_zero_pfn(unsigned long pfn) 1256 { 1257 return 0; 1258 } 1259 1260 static inline unsigned long my_zero_pfn(unsigned long addr) 1261 { 1262 return 0; 1263 } 1264 #endif /* CONFIG_MMU */ 1265 1266 #ifdef CONFIG_MMU 1267 1268 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1269 static inline int pmd_trans_huge(pmd_t pmd) 1270 { 1271 return 0; 1272 } 1273 #ifndef pmd_write 1274 static inline int pmd_write(pmd_t pmd) 1275 { 1276 BUG(); 1277 return 0; 1278 } 1279 #endif /* pmd_write */ 1280 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1281 1282 #ifndef pud_write 1283 static inline int pud_write(pud_t pud) 1284 { 1285 BUG(); 1286 return 0; 1287 } 1288 #endif /* pud_write */ 1289 1290 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1291 static inline int pmd_devmap(pmd_t pmd) 1292 { 1293 return 0; 1294 } 1295 static inline int pud_devmap(pud_t pud) 1296 { 1297 return 0; 1298 } 1299 static inline int pgd_devmap(pgd_t pgd) 1300 { 1301 return 0; 1302 } 1303 #endif 1304 1305 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1306 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1307 static inline int pud_trans_huge(pud_t pud) 1308 { 1309 return 0; 1310 } 1311 #endif 1312 1313 static inline int pud_trans_unstable(pud_t *pud) 1314 { 1315 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1316 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1317 pud_t pudval = READ_ONCE(*pud); 1318 1319 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1320 return 1; 1321 if (unlikely(pud_bad(pudval))) { 1322 pud_clear_bad(pud); 1323 return 1; 1324 } 1325 #endif 1326 return 0; 1327 } 1328 1329 #ifndef CONFIG_NUMA_BALANCING 1330 /* 1331 * Technically a PTE can be PROTNONE even when not doing NUMA balancing but 1332 * the only case the kernel cares is for NUMA balancing and is only ever set 1333 * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked 1334 * _PAGE_PROTNONE so by default, implement the helper as "always no". It 1335 * is the responsibility of the caller to distinguish between PROT_NONE 1336 * protections and NUMA hinting fault protections. 1337 */ 1338 static inline int pte_protnone(pte_t pte) 1339 { 1340 return 0; 1341 } 1342 1343 static inline int pmd_protnone(pmd_t pmd) 1344 { 1345 return 0; 1346 } 1347 #endif /* CONFIG_NUMA_BALANCING */ 1348 1349 #endif /* CONFIG_MMU */ 1350 1351 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1352 1353 #ifndef __PAGETABLE_P4D_FOLDED 1354 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1355 void p4d_clear_huge(p4d_t *p4d); 1356 #else 1357 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1358 { 1359 return 0; 1360 } 1361 static inline void p4d_clear_huge(p4d_t *p4d) { } 1362 #endif /* !__PAGETABLE_P4D_FOLDED */ 1363 1364 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1365 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1366 int pud_clear_huge(pud_t *pud); 1367 int pmd_clear_huge(pmd_t *pmd); 1368 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1369 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1370 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1371 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1372 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1373 { 1374 return 0; 1375 } 1376 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1377 { 1378 return 0; 1379 } 1380 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1381 { 1382 return 0; 1383 } 1384 static inline void p4d_clear_huge(p4d_t *p4d) { } 1385 static inline int pud_clear_huge(pud_t *pud) 1386 { 1387 return 0; 1388 } 1389 static inline int pmd_clear_huge(pmd_t *pmd) 1390 { 1391 return 0; 1392 } 1393 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1394 { 1395 return 0; 1396 } 1397 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1398 { 1399 return 0; 1400 } 1401 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1402 { 1403 return 0; 1404 } 1405 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1406 1407 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1408 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1409 /* 1410 * ARCHes with special requirements for evicting THP backing TLB entries can 1411 * implement this. Otherwise also, it can help optimize normal TLB flush in 1412 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1413 * entire TLB if flush span is greater than a threshold, which will 1414 * likely be true for a single huge page. Thus a single THP flush will 1415 * invalidate the entire TLB which is not desirable. 1416 * e.g. see arch/arc: flush_pmd_tlb_range 1417 */ 1418 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1419 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1420 #else 1421 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1422 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1423 #endif 1424 #endif 1425 1426 struct file; 1427 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1428 unsigned long size, pgprot_t *vma_prot); 1429 1430 #ifndef CONFIG_X86_ESPFIX64 1431 static inline void init_espfix_bsp(void) { } 1432 #endif 1433 1434 extern void __init pgtable_cache_init(void); 1435 1436 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1437 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1438 { 1439 return true; 1440 } 1441 1442 static inline bool arch_has_pfn_modify_check(void) 1443 { 1444 return false; 1445 } 1446 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1447 1448 /* 1449 * Architecture PAGE_KERNEL_* fallbacks 1450 * 1451 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1452 * because they really don't support them, or the port needs to be updated to 1453 * reflect the required functionality. Below are a set of relatively safe 1454 * fallbacks, as best effort, which we can count on in lieu of the architectures 1455 * not defining them on their own yet. 1456 */ 1457 1458 #ifndef PAGE_KERNEL_RO 1459 # define PAGE_KERNEL_RO PAGE_KERNEL 1460 #endif 1461 1462 #ifndef PAGE_KERNEL_EXEC 1463 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1464 #endif 1465 1466 /* 1467 * Page Table Modification bits for pgtbl_mod_mask. 1468 * 1469 * These are used by the p?d_alloc_track*() set of functions an in the generic 1470 * vmalloc/ioremap code to track at which page-table levels entries have been 1471 * modified. Based on that the code can better decide when vmalloc and ioremap 1472 * mapping changes need to be synchronized to other page-tables in the system. 1473 */ 1474 #define __PGTBL_PGD_MODIFIED 0 1475 #define __PGTBL_P4D_MODIFIED 1 1476 #define __PGTBL_PUD_MODIFIED 2 1477 #define __PGTBL_PMD_MODIFIED 3 1478 #define __PGTBL_PTE_MODIFIED 4 1479 1480 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1481 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1482 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1483 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1484 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1485 1486 /* Page-Table Modification Mask */ 1487 typedef unsigned int pgtbl_mod_mask; 1488 1489 #endif /* !__ASSEMBLY__ */ 1490 1491 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1492 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1493 /* 1494 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1495 * with physical address space extension, but falls back to 1496 * BITS_PER_LONG otherwise. 1497 */ 1498 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1499 #else 1500 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1501 #endif 1502 #endif 1503 1504 #ifndef has_transparent_hugepage 1505 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1506 #endif 1507 1508 /* 1509 * On some architectures it depends on the mm if the p4d/pud or pmd 1510 * layer of the page table hierarchy is folded or not. 1511 */ 1512 #ifndef mm_p4d_folded 1513 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1514 #endif 1515 1516 #ifndef mm_pud_folded 1517 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1518 #endif 1519 1520 #ifndef mm_pmd_folded 1521 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1522 #endif 1523 1524 #ifndef p4d_offset_lockless 1525 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1526 #endif 1527 #ifndef pud_offset_lockless 1528 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1529 #endif 1530 #ifndef pmd_offset_lockless 1531 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1532 #endif 1533 1534 /* 1535 * p?d_leaf() - true if this entry is a final mapping to a physical address. 1536 * This differs from p?d_huge() by the fact that they are always available (if 1537 * the architecture supports large pages at the appropriate level) even 1538 * if CONFIG_HUGETLB_PAGE is not defined. 1539 * Only meaningful when called on a valid entry. 1540 */ 1541 #ifndef pgd_leaf 1542 #define pgd_leaf(x) 0 1543 #endif 1544 #ifndef p4d_leaf 1545 #define p4d_leaf(x) 0 1546 #endif 1547 #ifndef pud_leaf 1548 #define pud_leaf(x) 0 1549 #endif 1550 #ifndef pmd_leaf 1551 #define pmd_leaf(x) 0 1552 #endif 1553 1554 #ifndef pgd_leaf_size 1555 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1556 #endif 1557 #ifndef p4d_leaf_size 1558 #define p4d_leaf_size(x) P4D_SIZE 1559 #endif 1560 #ifndef pud_leaf_size 1561 #define pud_leaf_size(x) PUD_SIZE 1562 #endif 1563 #ifndef pmd_leaf_size 1564 #define pmd_leaf_size(x) PMD_SIZE 1565 #endif 1566 #ifndef pte_leaf_size 1567 #define pte_leaf_size(x) PAGE_SIZE 1568 #endif 1569 1570 /* 1571 * Some architectures have MMUs that are configurable or selectable at boot 1572 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1573 * helps to have a static maximum value. 1574 */ 1575 1576 #ifndef MAX_PTRS_PER_PTE 1577 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1578 #endif 1579 1580 #ifndef MAX_PTRS_PER_PMD 1581 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1582 #endif 1583 1584 #ifndef MAX_PTRS_PER_PUD 1585 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1586 #endif 1587 1588 #ifndef MAX_PTRS_PER_P4D 1589 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1590 #endif 1591 1592 /* description of effects of mapping type and prot in current implementation. 1593 * this is due to the limited x86 page protection hardware. The expected 1594 * behavior is in parens: 1595 * 1596 * map_type prot 1597 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1598 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1599 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1600 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1601 * 1602 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1603 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1604 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1605 * 1606 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1607 * MAP_PRIVATE (with Enhanced PAN supported): 1608 * r: (no) no 1609 * w: (no) no 1610 * x: (yes) yes 1611 */ 1612 #define DECLARE_VM_GET_PAGE_PROT \ 1613 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1614 { \ 1615 return protection_map[vm_flags & \ 1616 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1617 } \ 1618 EXPORT_SYMBOL(vm_get_page_prot); 1619 1620 #endif /* _LINUX_PGTABLE_H */ 1621