1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT) 9 #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT) 10 11 #ifndef __ASSEMBLY__ 12 #ifdef CONFIG_MMU 13 14 #include <linux/mm_types.h> 15 #include <linux/bug.h> 16 #include <linux/errno.h> 17 #include <asm-generic/pgtable_uffd.h> 18 #include <linux/page_table_check.h> 19 20 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 22 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 23 #endif 24 25 /* 26 * On almost all architectures and configurations, 0 can be used as the 27 * upper ceiling to free_pgtables(): on many architectures it has the same 28 * effect as using TASK_SIZE. However, there is one configuration which 29 * must impose a more careful limit, to avoid freeing kernel pgtables. 30 */ 31 #ifndef USER_PGTABLES_CEILING 32 #define USER_PGTABLES_CEILING 0UL 33 #endif 34 35 /* 36 * This defines the first usable user address. Platforms 37 * can override its value with custom FIRST_USER_ADDRESS 38 * defined in their respective <asm/pgtable.h>. 39 */ 40 #ifndef FIRST_USER_ADDRESS 41 #define FIRST_USER_ADDRESS 0UL 42 #endif 43 44 /* 45 * This defines the generic helper for accessing PMD page 46 * table page. Although platforms can still override this 47 * via their respective <asm/pgtable.h>. 48 */ 49 #ifndef pmd_pgtable 50 #define pmd_pgtable(pmd) pmd_page(pmd) 51 #endif 52 53 #define pmd_folio(pmd) page_folio(pmd_page(pmd)) 54 55 /* 56 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 57 * 58 * The pXx_index() functions return the index of the entry in the page 59 * table page which would control the given virtual address 60 * 61 * As these functions may be used by the same code for different levels of 62 * the page table folding, they are always available, regardless of 63 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 64 * because in such cases PTRS_PER_PxD equals 1. 65 */ 66 67 static inline unsigned long pte_index(unsigned long address) 68 { 69 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 70 } 71 72 #ifndef pmd_index 73 static inline unsigned long pmd_index(unsigned long address) 74 { 75 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 76 } 77 #define pmd_index pmd_index 78 #endif 79 80 #ifndef pud_index 81 static inline unsigned long pud_index(unsigned long address) 82 { 83 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 84 } 85 #define pud_index pud_index 86 #endif 87 88 #ifndef pgd_index 89 /* Must be a compile-time constant, so implement it as a macro */ 90 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 91 #endif 92 93 #ifndef kernel_pte_init 94 static inline void kernel_pte_init(void *addr) 95 { 96 } 97 #define kernel_pte_init kernel_pte_init 98 #endif 99 100 #ifndef pmd_init 101 static inline void pmd_init(void *addr) 102 { 103 } 104 #define pmd_init pmd_init 105 #endif 106 107 #ifndef pud_init 108 static inline void pud_init(void *addr) 109 { 110 } 111 #define pud_init pud_init 112 #endif 113 114 #ifndef pte_offset_kernel 115 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 116 { 117 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 118 } 119 #define pte_offset_kernel pte_offset_kernel 120 #endif 121 122 #ifdef CONFIG_HIGHPTE 123 #define __pte_map(pmd, address) \ 124 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address))) 125 #define pte_unmap(pte) do { \ 126 kunmap_local((pte)); \ 127 rcu_read_unlock(); \ 128 } while (0) 129 #else 130 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address) 131 { 132 return pte_offset_kernel(pmd, address); 133 } 134 static inline void pte_unmap(pte_t *pte) 135 { 136 rcu_read_unlock(); 137 } 138 #endif 139 140 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable); 141 142 /* Find an entry in the second-level page table.. */ 143 #ifndef pmd_offset 144 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 145 { 146 return pud_pgtable(*pud) + pmd_index(address); 147 } 148 #define pmd_offset pmd_offset 149 #endif 150 151 #ifndef pud_offset 152 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 153 { 154 return p4d_pgtable(*p4d) + pud_index(address); 155 } 156 #define pud_offset pud_offset 157 #endif 158 159 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 160 { 161 return (pgd + pgd_index(address)); 162 }; 163 164 /* 165 * a shortcut to get a pgd_t in a given mm 166 */ 167 #ifndef pgd_offset 168 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 169 #endif 170 171 /* 172 * a shortcut which implies the use of the kernel's pgd, instead 173 * of a process's 174 */ 175 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 176 177 /* 178 * In many cases it is known that a virtual address is mapped at PMD or PTE 179 * level, so instead of traversing all the page table levels, we can get a 180 * pointer to the PMD entry in user or kernel page table or translate a virtual 181 * address to the pointer in the PTE in the kernel page tables with simple 182 * helpers. 183 */ 184 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 185 { 186 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 187 } 188 189 static inline pmd_t *pmd_off_k(unsigned long va) 190 { 191 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 192 } 193 194 static inline pte_t *virt_to_kpte(unsigned long vaddr) 195 { 196 pmd_t *pmd = pmd_off_k(vaddr); 197 198 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 199 } 200 201 #ifndef pmd_young 202 static inline int pmd_young(pmd_t pmd) 203 { 204 return 0; 205 } 206 #endif 207 208 #ifndef pmd_dirty 209 static inline int pmd_dirty(pmd_t pmd) 210 { 211 return 0; 212 } 213 #endif 214 215 /* 216 * A facility to provide lazy MMU batching. This allows PTE updates and 217 * page invalidations to be delayed until a call to leave lazy MMU mode 218 * is issued. Some architectures may benefit from doing this, and it is 219 * beneficial for both shadow and direct mode hypervisors, which may batch 220 * the PTE updates which happen during this window. Note that using this 221 * interface requires that read hazards be removed from the code. A read 222 * hazard could result in the direct mode hypervisor case, since the actual 223 * write to the page tables may not yet have taken place, so reads though 224 * a raw PTE pointer after it has been modified are not guaranteed to be 225 * up to date. This mode can only be entered and left under the protection of 226 * the page table locks for all page tables which may be modified. In the UP 227 * case, this is required so that preemption is disabled, and in the SMP case, 228 * it must synchronize the delayed page table writes properly on other CPUs. 229 */ 230 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 231 #define arch_enter_lazy_mmu_mode() do {} while (0) 232 #define arch_leave_lazy_mmu_mode() do {} while (0) 233 #define arch_flush_lazy_mmu_mode() do {} while (0) 234 #endif 235 236 #ifndef pte_batch_hint 237 /** 238 * pte_batch_hint - Number of pages that can be added to batch without scanning. 239 * @ptep: Page table pointer for the entry. 240 * @pte: Page table entry. 241 * 242 * Some architectures know that a set of contiguous ptes all map the same 243 * contiguous memory with the same permissions. In this case, it can provide a 244 * hint to aid pte batching without the core code needing to scan every pte. 245 * 246 * An architecture implementation may ignore the PTE accessed state. Further, 247 * the dirty state must apply atomically to all the PTEs described by the hint. 248 * 249 * May be overridden by the architecture, else pte_batch_hint is always 1. 250 */ 251 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 252 { 253 return 1; 254 } 255 #endif 256 257 #ifndef pte_advance_pfn 258 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 259 { 260 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 261 } 262 #endif 263 264 #define pte_next_pfn(pte) pte_advance_pfn(pte, 1) 265 266 #ifndef set_ptes 267 /** 268 * set_ptes - Map consecutive pages to a contiguous range of addresses. 269 * @mm: Address space to map the pages into. 270 * @addr: Address to map the first page at. 271 * @ptep: Page table pointer for the first entry. 272 * @pte: Page table entry for the first page. 273 * @nr: Number of pages to map. 274 * 275 * When nr==1, initial state of pte may be present or not present, and new state 276 * may be present or not present. When nr>1, initial state of all ptes must be 277 * not present, and new state must be present. 278 * 279 * May be overridden by the architecture, or the architecture can define 280 * set_pte() and PFN_PTE_SHIFT. 281 * 282 * Context: The caller holds the page table lock. The pages all belong 283 * to the same folio. The PTEs are all in the same PMD. 284 */ 285 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 286 pte_t *ptep, pte_t pte, unsigned int nr) 287 { 288 page_table_check_ptes_set(mm, ptep, pte, nr); 289 290 arch_enter_lazy_mmu_mode(); 291 for (;;) { 292 set_pte(ptep, pte); 293 if (--nr == 0) 294 break; 295 ptep++; 296 pte = pte_next_pfn(pte); 297 } 298 arch_leave_lazy_mmu_mode(); 299 } 300 #endif 301 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) 302 303 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 304 extern int ptep_set_access_flags(struct vm_area_struct *vma, 305 unsigned long address, pte_t *ptep, 306 pte_t entry, int dirty); 307 #endif 308 309 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 310 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 311 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 312 unsigned long address, pmd_t *pmdp, 313 pmd_t entry, int dirty); 314 extern int pudp_set_access_flags(struct vm_area_struct *vma, 315 unsigned long address, pud_t *pudp, 316 pud_t entry, int dirty); 317 #else 318 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 319 unsigned long address, pmd_t *pmdp, 320 pmd_t entry, int dirty) 321 { 322 BUILD_BUG(); 323 return 0; 324 } 325 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 326 unsigned long address, pud_t *pudp, 327 pud_t entry, int dirty) 328 { 329 BUILD_BUG(); 330 return 0; 331 } 332 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 333 #endif 334 335 #ifndef ptep_get 336 static inline pte_t ptep_get(pte_t *ptep) 337 { 338 return READ_ONCE(*ptep); 339 } 340 #endif 341 342 #ifndef pmdp_get 343 static inline pmd_t pmdp_get(pmd_t *pmdp) 344 { 345 return READ_ONCE(*pmdp); 346 } 347 #endif 348 349 #ifndef pudp_get 350 static inline pud_t pudp_get(pud_t *pudp) 351 { 352 return READ_ONCE(*pudp); 353 } 354 #endif 355 356 #ifndef p4dp_get 357 static inline p4d_t p4dp_get(p4d_t *p4dp) 358 { 359 return READ_ONCE(*p4dp); 360 } 361 #endif 362 363 #ifndef pgdp_get 364 static inline pgd_t pgdp_get(pgd_t *pgdp) 365 { 366 return READ_ONCE(*pgdp); 367 } 368 #endif 369 370 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 371 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 372 unsigned long address, 373 pte_t *ptep) 374 { 375 pte_t pte = ptep_get(ptep); 376 int r = 1; 377 if (!pte_young(pte)) 378 r = 0; 379 else 380 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 381 return r; 382 } 383 #endif 384 385 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 386 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 387 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 388 unsigned long address, 389 pmd_t *pmdp) 390 { 391 pmd_t pmd = *pmdp; 392 int r = 1; 393 if (!pmd_young(pmd)) 394 r = 0; 395 else 396 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 397 return r; 398 } 399 #else 400 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 401 unsigned long address, 402 pmd_t *pmdp) 403 { 404 BUILD_BUG(); 405 return 0; 406 } 407 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 408 #endif 409 410 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 411 int ptep_clear_flush_young(struct vm_area_struct *vma, 412 unsigned long address, pte_t *ptep); 413 #endif 414 415 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 416 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 417 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 418 unsigned long address, pmd_t *pmdp); 419 #else 420 /* 421 * Despite relevant to THP only, this API is called from generic rmap code 422 * under PageTransHuge(), hence needs a dummy implementation for !THP 423 */ 424 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 425 unsigned long address, pmd_t *pmdp) 426 { 427 BUILD_BUG(); 428 return 0; 429 } 430 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 431 #endif 432 433 #ifndef arch_has_hw_nonleaf_pmd_young 434 /* 435 * Return whether the accessed bit in non-leaf PMD entries is supported on the 436 * local CPU. 437 */ 438 static inline bool arch_has_hw_nonleaf_pmd_young(void) 439 { 440 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 441 } 442 #endif 443 444 #ifndef arch_has_hw_pte_young 445 /* 446 * Return whether the accessed bit is supported on the local CPU. 447 * 448 * This stub assumes accessing through an old PTE triggers a page fault. 449 * Architectures that automatically set the access bit should overwrite it. 450 */ 451 static inline bool arch_has_hw_pte_young(void) 452 { 453 return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG); 454 } 455 #endif 456 457 #ifndef arch_check_zapped_pte 458 static inline void arch_check_zapped_pte(struct vm_area_struct *vma, 459 pte_t pte) 460 { 461 } 462 #endif 463 464 #ifndef arch_check_zapped_pmd 465 static inline void arch_check_zapped_pmd(struct vm_area_struct *vma, 466 pmd_t pmd) 467 { 468 } 469 #endif 470 471 #ifndef arch_check_zapped_pud 472 static inline void arch_check_zapped_pud(struct vm_area_struct *vma, pud_t pud) 473 { 474 } 475 #endif 476 477 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 478 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 479 unsigned long address, 480 pte_t *ptep) 481 { 482 pte_t pte = ptep_get(ptep); 483 pte_clear(mm, address, ptep); 484 page_table_check_pte_clear(mm, pte); 485 return pte; 486 } 487 #endif 488 489 #ifndef clear_young_dirty_ptes 490 /** 491 * clear_young_dirty_ptes - Mark PTEs that map consecutive pages of the 492 * same folio as old/clean. 493 * @mm: Address space the pages are mapped into. 494 * @addr: Address the first page is mapped at. 495 * @ptep: Page table pointer for the first entry. 496 * @nr: Number of entries to mark old/clean. 497 * @flags: Flags to modify the PTE batch semantics. 498 * 499 * May be overridden by the architecture; otherwise, implemented by 500 * get_and_clear/modify/set for each pte in the range. 501 * 502 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 503 * some PTEs might be write-protected. 504 * 505 * Context: The caller holds the page table lock. The PTEs map consecutive 506 * pages that belong to the same folio. The PTEs are all in the same PMD. 507 */ 508 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 509 unsigned long addr, pte_t *ptep, 510 unsigned int nr, cydp_t flags) 511 { 512 pte_t pte; 513 514 for (;;) { 515 if (flags == CYDP_CLEAR_YOUNG) 516 ptep_test_and_clear_young(vma, addr, ptep); 517 else { 518 pte = ptep_get_and_clear(vma->vm_mm, addr, ptep); 519 if (flags & CYDP_CLEAR_YOUNG) 520 pte = pte_mkold(pte); 521 if (flags & CYDP_CLEAR_DIRTY) 522 pte = pte_mkclean(pte); 523 set_pte_at(vma->vm_mm, addr, ptep, pte); 524 } 525 if (--nr == 0) 526 break; 527 ptep++; 528 addr += PAGE_SIZE; 529 } 530 } 531 #endif 532 533 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 534 pte_t *ptep) 535 { 536 ptep_get_and_clear(mm, addr, ptep); 537 } 538 539 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH 540 /* 541 * For walking the pagetables without holding any locks. Some architectures 542 * (eg x86-32 PAE) cannot load the entries atomically without using expensive 543 * instructions. We are guaranteed that a PTE will only either go from not 544 * present to present, or present to not present -- it will not switch to a 545 * completely different present page without a TLB flush inbetween; which we 546 * are blocking by holding interrupts off. 547 * 548 * Setting ptes from not present to present goes: 549 * 550 * ptep->pte_high = h; 551 * smp_wmb(); 552 * ptep->pte_low = l; 553 * 554 * And present to not present goes: 555 * 556 * ptep->pte_low = 0; 557 * smp_wmb(); 558 * ptep->pte_high = 0; 559 * 560 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 561 * We load pte_high *after* loading pte_low, which ensures we don't see an older 562 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 563 * picked up a changed pte high. We might have gotten rubbish values from 564 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 565 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 566 * operates on present ptes we're safe. 567 */ 568 static inline pte_t ptep_get_lockless(pte_t *ptep) 569 { 570 pte_t pte; 571 572 do { 573 pte.pte_low = ptep->pte_low; 574 smp_rmb(); 575 pte.pte_high = ptep->pte_high; 576 smp_rmb(); 577 } while (unlikely(pte.pte_low != ptep->pte_low)); 578 579 return pte; 580 } 581 #define ptep_get_lockless ptep_get_lockless 582 583 #if CONFIG_PGTABLE_LEVELS > 2 584 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 585 { 586 pmd_t pmd; 587 588 do { 589 pmd.pmd_low = pmdp->pmd_low; 590 smp_rmb(); 591 pmd.pmd_high = pmdp->pmd_high; 592 smp_rmb(); 593 } while (unlikely(pmd.pmd_low != pmdp->pmd_low)); 594 595 return pmd; 596 } 597 #define pmdp_get_lockless pmdp_get_lockless 598 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one() 599 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 600 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */ 601 602 /* 603 * We require that the PTE can be read atomically. 604 */ 605 #ifndef ptep_get_lockless 606 static inline pte_t ptep_get_lockless(pte_t *ptep) 607 { 608 return ptep_get(ptep); 609 } 610 #endif 611 612 #ifndef pmdp_get_lockless 613 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 614 { 615 return pmdp_get(pmdp); 616 } 617 static inline void pmdp_get_lockless_sync(void) 618 { 619 } 620 #endif 621 622 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 623 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 624 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 625 unsigned long address, 626 pmd_t *pmdp) 627 { 628 pmd_t pmd = *pmdp; 629 630 pmd_clear(pmdp); 631 page_table_check_pmd_clear(mm, pmd); 632 633 return pmd; 634 } 635 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 636 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 637 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 638 unsigned long address, 639 pud_t *pudp) 640 { 641 pud_t pud = *pudp; 642 643 pud_clear(pudp); 644 page_table_check_pud_clear(mm, pud); 645 646 return pud; 647 } 648 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 649 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 650 651 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 652 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 653 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 654 unsigned long address, pmd_t *pmdp, 655 int full) 656 { 657 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 658 } 659 #endif 660 661 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 662 static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 663 unsigned long address, pud_t *pudp, 664 int full) 665 { 666 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp); 667 } 668 #endif 669 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 670 671 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 672 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 673 unsigned long address, pte_t *ptep, 674 int full) 675 { 676 return ptep_get_and_clear(mm, address, ptep); 677 } 678 #endif 679 680 #ifndef get_and_clear_full_ptes 681 /** 682 * get_and_clear_full_ptes - Clear present PTEs that map consecutive pages of 683 * the same folio, collecting dirty/accessed bits. 684 * @mm: Address space the pages are mapped into. 685 * @addr: Address the first page is mapped at. 686 * @ptep: Page table pointer for the first entry. 687 * @nr: Number of entries to clear. 688 * @full: Whether we are clearing a full mm. 689 * 690 * May be overridden by the architecture; otherwise, implemented as a simple 691 * loop over ptep_get_and_clear_full(), merging dirty/accessed bits into the 692 * returned PTE. 693 * 694 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 695 * some PTEs might be write-protected. 696 * 697 * Context: The caller holds the page table lock. The PTEs map consecutive 698 * pages that belong to the same folio. The PTEs are all in the same PMD. 699 */ 700 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 701 unsigned long addr, pte_t *ptep, unsigned int nr, int full) 702 { 703 pte_t pte, tmp_pte; 704 705 pte = ptep_get_and_clear_full(mm, addr, ptep, full); 706 while (--nr) { 707 ptep++; 708 addr += PAGE_SIZE; 709 tmp_pte = ptep_get_and_clear_full(mm, addr, ptep, full); 710 if (pte_dirty(tmp_pte)) 711 pte = pte_mkdirty(pte); 712 if (pte_young(tmp_pte)) 713 pte = pte_mkyoung(pte); 714 } 715 return pte; 716 } 717 #endif 718 719 #ifndef clear_full_ptes 720 /** 721 * clear_full_ptes - Clear present PTEs that map consecutive pages of the same 722 * folio. 723 * @mm: Address space the pages are mapped into. 724 * @addr: Address the first page is mapped at. 725 * @ptep: Page table pointer for the first entry. 726 * @nr: Number of entries to clear. 727 * @full: Whether we are clearing a full mm. 728 * 729 * May be overridden by the architecture; otherwise, implemented as a simple 730 * loop over ptep_get_and_clear_full(). 731 * 732 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 733 * some PTEs might be write-protected. 734 * 735 * Context: The caller holds the page table lock. The PTEs map consecutive 736 * pages that belong to the same folio. The PTEs are all in the same PMD. 737 */ 738 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 739 pte_t *ptep, unsigned int nr, int full) 740 { 741 for (;;) { 742 ptep_get_and_clear_full(mm, addr, ptep, full); 743 if (--nr == 0) 744 break; 745 ptep++; 746 addr += PAGE_SIZE; 747 } 748 } 749 #endif 750 751 /* 752 * If two threads concurrently fault at the same page, the thread that 753 * won the race updates the PTE and its local TLB/Cache. The other thread 754 * gives up, simply does nothing, and continues; on architectures where 755 * software can update TLB, local TLB can be updated here to avoid next page 756 * fault. This function updates TLB only, do nothing with cache or others. 757 * It is the difference with function update_mmu_cache. 758 */ 759 #ifndef update_mmu_tlb_range 760 static inline void update_mmu_tlb_range(struct vm_area_struct *vma, 761 unsigned long address, pte_t *ptep, unsigned int nr) 762 { 763 } 764 #endif 765 766 static inline void update_mmu_tlb(struct vm_area_struct *vma, 767 unsigned long address, pte_t *ptep) 768 { 769 update_mmu_tlb_range(vma, address, ptep, 1); 770 } 771 772 /* 773 * Some architectures may be able to avoid expensive synchronization 774 * primitives when modifications are made to PTE's which are already 775 * not present, or in the process of an address space destruction. 776 */ 777 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 778 static inline void pte_clear_not_present_full(struct mm_struct *mm, 779 unsigned long address, 780 pte_t *ptep, 781 int full) 782 { 783 pte_clear(mm, address, ptep); 784 } 785 #endif 786 787 #ifndef clear_not_present_full_ptes 788 /** 789 * clear_not_present_full_ptes - Clear multiple not present PTEs which are 790 * consecutive in the pgtable. 791 * @mm: Address space the ptes represent. 792 * @addr: Address of the first pte. 793 * @ptep: Page table pointer for the first entry. 794 * @nr: Number of entries to clear. 795 * @full: Whether we are clearing a full mm. 796 * 797 * May be overridden by the architecture; otherwise, implemented as a simple 798 * loop over pte_clear_not_present_full(). 799 * 800 * Context: The caller holds the page table lock. The PTEs are all not present. 801 * The PTEs are all in the same PMD. 802 */ 803 static inline void clear_not_present_full_ptes(struct mm_struct *mm, 804 unsigned long addr, pte_t *ptep, unsigned int nr, int full) 805 { 806 for (;;) { 807 pte_clear_not_present_full(mm, addr, ptep, full); 808 if (--nr == 0) 809 break; 810 ptep++; 811 addr += PAGE_SIZE; 812 } 813 } 814 #endif 815 816 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 817 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 818 unsigned long address, 819 pte_t *ptep); 820 #endif 821 822 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 823 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 824 unsigned long address, 825 pmd_t *pmdp); 826 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 827 unsigned long address, 828 pud_t *pudp); 829 #endif 830 831 #ifndef pte_mkwrite 832 static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma) 833 { 834 return pte_mkwrite_novma(pte); 835 } 836 #endif 837 838 #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite) 839 static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma) 840 { 841 return pmd_mkwrite_novma(pmd); 842 } 843 #endif 844 845 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 846 struct mm_struct; 847 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 848 { 849 pte_t old_pte = ptep_get(ptep); 850 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 851 } 852 #endif 853 854 #ifndef wrprotect_ptes 855 /** 856 * wrprotect_ptes - Write-protect PTEs that map consecutive pages of the same 857 * folio. 858 * @mm: Address space the pages are mapped into. 859 * @addr: Address the first page is mapped at. 860 * @ptep: Page table pointer for the first entry. 861 * @nr: Number of entries to write-protect. 862 * 863 * May be overridden by the architecture; otherwise, implemented as a simple 864 * loop over ptep_set_wrprotect(). 865 * 866 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 867 * some PTEs might be write-protected. 868 * 869 * Context: The caller holds the page table lock. The PTEs map consecutive 870 * pages that belong to the same folio. The PTEs are all in the same PMD. 871 */ 872 static inline void wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 873 pte_t *ptep, unsigned int nr) 874 { 875 for (;;) { 876 ptep_set_wrprotect(mm, addr, ptep); 877 if (--nr == 0) 878 break; 879 ptep++; 880 addr += PAGE_SIZE; 881 } 882 } 883 #endif 884 885 /* 886 * On some architectures hardware does not set page access bit when accessing 887 * memory page, it is responsibility of software setting this bit. It brings 888 * out extra page fault penalty to track page access bit. For optimization page 889 * access bit can be set during all page fault flow on these arches. 890 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 891 * where software maintains page access bit. 892 */ 893 #ifndef pte_sw_mkyoung 894 static inline pte_t pte_sw_mkyoung(pte_t pte) 895 { 896 return pte; 897 } 898 #define pte_sw_mkyoung pte_sw_mkyoung 899 #endif 900 901 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 902 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 903 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 904 unsigned long address, pmd_t *pmdp) 905 { 906 pmd_t old_pmd = *pmdp; 907 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 908 } 909 #else 910 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 911 unsigned long address, pmd_t *pmdp) 912 { 913 BUILD_BUG(); 914 } 915 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 916 #endif 917 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 918 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 919 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 920 static inline void pudp_set_wrprotect(struct mm_struct *mm, 921 unsigned long address, pud_t *pudp) 922 { 923 pud_t old_pud = *pudp; 924 925 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 926 } 927 #else 928 static inline void pudp_set_wrprotect(struct mm_struct *mm, 929 unsigned long address, pud_t *pudp) 930 { 931 BUILD_BUG(); 932 } 933 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 934 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 935 #endif 936 937 #ifndef pmdp_collapse_flush 938 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 939 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 940 unsigned long address, pmd_t *pmdp); 941 #else 942 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 943 unsigned long address, 944 pmd_t *pmdp) 945 { 946 BUILD_BUG(); 947 return *pmdp; 948 } 949 #define pmdp_collapse_flush pmdp_collapse_flush 950 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 951 #endif 952 953 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 954 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 955 pgtable_t pgtable); 956 #endif 957 958 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 959 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 960 #endif 961 962 #ifndef arch_needs_pgtable_deposit 963 #define arch_needs_pgtable_deposit() (false) 964 #endif 965 966 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 967 /* 968 * This is an implementation of pmdp_establish() that is only suitable for an 969 * architecture that doesn't have hardware dirty/accessed bits. In this case we 970 * can't race with CPU which sets these bits and non-atomic approach is fine. 971 */ 972 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 973 unsigned long address, pmd_t *pmdp, pmd_t pmd) 974 { 975 pmd_t old_pmd = *pmdp; 976 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 977 return old_pmd; 978 } 979 #endif 980 981 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 982 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 983 pmd_t *pmdp); 984 #endif 985 986 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 987 988 /* 989 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 990 * hugepage mapping in the page tables. This function is similar to 991 * pmdp_invalidate(), but should only be used if the access and dirty bits would 992 * not be cleared by the software in the new PMD value. The function ensures 993 * that hardware changes of the access and dirty bits updates would not be lost. 994 * 995 * Doing so can allow in certain architectures to avoid a TLB flush in most 996 * cases. Yet, another TLB flush might be necessary later if the PMD update 997 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 998 * even when a TLB flush is needed because of the update, the caller may be able 999 * to batch these TLB flushing operations, so fewer TLB flush operations are 1000 * needed. 1001 */ 1002 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 1003 unsigned long address, pmd_t *pmdp); 1004 #endif 1005 1006 #ifndef __HAVE_ARCH_PTE_SAME 1007 static inline int pte_same(pte_t pte_a, pte_t pte_b) 1008 { 1009 return pte_val(pte_a) == pte_val(pte_b); 1010 } 1011 #endif 1012 1013 #ifndef __HAVE_ARCH_PTE_UNUSED 1014 /* 1015 * Some architectures provide facilities to virtualization guests 1016 * so that they can flag allocated pages as unused. This allows the 1017 * host to transparently reclaim unused pages. This function returns 1018 * whether the pte's page is unused. 1019 */ 1020 static inline int pte_unused(pte_t pte) 1021 { 1022 return 0; 1023 } 1024 #endif 1025 1026 #ifndef pte_access_permitted 1027 #define pte_access_permitted(pte, write) \ 1028 (pte_present(pte) && (!(write) || pte_write(pte))) 1029 #endif 1030 1031 #ifndef pmd_access_permitted 1032 #define pmd_access_permitted(pmd, write) \ 1033 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 1034 #endif 1035 1036 #ifndef pud_access_permitted 1037 #define pud_access_permitted(pud, write) \ 1038 (pud_present(pud) && (!(write) || pud_write(pud))) 1039 #endif 1040 1041 #ifndef p4d_access_permitted 1042 #define p4d_access_permitted(p4d, write) \ 1043 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 1044 #endif 1045 1046 #ifndef pgd_access_permitted 1047 #define pgd_access_permitted(pgd, write) \ 1048 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 1049 #endif 1050 1051 #ifndef __HAVE_ARCH_PMD_SAME 1052 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1053 { 1054 return pmd_val(pmd_a) == pmd_val(pmd_b); 1055 } 1056 #endif 1057 1058 #ifndef pud_same 1059 static inline int pud_same(pud_t pud_a, pud_t pud_b) 1060 { 1061 return pud_val(pud_a) == pud_val(pud_b); 1062 } 1063 #define pud_same pud_same 1064 #endif 1065 1066 #ifndef __HAVE_ARCH_P4D_SAME 1067 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 1068 { 1069 return p4d_val(p4d_a) == p4d_val(p4d_b); 1070 } 1071 #endif 1072 1073 #ifndef __HAVE_ARCH_PGD_SAME 1074 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 1075 { 1076 return pgd_val(pgd_a) == pgd_val(pgd_b); 1077 } 1078 #endif 1079 1080 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 1081 static inline void arch_do_swap_page_nr(struct mm_struct *mm, 1082 struct vm_area_struct *vma, 1083 unsigned long addr, 1084 pte_t pte, pte_t oldpte, 1085 int nr) 1086 { 1087 1088 } 1089 #else 1090 /* 1091 * Some architectures support metadata associated with a page. When a 1092 * page is being swapped out, this metadata must be saved so it can be 1093 * restored when the page is swapped back in. SPARC M7 and newer 1094 * processors support an ADI (Application Data Integrity) tag for the 1095 * page as metadata for the page. arch_do_swap_page() can restore this 1096 * metadata when a page is swapped back in. 1097 */ 1098 static inline void arch_do_swap_page_nr(struct mm_struct *mm, 1099 struct vm_area_struct *vma, 1100 unsigned long addr, 1101 pte_t pte, pte_t oldpte, 1102 int nr) 1103 { 1104 for (int i = 0; i < nr; i++) { 1105 arch_do_swap_page(vma->vm_mm, vma, addr + i * PAGE_SIZE, 1106 pte_advance_pfn(pte, i), 1107 pte_advance_pfn(oldpte, i)); 1108 } 1109 } 1110 #endif 1111 1112 #ifndef __HAVE_ARCH_UNMAP_ONE 1113 /* 1114 * Some architectures support metadata associated with a page. When a 1115 * page is being swapped out, this metadata must be saved so it can be 1116 * restored when the page is swapped back in. SPARC M7 and newer 1117 * processors support an ADI (Application Data Integrity) tag for the 1118 * page as metadata for the page. arch_unmap_one() can save this 1119 * metadata on a swap-out of a page. 1120 */ 1121 static inline int arch_unmap_one(struct mm_struct *mm, 1122 struct vm_area_struct *vma, 1123 unsigned long addr, 1124 pte_t orig_pte) 1125 { 1126 return 0; 1127 } 1128 #endif 1129 1130 /* 1131 * Allow architectures to preserve additional metadata associated with 1132 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 1133 * prototypes must be defined in the arch-specific asm/pgtable.h file. 1134 */ 1135 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 1136 static inline int arch_prepare_to_swap(struct folio *folio) 1137 { 1138 return 0; 1139 } 1140 #endif 1141 1142 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 1143 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1144 { 1145 } 1146 1147 static inline void arch_swap_invalidate_area(int type) 1148 { 1149 } 1150 #endif 1151 1152 #ifndef __HAVE_ARCH_SWAP_RESTORE 1153 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1154 { 1155 } 1156 #endif 1157 1158 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 1159 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 1160 #endif 1161 1162 #ifndef __HAVE_ARCH_MOVE_PTE 1163 #define move_pte(pte, old_addr, new_addr) (pte) 1164 #endif 1165 1166 #ifndef pte_accessible 1167 # define pte_accessible(mm, pte) ((void)(pte), 1) 1168 #endif 1169 1170 #ifndef flush_tlb_fix_spurious_fault 1171 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address) 1172 #endif 1173 1174 /* 1175 * When walking page tables, get the address of the next boundary, 1176 * or the end address of the range if that comes earlier. Although no 1177 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 1178 */ 1179 1180 #define pgd_addr_end(addr, end) \ 1181 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 1182 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1183 }) 1184 1185 #ifndef p4d_addr_end 1186 #define p4d_addr_end(addr, end) \ 1187 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 1188 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1189 }) 1190 #endif 1191 1192 #ifndef pud_addr_end 1193 #define pud_addr_end(addr, end) \ 1194 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 1195 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1196 }) 1197 #endif 1198 1199 #ifndef pmd_addr_end 1200 #define pmd_addr_end(addr, end) \ 1201 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 1202 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1203 }) 1204 #endif 1205 1206 /* 1207 * When walking page tables, we usually want to skip any p?d_none entries; 1208 * and any p?d_bad entries - reporting the error before resetting to none. 1209 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 1210 */ 1211 void pgd_clear_bad(pgd_t *); 1212 1213 #ifndef __PAGETABLE_P4D_FOLDED 1214 void p4d_clear_bad(p4d_t *); 1215 #else 1216 #define p4d_clear_bad(p4d) do { } while (0) 1217 #endif 1218 1219 #ifndef __PAGETABLE_PUD_FOLDED 1220 void pud_clear_bad(pud_t *); 1221 #else 1222 #define pud_clear_bad(p4d) do { } while (0) 1223 #endif 1224 1225 void pmd_clear_bad(pmd_t *); 1226 1227 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 1228 { 1229 if (pgd_none(*pgd)) 1230 return 1; 1231 if (unlikely(pgd_bad(*pgd))) { 1232 pgd_clear_bad(pgd); 1233 return 1; 1234 } 1235 return 0; 1236 } 1237 1238 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 1239 { 1240 if (p4d_none(*p4d)) 1241 return 1; 1242 if (unlikely(p4d_bad(*p4d))) { 1243 p4d_clear_bad(p4d); 1244 return 1; 1245 } 1246 return 0; 1247 } 1248 1249 static inline int pud_none_or_clear_bad(pud_t *pud) 1250 { 1251 if (pud_none(*pud)) 1252 return 1; 1253 if (unlikely(pud_bad(*pud))) { 1254 pud_clear_bad(pud); 1255 return 1; 1256 } 1257 return 0; 1258 } 1259 1260 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 1261 { 1262 if (pmd_none(*pmd)) 1263 return 1; 1264 if (unlikely(pmd_bad(*pmd))) { 1265 pmd_clear_bad(pmd); 1266 return 1; 1267 } 1268 return 0; 1269 } 1270 1271 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 1272 unsigned long addr, 1273 pte_t *ptep) 1274 { 1275 /* 1276 * Get the current pte state, but zero it out to make it 1277 * non-present, preventing the hardware from asynchronously 1278 * updating it. 1279 */ 1280 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 1281 } 1282 1283 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 1284 unsigned long addr, 1285 pte_t *ptep, pte_t pte) 1286 { 1287 /* 1288 * The pte is non-present, so there's no hardware state to 1289 * preserve. 1290 */ 1291 set_pte_at(vma->vm_mm, addr, ptep, pte); 1292 } 1293 1294 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1295 /* 1296 * Start a pte protection read-modify-write transaction, which 1297 * protects against asynchronous hardware modifications to the pte. 1298 * The intention is not to prevent the hardware from making pte 1299 * updates, but to prevent any updates it may make from being lost. 1300 * 1301 * This does not protect against other software modifications of the 1302 * pte; the appropriate pte lock must be held over the transaction. 1303 * 1304 * Note that this interface is intended to be batchable, meaning that 1305 * ptep_modify_prot_commit may not actually update the pte, but merely 1306 * queue the update to be done at some later time. The update must be 1307 * actually committed before the pte lock is released, however. 1308 */ 1309 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1310 unsigned long addr, 1311 pte_t *ptep) 1312 { 1313 return __ptep_modify_prot_start(vma, addr, ptep); 1314 } 1315 1316 /* 1317 * Commit an update to a pte, leaving any hardware-controlled bits in 1318 * the PTE unmodified. 1319 */ 1320 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 1321 unsigned long addr, 1322 pte_t *ptep, pte_t old_pte, pte_t pte) 1323 { 1324 __ptep_modify_prot_commit(vma, addr, ptep, pte); 1325 } 1326 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 1327 #endif /* CONFIG_MMU */ 1328 1329 /* 1330 * No-op macros that just return the current protection value. Defined here 1331 * because these macros can be used even if CONFIG_MMU is not defined. 1332 */ 1333 1334 #ifndef pgprot_nx 1335 #define pgprot_nx(prot) (prot) 1336 #endif 1337 1338 #ifndef pgprot_noncached 1339 #define pgprot_noncached(prot) (prot) 1340 #endif 1341 1342 #ifndef pgprot_writecombine 1343 #define pgprot_writecombine pgprot_noncached 1344 #endif 1345 1346 #ifndef pgprot_writethrough 1347 #define pgprot_writethrough pgprot_noncached 1348 #endif 1349 1350 #ifndef pgprot_device 1351 #define pgprot_device pgprot_noncached 1352 #endif 1353 1354 #ifndef pgprot_mhp 1355 #define pgprot_mhp(prot) (prot) 1356 #endif 1357 1358 #ifdef CONFIG_MMU 1359 #ifndef pgprot_modify 1360 #define pgprot_modify pgprot_modify 1361 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 1362 { 1363 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 1364 newprot = pgprot_noncached(newprot); 1365 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 1366 newprot = pgprot_writecombine(newprot); 1367 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 1368 newprot = pgprot_device(newprot); 1369 return newprot; 1370 } 1371 #endif 1372 #endif /* CONFIG_MMU */ 1373 1374 #ifndef pgprot_encrypted 1375 #define pgprot_encrypted(prot) (prot) 1376 #endif 1377 1378 #ifndef pgprot_decrypted 1379 #define pgprot_decrypted(prot) (prot) 1380 #endif 1381 1382 /* 1383 * A facility to provide batching of the reload of page tables and 1384 * other process state with the actual context switch code for 1385 * paravirtualized guests. By convention, only one of the batched 1386 * update (lazy) modes (CPU, MMU) should be active at any given time, 1387 * entry should never be nested, and entry and exits should always be 1388 * paired. This is for sanity of maintaining and reasoning about the 1389 * kernel code. In this case, the exit (end of the context switch) is 1390 * in architecture-specific code, and so doesn't need a generic 1391 * definition. 1392 */ 1393 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1394 #define arch_start_context_switch(prev) do {} while (0) 1395 #endif 1396 1397 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1398 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1399 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1400 { 1401 return pmd; 1402 } 1403 1404 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1405 { 1406 return 0; 1407 } 1408 1409 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1410 { 1411 return pmd; 1412 } 1413 #endif 1414 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1415 static inline int pte_soft_dirty(pte_t pte) 1416 { 1417 return 0; 1418 } 1419 1420 static inline int pmd_soft_dirty(pmd_t pmd) 1421 { 1422 return 0; 1423 } 1424 1425 static inline pte_t pte_mksoft_dirty(pte_t pte) 1426 { 1427 return pte; 1428 } 1429 1430 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1431 { 1432 return pmd; 1433 } 1434 1435 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1436 { 1437 return pte; 1438 } 1439 1440 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1441 { 1442 return pmd; 1443 } 1444 1445 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1446 { 1447 return pte; 1448 } 1449 1450 static inline int pte_swp_soft_dirty(pte_t pte) 1451 { 1452 return 0; 1453 } 1454 1455 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1456 { 1457 return pte; 1458 } 1459 1460 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1461 { 1462 return pmd; 1463 } 1464 1465 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1466 { 1467 return 0; 1468 } 1469 1470 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1471 { 1472 return pmd; 1473 } 1474 #endif 1475 1476 #ifndef __HAVE_PFNMAP_TRACKING 1477 /* 1478 * Interfaces that can be used by architecture code to keep track of 1479 * memory type of pfn mappings specified by the remap_pfn_range, 1480 * vmf_insert_pfn. 1481 */ 1482 1483 /* 1484 * track_pfn_remap is called when a _new_ pfn mapping is being established 1485 * by remap_pfn_range() for physical range indicated by pfn and size. 1486 */ 1487 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1488 unsigned long pfn, unsigned long addr, 1489 unsigned long size) 1490 { 1491 return 0; 1492 } 1493 1494 /* 1495 * track_pfn_insert is called when a _new_ single pfn is established 1496 * by vmf_insert_pfn(). 1497 */ 1498 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1499 pfn_t pfn) 1500 { 1501 } 1502 1503 /* 1504 * track_pfn_copy is called when vma that is covering the pfnmap gets 1505 * copied through copy_page_range(). 1506 */ 1507 static inline int track_pfn_copy(struct vm_area_struct *vma) 1508 { 1509 return 0; 1510 } 1511 1512 /* 1513 * untrack_pfn is called while unmapping a pfnmap for a region. 1514 * untrack can be called for a specific region indicated by pfn and size or 1515 * can be for the entire vma (in which case pfn, size are zero). 1516 */ 1517 static inline void untrack_pfn(struct vm_area_struct *vma, 1518 unsigned long pfn, unsigned long size, 1519 bool mm_wr_locked) 1520 { 1521 } 1522 1523 /* 1524 * untrack_pfn_clear is called while mremapping a pfnmap for a new region 1525 * or fails to copy pgtable during duplicate vm area. 1526 */ 1527 static inline void untrack_pfn_clear(struct vm_area_struct *vma) 1528 { 1529 } 1530 #else 1531 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1532 unsigned long pfn, unsigned long addr, 1533 unsigned long size); 1534 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1535 pfn_t pfn); 1536 extern int track_pfn_copy(struct vm_area_struct *vma); 1537 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1538 unsigned long size, bool mm_wr_locked); 1539 extern void untrack_pfn_clear(struct vm_area_struct *vma); 1540 #endif 1541 1542 #ifdef CONFIG_MMU 1543 #ifdef __HAVE_COLOR_ZERO_PAGE 1544 static inline int is_zero_pfn(unsigned long pfn) 1545 { 1546 extern unsigned long zero_pfn; 1547 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1548 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1549 } 1550 1551 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1552 1553 #else 1554 static inline int is_zero_pfn(unsigned long pfn) 1555 { 1556 extern unsigned long zero_pfn; 1557 return pfn == zero_pfn; 1558 } 1559 1560 static inline unsigned long my_zero_pfn(unsigned long addr) 1561 { 1562 extern unsigned long zero_pfn; 1563 return zero_pfn; 1564 } 1565 #endif 1566 #else 1567 static inline int is_zero_pfn(unsigned long pfn) 1568 { 1569 return 0; 1570 } 1571 1572 static inline unsigned long my_zero_pfn(unsigned long addr) 1573 { 1574 return 0; 1575 } 1576 #endif /* CONFIG_MMU */ 1577 1578 #ifdef CONFIG_MMU 1579 1580 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1581 static inline int pmd_trans_huge(pmd_t pmd) 1582 { 1583 return 0; 1584 } 1585 #ifndef pmd_write 1586 static inline int pmd_write(pmd_t pmd) 1587 { 1588 BUG(); 1589 return 0; 1590 } 1591 #endif /* pmd_write */ 1592 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1593 1594 #ifndef pud_write 1595 static inline int pud_write(pud_t pud) 1596 { 1597 BUG(); 1598 return 0; 1599 } 1600 #endif /* pud_write */ 1601 1602 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1603 static inline int pmd_devmap(pmd_t pmd) 1604 { 1605 return 0; 1606 } 1607 static inline int pud_devmap(pud_t pud) 1608 { 1609 return 0; 1610 } 1611 static inline int pgd_devmap(pgd_t pgd) 1612 { 1613 return 0; 1614 } 1615 #endif 1616 1617 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1618 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1619 static inline int pud_trans_huge(pud_t pud) 1620 { 1621 return 0; 1622 } 1623 #endif 1624 1625 static inline int pud_trans_unstable(pud_t *pud) 1626 { 1627 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1628 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1629 pud_t pudval = READ_ONCE(*pud); 1630 1631 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1632 return 1; 1633 if (unlikely(pud_bad(pudval))) { 1634 pud_clear_bad(pud); 1635 return 1; 1636 } 1637 #endif 1638 return 0; 1639 } 1640 1641 #ifndef CONFIG_NUMA_BALANCING 1642 /* 1643 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is 1644 * perfectly valid to indicate "no" in that case, which is why our default 1645 * implementation defaults to "always no". 1646 * 1647 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE 1648 * page protection due to NUMA hinting. NUMA hinting faults only apply in 1649 * accessible VMAs. 1650 * 1651 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault, 1652 * looking at the VMA accessibility is sufficient. 1653 */ 1654 static inline int pte_protnone(pte_t pte) 1655 { 1656 return 0; 1657 } 1658 1659 static inline int pmd_protnone(pmd_t pmd) 1660 { 1661 return 0; 1662 } 1663 #endif /* CONFIG_NUMA_BALANCING */ 1664 1665 #endif /* CONFIG_MMU */ 1666 1667 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1668 1669 #ifndef __PAGETABLE_P4D_FOLDED 1670 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1671 void p4d_clear_huge(p4d_t *p4d); 1672 #else 1673 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1674 { 1675 return 0; 1676 } 1677 static inline void p4d_clear_huge(p4d_t *p4d) { } 1678 #endif /* !__PAGETABLE_P4D_FOLDED */ 1679 1680 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1681 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1682 int pud_clear_huge(pud_t *pud); 1683 int pmd_clear_huge(pmd_t *pmd); 1684 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1685 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1686 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1687 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1688 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1689 { 1690 return 0; 1691 } 1692 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1693 { 1694 return 0; 1695 } 1696 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1697 { 1698 return 0; 1699 } 1700 static inline void p4d_clear_huge(p4d_t *p4d) { } 1701 static inline int pud_clear_huge(pud_t *pud) 1702 { 1703 return 0; 1704 } 1705 static inline int pmd_clear_huge(pmd_t *pmd) 1706 { 1707 return 0; 1708 } 1709 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1710 { 1711 return 0; 1712 } 1713 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1714 { 1715 return 0; 1716 } 1717 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1718 { 1719 return 0; 1720 } 1721 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1722 1723 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1724 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1725 /* 1726 * ARCHes with special requirements for evicting THP backing TLB entries can 1727 * implement this. Otherwise also, it can help optimize normal TLB flush in 1728 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1729 * entire TLB if flush span is greater than a threshold, which will 1730 * likely be true for a single huge page. Thus a single THP flush will 1731 * invalidate the entire TLB which is not desirable. 1732 * e.g. see arch/arc: flush_pmd_tlb_range 1733 */ 1734 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1735 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1736 #else 1737 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1738 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1739 #endif 1740 #endif 1741 1742 struct file; 1743 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1744 unsigned long size, pgprot_t *vma_prot); 1745 1746 #ifndef CONFIG_X86_ESPFIX64 1747 static inline void init_espfix_bsp(void) { } 1748 #endif 1749 1750 extern void __init pgtable_cache_init(void); 1751 1752 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1753 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1754 { 1755 return true; 1756 } 1757 1758 static inline bool arch_has_pfn_modify_check(void) 1759 { 1760 return false; 1761 } 1762 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1763 1764 /* 1765 * Architecture PAGE_KERNEL_* fallbacks 1766 * 1767 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1768 * because they really don't support them, or the port needs to be updated to 1769 * reflect the required functionality. Below are a set of relatively safe 1770 * fallbacks, as best effort, which we can count on in lieu of the architectures 1771 * not defining them on their own yet. 1772 */ 1773 1774 #ifndef PAGE_KERNEL_RO 1775 # define PAGE_KERNEL_RO PAGE_KERNEL 1776 #endif 1777 1778 #ifndef PAGE_KERNEL_EXEC 1779 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1780 #endif 1781 1782 /* 1783 * Page Table Modification bits for pgtbl_mod_mask. 1784 * 1785 * These are used by the p?d_alloc_track*() set of functions an in the generic 1786 * vmalloc/ioremap code to track at which page-table levels entries have been 1787 * modified. Based on that the code can better decide when vmalloc and ioremap 1788 * mapping changes need to be synchronized to other page-tables in the system. 1789 */ 1790 #define __PGTBL_PGD_MODIFIED 0 1791 #define __PGTBL_P4D_MODIFIED 1 1792 #define __PGTBL_PUD_MODIFIED 2 1793 #define __PGTBL_PMD_MODIFIED 3 1794 #define __PGTBL_PTE_MODIFIED 4 1795 1796 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1797 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1798 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1799 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1800 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1801 1802 /* Page-Table Modification Mask */ 1803 typedef unsigned int pgtbl_mod_mask; 1804 1805 #endif /* !__ASSEMBLY__ */ 1806 1807 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1808 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1809 /* 1810 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1811 * with physical address space extension, but falls back to 1812 * BITS_PER_LONG otherwise. 1813 */ 1814 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1815 #else 1816 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1817 #endif 1818 #endif 1819 1820 #ifndef has_transparent_hugepage 1821 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1822 #endif 1823 1824 #ifndef has_transparent_pud_hugepage 1825 #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1826 #endif 1827 /* 1828 * On some architectures it depends on the mm if the p4d/pud or pmd 1829 * layer of the page table hierarchy is folded or not. 1830 */ 1831 #ifndef mm_p4d_folded 1832 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1833 #endif 1834 1835 #ifndef mm_pud_folded 1836 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1837 #endif 1838 1839 #ifndef mm_pmd_folded 1840 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1841 #endif 1842 1843 #ifndef p4d_offset_lockless 1844 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1845 #endif 1846 #ifndef pud_offset_lockless 1847 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1848 #endif 1849 #ifndef pmd_offset_lockless 1850 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1851 #endif 1852 1853 /* 1854 * pXd_leaf() is the API to check whether a pgtable entry is a huge page 1855 * mapping. It should work globally across all archs, without any 1856 * dependency on CONFIG_* options. For architectures that do not support 1857 * huge mappings on specific levels, below fallbacks will be used. 1858 * 1859 * A leaf pgtable entry should always imply the following: 1860 * 1861 * - It is a "present" entry. IOW, before using this API, please check it 1862 * with pXd_present() first. NOTE: it may not always mean the "present 1863 * bit" is set. For example, PROT_NONE entries are always "present". 1864 * 1865 * - It should _never_ be a swap entry of any type. Above "present" check 1866 * should have guarded this, but let's be crystal clear on this. 1867 * 1868 * - It should contain a huge PFN, which points to a huge page larger than 1869 * PAGE_SIZE of the platform. The PFN format isn't important here. 1870 * 1871 * - It should cover all kinds of huge mappings (e.g., pXd_trans_huge(), 1872 * pXd_devmap(), or hugetlb mappings). 1873 */ 1874 #ifndef pgd_leaf 1875 #define pgd_leaf(x) false 1876 #endif 1877 #ifndef p4d_leaf 1878 #define p4d_leaf(x) false 1879 #endif 1880 #ifndef pud_leaf 1881 #define pud_leaf(x) false 1882 #endif 1883 #ifndef pmd_leaf 1884 #define pmd_leaf(x) false 1885 #endif 1886 1887 #ifndef pgd_leaf_size 1888 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1889 #endif 1890 #ifndef p4d_leaf_size 1891 #define p4d_leaf_size(x) P4D_SIZE 1892 #endif 1893 #ifndef pud_leaf_size 1894 #define pud_leaf_size(x) PUD_SIZE 1895 #endif 1896 #ifndef pmd_leaf_size 1897 #define pmd_leaf_size(x) PMD_SIZE 1898 #endif 1899 #ifndef __pte_leaf_size 1900 #ifndef pte_leaf_size 1901 #define pte_leaf_size(x) PAGE_SIZE 1902 #endif 1903 #define __pte_leaf_size(x,y) pte_leaf_size(y) 1904 #endif 1905 1906 /* 1907 * We always define pmd_pfn for all archs as it's used in lots of generic 1908 * code. Now it happens too for pud_pfn (and can happen for larger 1909 * mappings too in the future; we're not there yet). Instead of defining 1910 * it for all archs (like pmd_pfn), provide a fallback. 1911 * 1912 * Note that returning 0 here means any arch that didn't define this can 1913 * get severely wrong when it hits a real pud leaf. It's arch's 1914 * responsibility to properly define it when a huge pud is possible. 1915 */ 1916 #ifndef pud_pfn 1917 #define pud_pfn(x) 0 1918 #endif 1919 1920 /* 1921 * Some architectures have MMUs that are configurable or selectable at boot 1922 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1923 * helps to have a static maximum value. 1924 */ 1925 1926 #ifndef MAX_PTRS_PER_PTE 1927 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1928 #endif 1929 1930 #ifndef MAX_PTRS_PER_PMD 1931 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1932 #endif 1933 1934 #ifndef MAX_PTRS_PER_PUD 1935 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1936 #endif 1937 1938 #ifndef MAX_PTRS_PER_P4D 1939 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1940 #endif 1941 1942 #ifndef pte_pgprot 1943 #define pte_pgprot(x) ((pgprot_t) {0}) 1944 #endif 1945 1946 #ifndef pmd_pgprot 1947 #define pmd_pgprot(x) ((pgprot_t) {0}) 1948 #endif 1949 1950 #ifndef pud_pgprot 1951 #define pud_pgprot(x) ((pgprot_t) {0}) 1952 #endif 1953 1954 /* description of effects of mapping type and prot in current implementation. 1955 * this is due to the limited x86 page protection hardware. The expected 1956 * behavior is in parens: 1957 * 1958 * map_type prot 1959 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1960 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1961 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1962 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1963 * 1964 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1965 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1966 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1967 * 1968 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1969 * MAP_PRIVATE (with Enhanced PAN supported): 1970 * r: (no) no 1971 * w: (no) no 1972 * x: (yes) yes 1973 */ 1974 #define DECLARE_VM_GET_PAGE_PROT \ 1975 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1976 { \ 1977 return protection_map[vm_flags & \ 1978 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1979 } \ 1980 EXPORT_SYMBOL(vm_get_page_prot); 1981 1982 #endif /* _LINUX_PGTABLE_H */ 1983