1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT) 9 #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT) 10 11 #ifndef __ASSEMBLY__ 12 #ifdef CONFIG_MMU 13 14 #include <linux/mm_types.h> 15 #include <linux/bug.h> 16 #include <linux/errno.h> 17 #include <asm-generic/pgtable_uffd.h> 18 #include <linux/page_table_check.h> 19 20 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 22 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 23 #endif 24 25 /* 26 * On almost all architectures and configurations, 0 can be used as the 27 * upper ceiling to free_pgtables(): on many architectures it has the same 28 * effect as using TASK_SIZE. However, there is one configuration which 29 * must impose a more careful limit, to avoid freeing kernel pgtables. 30 */ 31 #ifndef USER_PGTABLES_CEILING 32 #define USER_PGTABLES_CEILING 0UL 33 #endif 34 35 /* 36 * This defines the first usable user address. Platforms 37 * can override its value with custom FIRST_USER_ADDRESS 38 * defined in their respective <asm/pgtable.h>. 39 */ 40 #ifndef FIRST_USER_ADDRESS 41 #define FIRST_USER_ADDRESS 0UL 42 #endif 43 44 /* 45 * This defines the generic helper for accessing PMD page 46 * table page. Although platforms can still override this 47 * via their respective <asm/pgtable.h>. 48 */ 49 #ifndef pmd_pgtable 50 #define pmd_pgtable(pmd) pmd_page(pmd) 51 #endif 52 53 /* 54 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 55 * 56 * The pXx_index() functions return the index of the entry in the page 57 * table page which would control the given virtual address 58 * 59 * As these functions may be used by the same code for different levels of 60 * the page table folding, they are always available, regardless of 61 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 62 * because in such cases PTRS_PER_PxD equals 1. 63 */ 64 65 static inline unsigned long pte_index(unsigned long address) 66 { 67 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 68 } 69 70 #ifndef pmd_index 71 static inline unsigned long pmd_index(unsigned long address) 72 { 73 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 74 } 75 #define pmd_index pmd_index 76 #endif 77 78 #ifndef pud_index 79 static inline unsigned long pud_index(unsigned long address) 80 { 81 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 82 } 83 #define pud_index pud_index 84 #endif 85 86 #ifndef pgd_index 87 /* Must be a compile-time constant, so implement it as a macro */ 88 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 89 #endif 90 91 #ifndef pte_offset_kernel 92 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 93 { 94 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 95 } 96 #define pte_offset_kernel pte_offset_kernel 97 #endif 98 99 #ifdef CONFIG_HIGHPTE 100 #define __pte_map(pmd, address) \ 101 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address))) 102 #define pte_unmap(pte) do { \ 103 kunmap_local((pte)); \ 104 rcu_read_unlock(); \ 105 } while (0) 106 #else 107 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address) 108 { 109 return pte_offset_kernel(pmd, address); 110 } 111 static inline void pte_unmap(pte_t *pte) 112 { 113 rcu_read_unlock(); 114 } 115 #endif 116 117 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable); 118 119 /* Find an entry in the second-level page table.. */ 120 #ifndef pmd_offset 121 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 122 { 123 return pud_pgtable(*pud) + pmd_index(address); 124 } 125 #define pmd_offset pmd_offset 126 #endif 127 128 #ifndef pud_offset 129 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 130 { 131 return p4d_pgtable(*p4d) + pud_index(address); 132 } 133 #define pud_offset pud_offset 134 #endif 135 136 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 137 { 138 return (pgd + pgd_index(address)); 139 }; 140 141 /* 142 * a shortcut to get a pgd_t in a given mm 143 */ 144 #ifndef pgd_offset 145 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 146 #endif 147 148 /* 149 * a shortcut which implies the use of the kernel's pgd, instead 150 * of a process's 151 */ 152 #ifndef pgd_offset_k 153 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 154 #endif 155 156 /* 157 * In many cases it is known that a virtual address is mapped at PMD or PTE 158 * level, so instead of traversing all the page table levels, we can get a 159 * pointer to the PMD entry in user or kernel page table or translate a virtual 160 * address to the pointer in the PTE in the kernel page tables with simple 161 * helpers. 162 */ 163 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 164 { 165 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 166 } 167 168 static inline pmd_t *pmd_off_k(unsigned long va) 169 { 170 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 171 } 172 173 static inline pte_t *virt_to_kpte(unsigned long vaddr) 174 { 175 pmd_t *pmd = pmd_off_k(vaddr); 176 177 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 178 } 179 180 #ifndef pmd_young 181 static inline int pmd_young(pmd_t pmd) 182 { 183 return 0; 184 } 185 #endif 186 187 #ifndef pmd_dirty 188 static inline int pmd_dirty(pmd_t pmd) 189 { 190 return 0; 191 } 192 #endif 193 194 /* 195 * A facility to provide lazy MMU batching. This allows PTE updates and 196 * page invalidations to be delayed until a call to leave lazy MMU mode 197 * is issued. Some architectures may benefit from doing this, and it is 198 * beneficial for both shadow and direct mode hypervisors, which may batch 199 * the PTE updates which happen during this window. Note that using this 200 * interface requires that read hazards be removed from the code. A read 201 * hazard could result in the direct mode hypervisor case, since the actual 202 * write to the page tables may not yet have taken place, so reads though 203 * a raw PTE pointer after it has been modified are not guaranteed to be 204 * up to date. This mode can only be entered and left under the protection of 205 * the page table locks for all page tables which may be modified. In the UP 206 * case, this is required so that preemption is disabled, and in the SMP case, 207 * it must synchronize the delayed page table writes properly on other CPUs. 208 */ 209 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 210 #define arch_enter_lazy_mmu_mode() do {} while (0) 211 #define arch_leave_lazy_mmu_mode() do {} while (0) 212 #define arch_flush_lazy_mmu_mode() do {} while (0) 213 #endif 214 215 #ifndef set_ptes 216 217 #ifndef pte_next_pfn 218 static inline pte_t pte_next_pfn(pte_t pte) 219 { 220 return __pte(pte_val(pte) + (1UL << PFN_PTE_SHIFT)); 221 } 222 #endif 223 224 /** 225 * set_ptes - Map consecutive pages to a contiguous range of addresses. 226 * @mm: Address space to map the pages into. 227 * @addr: Address to map the first page at. 228 * @ptep: Page table pointer for the first entry. 229 * @pte: Page table entry for the first page. 230 * @nr: Number of pages to map. 231 * 232 * May be overridden by the architecture, or the architecture can define 233 * set_pte() and PFN_PTE_SHIFT. 234 * 235 * Context: The caller holds the page table lock. The pages all belong 236 * to the same folio. The PTEs are all in the same PMD. 237 */ 238 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 239 pte_t *ptep, pte_t pte, unsigned int nr) 240 { 241 page_table_check_ptes_set(mm, ptep, pte, nr); 242 243 arch_enter_lazy_mmu_mode(); 244 for (;;) { 245 set_pte(ptep, pte); 246 if (--nr == 0) 247 break; 248 ptep++; 249 pte = pte_next_pfn(pte); 250 } 251 arch_leave_lazy_mmu_mode(); 252 } 253 #endif 254 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) 255 256 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 257 extern int ptep_set_access_flags(struct vm_area_struct *vma, 258 unsigned long address, pte_t *ptep, 259 pte_t entry, int dirty); 260 #endif 261 262 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 263 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 264 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 265 unsigned long address, pmd_t *pmdp, 266 pmd_t entry, int dirty); 267 extern int pudp_set_access_flags(struct vm_area_struct *vma, 268 unsigned long address, pud_t *pudp, 269 pud_t entry, int dirty); 270 #else 271 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 272 unsigned long address, pmd_t *pmdp, 273 pmd_t entry, int dirty) 274 { 275 BUILD_BUG(); 276 return 0; 277 } 278 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 279 unsigned long address, pud_t *pudp, 280 pud_t entry, int dirty) 281 { 282 BUILD_BUG(); 283 return 0; 284 } 285 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 286 #endif 287 288 #ifndef ptep_get 289 static inline pte_t ptep_get(pte_t *ptep) 290 { 291 return READ_ONCE(*ptep); 292 } 293 #endif 294 295 #ifndef pmdp_get 296 static inline pmd_t pmdp_get(pmd_t *pmdp) 297 { 298 return READ_ONCE(*pmdp); 299 } 300 #endif 301 302 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 303 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 304 unsigned long address, 305 pte_t *ptep) 306 { 307 pte_t pte = ptep_get(ptep); 308 int r = 1; 309 if (!pte_young(pte)) 310 r = 0; 311 else 312 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 313 return r; 314 } 315 #endif 316 317 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 318 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 319 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 320 unsigned long address, 321 pmd_t *pmdp) 322 { 323 pmd_t pmd = *pmdp; 324 int r = 1; 325 if (!pmd_young(pmd)) 326 r = 0; 327 else 328 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 329 return r; 330 } 331 #else 332 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 333 unsigned long address, 334 pmd_t *pmdp) 335 { 336 BUILD_BUG(); 337 return 0; 338 } 339 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 340 #endif 341 342 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 343 int ptep_clear_flush_young(struct vm_area_struct *vma, 344 unsigned long address, pte_t *ptep); 345 #endif 346 347 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 348 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 349 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 350 unsigned long address, pmd_t *pmdp); 351 #else 352 /* 353 * Despite relevant to THP only, this API is called from generic rmap code 354 * under PageTransHuge(), hence needs a dummy implementation for !THP 355 */ 356 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 357 unsigned long address, pmd_t *pmdp) 358 { 359 BUILD_BUG(); 360 return 0; 361 } 362 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 363 #endif 364 365 #ifndef arch_has_hw_nonleaf_pmd_young 366 /* 367 * Return whether the accessed bit in non-leaf PMD entries is supported on the 368 * local CPU. 369 */ 370 static inline bool arch_has_hw_nonleaf_pmd_young(void) 371 { 372 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 373 } 374 #endif 375 376 #ifndef arch_has_hw_pte_young 377 /* 378 * Return whether the accessed bit is supported on the local CPU. 379 * 380 * This stub assumes accessing through an old PTE triggers a page fault. 381 * Architectures that automatically set the access bit should overwrite it. 382 */ 383 static inline bool arch_has_hw_pte_young(void) 384 { 385 return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG); 386 } 387 #endif 388 389 #ifndef arch_check_zapped_pte 390 static inline void arch_check_zapped_pte(struct vm_area_struct *vma, 391 pte_t pte) 392 { 393 } 394 #endif 395 396 #ifndef arch_check_zapped_pmd 397 static inline void arch_check_zapped_pmd(struct vm_area_struct *vma, 398 pmd_t pmd) 399 { 400 } 401 #endif 402 403 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 404 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 405 unsigned long address, 406 pte_t *ptep) 407 { 408 pte_t pte = ptep_get(ptep); 409 pte_clear(mm, address, ptep); 410 page_table_check_pte_clear(mm, pte); 411 return pte; 412 } 413 #endif 414 415 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 416 pte_t *ptep) 417 { 418 ptep_get_and_clear(mm, addr, ptep); 419 } 420 421 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH 422 /* 423 * For walking the pagetables without holding any locks. Some architectures 424 * (eg x86-32 PAE) cannot load the entries atomically without using expensive 425 * instructions. We are guaranteed that a PTE will only either go from not 426 * present to present, or present to not present -- it will not switch to a 427 * completely different present page without a TLB flush inbetween; which we 428 * are blocking by holding interrupts off. 429 * 430 * Setting ptes from not present to present goes: 431 * 432 * ptep->pte_high = h; 433 * smp_wmb(); 434 * ptep->pte_low = l; 435 * 436 * And present to not present goes: 437 * 438 * ptep->pte_low = 0; 439 * smp_wmb(); 440 * ptep->pte_high = 0; 441 * 442 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 443 * We load pte_high *after* loading pte_low, which ensures we don't see an older 444 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 445 * picked up a changed pte high. We might have gotten rubbish values from 446 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 447 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 448 * operates on present ptes we're safe. 449 */ 450 static inline pte_t ptep_get_lockless(pte_t *ptep) 451 { 452 pte_t pte; 453 454 do { 455 pte.pte_low = ptep->pte_low; 456 smp_rmb(); 457 pte.pte_high = ptep->pte_high; 458 smp_rmb(); 459 } while (unlikely(pte.pte_low != ptep->pte_low)); 460 461 return pte; 462 } 463 #define ptep_get_lockless ptep_get_lockless 464 465 #if CONFIG_PGTABLE_LEVELS > 2 466 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 467 { 468 pmd_t pmd; 469 470 do { 471 pmd.pmd_low = pmdp->pmd_low; 472 smp_rmb(); 473 pmd.pmd_high = pmdp->pmd_high; 474 smp_rmb(); 475 } while (unlikely(pmd.pmd_low != pmdp->pmd_low)); 476 477 return pmd; 478 } 479 #define pmdp_get_lockless pmdp_get_lockless 480 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one() 481 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 482 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */ 483 484 /* 485 * We require that the PTE can be read atomically. 486 */ 487 #ifndef ptep_get_lockless 488 static inline pte_t ptep_get_lockless(pte_t *ptep) 489 { 490 return ptep_get(ptep); 491 } 492 #endif 493 494 #ifndef pmdp_get_lockless 495 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 496 { 497 return pmdp_get(pmdp); 498 } 499 static inline void pmdp_get_lockless_sync(void) 500 { 501 } 502 #endif 503 504 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 505 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 506 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 507 unsigned long address, 508 pmd_t *pmdp) 509 { 510 pmd_t pmd = *pmdp; 511 512 pmd_clear(pmdp); 513 page_table_check_pmd_clear(mm, pmd); 514 515 return pmd; 516 } 517 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 518 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 519 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 520 unsigned long address, 521 pud_t *pudp) 522 { 523 pud_t pud = *pudp; 524 525 pud_clear(pudp); 526 page_table_check_pud_clear(mm, pud); 527 528 return pud; 529 } 530 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 531 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 532 533 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 534 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 535 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 536 unsigned long address, pmd_t *pmdp, 537 int full) 538 { 539 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 540 } 541 #endif 542 543 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 544 static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 545 unsigned long address, pud_t *pudp, 546 int full) 547 { 548 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp); 549 } 550 #endif 551 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 552 553 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 554 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 555 unsigned long address, pte_t *ptep, 556 int full) 557 { 558 return ptep_get_and_clear(mm, address, ptep); 559 } 560 #endif 561 562 563 /* 564 * If two threads concurrently fault at the same page, the thread that 565 * won the race updates the PTE and its local TLB/Cache. The other thread 566 * gives up, simply does nothing, and continues; on architectures where 567 * software can update TLB, local TLB can be updated here to avoid next page 568 * fault. This function updates TLB only, do nothing with cache or others. 569 * It is the difference with function update_mmu_cache. 570 */ 571 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 572 static inline void update_mmu_tlb(struct vm_area_struct *vma, 573 unsigned long address, pte_t *ptep) 574 { 575 } 576 #define __HAVE_ARCH_UPDATE_MMU_TLB 577 #endif 578 579 /* 580 * Some architectures may be able to avoid expensive synchronization 581 * primitives when modifications are made to PTE's which are already 582 * not present, or in the process of an address space destruction. 583 */ 584 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 585 static inline void pte_clear_not_present_full(struct mm_struct *mm, 586 unsigned long address, 587 pte_t *ptep, 588 int full) 589 { 590 pte_clear(mm, address, ptep); 591 } 592 #endif 593 594 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 595 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 596 unsigned long address, 597 pte_t *ptep); 598 #endif 599 600 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 601 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 602 unsigned long address, 603 pmd_t *pmdp); 604 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 605 unsigned long address, 606 pud_t *pudp); 607 #endif 608 609 #ifndef pte_mkwrite 610 static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma) 611 { 612 return pte_mkwrite_novma(pte); 613 } 614 #endif 615 616 #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite) 617 static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma) 618 { 619 return pmd_mkwrite_novma(pmd); 620 } 621 #endif 622 623 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 624 struct mm_struct; 625 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 626 { 627 pte_t old_pte = ptep_get(ptep); 628 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 629 } 630 #endif 631 632 /* 633 * On some architectures hardware does not set page access bit when accessing 634 * memory page, it is responsibility of software setting this bit. It brings 635 * out extra page fault penalty to track page access bit. For optimization page 636 * access bit can be set during all page fault flow on these arches. 637 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 638 * where software maintains page access bit. 639 */ 640 #ifndef pte_sw_mkyoung 641 static inline pte_t pte_sw_mkyoung(pte_t pte) 642 { 643 return pte; 644 } 645 #define pte_sw_mkyoung pte_sw_mkyoung 646 #endif 647 648 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 649 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 650 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 651 unsigned long address, pmd_t *pmdp) 652 { 653 pmd_t old_pmd = *pmdp; 654 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 655 } 656 #else 657 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 658 unsigned long address, pmd_t *pmdp) 659 { 660 BUILD_BUG(); 661 } 662 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 663 #endif 664 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 665 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 666 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 667 static inline void pudp_set_wrprotect(struct mm_struct *mm, 668 unsigned long address, pud_t *pudp) 669 { 670 pud_t old_pud = *pudp; 671 672 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 673 } 674 #else 675 static inline void pudp_set_wrprotect(struct mm_struct *mm, 676 unsigned long address, pud_t *pudp) 677 { 678 BUILD_BUG(); 679 } 680 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 681 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 682 #endif 683 684 #ifndef pmdp_collapse_flush 685 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 686 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 687 unsigned long address, pmd_t *pmdp); 688 #else 689 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 690 unsigned long address, 691 pmd_t *pmdp) 692 { 693 BUILD_BUG(); 694 return *pmdp; 695 } 696 #define pmdp_collapse_flush pmdp_collapse_flush 697 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 698 #endif 699 700 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 701 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 702 pgtable_t pgtable); 703 #endif 704 705 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 706 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 707 #endif 708 709 #ifndef arch_needs_pgtable_deposit 710 #define arch_needs_pgtable_deposit() (false) 711 #endif 712 713 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 714 /* 715 * This is an implementation of pmdp_establish() that is only suitable for an 716 * architecture that doesn't have hardware dirty/accessed bits. In this case we 717 * can't race with CPU which sets these bits and non-atomic approach is fine. 718 */ 719 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 720 unsigned long address, pmd_t *pmdp, pmd_t pmd) 721 { 722 pmd_t old_pmd = *pmdp; 723 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 724 return old_pmd; 725 } 726 #endif 727 728 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 729 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 730 pmd_t *pmdp); 731 #endif 732 733 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 734 735 /* 736 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 737 * hugepage mapping in the page tables. This function is similar to 738 * pmdp_invalidate(), but should only be used if the access and dirty bits would 739 * not be cleared by the software in the new PMD value. The function ensures 740 * that hardware changes of the access and dirty bits updates would not be lost. 741 * 742 * Doing so can allow in certain architectures to avoid a TLB flush in most 743 * cases. Yet, another TLB flush might be necessary later if the PMD update 744 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 745 * even when a TLB flush is needed because of the update, the caller may be able 746 * to batch these TLB flushing operations, so fewer TLB flush operations are 747 * needed. 748 */ 749 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 750 unsigned long address, pmd_t *pmdp); 751 #endif 752 753 #ifndef __HAVE_ARCH_PTE_SAME 754 static inline int pte_same(pte_t pte_a, pte_t pte_b) 755 { 756 return pte_val(pte_a) == pte_val(pte_b); 757 } 758 #endif 759 760 #ifndef __HAVE_ARCH_PTE_UNUSED 761 /* 762 * Some architectures provide facilities to virtualization guests 763 * so that they can flag allocated pages as unused. This allows the 764 * host to transparently reclaim unused pages. This function returns 765 * whether the pte's page is unused. 766 */ 767 static inline int pte_unused(pte_t pte) 768 { 769 return 0; 770 } 771 #endif 772 773 #ifndef pte_access_permitted 774 #define pte_access_permitted(pte, write) \ 775 (pte_present(pte) && (!(write) || pte_write(pte))) 776 #endif 777 778 #ifndef pmd_access_permitted 779 #define pmd_access_permitted(pmd, write) \ 780 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 781 #endif 782 783 #ifndef pud_access_permitted 784 #define pud_access_permitted(pud, write) \ 785 (pud_present(pud) && (!(write) || pud_write(pud))) 786 #endif 787 788 #ifndef p4d_access_permitted 789 #define p4d_access_permitted(p4d, write) \ 790 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 791 #endif 792 793 #ifndef pgd_access_permitted 794 #define pgd_access_permitted(pgd, write) \ 795 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 796 #endif 797 798 #ifndef __HAVE_ARCH_PMD_SAME 799 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 800 { 801 return pmd_val(pmd_a) == pmd_val(pmd_b); 802 } 803 #endif 804 805 #ifndef pud_same 806 static inline int pud_same(pud_t pud_a, pud_t pud_b) 807 { 808 return pud_val(pud_a) == pud_val(pud_b); 809 } 810 #define pud_same pud_same 811 #endif 812 813 #ifndef __HAVE_ARCH_P4D_SAME 814 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 815 { 816 return p4d_val(p4d_a) == p4d_val(p4d_b); 817 } 818 #endif 819 820 #ifndef __HAVE_ARCH_PGD_SAME 821 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 822 { 823 return pgd_val(pgd_a) == pgd_val(pgd_b); 824 } 825 #endif 826 827 /* 828 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 829 * TLB flush will be required as a result of the "set". For example, use 830 * in scenarios where it is known ahead of time that the routine is 831 * setting non-present entries, or re-setting an existing entry to the 832 * same value. Otherwise, use the typical "set" helpers and flush the 833 * TLB. 834 */ 835 #define set_pte_safe(ptep, pte) \ 836 ({ \ 837 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 838 set_pte(ptep, pte); \ 839 }) 840 841 #define set_pmd_safe(pmdp, pmd) \ 842 ({ \ 843 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 844 set_pmd(pmdp, pmd); \ 845 }) 846 847 #define set_pud_safe(pudp, pud) \ 848 ({ \ 849 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 850 set_pud(pudp, pud); \ 851 }) 852 853 #define set_p4d_safe(p4dp, p4d) \ 854 ({ \ 855 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 856 set_p4d(p4dp, p4d); \ 857 }) 858 859 #define set_pgd_safe(pgdp, pgd) \ 860 ({ \ 861 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 862 set_pgd(pgdp, pgd); \ 863 }) 864 865 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 866 /* 867 * Some architectures support metadata associated with a page. When a 868 * page is being swapped out, this metadata must be saved so it can be 869 * restored when the page is swapped back in. SPARC M7 and newer 870 * processors support an ADI (Application Data Integrity) tag for the 871 * page as metadata for the page. arch_do_swap_page() can restore this 872 * metadata when a page is swapped back in. 873 */ 874 static inline void arch_do_swap_page(struct mm_struct *mm, 875 struct vm_area_struct *vma, 876 unsigned long addr, 877 pte_t pte, pte_t oldpte) 878 { 879 880 } 881 #endif 882 883 #ifndef __HAVE_ARCH_UNMAP_ONE 884 /* 885 * Some architectures support metadata associated with a page. When a 886 * page is being swapped out, this metadata must be saved so it can be 887 * restored when the page is swapped back in. SPARC M7 and newer 888 * processors support an ADI (Application Data Integrity) tag for the 889 * page as metadata for the page. arch_unmap_one() can save this 890 * metadata on a swap-out of a page. 891 */ 892 static inline int arch_unmap_one(struct mm_struct *mm, 893 struct vm_area_struct *vma, 894 unsigned long addr, 895 pte_t orig_pte) 896 { 897 return 0; 898 } 899 #endif 900 901 /* 902 * Allow architectures to preserve additional metadata associated with 903 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 904 * prototypes must be defined in the arch-specific asm/pgtable.h file. 905 */ 906 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 907 static inline int arch_prepare_to_swap(struct page *page) 908 { 909 return 0; 910 } 911 #endif 912 913 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 914 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 915 { 916 } 917 918 static inline void arch_swap_invalidate_area(int type) 919 { 920 } 921 #endif 922 923 #ifndef __HAVE_ARCH_SWAP_RESTORE 924 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 925 { 926 } 927 #endif 928 929 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 930 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 931 #endif 932 933 #ifndef __HAVE_ARCH_MOVE_PTE 934 #define move_pte(pte, prot, old_addr, new_addr) (pte) 935 #endif 936 937 #ifndef pte_accessible 938 # define pte_accessible(mm, pte) ((void)(pte), 1) 939 #endif 940 941 #ifndef flush_tlb_fix_spurious_fault 942 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address) 943 #endif 944 945 /* 946 * When walking page tables, get the address of the next boundary, 947 * or the end address of the range if that comes earlier. Although no 948 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 949 */ 950 951 #define pgd_addr_end(addr, end) \ 952 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 953 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 954 }) 955 956 #ifndef p4d_addr_end 957 #define p4d_addr_end(addr, end) \ 958 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 959 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 960 }) 961 #endif 962 963 #ifndef pud_addr_end 964 #define pud_addr_end(addr, end) \ 965 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 966 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 967 }) 968 #endif 969 970 #ifndef pmd_addr_end 971 #define pmd_addr_end(addr, end) \ 972 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 973 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 974 }) 975 #endif 976 977 /* 978 * When walking page tables, we usually want to skip any p?d_none entries; 979 * and any p?d_bad entries - reporting the error before resetting to none. 980 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 981 */ 982 void pgd_clear_bad(pgd_t *); 983 984 #ifndef __PAGETABLE_P4D_FOLDED 985 void p4d_clear_bad(p4d_t *); 986 #else 987 #define p4d_clear_bad(p4d) do { } while (0) 988 #endif 989 990 #ifndef __PAGETABLE_PUD_FOLDED 991 void pud_clear_bad(pud_t *); 992 #else 993 #define pud_clear_bad(p4d) do { } while (0) 994 #endif 995 996 void pmd_clear_bad(pmd_t *); 997 998 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 999 { 1000 if (pgd_none(*pgd)) 1001 return 1; 1002 if (unlikely(pgd_bad(*pgd))) { 1003 pgd_clear_bad(pgd); 1004 return 1; 1005 } 1006 return 0; 1007 } 1008 1009 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 1010 { 1011 if (p4d_none(*p4d)) 1012 return 1; 1013 if (unlikely(p4d_bad(*p4d))) { 1014 p4d_clear_bad(p4d); 1015 return 1; 1016 } 1017 return 0; 1018 } 1019 1020 static inline int pud_none_or_clear_bad(pud_t *pud) 1021 { 1022 if (pud_none(*pud)) 1023 return 1; 1024 if (unlikely(pud_bad(*pud))) { 1025 pud_clear_bad(pud); 1026 return 1; 1027 } 1028 return 0; 1029 } 1030 1031 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 1032 { 1033 if (pmd_none(*pmd)) 1034 return 1; 1035 if (unlikely(pmd_bad(*pmd))) { 1036 pmd_clear_bad(pmd); 1037 return 1; 1038 } 1039 return 0; 1040 } 1041 1042 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 1043 unsigned long addr, 1044 pte_t *ptep) 1045 { 1046 /* 1047 * Get the current pte state, but zero it out to make it 1048 * non-present, preventing the hardware from asynchronously 1049 * updating it. 1050 */ 1051 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 1052 } 1053 1054 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 1055 unsigned long addr, 1056 pte_t *ptep, pte_t pte) 1057 { 1058 /* 1059 * The pte is non-present, so there's no hardware state to 1060 * preserve. 1061 */ 1062 set_pte_at(vma->vm_mm, addr, ptep, pte); 1063 } 1064 1065 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1066 /* 1067 * Start a pte protection read-modify-write transaction, which 1068 * protects against asynchronous hardware modifications to the pte. 1069 * The intention is not to prevent the hardware from making pte 1070 * updates, but to prevent any updates it may make from being lost. 1071 * 1072 * This does not protect against other software modifications of the 1073 * pte; the appropriate pte lock must be held over the transaction. 1074 * 1075 * Note that this interface is intended to be batchable, meaning that 1076 * ptep_modify_prot_commit may not actually update the pte, but merely 1077 * queue the update to be done at some later time. The update must be 1078 * actually committed before the pte lock is released, however. 1079 */ 1080 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1081 unsigned long addr, 1082 pte_t *ptep) 1083 { 1084 return __ptep_modify_prot_start(vma, addr, ptep); 1085 } 1086 1087 /* 1088 * Commit an update to a pte, leaving any hardware-controlled bits in 1089 * the PTE unmodified. 1090 */ 1091 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 1092 unsigned long addr, 1093 pte_t *ptep, pte_t old_pte, pte_t pte) 1094 { 1095 __ptep_modify_prot_commit(vma, addr, ptep, pte); 1096 } 1097 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 1098 #endif /* CONFIG_MMU */ 1099 1100 /* 1101 * No-op macros that just return the current protection value. Defined here 1102 * because these macros can be used even if CONFIG_MMU is not defined. 1103 */ 1104 1105 #ifndef pgprot_nx 1106 #define pgprot_nx(prot) (prot) 1107 #endif 1108 1109 #ifndef pgprot_noncached 1110 #define pgprot_noncached(prot) (prot) 1111 #endif 1112 1113 #ifndef pgprot_writecombine 1114 #define pgprot_writecombine pgprot_noncached 1115 #endif 1116 1117 #ifndef pgprot_writethrough 1118 #define pgprot_writethrough pgprot_noncached 1119 #endif 1120 1121 #ifndef pgprot_device 1122 #define pgprot_device pgprot_noncached 1123 #endif 1124 1125 #ifndef pgprot_mhp 1126 #define pgprot_mhp(prot) (prot) 1127 #endif 1128 1129 #ifdef CONFIG_MMU 1130 #ifndef pgprot_modify 1131 #define pgprot_modify pgprot_modify 1132 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 1133 { 1134 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 1135 newprot = pgprot_noncached(newprot); 1136 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 1137 newprot = pgprot_writecombine(newprot); 1138 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 1139 newprot = pgprot_device(newprot); 1140 return newprot; 1141 } 1142 #endif 1143 #endif /* CONFIG_MMU */ 1144 1145 #ifndef pgprot_encrypted 1146 #define pgprot_encrypted(prot) (prot) 1147 #endif 1148 1149 #ifndef pgprot_decrypted 1150 #define pgprot_decrypted(prot) (prot) 1151 #endif 1152 1153 /* 1154 * A facility to provide batching of the reload of page tables and 1155 * other process state with the actual context switch code for 1156 * paravirtualized guests. By convention, only one of the batched 1157 * update (lazy) modes (CPU, MMU) should be active at any given time, 1158 * entry should never be nested, and entry and exits should always be 1159 * paired. This is for sanity of maintaining and reasoning about the 1160 * kernel code. In this case, the exit (end of the context switch) is 1161 * in architecture-specific code, and so doesn't need a generic 1162 * definition. 1163 */ 1164 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1165 #define arch_start_context_switch(prev) do {} while (0) 1166 #endif 1167 1168 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1169 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1170 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1171 { 1172 return pmd; 1173 } 1174 1175 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1176 { 1177 return 0; 1178 } 1179 1180 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1181 { 1182 return pmd; 1183 } 1184 #endif 1185 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1186 static inline int pte_soft_dirty(pte_t pte) 1187 { 1188 return 0; 1189 } 1190 1191 static inline int pmd_soft_dirty(pmd_t pmd) 1192 { 1193 return 0; 1194 } 1195 1196 static inline pte_t pte_mksoft_dirty(pte_t pte) 1197 { 1198 return pte; 1199 } 1200 1201 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1202 { 1203 return pmd; 1204 } 1205 1206 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1207 { 1208 return pte; 1209 } 1210 1211 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1212 { 1213 return pmd; 1214 } 1215 1216 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1217 { 1218 return pte; 1219 } 1220 1221 static inline int pte_swp_soft_dirty(pte_t pte) 1222 { 1223 return 0; 1224 } 1225 1226 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1227 { 1228 return pte; 1229 } 1230 1231 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1232 { 1233 return pmd; 1234 } 1235 1236 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1237 { 1238 return 0; 1239 } 1240 1241 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1242 { 1243 return pmd; 1244 } 1245 #endif 1246 1247 #ifndef __HAVE_PFNMAP_TRACKING 1248 /* 1249 * Interfaces that can be used by architecture code to keep track of 1250 * memory type of pfn mappings specified by the remap_pfn_range, 1251 * vmf_insert_pfn. 1252 */ 1253 1254 /* 1255 * track_pfn_remap is called when a _new_ pfn mapping is being established 1256 * by remap_pfn_range() for physical range indicated by pfn and size. 1257 */ 1258 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1259 unsigned long pfn, unsigned long addr, 1260 unsigned long size) 1261 { 1262 return 0; 1263 } 1264 1265 /* 1266 * track_pfn_insert is called when a _new_ single pfn is established 1267 * by vmf_insert_pfn(). 1268 */ 1269 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1270 pfn_t pfn) 1271 { 1272 } 1273 1274 /* 1275 * track_pfn_copy is called when vma that is covering the pfnmap gets 1276 * copied through copy_page_range(). 1277 */ 1278 static inline int track_pfn_copy(struct vm_area_struct *vma) 1279 { 1280 return 0; 1281 } 1282 1283 /* 1284 * untrack_pfn is called while unmapping a pfnmap for a region. 1285 * untrack can be called for a specific region indicated by pfn and size or 1286 * can be for the entire vma (in which case pfn, size are zero). 1287 */ 1288 static inline void untrack_pfn(struct vm_area_struct *vma, 1289 unsigned long pfn, unsigned long size, 1290 bool mm_wr_locked) 1291 { 1292 } 1293 1294 /* 1295 * untrack_pfn_clear is called while mremapping a pfnmap for a new region 1296 * or fails to copy pgtable during duplicate vm area. 1297 */ 1298 static inline void untrack_pfn_clear(struct vm_area_struct *vma) 1299 { 1300 } 1301 #else 1302 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1303 unsigned long pfn, unsigned long addr, 1304 unsigned long size); 1305 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1306 pfn_t pfn); 1307 extern int track_pfn_copy(struct vm_area_struct *vma); 1308 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1309 unsigned long size, bool mm_wr_locked); 1310 extern void untrack_pfn_clear(struct vm_area_struct *vma); 1311 #endif 1312 1313 #ifdef CONFIG_MMU 1314 #ifdef __HAVE_COLOR_ZERO_PAGE 1315 static inline int is_zero_pfn(unsigned long pfn) 1316 { 1317 extern unsigned long zero_pfn; 1318 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1319 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1320 } 1321 1322 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1323 1324 #else 1325 static inline int is_zero_pfn(unsigned long pfn) 1326 { 1327 extern unsigned long zero_pfn; 1328 return pfn == zero_pfn; 1329 } 1330 1331 static inline unsigned long my_zero_pfn(unsigned long addr) 1332 { 1333 extern unsigned long zero_pfn; 1334 return zero_pfn; 1335 } 1336 #endif 1337 #else 1338 static inline int is_zero_pfn(unsigned long pfn) 1339 { 1340 return 0; 1341 } 1342 1343 static inline unsigned long my_zero_pfn(unsigned long addr) 1344 { 1345 return 0; 1346 } 1347 #endif /* CONFIG_MMU */ 1348 1349 #ifdef CONFIG_MMU 1350 1351 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1352 static inline int pmd_trans_huge(pmd_t pmd) 1353 { 1354 return 0; 1355 } 1356 #ifndef pmd_write 1357 static inline int pmd_write(pmd_t pmd) 1358 { 1359 BUG(); 1360 return 0; 1361 } 1362 #endif /* pmd_write */ 1363 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1364 1365 #ifndef pud_write 1366 static inline int pud_write(pud_t pud) 1367 { 1368 BUG(); 1369 return 0; 1370 } 1371 #endif /* pud_write */ 1372 1373 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1374 static inline int pmd_devmap(pmd_t pmd) 1375 { 1376 return 0; 1377 } 1378 static inline int pud_devmap(pud_t pud) 1379 { 1380 return 0; 1381 } 1382 static inline int pgd_devmap(pgd_t pgd) 1383 { 1384 return 0; 1385 } 1386 #endif 1387 1388 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1389 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1390 static inline int pud_trans_huge(pud_t pud) 1391 { 1392 return 0; 1393 } 1394 #endif 1395 1396 static inline int pud_trans_unstable(pud_t *pud) 1397 { 1398 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1399 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1400 pud_t pudval = READ_ONCE(*pud); 1401 1402 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1403 return 1; 1404 if (unlikely(pud_bad(pudval))) { 1405 pud_clear_bad(pud); 1406 return 1; 1407 } 1408 #endif 1409 return 0; 1410 } 1411 1412 #ifndef CONFIG_NUMA_BALANCING 1413 /* 1414 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is 1415 * perfectly valid to indicate "no" in that case, which is why our default 1416 * implementation defaults to "always no". 1417 * 1418 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE 1419 * page protection due to NUMA hinting. NUMA hinting faults only apply in 1420 * accessible VMAs. 1421 * 1422 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault, 1423 * looking at the VMA accessibility is sufficient. 1424 */ 1425 static inline int pte_protnone(pte_t pte) 1426 { 1427 return 0; 1428 } 1429 1430 static inline int pmd_protnone(pmd_t pmd) 1431 { 1432 return 0; 1433 } 1434 #endif /* CONFIG_NUMA_BALANCING */ 1435 1436 #endif /* CONFIG_MMU */ 1437 1438 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1439 1440 #ifndef __PAGETABLE_P4D_FOLDED 1441 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1442 void p4d_clear_huge(p4d_t *p4d); 1443 #else 1444 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1445 { 1446 return 0; 1447 } 1448 static inline void p4d_clear_huge(p4d_t *p4d) { } 1449 #endif /* !__PAGETABLE_P4D_FOLDED */ 1450 1451 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1452 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1453 int pud_clear_huge(pud_t *pud); 1454 int pmd_clear_huge(pmd_t *pmd); 1455 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1456 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1457 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1458 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1459 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1460 { 1461 return 0; 1462 } 1463 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1464 { 1465 return 0; 1466 } 1467 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1468 { 1469 return 0; 1470 } 1471 static inline void p4d_clear_huge(p4d_t *p4d) { } 1472 static inline int pud_clear_huge(pud_t *pud) 1473 { 1474 return 0; 1475 } 1476 static inline int pmd_clear_huge(pmd_t *pmd) 1477 { 1478 return 0; 1479 } 1480 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1481 { 1482 return 0; 1483 } 1484 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1485 { 1486 return 0; 1487 } 1488 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1489 { 1490 return 0; 1491 } 1492 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1493 1494 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1495 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1496 /* 1497 * ARCHes with special requirements for evicting THP backing TLB entries can 1498 * implement this. Otherwise also, it can help optimize normal TLB flush in 1499 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1500 * entire TLB if flush span is greater than a threshold, which will 1501 * likely be true for a single huge page. Thus a single THP flush will 1502 * invalidate the entire TLB which is not desirable. 1503 * e.g. see arch/arc: flush_pmd_tlb_range 1504 */ 1505 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1506 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1507 #else 1508 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1509 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1510 #endif 1511 #endif 1512 1513 struct file; 1514 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1515 unsigned long size, pgprot_t *vma_prot); 1516 1517 #ifndef CONFIG_X86_ESPFIX64 1518 static inline void init_espfix_bsp(void) { } 1519 #endif 1520 1521 extern void __init pgtable_cache_init(void); 1522 1523 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1524 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1525 { 1526 return true; 1527 } 1528 1529 static inline bool arch_has_pfn_modify_check(void) 1530 { 1531 return false; 1532 } 1533 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1534 1535 /* 1536 * Architecture PAGE_KERNEL_* fallbacks 1537 * 1538 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1539 * because they really don't support them, or the port needs to be updated to 1540 * reflect the required functionality. Below are a set of relatively safe 1541 * fallbacks, as best effort, which we can count on in lieu of the architectures 1542 * not defining them on their own yet. 1543 */ 1544 1545 #ifndef PAGE_KERNEL_RO 1546 # define PAGE_KERNEL_RO PAGE_KERNEL 1547 #endif 1548 1549 #ifndef PAGE_KERNEL_EXEC 1550 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1551 #endif 1552 1553 /* 1554 * Page Table Modification bits for pgtbl_mod_mask. 1555 * 1556 * These are used by the p?d_alloc_track*() set of functions an in the generic 1557 * vmalloc/ioremap code to track at which page-table levels entries have been 1558 * modified. Based on that the code can better decide when vmalloc and ioremap 1559 * mapping changes need to be synchronized to other page-tables in the system. 1560 */ 1561 #define __PGTBL_PGD_MODIFIED 0 1562 #define __PGTBL_P4D_MODIFIED 1 1563 #define __PGTBL_PUD_MODIFIED 2 1564 #define __PGTBL_PMD_MODIFIED 3 1565 #define __PGTBL_PTE_MODIFIED 4 1566 1567 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1568 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1569 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1570 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1571 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1572 1573 /* Page-Table Modification Mask */ 1574 typedef unsigned int pgtbl_mod_mask; 1575 1576 #endif /* !__ASSEMBLY__ */ 1577 1578 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1579 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1580 /* 1581 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1582 * with physical address space extension, but falls back to 1583 * BITS_PER_LONG otherwise. 1584 */ 1585 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1586 #else 1587 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1588 #endif 1589 #endif 1590 1591 #ifndef has_transparent_hugepage 1592 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1593 #endif 1594 1595 #ifndef has_transparent_pud_hugepage 1596 #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1597 #endif 1598 /* 1599 * On some architectures it depends on the mm if the p4d/pud or pmd 1600 * layer of the page table hierarchy is folded or not. 1601 */ 1602 #ifndef mm_p4d_folded 1603 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1604 #endif 1605 1606 #ifndef mm_pud_folded 1607 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1608 #endif 1609 1610 #ifndef mm_pmd_folded 1611 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1612 #endif 1613 1614 #ifndef p4d_offset_lockless 1615 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1616 #endif 1617 #ifndef pud_offset_lockless 1618 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1619 #endif 1620 #ifndef pmd_offset_lockless 1621 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1622 #endif 1623 1624 /* 1625 * p?d_leaf() - true if this entry is a final mapping to a physical address. 1626 * This differs from p?d_huge() by the fact that they are always available (if 1627 * the architecture supports large pages at the appropriate level) even 1628 * if CONFIG_HUGETLB_PAGE is not defined. 1629 * Only meaningful when called on a valid entry. 1630 */ 1631 #ifndef pgd_leaf 1632 #define pgd_leaf(x) 0 1633 #endif 1634 #ifndef p4d_leaf 1635 #define p4d_leaf(x) 0 1636 #endif 1637 #ifndef pud_leaf 1638 #define pud_leaf(x) 0 1639 #endif 1640 #ifndef pmd_leaf 1641 #define pmd_leaf(x) 0 1642 #endif 1643 1644 #ifndef pgd_leaf_size 1645 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1646 #endif 1647 #ifndef p4d_leaf_size 1648 #define p4d_leaf_size(x) P4D_SIZE 1649 #endif 1650 #ifndef pud_leaf_size 1651 #define pud_leaf_size(x) PUD_SIZE 1652 #endif 1653 #ifndef pmd_leaf_size 1654 #define pmd_leaf_size(x) PMD_SIZE 1655 #endif 1656 #ifndef pte_leaf_size 1657 #define pte_leaf_size(x) PAGE_SIZE 1658 #endif 1659 1660 /* 1661 * Some architectures have MMUs that are configurable or selectable at boot 1662 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1663 * helps to have a static maximum value. 1664 */ 1665 1666 #ifndef MAX_PTRS_PER_PTE 1667 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1668 #endif 1669 1670 #ifndef MAX_PTRS_PER_PMD 1671 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1672 #endif 1673 1674 #ifndef MAX_PTRS_PER_PUD 1675 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1676 #endif 1677 1678 #ifndef MAX_PTRS_PER_P4D 1679 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1680 #endif 1681 1682 /* description of effects of mapping type and prot in current implementation. 1683 * this is due to the limited x86 page protection hardware. The expected 1684 * behavior is in parens: 1685 * 1686 * map_type prot 1687 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1688 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1689 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1690 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1691 * 1692 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1693 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1694 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1695 * 1696 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1697 * MAP_PRIVATE (with Enhanced PAN supported): 1698 * r: (no) no 1699 * w: (no) no 1700 * x: (yes) yes 1701 */ 1702 #define DECLARE_VM_GET_PAGE_PROT \ 1703 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1704 { \ 1705 return protection_map[vm_flags & \ 1706 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1707 } \ 1708 EXPORT_SYMBOL(vm_get_page_prot); 1709 1710 #endif /* _LINUX_PGTABLE_H */ 1711