1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_PGTABLE_H 3 #define _LINUX_PGTABLE_H 4 5 #include <linux/pfn.h> 6 #include <asm/pgtable.h> 7 8 #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT) 9 #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT) 10 11 #ifndef __ASSEMBLY__ 12 #ifdef CONFIG_MMU 13 14 #include <linux/mm_types.h> 15 #include <linux/bug.h> 16 #include <linux/errno.h> 17 #include <asm-generic/pgtable_uffd.h> 18 #include <linux/page_table_check.h> 19 20 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ 21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS 22 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED 23 #endif 24 25 /* 26 * On almost all architectures and configurations, 0 can be used as the 27 * upper ceiling to free_pgtables(): on many architectures it has the same 28 * effect as using TASK_SIZE. However, there is one configuration which 29 * must impose a more careful limit, to avoid freeing kernel pgtables. 30 */ 31 #ifndef USER_PGTABLES_CEILING 32 #define USER_PGTABLES_CEILING 0UL 33 #endif 34 35 /* 36 * This defines the first usable user address. Platforms 37 * can override its value with custom FIRST_USER_ADDRESS 38 * defined in their respective <asm/pgtable.h>. 39 */ 40 #ifndef FIRST_USER_ADDRESS 41 #define FIRST_USER_ADDRESS 0UL 42 #endif 43 44 /* 45 * This defines the generic helper for accessing PMD page 46 * table page. Although platforms can still override this 47 * via their respective <asm/pgtable.h>. 48 */ 49 #ifndef pmd_pgtable 50 #define pmd_pgtable(pmd) pmd_page(pmd) 51 #endif 52 53 #define pmd_folio(pmd) page_folio(pmd_page(pmd)) 54 55 /* 56 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] 57 * 58 * The pXx_index() functions return the index of the entry in the page 59 * table page which would control the given virtual address 60 * 61 * As these functions may be used by the same code for different levels of 62 * the page table folding, they are always available, regardless of 63 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 64 * because in such cases PTRS_PER_PxD equals 1. 65 */ 66 67 static inline unsigned long pte_index(unsigned long address) 68 { 69 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); 70 } 71 72 #ifndef pmd_index 73 static inline unsigned long pmd_index(unsigned long address) 74 { 75 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); 76 } 77 #define pmd_index pmd_index 78 #endif 79 80 #ifndef pud_index 81 static inline unsigned long pud_index(unsigned long address) 82 { 83 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); 84 } 85 #define pud_index pud_index 86 #endif 87 88 #ifndef pgd_index 89 /* Must be a compile-time constant, so implement it as a macro */ 90 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 91 #endif 92 93 #ifndef pte_offset_kernel 94 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) 95 { 96 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); 97 } 98 #define pte_offset_kernel pte_offset_kernel 99 #endif 100 101 #ifdef CONFIG_HIGHPTE 102 #define __pte_map(pmd, address) \ 103 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address))) 104 #define pte_unmap(pte) do { \ 105 kunmap_local((pte)); \ 106 rcu_read_unlock(); \ 107 } while (0) 108 #else 109 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address) 110 { 111 return pte_offset_kernel(pmd, address); 112 } 113 static inline void pte_unmap(pte_t *pte) 114 { 115 rcu_read_unlock(); 116 } 117 #endif 118 119 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable); 120 121 /* Find an entry in the second-level page table.. */ 122 #ifndef pmd_offset 123 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 124 { 125 return pud_pgtable(*pud) + pmd_index(address); 126 } 127 #define pmd_offset pmd_offset 128 #endif 129 130 #ifndef pud_offset 131 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) 132 { 133 return p4d_pgtable(*p4d) + pud_index(address); 134 } 135 #define pud_offset pud_offset 136 #endif 137 138 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) 139 { 140 return (pgd + pgd_index(address)); 141 }; 142 143 /* 144 * a shortcut to get a pgd_t in a given mm 145 */ 146 #ifndef pgd_offset 147 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) 148 #endif 149 150 /* 151 * a shortcut which implies the use of the kernel's pgd, instead 152 * of a process's 153 */ 154 #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) 155 156 /* 157 * In many cases it is known that a virtual address is mapped at PMD or PTE 158 * level, so instead of traversing all the page table levels, we can get a 159 * pointer to the PMD entry in user or kernel page table or translate a virtual 160 * address to the pointer in the PTE in the kernel page tables with simple 161 * helpers. 162 */ 163 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) 164 { 165 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); 166 } 167 168 static inline pmd_t *pmd_off_k(unsigned long va) 169 { 170 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); 171 } 172 173 static inline pte_t *virt_to_kpte(unsigned long vaddr) 174 { 175 pmd_t *pmd = pmd_off_k(vaddr); 176 177 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); 178 } 179 180 #ifndef pmd_young 181 static inline int pmd_young(pmd_t pmd) 182 { 183 return 0; 184 } 185 #endif 186 187 #ifndef pmd_dirty 188 static inline int pmd_dirty(pmd_t pmd) 189 { 190 return 0; 191 } 192 #endif 193 194 /* 195 * A facility to provide lazy MMU batching. This allows PTE updates and 196 * page invalidations to be delayed until a call to leave lazy MMU mode 197 * is issued. Some architectures may benefit from doing this, and it is 198 * beneficial for both shadow and direct mode hypervisors, which may batch 199 * the PTE updates which happen during this window. Note that using this 200 * interface requires that read hazards be removed from the code. A read 201 * hazard could result in the direct mode hypervisor case, since the actual 202 * write to the page tables may not yet have taken place, so reads though 203 * a raw PTE pointer after it has been modified are not guaranteed to be 204 * up to date. This mode can only be entered and left under the protection of 205 * the page table locks for all page tables which may be modified. In the UP 206 * case, this is required so that preemption is disabled, and in the SMP case, 207 * it must synchronize the delayed page table writes properly on other CPUs. 208 */ 209 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE 210 #define arch_enter_lazy_mmu_mode() do {} while (0) 211 #define arch_leave_lazy_mmu_mode() do {} while (0) 212 #define arch_flush_lazy_mmu_mode() do {} while (0) 213 #endif 214 215 #ifndef pte_batch_hint 216 /** 217 * pte_batch_hint - Number of pages that can be added to batch without scanning. 218 * @ptep: Page table pointer for the entry. 219 * @pte: Page table entry. 220 * 221 * Some architectures know that a set of contiguous ptes all map the same 222 * contiguous memory with the same permissions. In this case, it can provide a 223 * hint to aid pte batching without the core code needing to scan every pte. 224 * 225 * An architecture implementation may ignore the PTE accessed state. Further, 226 * the dirty state must apply atomically to all the PTEs described by the hint. 227 * 228 * May be overridden by the architecture, else pte_batch_hint is always 1. 229 */ 230 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 231 { 232 return 1; 233 } 234 #endif 235 236 #ifndef pte_advance_pfn 237 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 238 { 239 return __pte(pte_val(pte) + (nr << PFN_PTE_SHIFT)); 240 } 241 #endif 242 243 #define pte_next_pfn(pte) pte_advance_pfn(pte, 1) 244 245 #ifndef set_ptes 246 /** 247 * set_ptes - Map consecutive pages to a contiguous range of addresses. 248 * @mm: Address space to map the pages into. 249 * @addr: Address to map the first page at. 250 * @ptep: Page table pointer for the first entry. 251 * @pte: Page table entry for the first page. 252 * @nr: Number of pages to map. 253 * 254 * When nr==1, initial state of pte may be present or not present, and new state 255 * may be present or not present. When nr>1, initial state of all ptes must be 256 * not present, and new state must be present. 257 * 258 * May be overridden by the architecture, or the architecture can define 259 * set_pte() and PFN_PTE_SHIFT. 260 * 261 * Context: The caller holds the page table lock. The pages all belong 262 * to the same folio. The PTEs are all in the same PMD. 263 */ 264 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 265 pte_t *ptep, pte_t pte, unsigned int nr) 266 { 267 page_table_check_ptes_set(mm, ptep, pte, nr); 268 269 arch_enter_lazy_mmu_mode(); 270 for (;;) { 271 set_pte(ptep, pte); 272 if (--nr == 0) 273 break; 274 ptep++; 275 pte = pte_next_pfn(pte); 276 } 277 arch_leave_lazy_mmu_mode(); 278 } 279 #endif 280 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) 281 282 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 283 extern int ptep_set_access_flags(struct vm_area_struct *vma, 284 unsigned long address, pte_t *ptep, 285 pte_t entry, int dirty); 286 #endif 287 288 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 289 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 290 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 291 unsigned long address, pmd_t *pmdp, 292 pmd_t entry, int dirty); 293 extern int pudp_set_access_flags(struct vm_area_struct *vma, 294 unsigned long address, pud_t *pudp, 295 pud_t entry, int dirty); 296 #else 297 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 298 unsigned long address, pmd_t *pmdp, 299 pmd_t entry, int dirty) 300 { 301 BUILD_BUG(); 302 return 0; 303 } 304 static inline int pudp_set_access_flags(struct vm_area_struct *vma, 305 unsigned long address, pud_t *pudp, 306 pud_t entry, int dirty) 307 { 308 BUILD_BUG(); 309 return 0; 310 } 311 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 312 #endif 313 314 #ifndef ptep_get 315 static inline pte_t ptep_get(pte_t *ptep) 316 { 317 return READ_ONCE(*ptep); 318 } 319 #endif 320 321 #ifndef pmdp_get 322 static inline pmd_t pmdp_get(pmd_t *pmdp) 323 { 324 return READ_ONCE(*pmdp); 325 } 326 #endif 327 328 #ifndef pudp_get 329 static inline pud_t pudp_get(pud_t *pudp) 330 { 331 return READ_ONCE(*pudp); 332 } 333 #endif 334 335 #ifndef p4dp_get 336 static inline p4d_t p4dp_get(p4d_t *p4dp) 337 { 338 return READ_ONCE(*p4dp); 339 } 340 #endif 341 342 #ifndef pgdp_get 343 static inline pgd_t pgdp_get(pgd_t *pgdp) 344 { 345 return READ_ONCE(*pgdp); 346 } 347 #endif 348 349 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 350 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 351 unsigned long address, 352 pte_t *ptep) 353 { 354 pte_t pte = ptep_get(ptep); 355 int r = 1; 356 if (!pte_young(pte)) 357 r = 0; 358 else 359 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); 360 return r; 361 } 362 #endif 363 364 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 365 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 366 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 367 unsigned long address, 368 pmd_t *pmdp) 369 { 370 pmd_t pmd = *pmdp; 371 int r = 1; 372 if (!pmd_young(pmd)) 373 r = 0; 374 else 375 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); 376 return r; 377 } 378 #else 379 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 380 unsigned long address, 381 pmd_t *pmdp) 382 { 383 BUILD_BUG(); 384 return 0; 385 } 386 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 387 #endif 388 389 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 390 int ptep_clear_flush_young(struct vm_area_struct *vma, 391 unsigned long address, pte_t *ptep); 392 #endif 393 394 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 395 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 396 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 397 unsigned long address, pmd_t *pmdp); 398 #else 399 /* 400 * Despite relevant to THP only, this API is called from generic rmap code 401 * under PageTransHuge(), hence needs a dummy implementation for !THP 402 */ 403 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 404 unsigned long address, pmd_t *pmdp) 405 { 406 BUILD_BUG(); 407 return 0; 408 } 409 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 410 #endif 411 412 #ifndef arch_has_hw_nonleaf_pmd_young 413 /* 414 * Return whether the accessed bit in non-leaf PMD entries is supported on the 415 * local CPU. 416 */ 417 static inline bool arch_has_hw_nonleaf_pmd_young(void) 418 { 419 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG); 420 } 421 #endif 422 423 #ifndef arch_has_hw_pte_young 424 /* 425 * Return whether the accessed bit is supported on the local CPU. 426 * 427 * This stub assumes accessing through an old PTE triggers a page fault. 428 * Architectures that automatically set the access bit should overwrite it. 429 */ 430 static inline bool arch_has_hw_pte_young(void) 431 { 432 return IS_ENABLED(CONFIG_ARCH_HAS_HW_PTE_YOUNG); 433 } 434 #endif 435 436 #ifndef arch_check_zapped_pte 437 static inline void arch_check_zapped_pte(struct vm_area_struct *vma, 438 pte_t pte) 439 { 440 } 441 #endif 442 443 #ifndef arch_check_zapped_pmd 444 static inline void arch_check_zapped_pmd(struct vm_area_struct *vma, 445 pmd_t pmd) 446 { 447 } 448 #endif 449 450 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR 451 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 452 unsigned long address, 453 pte_t *ptep) 454 { 455 pte_t pte = ptep_get(ptep); 456 pte_clear(mm, address, ptep); 457 page_table_check_pte_clear(mm, pte); 458 return pte; 459 } 460 #endif 461 462 #ifndef clear_young_dirty_ptes 463 /** 464 * clear_young_dirty_ptes - Mark PTEs that map consecutive pages of the 465 * same folio as old/clean. 466 * @mm: Address space the pages are mapped into. 467 * @addr: Address the first page is mapped at. 468 * @ptep: Page table pointer for the first entry. 469 * @nr: Number of entries to mark old/clean. 470 * @flags: Flags to modify the PTE batch semantics. 471 * 472 * May be overridden by the architecture; otherwise, implemented by 473 * get_and_clear/modify/set for each pte in the range. 474 * 475 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 476 * some PTEs might be write-protected. 477 * 478 * Context: The caller holds the page table lock. The PTEs map consecutive 479 * pages that belong to the same folio. The PTEs are all in the same PMD. 480 */ 481 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 482 unsigned long addr, pte_t *ptep, 483 unsigned int nr, cydp_t flags) 484 { 485 pte_t pte; 486 487 for (;;) { 488 if (flags == CYDP_CLEAR_YOUNG) 489 ptep_test_and_clear_young(vma, addr, ptep); 490 else { 491 pte = ptep_get_and_clear(vma->vm_mm, addr, ptep); 492 if (flags & CYDP_CLEAR_YOUNG) 493 pte = pte_mkold(pte); 494 if (flags & CYDP_CLEAR_DIRTY) 495 pte = pte_mkclean(pte); 496 set_pte_at(vma->vm_mm, addr, ptep, pte); 497 } 498 if (--nr == 0) 499 break; 500 ptep++; 501 addr += PAGE_SIZE; 502 } 503 } 504 #endif 505 506 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr, 507 pte_t *ptep) 508 { 509 ptep_get_and_clear(mm, addr, ptep); 510 } 511 512 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH 513 /* 514 * For walking the pagetables without holding any locks. Some architectures 515 * (eg x86-32 PAE) cannot load the entries atomically without using expensive 516 * instructions. We are guaranteed that a PTE will only either go from not 517 * present to present, or present to not present -- it will not switch to a 518 * completely different present page without a TLB flush inbetween; which we 519 * are blocking by holding interrupts off. 520 * 521 * Setting ptes from not present to present goes: 522 * 523 * ptep->pte_high = h; 524 * smp_wmb(); 525 * ptep->pte_low = l; 526 * 527 * And present to not present goes: 528 * 529 * ptep->pte_low = 0; 530 * smp_wmb(); 531 * ptep->pte_high = 0; 532 * 533 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. 534 * We load pte_high *after* loading pte_low, which ensures we don't see an older 535 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't 536 * picked up a changed pte high. We might have gotten rubbish values from 537 * pte_low and pte_high, but we are guaranteed that pte_low will not have the 538 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only 539 * operates on present ptes we're safe. 540 */ 541 static inline pte_t ptep_get_lockless(pte_t *ptep) 542 { 543 pte_t pte; 544 545 do { 546 pte.pte_low = ptep->pte_low; 547 smp_rmb(); 548 pte.pte_high = ptep->pte_high; 549 smp_rmb(); 550 } while (unlikely(pte.pte_low != ptep->pte_low)); 551 552 return pte; 553 } 554 #define ptep_get_lockless ptep_get_lockless 555 556 #if CONFIG_PGTABLE_LEVELS > 2 557 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 558 { 559 pmd_t pmd; 560 561 do { 562 pmd.pmd_low = pmdp->pmd_low; 563 smp_rmb(); 564 pmd.pmd_high = pmdp->pmd_high; 565 smp_rmb(); 566 } while (unlikely(pmd.pmd_low != pmdp->pmd_low)); 567 568 return pmd; 569 } 570 #define pmdp_get_lockless pmdp_get_lockless 571 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one() 572 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 573 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */ 574 575 /* 576 * We require that the PTE can be read atomically. 577 */ 578 #ifndef ptep_get_lockless 579 static inline pte_t ptep_get_lockless(pte_t *ptep) 580 { 581 return ptep_get(ptep); 582 } 583 #endif 584 585 #ifndef pmdp_get_lockless 586 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp) 587 { 588 return pmdp_get(pmdp); 589 } 590 static inline void pmdp_get_lockless_sync(void) 591 { 592 } 593 #endif 594 595 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 596 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 597 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 598 unsigned long address, 599 pmd_t *pmdp) 600 { 601 pmd_t pmd = *pmdp; 602 603 pmd_clear(pmdp); 604 page_table_check_pmd_clear(mm, pmd); 605 606 return pmd; 607 } 608 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ 609 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 610 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 611 unsigned long address, 612 pud_t *pudp) 613 { 614 pud_t pud = *pudp; 615 616 pud_clear(pudp); 617 page_table_check_pud_clear(mm, pud); 618 619 return pud; 620 } 621 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ 622 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 623 624 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 625 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 626 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 627 unsigned long address, pmd_t *pmdp, 628 int full) 629 { 630 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 631 } 632 #endif 633 634 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 635 static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 636 unsigned long address, pud_t *pudp, 637 int full) 638 { 639 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp); 640 } 641 #endif 642 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 643 644 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 645 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 646 unsigned long address, pte_t *ptep, 647 int full) 648 { 649 return ptep_get_and_clear(mm, address, ptep); 650 } 651 #endif 652 653 #ifndef get_and_clear_full_ptes 654 /** 655 * get_and_clear_full_ptes - Clear present PTEs that map consecutive pages of 656 * the same folio, collecting dirty/accessed bits. 657 * @mm: Address space the pages are mapped into. 658 * @addr: Address the first page is mapped at. 659 * @ptep: Page table pointer for the first entry. 660 * @nr: Number of entries to clear. 661 * @full: Whether we are clearing a full mm. 662 * 663 * May be overridden by the architecture; otherwise, implemented as a simple 664 * loop over ptep_get_and_clear_full(), merging dirty/accessed bits into the 665 * returned PTE. 666 * 667 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 668 * some PTEs might be write-protected. 669 * 670 * Context: The caller holds the page table lock. The PTEs map consecutive 671 * pages that belong to the same folio. The PTEs are all in the same PMD. 672 */ 673 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 674 unsigned long addr, pte_t *ptep, unsigned int nr, int full) 675 { 676 pte_t pte, tmp_pte; 677 678 pte = ptep_get_and_clear_full(mm, addr, ptep, full); 679 while (--nr) { 680 ptep++; 681 addr += PAGE_SIZE; 682 tmp_pte = ptep_get_and_clear_full(mm, addr, ptep, full); 683 if (pte_dirty(tmp_pte)) 684 pte = pte_mkdirty(pte); 685 if (pte_young(tmp_pte)) 686 pte = pte_mkyoung(pte); 687 } 688 return pte; 689 } 690 #endif 691 692 #ifndef clear_full_ptes 693 /** 694 * clear_full_ptes - Clear present PTEs that map consecutive pages of the same 695 * folio. 696 * @mm: Address space the pages are mapped into. 697 * @addr: Address the first page is mapped at. 698 * @ptep: Page table pointer for the first entry. 699 * @nr: Number of entries to clear. 700 * @full: Whether we are clearing a full mm. 701 * 702 * May be overridden by the architecture; otherwise, implemented as a simple 703 * loop over ptep_get_and_clear_full(). 704 * 705 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 706 * some PTEs might be write-protected. 707 * 708 * Context: The caller holds the page table lock. The PTEs map consecutive 709 * pages that belong to the same folio. The PTEs are all in the same PMD. 710 */ 711 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 712 pte_t *ptep, unsigned int nr, int full) 713 { 714 for (;;) { 715 ptep_get_and_clear_full(mm, addr, ptep, full); 716 if (--nr == 0) 717 break; 718 ptep++; 719 addr += PAGE_SIZE; 720 } 721 } 722 #endif 723 724 /* 725 * If two threads concurrently fault at the same page, the thread that 726 * won the race updates the PTE and its local TLB/Cache. The other thread 727 * gives up, simply does nothing, and continues; on architectures where 728 * software can update TLB, local TLB can be updated here to avoid next page 729 * fault. This function updates TLB only, do nothing with cache or others. 730 * It is the difference with function update_mmu_cache. 731 */ 732 #ifndef update_mmu_tlb_range 733 static inline void update_mmu_tlb_range(struct vm_area_struct *vma, 734 unsigned long address, pte_t *ptep, unsigned int nr) 735 { 736 } 737 #endif 738 739 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB 740 static inline void update_mmu_tlb(struct vm_area_struct *vma, 741 unsigned long address, pte_t *ptep) 742 { 743 } 744 #define __HAVE_ARCH_UPDATE_MMU_TLB 745 #endif 746 747 /* 748 * Some architectures may be able to avoid expensive synchronization 749 * primitives when modifications are made to PTE's which are already 750 * not present, or in the process of an address space destruction. 751 */ 752 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL 753 static inline void pte_clear_not_present_full(struct mm_struct *mm, 754 unsigned long address, 755 pte_t *ptep, 756 int full) 757 { 758 pte_clear(mm, address, ptep); 759 } 760 #endif 761 762 #ifndef clear_not_present_full_ptes 763 /** 764 * clear_not_present_full_ptes - Clear multiple not present PTEs which are 765 * consecutive in the pgtable. 766 * @mm: Address space the ptes represent. 767 * @addr: Address of the first pte. 768 * @ptep: Page table pointer for the first entry. 769 * @nr: Number of entries to clear. 770 * @full: Whether we are clearing a full mm. 771 * 772 * May be overridden by the architecture; otherwise, implemented as a simple 773 * loop over pte_clear_not_present_full(). 774 * 775 * Context: The caller holds the page table lock. The PTEs are all not present. 776 * The PTEs are all in the same PMD. 777 */ 778 static inline void clear_not_present_full_ptes(struct mm_struct *mm, 779 unsigned long addr, pte_t *ptep, unsigned int nr, int full) 780 { 781 for (;;) { 782 pte_clear_not_present_full(mm, addr, ptep, full); 783 if (--nr == 0) 784 break; 785 ptep++; 786 addr += PAGE_SIZE; 787 } 788 } 789 #endif 790 791 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH 792 extern pte_t ptep_clear_flush(struct vm_area_struct *vma, 793 unsigned long address, 794 pte_t *ptep); 795 #endif 796 797 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 798 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 799 unsigned long address, 800 pmd_t *pmdp); 801 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, 802 unsigned long address, 803 pud_t *pudp); 804 #endif 805 806 #ifndef pte_mkwrite 807 static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma) 808 { 809 return pte_mkwrite_novma(pte); 810 } 811 #endif 812 813 #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite) 814 static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma) 815 { 816 return pmd_mkwrite_novma(pmd); 817 } 818 #endif 819 820 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT 821 struct mm_struct; 822 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 823 { 824 pte_t old_pte = ptep_get(ptep); 825 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); 826 } 827 #endif 828 829 #ifndef wrprotect_ptes 830 /** 831 * wrprotect_ptes - Write-protect PTEs that map consecutive pages of the same 832 * folio. 833 * @mm: Address space the pages are mapped into. 834 * @addr: Address the first page is mapped at. 835 * @ptep: Page table pointer for the first entry. 836 * @nr: Number of entries to write-protect. 837 * 838 * May be overridden by the architecture; otherwise, implemented as a simple 839 * loop over ptep_set_wrprotect(). 840 * 841 * Note that PTE bits in the PTE range besides the PFN can differ. For example, 842 * some PTEs might be write-protected. 843 * 844 * Context: The caller holds the page table lock. The PTEs map consecutive 845 * pages that belong to the same folio. The PTEs are all in the same PMD. 846 */ 847 static inline void wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 848 pte_t *ptep, unsigned int nr) 849 { 850 for (;;) { 851 ptep_set_wrprotect(mm, addr, ptep); 852 if (--nr == 0) 853 break; 854 ptep++; 855 addr += PAGE_SIZE; 856 } 857 } 858 #endif 859 860 /* 861 * On some architectures hardware does not set page access bit when accessing 862 * memory page, it is responsibility of software setting this bit. It brings 863 * out extra page fault penalty to track page access bit. For optimization page 864 * access bit can be set during all page fault flow on these arches. 865 * To be differentiate with macro pte_mkyoung, this macro is used on platforms 866 * where software maintains page access bit. 867 */ 868 #ifndef pte_sw_mkyoung 869 static inline pte_t pte_sw_mkyoung(pte_t pte) 870 { 871 return pte; 872 } 873 #define pte_sw_mkyoung pte_sw_mkyoung 874 #endif 875 876 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT 877 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 878 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 879 unsigned long address, pmd_t *pmdp) 880 { 881 pmd_t old_pmd = *pmdp; 882 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); 883 } 884 #else 885 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 886 unsigned long address, pmd_t *pmdp) 887 { 888 BUILD_BUG(); 889 } 890 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 891 #endif 892 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT 893 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD 894 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 895 static inline void pudp_set_wrprotect(struct mm_struct *mm, 896 unsigned long address, pud_t *pudp) 897 { 898 pud_t old_pud = *pudp; 899 900 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); 901 } 902 #else 903 static inline void pudp_set_wrprotect(struct mm_struct *mm, 904 unsigned long address, pud_t *pudp) 905 { 906 BUILD_BUG(); 907 } 908 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 909 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ 910 #endif 911 912 #ifndef pmdp_collapse_flush 913 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 914 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 915 unsigned long address, pmd_t *pmdp); 916 #else 917 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 918 unsigned long address, 919 pmd_t *pmdp) 920 { 921 BUILD_BUG(); 922 return *pmdp; 923 } 924 #define pmdp_collapse_flush pmdp_collapse_flush 925 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 926 #endif 927 928 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT 929 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 930 pgtable_t pgtable); 931 #endif 932 933 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW 934 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 935 #endif 936 937 #ifndef arch_needs_pgtable_deposit 938 #define arch_needs_pgtable_deposit() (false) 939 #endif 940 941 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 942 /* 943 * This is an implementation of pmdp_establish() that is only suitable for an 944 * architecture that doesn't have hardware dirty/accessed bits. In this case we 945 * can't race with CPU which sets these bits and non-atomic approach is fine. 946 */ 947 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, 948 unsigned long address, pmd_t *pmdp, pmd_t pmd) 949 { 950 pmd_t old_pmd = *pmdp; 951 set_pmd_at(vma->vm_mm, address, pmdp, pmd); 952 return old_pmd; 953 } 954 #endif 955 956 #ifndef __HAVE_ARCH_PMDP_INVALIDATE 957 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 958 pmd_t *pmdp); 959 #endif 960 961 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD 962 963 /* 964 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent 965 * hugepage mapping in the page tables. This function is similar to 966 * pmdp_invalidate(), but should only be used if the access and dirty bits would 967 * not be cleared by the software in the new PMD value. The function ensures 968 * that hardware changes of the access and dirty bits updates would not be lost. 969 * 970 * Doing so can allow in certain architectures to avoid a TLB flush in most 971 * cases. Yet, another TLB flush might be necessary later if the PMD update 972 * itself requires such flush (e.g., if protection was set to be stricter). Yet, 973 * even when a TLB flush is needed because of the update, the caller may be able 974 * to batch these TLB flushing operations, so fewer TLB flush operations are 975 * needed. 976 */ 977 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma, 978 unsigned long address, pmd_t *pmdp); 979 #endif 980 981 #ifndef __HAVE_ARCH_PTE_SAME 982 static inline int pte_same(pte_t pte_a, pte_t pte_b) 983 { 984 return pte_val(pte_a) == pte_val(pte_b); 985 } 986 #endif 987 988 #ifndef __HAVE_ARCH_PTE_UNUSED 989 /* 990 * Some architectures provide facilities to virtualization guests 991 * so that they can flag allocated pages as unused. This allows the 992 * host to transparently reclaim unused pages. This function returns 993 * whether the pte's page is unused. 994 */ 995 static inline int pte_unused(pte_t pte) 996 { 997 return 0; 998 } 999 #endif 1000 1001 #ifndef pte_access_permitted 1002 #define pte_access_permitted(pte, write) \ 1003 (pte_present(pte) && (!(write) || pte_write(pte))) 1004 #endif 1005 1006 #ifndef pmd_access_permitted 1007 #define pmd_access_permitted(pmd, write) \ 1008 (pmd_present(pmd) && (!(write) || pmd_write(pmd))) 1009 #endif 1010 1011 #ifndef pud_access_permitted 1012 #define pud_access_permitted(pud, write) \ 1013 (pud_present(pud) && (!(write) || pud_write(pud))) 1014 #endif 1015 1016 #ifndef p4d_access_permitted 1017 #define p4d_access_permitted(p4d, write) \ 1018 (p4d_present(p4d) && (!(write) || p4d_write(p4d))) 1019 #endif 1020 1021 #ifndef pgd_access_permitted 1022 #define pgd_access_permitted(pgd, write) \ 1023 (pgd_present(pgd) && (!(write) || pgd_write(pgd))) 1024 #endif 1025 1026 #ifndef __HAVE_ARCH_PMD_SAME 1027 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1028 { 1029 return pmd_val(pmd_a) == pmd_val(pmd_b); 1030 } 1031 #endif 1032 1033 #ifndef pud_same 1034 static inline int pud_same(pud_t pud_a, pud_t pud_b) 1035 { 1036 return pud_val(pud_a) == pud_val(pud_b); 1037 } 1038 #define pud_same pud_same 1039 #endif 1040 1041 #ifndef __HAVE_ARCH_P4D_SAME 1042 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) 1043 { 1044 return p4d_val(p4d_a) == p4d_val(p4d_b); 1045 } 1046 #endif 1047 1048 #ifndef __HAVE_ARCH_PGD_SAME 1049 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) 1050 { 1051 return pgd_val(pgd_a) == pgd_val(pgd_b); 1052 } 1053 #endif 1054 1055 /* 1056 * Use set_p*_safe(), and elide TLB flushing, when confident that *no* 1057 * TLB flush will be required as a result of the "set". For example, use 1058 * in scenarios where it is known ahead of time that the routine is 1059 * setting non-present entries, or re-setting an existing entry to the 1060 * same value. Otherwise, use the typical "set" helpers and flush the 1061 * TLB. 1062 */ 1063 #define set_pte_safe(ptep, pte) \ 1064 ({ \ 1065 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ 1066 set_pte(ptep, pte); \ 1067 }) 1068 1069 #define set_pmd_safe(pmdp, pmd) \ 1070 ({ \ 1071 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ 1072 set_pmd(pmdp, pmd); \ 1073 }) 1074 1075 #define set_pud_safe(pudp, pud) \ 1076 ({ \ 1077 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ 1078 set_pud(pudp, pud); \ 1079 }) 1080 1081 #define set_p4d_safe(p4dp, p4d) \ 1082 ({ \ 1083 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ 1084 set_p4d(p4dp, p4d); \ 1085 }) 1086 1087 #define set_pgd_safe(pgdp, pgd) \ 1088 ({ \ 1089 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ 1090 set_pgd(pgdp, pgd); \ 1091 }) 1092 1093 #ifndef __HAVE_ARCH_DO_SWAP_PAGE 1094 /* 1095 * Some architectures support metadata associated with a page. When a 1096 * page is being swapped out, this metadata must be saved so it can be 1097 * restored when the page is swapped back in. SPARC M7 and newer 1098 * processors support an ADI (Application Data Integrity) tag for the 1099 * page as metadata for the page. arch_do_swap_page() can restore this 1100 * metadata when a page is swapped back in. 1101 */ 1102 static inline void arch_do_swap_page(struct mm_struct *mm, 1103 struct vm_area_struct *vma, 1104 unsigned long addr, 1105 pte_t pte, pte_t oldpte) 1106 { 1107 1108 } 1109 #endif 1110 1111 #ifndef __HAVE_ARCH_UNMAP_ONE 1112 /* 1113 * Some architectures support metadata associated with a page. When a 1114 * page is being swapped out, this metadata must be saved so it can be 1115 * restored when the page is swapped back in. SPARC M7 and newer 1116 * processors support an ADI (Application Data Integrity) tag for the 1117 * page as metadata for the page. arch_unmap_one() can save this 1118 * metadata on a swap-out of a page. 1119 */ 1120 static inline int arch_unmap_one(struct mm_struct *mm, 1121 struct vm_area_struct *vma, 1122 unsigned long addr, 1123 pte_t orig_pte) 1124 { 1125 return 0; 1126 } 1127 #endif 1128 1129 /* 1130 * Allow architectures to preserve additional metadata associated with 1131 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function 1132 * prototypes must be defined in the arch-specific asm/pgtable.h file. 1133 */ 1134 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP 1135 static inline int arch_prepare_to_swap(struct folio *folio) 1136 { 1137 return 0; 1138 } 1139 #endif 1140 1141 #ifndef __HAVE_ARCH_SWAP_INVALIDATE 1142 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1143 { 1144 } 1145 1146 static inline void arch_swap_invalidate_area(int type) 1147 { 1148 } 1149 #endif 1150 1151 #ifndef __HAVE_ARCH_SWAP_RESTORE 1152 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1153 { 1154 } 1155 #endif 1156 1157 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE 1158 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) 1159 #endif 1160 1161 #ifndef __HAVE_ARCH_MOVE_PTE 1162 #define move_pte(pte, old_addr, new_addr) (pte) 1163 #endif 1164 1165 #ifndef pte_accessible 1166 # define pte_accessible(mm, pte) ((void)(pte), 1) 1167 #endif 1168 1169 #ifndef flush_tlb_fix_spurious_fault 1170 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address) 1171 #endif 1172 1173 /* 1174 * When walking page tables, get the address of the next boundary, 1175 * or the end address of the range if that comes earlier. Although no 1176 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. 1177 */ 1178 1179 #define pgd_addr_end(addr, end) \ 1180 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ 1181 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1182 }) 1183 1184 #ifndef p4d_addr_end 1185 #define p4d_addr_end(addr, end) \ 1186 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ 1187 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1188 }) 1189 #endif 1190 1191 #ifndef pud_addr_end 1192 #define pud_addr_end(addr, end) \ 1193 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ 1194 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1195 }) 1196 #endif 1197 1198 #ifndef pmd_addr_end 1199 #define pmd_addr_end(addr, end) \ 1200 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ 1201 (__boundary - 1 < (end) - 1)? __boundary: (end); \ 1202 }) 1203 #endif 1204 1205 /* 1206 * When walking page tables, we usually want to skip any p?d_none entries; 1207 * and any p?d_bad entries - reporting the error before resetting to none. 1208 * Do the tests inline, but report and clear the bad entry in mm/memory.c. 1209 */ 1210 void pgd_clear_bad(pgd_t *); 1211 1212 #ifndef __PAGETABLE_P4D_FOLDED 1213 void p4d_clear_bad(p4d_t *); 1214 #else 1215 #define p4d_clear_bad(p4d) do { } while (0) 1216 #endif 1217 1218 #ifndef __PAGETABLE_PUD_FOLDED 1219 void pud_clear_bad(pud_t *); 1220 #else 1221 #define pud_clear_bad(p4d) do { } while (0) 1222 #endif 1223 1224 void pmd_clear_bad(pmd_t *); 1225 1226 static inline int pgd_none_or_clear_bad(pgd_t *pgd) 1227 { 1228 if (pgd_none(*pgd)) 1229 return 1; 1230 if (unlikely(pgd_bad(*pgd))) { 1231 pgd_clear_bad(pgd); 1232 return 1; 1233 } 1234 return 0; 1235 } 1236 1237 static inline int p4d_none_or_clear_bad(p4d_t *p4d) 1238 { 1239 if (p4d_none(*p4d)) 1240 return 1; 1241 if (unlikely(p4d_bad(*p4d))) { 1242 p4d_clear_bad(p4d); 1243 return 1; 1244 } 1245 return 0; 1246 } 1247 1248 static inline int pud_none_or_clear_bad(pud_t *pud) 1249 { 1250 if (pud_none(*pud)) 1251 return 1; 1252 if (unlikely(pud_bad(*pud))) { 1253 pud_clear_bad(pud); 1254 return 1; 1255 } 1256 return 0; 1257 } 1258 1259 static inline int pmd_none_or_clear_bad(pmd_t *pmd) 1260 { 1261 if (pmd_none(*pmd)) 1262 return 1; 1263 if (unlikely(pmd_bad(*pmd))) { 1264 pmd_clear_bad(pmd); 1265 return 1; 1266 } 1267 return 0; 1268 } 1269 1270 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, 1271 unsigned long addr, 1272 pte_t *ptep) 1273 { 1274 /* 1275 * Get the current pte state, but zero it out to make it 1276 * non-present, preventing the hardware from asynchronously 1277 * updating it. 1278 */ 1279 return ptep_get_and_clear(vma->vm_mm, addr, ptep); 1280 } 1281 1282 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, 1283 unsigned long addr, 1284 pte_t *ptep, pte_t pte) 1285 { 1286 /* 1287 * The pte is non-present, so there's no hardware state to 1288 * preserve. 1289 */ 1290 set_pte_at(vma->vm_mm, addr, ptep, pte); 1291 } 1292 1293 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1294 /* 1295 * Start a pte protection read-modify-write transaction, which 1296 * protects against asynchronous hardware modifications to the pte. 1297 * The intention is not to prevent the hardware from making pte 1298 * updates, but to prevent any updates it may make from being lost. 1299 * 1300 * This does not protect against other software modifications of the 1301 * pte; the appropriate pte lock must be held over the transaction. 1302 * 1303 * Note that this interface is intended to be batchable, meaning that 1304 * ptep_modify_prot_commit may not actually update the pte, but merely 1305 * queue the update to be done at some later time. The update must be 1306 * actually committed before the pte lock is released, however. 1307 */ 1308 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1309 unsigned long addr, 1310 pte_t *ptep) 1311 { 1312 return __ptep_modify_prot_start(vma, addr, ptep); 1313 } 1314 1315 /* 1316 * Commit an update to a pte, leaving any hardware-controlled bits in 1317 * the PTE unmodified. 1318 */ 1319 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, 1320 unsigned long addr, 1321 pte_t *ptep, pte_t old_pte, pte_t pte) 1322 { 1323 __ptep_modify_prot_commit(vma, addr, ptep, pte); 1324 } 1325 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ 1326 #endif /* CONFIG_MMU */ 1327 1328 /* 1329 * No-op macros that just return the current protection value. Defined here 1330 * because these macros can be used even if CONFIG_MMU is not defined. 1331 */ 1332 1333 #ifndef pgprot_nx 1334 #define pgprot_nx(prot) (prot) 1335 #endif 1336 1337 #ifndef pgprot_noncached 1338 #define pgprot_noncached(prot) (prot) 1339 #endif 1340 1341 #ifndef pgprot_writecombine 1342 #define pgprot_writecombine pgprot_noncached 1343 #endif 1344 1345 #ifndef pgprot_writethrough 1346 #define pgprot_writethrough pgprot_noncached 1347 #endif 1348 1349 #ifndef pgprot_device 1350 #define pgprot_device pgprot_noncached 1351 #endif 1352 1353 #ifndef pgprot_mhp 1354 #define pgprot_mhp(prot) (prot) 1355 #endif 1356 1357 #ifdef CONFIG_MMU 1358 #ifndef pgprot_modify 1359 #define pgprot_modify pgprot_modify 1360 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) 1361 { 1362 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) 1363 newprot = pgprot_noncached(newprot); 1364 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) 1365 newprot = pgprot_writecombine(newprot); 1366 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) 1367 newprot = pgprot_device(newprot); 1368 return newprot; 1369 } 1370 #endif 1371 #endif /* CONFIG_MMU */ 1372 1373 #ifndef pgprot_encrypted 1374 #define pgprot_encrypted(prot) (prot) 1375 #endif 1376 1377 #ifndef pgprot_decrypted 1378 #define pgprot_decrypted(prot) (prot) 1379 #endif 1380 1381 /* 1382 * A facility to provide batching of the reload of page tables and 1383 * other process state with the actual context switch code for 1384 * paravirtualized guests. By convention, only one of the batched 1385 * update (lazy) modes (CPU, MMU) should be active at any given time, 1386 * entry should never be nested, and entry and exits should always be 1387 * paired. This is for sanity of maintaining and reasoning about the 1388 * kernel code. In this case, the exit (end of the context switch) is 1389 * in architecture-specific code, and so doesn't need a generic 1390 * definition. 1391 */ 1392 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH 1393 #define arch_start_context_switch(prev) do {} while (0) 1394 #endif 1395 1396 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1397 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION 1398 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1399 { 1400 return pmd; 1401 } 1402 1403 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1404 { 1405 return 0; 1406 } 1407 1408 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1409 { 1410 return pmd; 1411 } 1412 #endif 1413 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1414 static inline int pte_soft_dirty(pte_t pte) 1415 { 1416 return 0; 1417 } 1418 1419 static inline int pmd_soft_dirty(pmd_t pmd) 1420 { 1421 return 0; 1422 } 1423 1424 static inline pte_t pte_mksoft_dirty(pte_t pte) 1425 { 1426 return pte; 1427 } 1428 1429 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 1430 { 1431 return pmd; 1432 } 1433 1434 static inline pte_t pte_clear_soft_dirty(pte_t pte) 1435 { 1436 return pte; 1437 } 1438 1439 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 1440 { 1441 return pmd; 1442 } 1443 1444 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 1445 { 1446 return pte; 1447 } 1448 1449 static inline int pte_swp_soft_dirty(pte_t pte) 1450 { 1451 return 0; 1452 } 1453 1454 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 1455 { 1456 return pte; 1457 } 1458 1459 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) 1460 { 1461 return pmd; 1462 } 1463 1464 static inline int pmd_swp_soft_dirty(pmd_t pmd) 1465 { 1466 return 0; 1467 } 1468 1469 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) 1470 { 1471 return pmd; 1472 } 1473 #endif 1474 1475 #ifndef __HAVE_PFNMAP_TRACKING 1476 /* 1477 * Interfaces that can be used by architecture code to keep track of 1478 * memory type of pfn mappings specified by the remap_pfn_range, 1479 * vmf_insert_pfn. 1480 */ 1481 1482 /* 1483 * track_pfn_remap is called when a _new_ pfn mapping is being established 1484 * by remap_pfn_range() for physical range indicated by pfn and size. 1485 */ 1486 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1487 unsigned long pfn, unsigned long addr, 1488 unsigned long size) 1489 { 1490 return 0; 1491 } 1492 1493 /* 1494 * track_pfn_insert is called when a _new_ single pfn is established 1495 * by vmf_insert_pfn(). 1496 */ 1497 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1498 pfn_t pfn) 1499 { 1500 } 1501 1502 /* 1503 * track_pfn_copy is called when vma that is covering the pfnmap gets 1504 * copied through copy_page_range(). 1505 */ 1506 static inline int track_pfn_copy(struct vm_area_struct *vma) 1507 { 1508 return 0; 1509 } 1510 1511 /* 1512 * untrack_pfn is called while unmapping a pfnmap for a region. 1513 * untrack can be called for a specific region indicated by pfn and size or 1514 * can be for the entire vma (in which case pfn, size are zero). 1515 */ 1516 static inline void untrack_pfn(struct vm_area_struct *vma, 1517 unsigned long pfn, unsigned long size, 1518 bool mm_wr_locked) 1519 { 1520 } 1521 1522 /* 1523 * untrack_pfn_clear is called while mremapping a pfnmap for a new region 1524 * or fails to copy pgtable during duplicate vm area. 1525 */ 1526 static inline void untrack_pfn_clear(struct vm_area_struct *vma) 1527 { 1528 } 1529 #else 1530 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, 1531 unsigned long pfn, unsigned long addr, 1532 unsigned long size); 1533 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, 1534 pfn_t pfn); 1535 extern int track_pfn_copy(struct vm_area_struct *vma); 1536 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, 1537 unsigned long size, bool mm_wr_locked); 1538 extern void untrack_pfn_clear(struct vm_area_struct *vma); 1539 #endif 1540 1541 #ifdef CONFIG_MMU 1542 #ifdef __HAVE_COLOR_ZERO_PAGE 1543 static inline int is_zero_pfn(unsigned long pfn) 1544 { 1545 extern unsigned long zero_pfn; 1546 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 1547 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 1548 } 1549 1550 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 1551 1552 #else 1553 static inline int is_zero_pfn(unsigned long pfn) 1554 { 1555 extern unsigned long zero_pfn; 1556 return pfn == zero_pfn; 1557 } 1558 1559 static inline unsigned long my_zero_pfn(unsigned long addr) 1560 { 1561 extern unsigned long zero_pfn; 1562 return zero_pfn; 1563 } 1564 #endif 1565 #else 1566 static inline int is_zero_pfn(unsigned long pfn) 1567 { 1568 return 0; 1569 } 1570 1571 static inline unsigned long my_zero_pfn(unsigned long addr) 1572 { 1573 return 0; 1574 } 1575 #endif /* CONFIG_MMU */ 1576 1577 #ifdef CONFIG_MMU 1578 1579 #ifndef CONFIG_TRANSPARENT_HUGEPAGE 1580 static inline int pmd_trans_huge(pmd_t pmd) 1581 { 1582 return 0; 1583 } 1584 #ifndef pmd_write 1585 static inline int pmd_write(pmd_t pmd) 1586 { 1587 BUG(); 1588 return 0; 1589 } 1590 #endif /* pmd_write */ 1591 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1592 1593 #ifndef pud_write 1594 static inline int pud_write(pud_t pud) 1595 { 1596 BUG(); 1597 return 0; 1598 } 1599 #endif /* pud_write */ 1600 1601 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) 1602 static inline int pmd_devmap(pmd_t pmd) 1603 { 1604 return 0; 1605 } 1606 static inline int pud_devmap(pud_t pud) 1607 { 1608 return 0; 1609 } 1610 static inline int pgd_devmap(pgd_t pgd) 1611 { 1612 return 0; 1613 } 1614 #endif 1615 1616 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ 1617 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1618 static inline int pud_trans_huge(pud_t pud) 1619 { 1620 return 0; 1621 } 1622 #endif 1623 1624 static inline int pud_trans_unstable(pud_t *pud) 1625 { 1626 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ 1627 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1628 pud_t pudval = READ_ONCE(*pud); 1629 1630 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) 1631 return 1; 1632 if (unlikely(pud_bad(pudval))) { 1633 pud_clear_bad(pud); 1634 return 1; 1635 } 1636 #endif 1637 return 0; 1638 } 1639 1640 #ifndef CONFIG_NUMA_BALANCING 1641 /* 1642 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is 1643 * perfectly valid to indicate "no" in that case, which is why our default 1644 * implementation defaults to "always no". 1645 * 1646 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE 1647 * page protection due to NUMA hinting. NUMA hinting faults only apply in 1648 * accessible VMAs. 1649 * 1650 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault, 1651 * looking at the VMA accessibility is sufficient. 1652 */ 1653 static inline int pte_protnone(pte_t pte) 1654 { 1655 return 0; 1656 } 1657 1658 static inline int pmd_protnone(pmd_t pmd) 1659 { 1660 return 0; 1661 } 1662 #endif /* CONFIG_NUMA_BALANCING */ 1663 1664 #endif /* CONFIG_MMU */ 1665 1666 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP 1667 1668 #ifndef __PAGETABLE_P4D_FOLDED 1669 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); 1670 void p4d_clear_huge(p4d_t *p4d); 1671 #else 1672 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1673 { 1674 return 0; 1675 } 1676 static inline void p4d_clear_huge(p4d_t *p4d) { } 1677 #endif /* !__PAGETABLE_P4D_FOLDED */ 1678 1679 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); 1680 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); 1681 int pud_clear_huge(pud_t *pud); 1682 int pmd_clear_huge(pmd_t *pmd); 1683 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); 1684 int pud_free_pmd_page(pud_t *pud, unsigned long addr); 1685 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); 1686 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ 1687 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) 1688 { 1689 return 0; 1690 } 1691 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) 1692 { 1693 return 0; 1694 } 1695 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) 1696 { 1697 return 0; 1698 } 1699 static inline void p4d_clear_huge(p4d_t *p4d) { } 1700 static inline int pud_clear_huge(pud_t *pud) 1701 { 1702 return 0; 1703 } 1704 static inline int pmd_clear_huge(pmd_t *pmd) 1705 { 1706 return 0; 1707 } 1708 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) 1709 { 1710 return 0; 1711 } 1712 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) 1713 { 1714 return 0; 1715 } 1716 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) 1717 { 1718 return 0; 1719 } 1720 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 1721 1722 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 1723 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1724 /* 1725 * ARCHes with special requirements for evicting THP backing TLB entries can 1726 * implement this. Otherwise also, it can help optimize normal TLB flush in 1727 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the 1728 * entire TLB if flush span is greater than a threshold, which will 1729 * likely be true for a single huge page. Thus a single THP flush will 1730 * invalidate the entire TLB which is not desirable. 1731 * e.g. see arch/arc: flush_pmd_tlb_range 1732 */ 1733 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1734 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) 1735 #else 1736 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() 1737 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() 1738 #endif 1739 #endif 1740 1741 struct file; 1742 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, 1743 unsigned long size, pgprot_t *vma_prot); 1744 1745 #ifndef CONFIG_X86_ESPFIX64 1746 static inline void init_espfix_bsp(void) { } 1747 #endif 1748 1749 extern void __init pgtable_cache_init(void); 1750 1751 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED 1752 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) 1753 { 1754 return true; 1755 } 1756 1757 static inline bool arch_has_pfn_modify_check(void) 1758 { 1759 return false; 1760 } 1761 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ 1762 1763 /* 1764 * Architecture PAGE_KERNEL_* fallbacks 1765 * 1766 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either 1767 * because they really don't support them, or the port needs to be updated to 1768 * reflect the required functionality. Below are a set of relatively safe 1769 * fallbacks, as best effort, which we can count on in lieu of the architectures 1770 * not defining them on their own yet. 1771 */ 1772 1773 #ifndef PAGE_KERNEL_RO 1774 # define PAGE_KERNEL_RO PAGE_KERNEL 1775 #endif 1776 1777 #ifndef PAGE_KERNEL_EXEC 1778 # define PAGE_KERNEL_EXEC PAGE_KERNEL 1779 #endif 1780 1781 /* 1782 * Page Table Modification bits for pgtbl_mod_mask. 1783 * 1784 * These are used by the p?d_alloc_track*() set of functions an in the generic 1785 * vmalloc/ioremap code to track at which page-table levels entries have been 1786 * modified. Based on that the code can better decide when vmalloc and ioremap 1787 * mapping changes need to be synchronized to other page-tables in the system. 1788 */ 1789 #define __PGTBL_PGD_MODIFIED 0 1790 #define __PGTBL_P4D_MODIFIED 1 1791 #define __PGTBL_PUD_MODIFIED 2 1792 #define __PGTBL_PMD_MODIFIED 3 1793 #define __PGTBL_PTE_MODIFIED 4 1794 1795 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) 1796 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) 1797 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) 1798 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) 1799 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) 1800 1801 /* Page-Table Modification Mask */ 1802 typedef unsigned int pgtbl_mod_mask; 1803 1804 #endif /* !__ASSEMBLY__ */ 1805 1806 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) 1807 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1808 /* 1809 * ZSMALLOC needs to know the highest PFN on 32-bit architectures 1810 * with physical address space extension, but falls back to 1811 * BITS_PER_LONG otherwise. 1812 */ 1813 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition 1814 #else 1815 #define MAX_POSSIBLE_PHYSMEM_BITS 32 1816 #endif 1817 #endif 1818 1819 #ifndef has_transparent_hugepage 1820 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE) 1821 #endif 1822 1823 #ifndef has_transparent_pud_hugepage 1824 #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) 1825 #endif 1826 /* 1827 * On some architectures it depends on the mm if the p4d/pud or pmd 1828 * layer of the page table hierarchy is folded or not. 1829 */ 1830 #ifndef mm_p4d_folded 1831 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) 1832 #endif 1833 1834 #ifndef mm_pud_folded 1835 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) 1836 #endif 1837 1838 #ifndef mm_pmd_folded 1839 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) 1840 #endif 1841 1842 #ifndef p4d_offset_lockless 1843 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) 1844 #endif 1845 #ifndef pud_offset_lockless 1846 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) 1847 #endif 1848 #ifndef pmd_offset_lockless 1849 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) 1850 #endif 1851 1852 /* 1853 * pXd_leaf() is the API to check whether a pgtable entry is a huge page 1854 * mapping. It should work globally across all archs, without any 1855 * dependency on CONFIG_* options. For architectures that do not support 1856 * huge mappings on specific levels, below fallbacks will be used. 1857 * 1858 * A leaf pgtable entry should always imply the following: 1859 * 1860 * - It is a "present" entry. IOW, before using this API, please check it 1861 * with pXd_present() first. NOTE: it may not always mean the "present 1862 * bit" is set. For example, PROT_NONE entries are always "present". 1863 * 1864 * - It should _never_ be a swap entry of any type. Above "present" check 1865 * should have guarded this, but let's be crystal clear on this. 1866 * 1867 * - It should contain a huge PFN, which points to a huge page larger than 1868 * PAGE_SIZE of the platform. The PFN format isn't important here. 1869 * 1870 * - It should cover all kinds of huge mappings (e.g., pXd_trans_huge(), 1871 * pXd_devmap(), or hugetlb mappings). 1872 */ 1873 #ifndef pgd_leaf 1874 #define pgd_leaf(x) false 1875 #endif 1876 #ifndef p4d_leaf 1877 #define p4d_leaf(x) false 1878 #endif 1879 #ifndef pud_leaf 1880 #define pud_leaf(x) false 1881 #endif 1882 #ifndef pmd_leaf 1883 #define pmd_leaf(x) false 1884 #endif 1885 1886 #ifndef pgd_leaf_size 1887 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) 1888 #endif 1889 #ifndef p4d_leaf_size 1890 #define p4d_leaf_size(x) P4D_SIZE 1891 #endif 1892 #ifndef pud_leaf_size 1893 #define pud_leaf_size(x) PUD_SIZE 1894 #endif 1895 #ifndef pmd_leaf_size 1896 #define pmd_leaf_size(x) PMD_SIZE 1897 #endif 1898 #ifndef pte_leaf_size 1899 #define pte_leaf_size(x) PAGE_SIZE 1900 #endif 1901 1902 /* 1903 * We always define pmd_pfn for all archs as it's used in lots of generic 1904 * code. Now it happens too for pud_pfn (and can happen for larger 1905 * mappings too in the future; we're not there yet). Instead of defining 1906 * it for all archs (like pmd_pfn), provide a fallback. 1907 * 1908 * Note that returning 0 here means any arch that didn't define this can 1909 * get severely wrong when it hits a real pud leaf. It's arch's 1910 * responsibility to properly define it when a huge pud is possible. 1911 */ 1912 #ifndef pud_pfn 1913 #define pud_pfn(x) 0 1914 #endif 1915 1916 /* 1917 * Some architectures have MMUs that are configurable or selectable at boot 1918 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it 1919 * helps to have a static maximum value. 1920 */ 1921 1922 #ifndef MAX_PTRS_PER_PTE 1923 #define MAX_PTRS_PER_PTE PTRS_PER_PTE 1924 #endif 1925 1926 #ifndef MAX_PTRS_PER_PMD 1927 #define MAX_PTRS_PER_PMD PTRS_PER_PMD 1928 #endif 1929 1930 #ifndef MAX_PTRS_PER_PUD 1931 #define MAX_PTRS_PER_PUD PTRS_PER_PUD 1932 #endif 1933 1934 #ifndef MAX_PTRS_PER_P4D 1935 #define MAX_PTRS_PER_P4D PTRS_PER_P4D 1936 #endif 1937 1938 /* description of effects of mapping type and prot in current implementation. 1939 * this is due to the limited x86 page protection hardware. The expected 1940 * behavior is in parens: 1941 * 1942 * map_type prot 1943 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC 1944 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1945 * w: (no) no w: (no) no w: (yes) yes w: (no) no 1946 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1947 * 1948 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes 1949 * w: (no) no w: (no) no w: (copy) copy w: (no) no 1950 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes 1951 * 1952 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and 1953 * MAP_PRIVATE (with Enhanced PAN supported): 1954 * r: (no) no 1955 * w: (no) no 1956 * x: (yes) yes 1957 */ 1958 #define DECLARE_VM_GET_PAGE_PROT \ 1959 pgprot_t vm_get_page_prot(unsigned long vm_flags) \ 1960 { \ 1961 return protection_map[vm_flags & \ 1962 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \ 1963 } \ 1964 EXPORT_SYMBOL(vm_get_page_prot); 1965 1966 #endif /* _LINUX_PGTABLE_H */ 1967