1 /* 2 * linux/arch/arm/include/asm/pmu.h 3 * 4 * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 */ 11 12 #ifndef __ARM_PMU_H__ 13 #define __ARM_PMU_H__ 14 15 #include <linux/interrupt.h> 16 #include <linux/perf_event.h> 17 #include <linux/platform_device.h> 18 #include <linux/sysfs.h> 19 #include <asm/cputype.h> 20 21 #ifdef CONFIG_ARM_PMU 22 23 /* 24 * The ARMv7 CPU PMU supports up to 32 event counters. 25 */ 26 #define ARMPMU_MAX_HWEVENTS 32 27 28 #define HW_OP_UNSUPPORTED 0xFFFF 29 #define C(_x) PERF_COUNT_HW_CACHE_##_x 30 #define CACHE_OP_UNSUPPORTED 0xFFFF 31 32 #define PERF_MAP_ALL_UNSUPPORTED \ 33 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED 34 35 #define PERF_CACHE_MAP_ALL_UNSUPPORTED \ 36 [0 ... C(MAX) - 1] = { \ 37 [0 ... C(OP_MAX) - 1] = { \ 38 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \ 39 }, \ 40 } 41 42 /* The events for a given PMU register set. */ 43 struct pmu_hw_events { 44 /* 45 * The events that are active on the PMU for the given index. 46 */ 47 struct perf_event *events[ARMPMU_MAX_HWEVENTS]; 48 49 /* 50 * A 1 bit for an index indicates that the counter is being used for 51 * an event. A 0 means that the counter can be used. 52 */ 53 DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS); 54 55 /* 56 * Hardware lock to serialize accesses to PMU registers. Needed for the 57 * read/modify/write sequences. 58 */ 59 raw_spinlock_t pmu_lock; 60 61 /* 62 * When using percpu IRQs, we need a percpu dev_id. Place it here as we 63 * already have to allocate this struct per cpu. 64 */ 65 struct arm_pmu *percpu_pmu; 66 67 int irq; 68 }; 69 70 enum armpmu_attr_groups { 71 ARMPMU_ATTR_GROUP_COMMON, 72 ARMPMU_ATTR_GROUP_EVENTS, 73 ARMPMU_ATTR_GROUP_FORMATS, 74 ARMPMU_NR_ATTR_GROUPS 75 }; 76 77 struct arm_pmu { 78 struct pmu pmu; 79 cpumask_t supported_cpus; 80 char *name; 81 irqreturn_t (*handle_irq)(int irq_num, void *dev); 82 void (*enable)(struct perf_event *event); 83 void (*disable)(struct perf_event *event); 84 int (*get_event_idx)(struct pmu_hw_events *hw_events, 85 struct perf_event *event); 86 void (*clear_event_idx)(struct pmu_hw_events *hw_events, 87 struct perf_event *event); 88 int (*set_event_filter)(struct hw_perf_event *evt, 89 struct perf_event_attr *attr); 90 u32 (*read_counter)(struct perf_event *event); 91 void (*write_counter)(struct perf_event *event, u32 val); 92 void (*start)(struct arm_pmu *); 93 void (*stop)(struct arm_pmu *); 94 void (*reset)(void *); 95 int (*map_event)(struct perf_event *event); 96 int num_events; 97 u64 max_period; 98 bool secure_access; /* 32-bit ARM only */ 99 #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40 100 DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); 101 struct platform_device *plat_device; 102 struct pmu_hw_events __percpu *hw_events; 103 struct hlist_node node; 104 struct notifier_block cpu_pm_nb; 105 /* the attr_groups array must be NULL-terminated */ 106 const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1]; 107 108 /* Only to be used by ACPI probing code */ 109 unsigned long acpi_cpuid; 110 }; 111 112 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) 113 114 u64 armpmu_event_update(struct perf_event *event); 115 116 int armpmu_event_set_period(struct perf_event *event); 117 118 int armpmu_map_event(struct perf_event *event, 119 const unsigned (*event_map)[PERF_COUNT_HW_MAX], 120 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] 121 [PERF_COUNT_HW_CACHE_OP_MAX] 122 [PERF_COUNT_HW_CACHE_RESULT_MAX], 123 u32 raw_event_mask); 124 125 typedef int (*armpmu_init_fn)(struct arm_pmu *); 126 127 struct pmu_probe_info { 128 unsigned int cpuid; 129 unsigned int mask; 130 armpmu_init_fn init; 131 }; 132 133 #define PMU_PROBE(_cpuid, _mask, _fn) \ 134 { \ 135 .cpuid = (_cpuid), \ 136 .mask = (_mask), \ 137 .init = (_fn), \ 138 } 139 140 #define ARM_PMU_PROBE(_cpuid, _fn) \ 141 PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn) 142 143 #define ARM_PMU_XSCALE_MASK ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK) 144 145 #define XSCALE_PMU_PROBE(_version, _fn) \ 146 PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn) 147 148 int arm_pmu_device_probe(struct platform_device *pdev, 149 const struct of_device_id *of_table, 150 const struct pmu_probe_info *probe_table); 151 152 #ifdef CONFIG_ACPI 153 int arm_pmu_acpi_probe(armpmu_init_fn init_fn); 154 #else 155 static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; } 156 #endif 157 158 /* Internal functions only for core arm_pmu code */ 159 struct arm_pmu *armpmu_alloc(void); 160 struct arm_pmu *armpmu_alloc_atomic(void); 161 void armpmu_free(struct arm_pmu *pmu); 162 int armpmu_register(struct arm_pmu *pmu); 163 int armpmu_request_irq(int irq, int cpu); 164 void armpmu_free_irq(int irq, int cpu); 165 166 #define ARMV8_PMU_PDEV_NAME "armv8-pmu" 167 168 #endif /* CONFIG_ARM_PMU */ 169 170 #endif /* __ARM_PMU_H__ */ 171