1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <linux/resource_ext.h> 33 #include <uapi/linux/pci.h> 34 35 #include <linux/pci_ids.h> 36 37 /* 38 * The PCI interface treats multi-function devices as independent 39 * devices. The slot/function address of each device is encoded 40 * in a single byte as follows: 41 * 42 * 7:3 = slot 43 * 2:0 = function 44 * 45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 46 * In the interest of not exposing interfaces to user-space unnecessarily, 47 * the following kernel-only defines are being added here. 48 */ 49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 52 53 /* pci_slot represents a physical slot */ 54 struct pci_slot { 55 struct pci_bus *bus; /* The bus this slot is on */ 56 struct list_head list; /* node in list of slots on this bus */ 57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 59 struct kobject kobj; 60 }; 61 62 static inline const char *pci_slot_name(const struct pci_slot *slot) 63 { 64 return kobject_name(&slot->kobj); 65 } 66 67 /* File state for mmap()s on /proc/bus/pci/X/Y */ 68 enum pci_mmap_state { 69 pci_mmap_io, 70 pci_mmap_mem 71 }; 72 73 /* This defines the direction arg to the DMA mapping routines. */ 74 #define PCI_DMA_BIDIRECTIONAL 0 75 #define PCI_DMA_TODEVICE 1 76 #define PCI_DMA_FROMDEVICE 2 77 #define PCI_DMA_NONE 3 78 79 /* 80 * For PCI devices, the region numbers are assigned this way: 81 */ 82 enum { 83 /* #0-5: standard PCI resources */ 84 PCI_STD_RESOURCES, 85 PCI_STD_RESOURCE_END = 5, 86 87 /* #6: expansion ROM resource */ 88 PCI_ROM_RESOURCE, 89 90 /* device specific resources */ 91 #ifdef CONFIG_PCI_IOV 92 PCI_IOV_RESOURCES, 93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 94 #endif 95 96 /* resources assigned to buses behind the bridge */ 97 #define PCI_BRIDGE_RESOURCE_NUM 4 98 99 PCI_BRIDGE_RESOURCES, 100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 101 PCI_BRIDGE_RESOURCE_NUM - 1, 102 103 /* total resources associated with a PCI device */ 104 PCI_NUM_RESOURCES, 105 106 /* preserve this for compatibility */ 107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 108 }; 109 110 typedef int __bitwise pci_power_t; 111 112 #define PCI_D0 ((pci_power_t __force) 0) 113 #define PCI_D1 ((pci_power_t __force) 1) 114 #define PCI_D2 ((pci_power_t __force) 2) 115 #define PCI_D3hot ((pci_power_t __force) 3) 116 #define PCI_D3cold ((pci_power_t __force) 4) 117 #define PCI_UNKNOWN ((pci_power_t __force) 5) 118 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 119 120 /* Remember to update this when the list above changes! */ 121 extern const char *pci_power_names[]; 122 123 static inline const char *pci_power_name(pci_power_t state) 124 { 125 return pci_power_names[1 + (int) state]; 126 } 127 128 #define PCI_PM_D2_DELAY 200 129 #define PCI_PM_D3_WAIT 10 130 #define PCI_PM_D3COLD_WAIT 100 131 #define PCI_PM_BUS_WAIT 50 132 133 /** The pci_channel state describes connectivity between the CPU and 134 * the pci device. If some PCI bus between here and the pci device 135 * has crashed or locked up, this info is reflected here. 136 */ 137 typedef unsigned int __bitwise pci_channel_state_t; 138 139 enum pci_channel_state { 140 /* I/O channel is in normal state */ 141 pci_channel_io_normal = (__force pci_channel_state_t) 1, 142 143 /* I/O to channel is blocked */ 144 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 145 146 /* PCI card is dead */ 147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 148 }; 149 150 typedef unsigned int __bitwise pcie_reset_state_t; 151 152 enum pcie_reset_state { 153 /* Reset is NOT asserted (Use to deassert reset) */ 154 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 155 156 /* Use #PERST to reset PCIe device */ 157 pcie_warm_reset = (__force pcie_reset_state_t) 2, 158 159 /* Use PCIe Hot Reset to reset device */ 160 pcie_hot_reset = (__force pcie_reset_state_t) 3 161 }; 162 163 typedef unsigned short __bitwise pci_dev_flags_t; 164 enum pci_dev_flags { 165 /* INTX_DISABLE in PCI_COMMAND register disables MSI 166 * generation too. 167 */ 168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 169 /* Device configuration is irrevocably lost if disabled into D3 */ 170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 171 /* Provide indication device is assigned by a Virtual Machine Manager */ 172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 173 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 175 /* Flag to indicate the device uses dma_alias_devfn */ 176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), 177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 179 /* Do not use bus resets for device */ 180 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 181 /* Do not use PM reset even if device advertises NoSoftRst- */ 182 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 183 /* Get VPD from function 0 VPD */ 184 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 185 }; 186 187 enum pci_irq_reroute_variant { 188 INTEL_IRQ_REROUTE_VARIANT = 1, 189 MAX_IRQ_REROUTE_VARIANTS = 3 190 }; 191 192 typedef unsigned short __bitwise pci_bus_flags_t; 193 enum pci_bus_flags { 194 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 195 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 196 }; 197 198 /* These values come from the PCI Express Spec */ 199 enum pcie_link_width { 200 PCIE_LNK_WIDTH_RESRV = 0x00, 201 PCIE_LNK_X1 = 0x01, 202 PCIE_LNK_X2 = 0x02, 203 PCIE_LNK_X4 = 0x04, 204 PCIE_LNK_X8 = 0x08, 205 PCIE_LNK_X12 = 0x0C, 206 PCIE_LNK_X16 = 0x10, 207 PCIE_LNK_X32 = 0x20, 208 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 209 }; 210 211 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 212 enum pci_bus_speed { 213 PCI_SPEED_33MHz = 0x00, 214 PCI_SPEED_66MHz = 0x01, 215 PCI_SPEED_66MHz_PCIX = 0x02, 216 PCI_SPEED_100MHz_PCIX = 0x03, 217 PCI_SPEED_133MHz_PCIX = 0x04, 218 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 219 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 220 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 221 PCI_SPEED_66MHz_PCIX_266 = 0x09, 222 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 223 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 224 AGP_UNKNOWN = 0x0c, 225 AGP_1X = 0x0d, 226 AGP_2X = 0x0e, 227 AGP_4X = 0x0f, 228 AGP_8X = 0x10, 229 PCI_SPEED_66MHz_PCIX_533 = 0x11, 230 PCI_SPEED_100MHz_PCIX_533 = 0x12, 231 PCI_SPEED_133MHz_PCIX_533 = 0x13, 232 PCIE_SPEED_2_5GT = 0x14, 233 PCIE_SPEED_5_0GT = 0x15, 234 PCIE_SPEED_8_0GT = 0x16, 235 PCI_SPEED_UNKNOWN = 0xff, 236 }; 237 238 struct pci_cap_saved_data { 239 u16 cap_nr; 240 bool cap_extended; 241 unsigned int size; 242 u32 data[0]; 243 }; 244 245 struct pci_cap_saved_state { 246 struct hlist_node next; 247 struct pci_cap_saved_data cap; 248 }; 249 250 struct pcie_link_state; 251 struct pci_vpd; 252 struct pci_sriov; 253 struct pci_ats; 254 255 /* 256 * The pci_dev structure is used to describe PCI devices. 257 */ 258 struct pci_dev { 259 struct list_head bus_list; /* node in per-bus list */ 260 struct pci_bus *bus; /* bus this device is on */ 261 struct pci_bus *subordinate; /* bus this device bridges to */ 262 263 void *sysdata; /* hook for sys-specific extension */ 264 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 265 struct pci_slot *slot; /* Physical slot this device is in */ 266 267 unsigned int devfn; /* encoded device & function index */ 268 unsigned short vendor; 269 unsigned short device; 270 unsigned short subsystem_vendor; 271 unsigned short subsystem_device; 272 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 273 u8 revision; /* PCI revision, low byte of class word */ 274 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 275 u8 pcie_cap; /* PCIe capability offset */ 276 u8 msi_cap; /* MSI capability offset */ 277 u8 msix_cap; /* MSI-X capability offset */ 278 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 279 u8 rom_base_reg; /* which config register controls the ROM */ 280 u8 pin; /* which interrupt pin this device uses */ 281 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 282 u8 dma_alias_devfn;/* devfn of DMA alias, if any */ 283 284 struct pci_driver *driver; /* which driver has allocated this device */ 285 u64 dma_mask; /* Mask of the bits of bus address this 286 device implements. Normally this is 287 0xffffffff. You only need to change 288 this if your device has broken DMA 289 or supports 64-bit transfers. */ 290 291 struct device_dma_parameters dma_parms; 292 293 pci_power_t current_state; /* Current operating state. In ACPI-speak, 294 this is D0-D3, D0 being fully functional, 295 and D3 being off. */ 296 u8 pm_cap; /* PM capability offset */ 297 unsigned int pme_support:5; /* Bitmask of states from which PME# 298 can be generated */ 299 unsigned int pme_interrupt:1; 300 unsigned int pme_poll:1; /* Poll device's PME status bit */ 301 unsigned int d1_support:1; /* Low power state D1 is supported */ 302 unsigned int d2_support:1; /* Low power state D2 is supported */ 303 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 304 unsigned int no_d3cold:1; /* D3cold is forbidden */ 305 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 306 unsigned int mmio_always_on:1; /* disallow turning off io/mem 307 decoding during bar sizing */ 308 unsigned int wakeup_prepared:1; 309 unsigned int runtime_d3cold:1; /* whether go through runtime 310 D3cold, not set for devices 311 powered on/off by the 312 corresponding bridge */ 313 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 314 unsigned int d3_delay; /* D3->D0 transition time in ms */ 315 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 316 317 #ifdef CONFIG_PCIEASPM 318 struct pcie_link_state *link_state; /* ASPM link state */ 319 #endif 320 321 pci_channel_state_t error_state; /* current connectivity state */ 322 struct device dev; /* Generic device interface */ 323 324 int cfg_size; /* Size of configuration space */ 325 326 /* 327 * Instead of touching interrupt line and base address registers 328 * directly, use the values stored here. They might be different! 329 */ 330 unsigned int irq; 331 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 332 333 bool match_driver; /* Skip attaching driver */ 334 /* These fields are used by common fixups */ 335 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 336 unsigned int multifunction:1;/* Part of multi-function device */ 337 /* keep track of device state */ 338 unsigned int is_added:1; 339 unsigned int is_busmaster:1; /* device is busmaster */ 340 unsigned int no_msi:1; /* device may not use msi */ 341 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 342 unsigned int block_cfg_access:1; /* config space access is blocked */ 343 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 344 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 345 unsigned int msi_enabled:1; 346 unsigned int msix_enabled:1; 347 unsigned int ari_enabled:1; /* ARI forwarding */ 348 unsigned int ats_enabled:1; /* Address Translation Service */ 349 unsigned int is_managed:1; 350 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 351 unsigned int state_saved:1; 352 unsigned int is_physfn:1; 353 unsigned int is_virtfn:1; 354 unsigned int reset_fn:1; 355 unsigned int is_hotplug_bridge:1; 356 unsigned int __aer_firmware_first_valid:1; 357 unsigned int __aer_firmware_first:1; 358 unsigned int broken_intx_masking:1; 359 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 360 unsigned int irq_managed:1; 361 unsigned int has_secondary_link:1; 362 pci_dev_flags_t dev_flags; 363 atomic_t enable_cnt; /* pci_enable_device has been called */ 364 365 u32 saved_config_space[16]; /* config space saved at suspend time */ 366 struct hlist_head saved_cap_space; 367 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 368 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 369 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 370 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 371 #ifdef CONFIG_PCI_MSI 372 const struct attribute_group **msi_irq_groups; 373 #endif 374 struct pci_vpd *vpd; 375 #ifdef CONFIG_PCI_ATS 376 union { 377 struct pci_sriov *sriov; /* SR-IOV capability related */ 378 struct pci_dev *physfn; /* the PF this VF is associated with */ 379 }; 380 u16 ats_cap; /* ATS Capability offset */ 381 u8 ats_stu; /* ATS Smallest Translation Unit */ 382 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 383 #endif 384 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 385 size_t romlen; /* Length of ROM if it's not from the BAR */ 386 char *driver_override; /* Driver name to force a match */ 387 }; 388 389 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 390 { 391 #ifdef CONFIG_PCI_IOV 392 if (dev->is_virtfn) 393 dev = dev->physfn; 394 #endif 395 return dev; 396 } 397 398 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 399 400 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 401 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 402 403 static inline int pci_channel_offline(struct pci_dev *pdev) 404 { 405 return (pdev->error_state != pci_channel_io_normal); 406 } 407 408 struct pci_host_bridge { 409 struct device dev; 410 struct pci_bus *bus; /* root bus */ 411 struct list_head windows; /* resource_entry */ 412 void (*release_fn)(struct pci_host_bridge *); 413 void *release_data; 414 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 415 }; 416 417 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 418 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 419 void (*release_fn)(struct pci_host_bridge *), 420 void *release_data); 421 422 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 423 424 /* 425 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 426 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 427 * buses below host bridges or subtractive decode bridges) go in the list. 428 * Use pci_bus_for_each_resource() to iterate through all the resources. 429 */ 430 431 /* 432 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 433 * and there's no way to program the bridge with the details of the window. 434 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 435 * decode bit set, because they are explicit and can be programmed with _SRS. 436 */ 437 #define PCI_SUBTRACTIVE_DECODE 0x1 438 439 struct pci_bus_resource { 440 struct list_head list; 441 struct resource *res; 442 unsigned int flags; 443 }; 444 445 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 446 447 struct pci_bus { 448 struct list_head node; /* node in list of buses */ 449 struct pci_bus *parent; /* parent bus this bridge is on */ 450 struct list_head children; /* list of child buses */ 451 struct list_head devices; /* list of devices on this bus */ 452 struct pci_dev *self; /* bridge device as seen by parent */ 453 struct list_head slots; /* list of slots on this bus; 454 protected by pci_slot_mutex */ 455 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 456 struct list_head resources; /* address space routed to this bus */ 457 struct resource busn_res; /* bus numbers routed to this bus */ 458 459 struct pci_ops *ops; /* configuration access functions */ 460 struct msi_controller *msi; /* MSI controller */ 461 void *sysdata; /* hook for sys-specific extension */ 462 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 463 464 unsigned char number; /* bus number */ 465 unsigned char primary; /* number of primary bridge */ 466 unsigned char max_bus_speed; /* enum pci_bus_speed */ 467 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 468 #ifdef CONFIG_PCI_DOMAINS_GENERIC 469 int domain_nr; 470 #endif 471 472 char name[48]; 473 474 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 475 pci_bus_flags_t bus_flags; /* inherited by child buses */ 476 struct device *bridge; 477 struct device dev; 478 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 479 struct bin_attribute *legacy_mem; /* legacy mem */ 480 unsigned int is_added:1; 481 }; 482 483 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 484 485 /* 486 * Returns true if the PCI bus is root (behind host-PCI bridge), 487 * false otherwise 488 * 489 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 490 * This is incorrect because "virtual" buses added for SR-IOV (via 491 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 492 */ 493 static inline bool pci_is_root_bus(struct pci_bus *pbus) 494 { 495 return !(pbus->parent); 496 } 497 498 /** 499 * pci_is_bridge - check if the PCI device is a bridge 500 * @dev: PCI device 501 * 502 * Return true if the PCI device is bridge whether it has subordinate 503 * or not. 504 */ 505 static inline bool pci_is_bridge(struct pci_dev *dev) 506 { 507 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 508 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 509 } 510 511 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 512 { 513 dev = pci_physfn(dev); 514 if (pci_is_root_bus(dev->bus)) 515 return NULL; 516 517 return dev->bus->self; 518 } 519 520 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 521 void pci_put_host_bridge_device(struct device *dev); 522 523 #ifdef CONFIG_PCI_MSI 524 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 525 { 526 return pci_dev->msi_enabled || pci_dev->msix_enabled; 527 } 528 #else 529 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 530 #endif 531 532 /* 533 * Error values that may be returned by PCI functions. 534 */ 535 #define PCIBIOS_SUCCESSFUL 0x00 536 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 537 #define PCIBIOS_BAD_VENDOR_ID 0x83 538 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 539 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 540 #define PCIBIOS_SET_FAILED 0x88 541 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 542 543 /* 544 * Translate above to generic errno for passing back through non-PCI code. 545 */ 546 static inline int pcibios_err_to_errno(int err) 547 { 548 if (err <= PCIBIOS_SUCCESSFUL) 549 return err; /* Assume already errno */ 550 551 switch (err) { 552 case PCIBIOS_FUNC_NOT_SUPPORTED: 553 return -ENOENT; 554 case PCIBIOS_BAD_VENDOR_ID: 555 return -ENOTTY; 556 case PCIBIOS_DEVICE_NOT_FOUND: 557 return -ENODEV; 558 case PCIBIOS_BAD_REGISTER_NUMBER: 559 return -EFAULT; 560 case PCIBIOS_SET_FAILED: 561 return -EIO; 562 case PCIBIOS_BUFFER_TOO_SMALL: 563 return -ENOSPC; 564 } 565 566 return -ERANGE; 567 } 568 569 /* Low-level architecture-dependent routines */ 570 571 struct pci_ops { 572 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 573 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 574 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 575 }; 576 577 /* 578 * ACPI needs to be able to access PCI config space before we've done a 579 * PCI bus scan and created pci_bus structures. 580 */ 581 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 582 int reg, int len, u32 *val); 583 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 584 int reg, int len, u32 val); 585 586 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 587 typedef u64 pci_bus_addr_t; 588 #else 589 typedef u32 pci_bus_addr_t; 590 #endif 591 592 struct pci_bus_region { 593 pci_bus_addr_t start; 594 pci_bus_addr_t end; 595 }; 596 597 struct pci_dynids { 598 spinlock_t lock; /* protects list, index */ 599 struct list_head list; /* for IDs added at runtime */ 600 }; 601 602 603 /* 604 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 605 * a set of callbacks in struct pci_error_handlers, that device driver 606 * will be notified of PCI bus errors, and will be driven to recovery 607 * when an error occurs. 608 */ 609 610 typedef unsigned int __bitwise pci_ers_result_t; 611 612 enum pci_ers_result { 613 /* no result/none/not supported in device driver */ 614 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 615 616 /* Device driver can recover without slot reset */ 617 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 618 619 /* Device driver wants slot to be reset. */ 620 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 621 622 /* Device has completely failed, is unrecoverable */ 623 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 624 625 /* Device driver is fully recovered and operational */ 626 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 627 628 /* No AER capabilities registered for the driver */ 629 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 630 }; 631 632 /* PCI bus error event callbacks */ 633 struct pci_error_handlers { 634 /* PCI bus error detected on this device */ 635 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 636 enum pci_channel_state error); 637 638 /* MMIO has been re-enabled, but not DMA */ 639 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 640 641 /* PCI Express link has been reset */ 642 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 643 644 /* PCI slot has been reset */ 645 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 646 647 /* PCI function reset prepare or completed */ 648 void (*reset_notify)(struct pci_dev *dev, bool prepare); 649 650 /* Device driver may resume normal operations */ 651 void (*resume)(struct pci_dev *dev); 652 }; 653 654 655 struct module; 656 struct pci_driver { 657 struct list_head node; 658 const char *name; 659 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 660 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 661 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 662 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 663 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 664 int (*resume_early) (struct pci_dev *dev); 665 int (*resume) (struct pci_dev *dev); /* Device woken up */ 666 void (*shutdown) (struct pci_dev *dev); 667 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 668 const struct pci_error_handlers *err_handler; 669 struct device_driver driver; 670 struct pci_dynids dynids; 671 }; 672 673 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 674 675 /** 676 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 677 * @_table: device table name 678 * 679 * This macro is deprecated and should not be used in new code. 680 */ 681 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 682 const struct pci_device_id _table[] 683 684 /** 685 * PCI_DEVICE - macro used to describe a specific pci device 686 * @vend: the 16 bit PCI Vendor ID 687 * @dev: the 16 bit PCI Device ID 688 * 689 * This macro is used to create a struct pci_device_id that matches a 690 * specific device. The subvendor and subdevice fields will be set to 691 * PCI_ANY_ID. 692 */ 693 #define PCI_DEVICE(vend,dev) \ 694 .vendor = (vend), .device = (dev), \ 695 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 696 697 /** 698 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 699 * @vend: the 16 bit PCI Vendor ID 700 * @dev: the 16 bit PCI Device ID 701 * @subvend: the 16 bit PCI Subvendor ID 702 * @subdev: the 16 bit PCI Subdevice ID 703 * 704 * This macro is used to create a struct pci_device_id that matches a 705 * specific device with subsystem information. 706 */ 707 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 708 .vendor = (vend), .device = (dev), \ 709 .subvendor = (subvend), .subdevice = (subdev) 710 711 /** 712 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 713 * @dev_class: the class, subclass, prog-if triple for this device 714 * @dev_class_mask: the class mask for this device 715 * 716 * This macro is used to create a struct pci_device_id that matches a 717 * specific PCI class. The vendor, device, subvendor, and subdevice 718 * fields will be set to PCI_ANY_ID. 719 */ 720 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 721 .class = (dev_class), .class_mask = (dev_class_mask), \ 722 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 723 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 724 725 /** 726 * PCI_VDEVICE - macro used to describe a specific pci device in short form 727 * @vend: the vendor name 728 * @dev: the 16 bit PCI Device ID 729 * 730 * This macro is used to create a struct pci_device_id that matches a 731 * specific PCI device. The subvendor, and subdevice fields will be set 732 * to PCI_ANY_ID. The macro allows the next field to follow as the device 733 * private data. 734 */ 735 736 #define PCI_VDEVICE(vend, dev) \ 737 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 738 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 739 740 /* these external functions are only available when PCI support is enabled */ 741 #ifdef CONFIG_PCI 742 743 void pcie_bus_configure_settings(struct pci_bus *bus); 744 745 enum pcie_bus_config_types { 746 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 747 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 748 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 749 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 750 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 751 }; 752 753 extern enum pcie_bus_config_types pcie_bus_config; 754 755 extern struct bus_type pci_bus_type; 756 757 /* Do NOT directly access these two variables, unless you are arch-specific PCI 758 * code, or PCI core code. */ 759 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 760 /* Some device drivers need know if PCI is initiated */ 761 int no_pci_devices(void); 762 763 void pcibios_resource_survey_bus(struct pci_bus *bus); 764 void pcibios_add_bus(struct pci_bus *bus); 765 void pcibios_remove_bus(struct pci_bus *bus); 766 void pcibios_fixup_bus(struct pci_bus *); 767 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 768 /* Architecture-specific versions may override this (weak) */ 769 char *pcibios_setup(char *str); 770 771 /* Used only when drivers/pci/setup.c is used */ 772 resource_size_t pcibios_align_resource(void *, const struct resource *, 773 resource_size_t, 774 resource_size_t); 775 void pcibios_update_irq(struct pci_dev *, int irq); 776 777 /* Weak but can be overriden by arch */ 778 void pci_fixup_cardbus(struct pci_bus *); 779 780 /* Generic PCI functions used internally */ 781 782 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 783 struct resource *res); 784 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 785 struct pci_bus_region *region); 786 void pcibios_scan_specific_bus(int busn); 787 struct pci_bus *pci_find_bus(int domain, int busnr); 788 void pci_bus_add_devices(const struct pci_bus *bus); 789 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 790 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 791 struct pci_ops *ops, void *sysdata, 792 struct list_head *resources); 793 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 794 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 795 void pci_bus_release_busn_res(struct pci_bus *b); 796 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, 797 struct pci_ops *ops, void *sysdata, 798 struct list_head *resources, 799 struct msi_controller *msi); 800 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 801 struct pci_ops *ops, void *sysdata, 802 struct list_head *resources); 803 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 804 int busnr); 805 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 806 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 807 const char *name, 808 struct hotplug_slot *hotplug); 809 void pci_destroy_slot(struct pci_slot *slot); 810 #ifdef CONFIG_SYSFS 811 void pci_dev_assign_slot(struct pci_dev *dev); 812 #else 813 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 814 #endif 815 int pci_scan_slot(struct pci_bus *bus, int devfn); 816 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 817 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 818 unsigned int pci_scan_child_bus(struct pci_bus *bus); 819 void pci_bus_add_device(struct pci_dev *dev); 820 void pci_read_bridge_bases(struct pci_bus *child); 821 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 822 struct resource *res); 823 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 824 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 825 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 826 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 827 struct pci_dev *pci_dev_get(struct pci_dev *dev); 828 void pci_dev_put(struct pci_dev *dev); 829 void pci_remove_bus(struct pci_bus *b); 830 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 831 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 832 void pci_stop_root_bus(struct pci_bus *bus); 833 void pci_remove_root_bus(struct pci_bus *bus); 834 void pci_setup_cardbus(struct pci_bus *bus); 835 void pci_sort_breadthfirst(void); 836 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 837 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 838 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 839 840 /* Generic PCI functions exported to card drivers */ 841 842 enum pci_lost_interrupt_reason { 843 PCI_LOST_IRQ_NO_INFORMATION = 0, 844 PCI_LOST_IRQ_DISABLE_MSI, 845 PCI_LOST_IRQ_DISABLE_MSIX, 846 PCI_LOST_IRQ_DISABLE_ACPI, 847 }; 848 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 849 int pci_find_capability(struct pci_dev *dev, int cap); 850 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 851 int pci_find_ext_capability(struct pci_dev *dev, int cap); 852 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 853 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 854 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 855 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 856 857 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 858 struct pci_dev *from); 859 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 860 unsigned int ss_vendor, unsigned int ss_device, 861 struct pci_dev *from); 862 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 863 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 864 unsigned int devfn); 865 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 866 unsigned int devfn) 867 { 868 return pci_get_domain_bus_and_slot(0, bus, devfn); 869 } 870 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 871 int pci_dev_present(const struct pci_device_id *ids); 872 873 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 874 int where, u8 *val); 875 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 876 int where, u16 *val); 877 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 878 int where, u32 *val); 879 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 880 int where, u8 val); 881 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 882 int where, u16 val); 883 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 884 int where, u32 val); 885 886 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 887 int where, int size, u32 *val); 888 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 889 int where, int size, u32 val); 890 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 891 int where, int size, u32 *val); 892 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 893 int where, int size, u32 val); 894 895 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 896 897 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 898 { 899 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 900 } 901 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 902 { 903 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 904 } 905 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 906 u32 *val) 907 { 908 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 909 } 910 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 911 { 912 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 913 } 914 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 915 { 916 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 917 } 918 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 919 u32 val) 920 { 921 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 922 } 923 924 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 925 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 926 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 927 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 928 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 929 u16 clear, u16 set); 930 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 931 u32 clear, u32 set); 932 933 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 934 u16 set) 935 { 936 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 937 } 938 939 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 940 u32 set) 941 { 942 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 943 } 944 945 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 946 u16 clear) 947 { 948 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 949 } 950 951 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 952 u32 clear) 953 { 954 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 955 } 956 957 /* user-space driven config access */ 958 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 959 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 960 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 961 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 962 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 963 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 964 965 int __must_check pci_enable_device(struct pci_dev *dev); 966 int __must_check pci_enable_device_io(struct pci_dev *dev); 967 int __must_check pci_enable_device_mem(struct pci_dev *dev); 968 int __must_check pci_reenable_device(struct pci_dev *); 969 int __must_check pcim_enable_device(struct pci_dev *pdev); 970 void pcim_pin_device(struct pci_dev *pdev); 971 972 static inline int pci_is_enabled(struct pci_dev *pdev) 973 { 974 return (atomic_read(&pdev->enable_cnt) > 0); 975 } 976 977 static inline int pci_is_managed(struct pci_dev *pdev) 978 { 979 return pdev->is_managed; 980 } 981 982 static inline void pci_set_managed_irq(struct pci_dev *pdev, unsigned int irq) 983 { 984 pdev->irq = irq; 985 pdev->irq_managed = 1; 986 } 987 988 static inline void pci_reset_managed_irq(struct pci_dev *pdev) 989 { 990 pdev->irq = 0; 991 pdev->irq_managed = 0; 992 } 993 994 static inline bool pci_has_managed_irq(struct pci_dev *pdev) 995 { 996 return pdev->irq_managed && pdev->irq > 0; 997 } 998 999 void pci_disable_device(struct pci_dev *dev); 1000 1001 extern unsigned int pcibios_max_latency; 1002 void pci_set_master(struct pci_dev *dev); 1003 void pci_clear_master(struct pci_dev *dev); 1004 1005 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1006 int pci_set_cacheline_size(struct pci_dev *dev); 1007 #define HAVE_PCI_SET_MWI 1008 int __must_check pci_set_mwi(struct pci_dev *dev); 1009 int pci_try_set_mwi(struct pci_dev *dev); 1010 void pci_clear_mwi(struct pci_dev *dev); 1011 void pci_intx(struct pci_dev *dev, int enable); 1012 bool pci_intx_mask_supported(struct pci_dev *dev); 1013 bool pci_check_and_mask_intx(struct pci_dev *dev); 1014 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1015 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 1016 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 1017 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1018 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1019 int pcix_get_max_mmrbc(struct pci_dev *dev); 1020 int pcix_get_mmrbc(struct pci_dev *dev); 1021 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1022 int pcie_get_readrq(struct pci_dev *dev); 1023 int pcie_set_readrq(struct pci_dev *dev, int rq); 1024 int pcie_get_mps(struct pci_dev *dev); 1025 int pcie_set_mps(struct pci_dev *dev, int mps); 1026 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1027 enum pcie_link_width *width); 1028 int __pci_reset_function(struct pci_dev *dev); 1029 int __pci_reset_function_locked(struct pci_dev *dev); 1030 int pci_reset_function(struct pci_dev *dev); 1031 int pci_try_reset_function(struct pci_dev *dev); 1032 int pci_probe_reset_slot(struct pci_slot *slot); 1033 int pci_reset_slot(struct pci_slot *slot); 1034 int pci_try_reset_slot(struct pci_slot *slot); 1035 int pci_probe_reset_bus(struct pci_bus *bus); 1036 int pci_reset_bus(struct pci_bus *bus); 1037 int pci_try_reset_bus(struct pci_bus *bus); 1038 void pci_reset_secondary_bus(struct pci_dev *dev); 1039 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1040 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1041 void pci_update_resource(struct pci_dev *dev, int resno); 1042 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1043 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1044 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1045 bool pci_device_is_present(struct pci_dev *pdev); 1046 void pci_ignore_hotplug(struct pci_dev *dev); 1047 1048 /* ROM control related routines */ 1049 int pci_enable_rom(struct pci_dev *pdev); 1050 void pci_disable_rom(struct pci_dev *pdev); 1051 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1052 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1053 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1054 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1055 1056 /* Power management related routines */ 1057 int pci_save_state(struct pci_dev *dev); 1058 void pci_restore_state(struct pci_dev *dev); 1059 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1060 int pci_load_saved_state(struct pci_dev *dev, 1061 struct pci_saved_state *state); 1062 int pci_load_and_free_saved_state(struct pci_dev *dev, 1063 struct pci_saved_state **state); 1064 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1065 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1066 u16 cap); 1067 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1068 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1069 u16 cap, unsigned int size); 1070 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1071 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1072 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1073 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1074 void pci_pme_active(struct pci_dev *dev, bool enable); 1075 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1076 bool runtime, bool enable); 1077 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1078 int pci_prepare_to_sleep(struct pci_dev *dev); 1079 int pci_back_from_sleep(struct pci_dev *dev); 1080 bool pci_dev_run_wake(struct pci_dev *dev); 1081 bool pci_check_pme_status(struct pci_dev *dev); 1082 void pci_pme_wakeup_bus(struct pci_bus *bus); 1083 1084 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1085 bool enable) 1086 { 1087 return __pci_enable_wake(dev, state, false, enable); 1088 } 1089 1090 /* PCI Virtual Channel */ 1091 int pci_save_vc_state(struct pci_dev *dev); 1092 void pci_restore_vc_state(struct pci_dev *dev); 1093 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1094 1095 /* For use by arch with custom probe code */ 1096 void set_pcie_port_type(struct pci_dev *pdev); 1097 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1098 1099 /* Functions for PCI Hotplug drivers to use */ 1100 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1101 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1102 unsigned int pci_rescan_bus(struct pci_bus *bus); 1103 void pci_lock_rescan_remove(void); 1104 void pci_unlock_rescan_remove(void); 1105 1106 /* Vital product data routines */ 1107 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1108 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1109 1110 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1111 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1112 void pci_bus_assign_resources(const struct pci_bus *bus); 1113 void pci_bus_size_bridges(struct pci_bus *bus); 1114 int pci_claim_resource(struct pci_dev *, int); 1115 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1116 void pci_assign_unassigned_resources(void); 1117 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1118 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1119 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1120 void pdev_enable_device(struct pci_dev *); 1121 int pci_enable_resources(struct pci_dev *, int mask); 1122 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1123 int (*)(const struct pci_dev *, u8, u8)); 1124 #define HAVE_PCI_REQ_REGIONS 2 1125 int __must_check pci_request_regions(struct pci_dev *, const char *); 1126 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1127 void pci_release_regions(struct pci_dev *); 1128 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1129 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1130 void pci_release_region(struct pci_dev *, int); 1131 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1132 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1133 void pci_release_selected_regions(struct pci_dev *, int); 1134 1135 /* drivers/pci/bus.c */ 1136 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1137 void pci_bus_put(struct pci_bus *bus); 1138 void pci_add_resource(struct list_head *resources, struct resource *res); 1139 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1140 resource_size_t offset); 1141 void pci_free_resource_list(struct list_head *resources); 1142 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1143 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1144 void pci_bus_remove_resources(struct pci_bus *bus); 1145 1146 #define pci_bus_for_each_resource(bus, res, i) \ 1147 for (i = 0; \ 1148 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1149 i++) 1150 1151 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1152 struct resource *res, resource_size_t size, 1153 resource_size_t align, resource_size_t min, 1154 unsigned long type_mask, 1155 resource_size_t (*alignf)(void *, 1156 const struct resource *, 1157 resource_size_t, 1158 resource_size_t), 1159 void *alignf_data); 1160 1161 1162 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1163 1164 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1165 { 1166 struct pci_bus_region region; 1167 1168 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1169 return region.start; 1170 } 1171 1172 /* Proper probing supporting hot-pluggable devices */ 1173 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1174 const char *mod_name); 1175 1176 /* 1177 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1178 */ 1179 #define pci_register_driver(driver) \ 1180 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1181 1182 void pci_unregister_driver(struct pci_driver *dev); 1183 1184 /** 1185 * module_pci_driver() - Helper macro for registering a PCI driver 1186 * @__pci_driver: pci_driver struct 1187 * 1188 * Helper macro for PCI drivers which do not do anything special in module 1189 * init/exit. This eliminates a lot of boilerplate. Each module may only 1190 * use this macro once, and calling it replaces module_init() and module_exit() 1191 */ 1192 #define module_pci_driver(__pci_driver) \ 1193 module_driver(__pci_driver, pci_register_driver, \ 1194 pci_unregister_driver) 1195 1196 /** 1197 * builtin_pci_driver() - Helper macro for registering a PCI driver 1198 * @__pci_driver: pci_driver struct 1199 * 1200 * Helper macro for PCI drivers which do not do anything special in their 1201 * init code. This eliminates a lot of boilerplate. Each driver may only 1202 * use this macro once, and calling it replaces device_initcall(...) 1203 */ 1204 #define builtin_pci_driver(__pci_driver) \ 1205 builtin_driver(__pci_driver, pci_register_driver) 1206 1207 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1208 int pci_add_dynid(struct pci_driver *drv, 1209 unsigned int vendor, unsigned int device, 1210 unsigned int subvendor, unsigned int subdevice, 1211 unsigned int class, unsigned int class_mask, 1212 unsigned long driver_data); 1213 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1214 struct pci_dev *dev); 1215 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1216 int pass); 1217 1218 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1219 void *userdata); 1220 int pci_cfg_space_size(struct pci_dev *dev); 1221 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1222 void pci_setup_bridge(struct pci_bus *bus); 1223 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1224 unsigned long type); 1225 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1226 1227 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1228 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1229 1230 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1231 unsigned int command_bits, u32 flags); 1232 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1233 1234 #include <linux/pci-dma.h> 1235 #include <linux/dmapool.h> 1236 1237 #define pci_pool dma_pool 1238 #define pci_pool_create(name, pdev, size, align, allocation) \ 1239 dma_pool_create(name, &pdev->dev, size, align, allocation) 1240 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1241 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1242 #define pci_pool_zalloc(pool, flags, handle) \ 1243 dma_pool_zalloc(pool, flags, handle) 1244 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1245 1246 struct msix_entry { 1247 u32 vector; /* kernel uses to write allocated vector */ 1248 u16 entry; /* driver uses to specify entry, OS writes */ 1249 }; 1250 1251 void pci_msi_setup_pci_dev(struct pci_dev *dev); 1252 1253 #ifdef CONFIG_PCI_MSI 1254 int pci_msi_vec_count(struct pci_dev *dev); 1255 void pci_msi_shutdown(struct pci_dev *dev); 1256 void pci_disable_msi(struct pci_dev *dev); 1257 int pci_msix_vec_count(struct pci_dev *dev); 1258 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1259 void pci_msix_shutdown(struct pci_dev *dev); 1260 void pci_disable_msix(struct pci_dev *dev); 1261 void pci_restore_msi_state(struct pci_dev *dev); 1262 int pci_msi_enabled(void); 1263 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1264 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1265 { 1266 int rc = pci_enable_msi_range(dev, nvec, nvec); 1267 if (rc < 0) 1268 return rc; 1269 return 0; 1270 } 1271 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1272 int minvec, int maxvec); 1273 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1274 struct msix_entry *entries, int nvec) 1275 { 1276 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1277 if (rc < 0) 1278 return rc; 1279 return 0; 1280 } 1281 #else 1282 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1283 static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1284 static inline void pci_disable_msi(struct pci_dev *dev) { } 1285 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1286 static inline int pci_enable_msix(struct pci_dev *dev, 1287 struct msix_entry *entries, int nvec) 1288 { return -ENOSYS; } 1289 static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1290 static inline void pci_disable_msix(struct pci_dev *dev) { } 1291 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1292 static inline int pci_msi_enabled(void) { return 0; } 1293 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1294 int maxvec) 1295 { return -ENOSYS; } 1296 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1297 { return -ENOSYS; } 1298 static inline int pci_enable_msix_range(struct pci_dev *dev, 1299 struct msix_entry *entries, int minvec, int maxvec) 1300 { return -ENOSYS; } 1301 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1302 struct msix_entry *entries, int nvec) 1303 { return -ENOSYS; } 1304 #endif 1305 1306 #ifdef CONFIG_PCIEPORTBUS 1307 extern bool pcie_ports_disabled; 1308 extern bool pcie_ports_auto; 1309 #else 1310 #define pcie_ports_disabled true 1311 #define pcie_ports_auto false 1312 #endif 1313 1314 #ifdef CONFIG_PCIEASPM 1315 bool pcie_aspm_support_enabled(void); 1316 #else 1317 static inline bool pcie_aspm_support_enabled(void) { return false; } 1318 #endif 1319 1320 #ifdef CONFIG_PCIEAER 1321 void pci_no_aer(void); 1322 bool pci_aer_available(void); 1323 #else 1324 static inline void pci_no_aer(void) { } 1325 static inline bool pci_aer_available(void) { return false; } 1326 #endif 1327 1328 #ifdef CONFIG_PCIE_ECRC 1329 void pcie_set_ecrc_checking(struct pci_dev *dev); 1330 void pcie_ecrc_get_policy(char *str); 1331 #else 1332 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1333 static inline void pcie_ecrc_get_policy(char *str) { } 1334 #endif 1335 1336 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) 1337 1338 #ifdef CONFIG_HT_IRQ 1339 /* The functions a driver should call */ 1340 int ht_create_irq(struct pci_dev *dev, int idx); 1341 void ht_destroy_irq(unsigned int irq); 1342 #endif /* CONFIG_HT_IRQ */ 1343 1344 #ifdef CONFIG_PCI_ATS 1345 /* Address Translation Service */ 1346 void pci_ats_init(struct pci_dev *dev); 1347 int pci_enable_ats(struct pci_dev *dev, int ps); 1348 void pci_disable_ats(struct pci_dev *dev); 1349 int pci_ats_queue_depth(struct pci_dev *dev); 1350 #else 1351 static inline void pci_ats_init(struct pci_dev *d) { } 1352 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1353 static inline void pci_disable_ats(struct pci_dev *d) { } 1354 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1355 #endif 1356 1357 void pci_cfg_access_lock(struct pci_dev *dev); 1358 bool pci_cfg_access_trylock(struct pci_dev *dev); 1359 void pci_cfg_access_unlock(struct pci_dev *dev); 1360 1361 /* 1362 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1363 * a PCI domain is defined to be a set of PCI buses which share 1364 * configuration space. 1365 */ 1366 #ifdef CONFIG_PCI_DOMAINS 1367 extern int pci_domains_supported; 1368 int pci_get_new_domain_nr(void); 1369 #else 1370 enum { pci_domains_supported = 0 }; 1371 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1372 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1373 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1374 #endif /* CONFIG_PCI_DOMAINS */ 1375 1376 /* 1377 * Generic implementation for PCI domain support. If your 1378 * architecture does not need custom management of PCI 1379 * domains then this implementation will be used 1380 */ 1381 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1382 static inline int pci_domain_nr(struct pci_bus *bus) 1383 { 1384 return bus->domain_nr; 1385 } 1386 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); 1387 #else 1388 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, 1389 struct device *parent) 1390 { 1391 } 1392 #endif 1393 1394 /* some architectures require additional setup to direct VGA traffic */ 1395 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1396 unsigned int command_bits, u32 flags); 1397 void pci_register_set_vga_state(arch_set_vga_state_t func); 1398 1399 #else /* CONFIG_PCI is not enabled */ 1400 1401 /* 1402 * If the system does not have PCI, clearly these return errors. Define 1403 * these as simple inline functions to avoid hair in drivers. 1404 */ 1405 1406 #define _PCI_NOP(o, s, t) \ 1407 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1408 int where, t val) \ 1409 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1410 1411 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1412 _PCI_NOP(o, word, u16 x) \ 1413 _PCI_NOP(o, dword, u32 x) 1414 _PCI_NOP_ALL(read, *) 1415 _PCI_NOP_ALL(write,) 1416 1417 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1418 unsigned int device, 1419 struct pci_dev *from) 1420 { return NULL; } 1421 1422 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1423 unsigned int device, 1424 unsigned int ss_vendor, 1425 unsigned int ss_device, 1426 struct pci_dev *from) 1427 { return NULL; } 1428 1429 static inline struct pci_dev *pci_get_class(unsigned int class, 1430 struct pci_dev *from) 1431 { return NULL; } 1432 1433 #define pci_dev_present(ids) (0) 1434 #define no_pci_devices() (1) 1435 #define pci_dev_put(dev) do { } while (0) 1436 1437 static inline void pci_set_master(struct pci_dev *dev) { } 1438 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1439 static inline void pci_disable_device(struct pci_dev *dev) { } 1440 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1441 { return -EIO; } 1442 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1443 { return -EIO; } 1444 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1445 unsigned int size) 1446 { return -EIO; } 1447 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1448 unsigned long mask) 1449 { return -EIO; } 1450 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1451 { return -EBUSY; } 1452 static inline int __pci_register_driver(struct pci_driver *drv, 1453 struct module *owner) 1454 { return 0; } 1455 static inline int pci_register_driver(struct pci_driver *drv) 1456 { return 0; } 1457 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1458 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1459 { return 0; } 1460 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1461 int cap) 1462 { return 0; } 1463 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1464 { return 0; } 1465 1466 /* Power management related routines */ 1467 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1468 static inline void pci_restore_state(struct pci_dev *dev) { } 1469 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1470 { return 0; } 1471 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1472 { return 0; } 1473 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1474 pm_message_t state) 1475 { return PCI_D0; } 1476 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1477 int enable) 1478 { return 0; } 1479 1480 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1481 { return -EIO; } 1482 static inline void pci_release_regions(struct pci_dev *dev) { } 1483 1484 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1485 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1486 { return 0; } 1487 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1488 1489 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1490 { return NULL; } 1491 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1492 unsigned int devfn) 1493 { return NULL; } 1494 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1495 unsigned int devfn) 1496 { return NULL; } 1497 1498 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1499 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1500 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1501 1502 #define dev_is_pci(d) (false) 1503 #define dev_is_pf(d) (false) 1504 #define dev_num_vf(d) (0) 1505 #endif /* CONFIG_PCI */ 1506 1507 /* Include architecture-dependent settings and functions */ 1508 1509 #include <asm/pci.h> 1510 1511 /* these helpers provide future and backwards compatibility 1512 * for accessing popular PCI BAR info */ 1513 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1514 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1515 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1516 #define pci_resource_len(dev,bar) \ 1517 ((pci_resource_start((dev), (bar)) == 0 && \ 1518 pci_resource_end((dev), (bar)) == \ 1519 pci_resource_start((dev), (bar))) ? 0 : \ 1520 \ 1521 (pci_resource_end((dev), (bar)) - \ 1522 pci_resource_start((dev), (bar)) + 1)) 1523 1524 /* Similar to the helpers above, these manipulate per-pci_dev 1525 * driver-specific data. They are really just a wrapper around 1526 * the generic device structure functions of these calls. 1527 */ 1528 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1529 { 1530 return dev_get_drvdata(&pdev->dev); 1531 } 1532 1533 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1534 { 1535 dev_set_drvdata(&pdev->dev, data); 1536 } 1537 1538 /* If you want to know what to call your pci_dev, ask this function. 1539 * Again, it's a wrapper around the generic device. 1540 */ 1541 static inline const char *pci_name(const struct pci_dev *pdev) 1542 { 1543 return dev_name(&pdev->dev); 1544 } 1545 1546 1547 /* Some archs don't want to expose struct resource to userland as-is 1548 * in sysfs and /proc 1549 */ 1550 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1551 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1552 const struct resource *rsrc, resource_size_t *start, 1553 resource_size_t *end) 1554 { 1555 *start = rsrc->start; 1556 *end = rsrc->end; 1557 } 1558 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1559 1560 1561 /* 1562 * The world is not perfect and supplies us with broken PCI devices. 1563 * For at least a part of these bugs we need a work-around, so both 1564 * generic (drivers/pci/quirks.c) and per-architecture code can define 1565 * fixup hooks to be called for particular buggy devices. 1566 */ 1567 1568 struct pci_fixup { 1569 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1570 u16 device; /* You can use PCI_ANY_ID here of course */ 1571 u32 class; /* You can use PCI_ANY_ID here too */ 1572 unsigned int class_shift; /* should be 0, 8, 16 */ 1573 void (*hook)(struct pci_dev *dev); 1574 }; 1575 1576 enum pci_fixup_pass { 1577 pci_fixup_early, /* Before probing BARs */ 1578 pci_fixup_header, /* After reading configuration header */ 1579 pci_fixup_final, /* Final phase of device fixups */ 1580 pci_fixup_enable, /* pci_enable_device() time */ 1581 pci_fixup_resume, /* pci_device_resume() */ 1582 pci_fixup_suspend, /* pci_device_suspend() */ 1583 pci_fixup_resume_early, /* pci_device_resume_early() */ 1584 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1585 }; 1586 1587 /* Anonymous variables would be nice... */ 1588 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1589 class_shift, hook) \ 1590 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1591 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1592 = { vendor, device, class, class_shift, hook }; 1593 1594 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1595 class_shift, hook) \ 1596 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1597 hook, vendor, device, class, class_shift, hook) 1598 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1599 class_shift, hook) \ 1600 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1601 hook, vendor, device, class, class_shift, hook) 1602 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1603 class_shift, hook) \ 1604 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1605 hook, vendor, device, class, class_shift, hook) 1606 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1607 class_shift, hook) \ 1608 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1609 hook, vendor, device, class, class_shift, hook) 1610 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1611 class_shift, hook) \ 1612 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1613 resume##hook, vendor, device, class, \ 1614 class_shift, hook) 1615 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1616 class_shift, hook) \ 1617 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1618 resume_early##hook, vendor, device, \ 1619 class, class_shift, hook) 1620 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1621 class_shift, hook) \ 1622 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1623 suspend##hook, vendor, device, class, \ 1624 class_shift, hook) 1625 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1626 class_shift, hook) \ 1627 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1628 suspend_late##hook, vendor, device, \ 1629 class, class_shift, hook) 1630 1631 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1632 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1633 hook, vendor, device, PCI_ANY_ID, 0, hook) 1634 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1635 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1636 hook, vendor, device, PCI_ANY_ID, 0, hook) 1637 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1638 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1639 hook, vendor, device, PCI_ANY_ID, 0, hook) 1640 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1641 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1642 hook, vendor, device, PCI_ANY_ID, 0, hook) 1643 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1644 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1645 resume##hook, vendor, device, \ 1646 PCI_ANY_ID, 0, hook) 1647 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1648 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1649 resume_early##hook, vendor, device, \ 1650 PCI_ANY_ID, 0, hook) 1651 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1652 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1653 suspend##hook, vendor, device, \ 1654 PCI_ANY_ID, 0, hook) 1655 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1656 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1657 suspend_late##hook, vendor, device, \ 1658 PCI_ANY_ID, 0, hook) 1659 1660 #ifdef CONFIG_PCI_QUIRKS 1661 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1662 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1663 void pci_dev_specific_enable_acs(struct pci_dev *dev); 1664 #else 1665 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1666 struct pci_dev *dev) { } 1667 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1668 u16 acs_flags) 1669 { 1670 return -ENOTTY; 1671 } 1672 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } 1673 #endif 1674 1675 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1676 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1677 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1678 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1679 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1680 const char *name); 1681 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1682 1683 extern int pci_pci_problems; 1684 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1685 #define PCIPCI_TRITON 2 1686 #define PCIPCI_NATOMA 4 1687 #define PCIPCI_VIAETBF 8 1688 #define PCIPCI_VSFX 16 1689 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1690 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1691 1692 extern unsigned long pci_cardbus_io_size; 1693 extern unsigned long pci_cardbus_mem_size; 1694 extern u8 pci_dfl_cache_line_size; 1695 extern u8 pci_cache_line_size; 1696 1697 extern unsigned long pci_hotplug_io_size; 1698 extern unsigned long pci_hotplug_mem_size; 1699 1700 /* Architecture-specific versions may override these (weak) */ 1701 void pcibios_disable_device(struct pci_dev *dev); 1702 void pcibios_set_master(struct pci_dev *dev); 1703 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1704 enum pcie_reset_state state); 1705 int pcibios_add_device(struct pci_dev *dev); 1706 void pcibios_release_device(struct pci_dev *dev); 1707 void pcibios_penalize_isa_irq(int irq, int active); 1708 int pcibios_alloc_irq(struct pci_dev *dev); 1709 void pcibios_free_irq(struct pci_dev *dev); 1710 1711 #ifdef CONFIG_HIBERNATE_CALLBACKS 1712 extern struct dev_pm_ops pcibios_pm_ops; 1713 #endif 1714 1715 #ifdef CONFIG_PCI_MMCONFIG 1716 void __init pci_mmcfg_early_init(void); 1717 void __init pci_mmcfg_late_init(void); 1718 #else 1719 static inline void pci_mmcfg_early_init(void) { } 1720 static inline void pci_mmcfg_late_init(void) { } 1721 #endif 1722 1723 int pci_ext_cfg_avail(void); 1724 1725 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1726 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1727 1728 #ifdef CONFIG_PCI_IOV 1729 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1730 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1731 1732 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1733 void pci_disable_sriov(struct pci_dev *dev); 1734 int pci_num_vf(struct pci_dev *dev); 1735 int pci_vfs_assigned(struct pci_dev *dev); 1736 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1737 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1738 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1739 #else 1740 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1741 { 1742 return -ENOSYS; 1743 } 1744 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1745 { 1746 return -ENOSYS; 1747 } 1748 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1749 { return -ENODEV; } 1750 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1751 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1752 static inline int pci_vfs_assigned(struct pci_dev *dev) 1753 { return 0; } 1754 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1755 { return 0; } 1756 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1757 { return 0; } 1758 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1759 { return 0; } 1760 #endif 1761 1762 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1763 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1764 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1765 #endif 1766 1767 /** 1768 * pci_pcie_cap - get the saved PCIe capability offset 1769 * @dev: PCI device 1770 * 1771 * PCIe capability offset is calculated at PCI device initialization 1772 * time and saved in the data structure. This function returns saved 1773 * PCIe capability offset. Using this instead of pci_find_capability() 1774 * reduces unnecessary search in the PCI configuration space. If you 1775 * need to calculate PCIe capability offset from raw device for some 1776 * reasons, please use pci_find_capability() instead. 1777 */ 1778 static inline int pci_pcie_cap(struct pci_dev *dev) 1779 { 1780 return dev->pcie_cap; 1781 } 1782 1783 /** 1784 * pci_is_pcie - check if the PCI device is PCI Express capable 1785 * @dev: PCI device 1786 * 1787 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1788 */ 1789 static inline bool pci_is_pcie(struct pci_dev *dev) 1790 { 1791 return pci_pcie_cap(dev); 1792 } 1793 1794 /** 1795 * pcie_caps_reg - get the PCIe Capabilities Register 1796 * @dev: PCI device 1797 */ 1798 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1799 { 1800 return dev->pcie_flags_reg; 1801 } 1802 1803 /** 1804 * pci_pcie_type - get the PCIe device/port type 1805 * @dev: PCI device 1806 */ 1807 static inline int pci_pcie_type(const struct pci_dev *dev) 1808 { 1809 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1810 } 1811 1812 void pci_request_acs(void); 1813 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1814 bool pci_acs_path_enabled(struct pci_dev *start, 1815 struct pci_dev *end, u16 acs_flags); 1816 1817 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1818 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1819 1820 /* Large Resource Data Type Tag Item Names */ 1821 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1822 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1823 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1824 1825 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1826 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1827 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1828 1829 /* Small Resource Data Type Tag Item Names */ 1830 #define PCI_VPD_STIN_END 0x78 /* End */ 1831 1832 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1833 1834 #define PCI_VPD_SRDT_TIN_MASK 0x78 1835 #define PCI_VPD_SRDT_LEN_MASK 0x07 1836 1837 #define PCI_VPD_LRDT_TAG_SIZE 3 1838 #define PCI_VPD_SRDT_TAG_SIZE 1 1839 1840 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1841 1842 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1843 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1844 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1845 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1846 1847 /** 1848 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1849 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1850 * 1851 * Returns the extracted Large Resource Data Type length. 1852 */ 1853 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1854 { 1855 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1856 } 1857 1858 /** 1859 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1860 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1861 * 1862 * Returns the extracted Small Resource Data Type length. 1863 */ 1864 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1865 { 1866 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1867 } 1868 1869 /** 1870 * pci_vpd_info_field_size - Extracts the information field length 1871 * @lrdt: Pointer to the beginning of an information field header 1872 * 1873 * Returns the extracted information field length. 1874 */ 1875 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1876 { 1877 return info_field[2]; 1878 } 1879 1880 /** 1881 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1882 * @buf: Pointer to buffered vpd data 1883 * @off: The offset into the buffer at which to begin the search 1884 * @len: The length of the vpd buffer 1885 * @rdt: The Resource Data Type to search for 1886 * 1887 * Returns the index where the Resource Data Type was found or 1888 * -ENOENT otherwise. 1889 */ 1890 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1891 1892 /** 1893 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1894 * @buf: Pointer to buffered vpd data 1895 * @off: The offset into the buffer at which to begin the search 1896 * @len: The length of the buffer area, relative to off, in which to search 1897 * @kw: The keyword to search for 1898 * 1899 * Returns the index where the information field keyword was found or 1900 * -ENOENT otherwise. 1901 */ 1902 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1903 unsigned int len, const char *kw); 1904 1905 /* PCI <-> OF binding helpers */ 1906 #ifdef CONFIG_OF 1907 struct device_node; 1908 struct irq_domain; 1909 void pci_set_of_node(struct pci_dev *dev); 1910 void pci_release_of_node(struct pci_dev *dev); 1911 void pci_set_bus_of_node(struct pci_bus *bus); 1912 void pci_release_bus_of_node(struct pci_bus *bus); 1913 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 1914 1915 /* Arch may override this (weak) */ 1916 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1917 1918 static inline struct device_node * 1919 pci_device_to_OF_node(const struct pci_dev *pdev) 1920 { 1921 return pdev ? pdev->dev.of_node : NULL; 1922 } 1923 1924 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1925 { 1926 return bus ? bus->dev.of_node : NULL; 1927 } 1928 1929 #else /* CONFIG_OF */ 1930 static inline void pci_set_of_node(struct pci_dev *dev) { } 1931 static inline void pci_release_of_node(struct pci_dev *dev) { } 1932 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1933 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1934 static inline struct device_node * 1935 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 1936 static inline struct irq_domain * 1937 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 1938 #endif /* CONFIG_OF */ 1939 1940 #ifdef CONFIG_EEH 1941 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1942 { 1943 return pdev->dev.archdata.edev; 1944 } 1945 #endif 1946 1947 int pci_for_each_dma_alias(struct pci_dev *pdev, 1948 int (*fn)(struct pci_dev *pdev, 1949 u16 alias, void *data), void *data); 1950 1951 /* helper functions for operation of device flag */ 1952 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 1953 { 1954 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 1955 } 1956 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 1957 { 1958 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 1959 } 1960 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 1961 { 1962 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 1963 } 1964 1965 /** 1966 * pci_ari_enabled - query ARI forwarding status 1967 * @bus: the PCI bus 1968 * 1969 * Returns true if ARI forwarding is enabled. 1970 */ 1971 static inline bool pci_ari_enabled(struct pci_bus *bus) 1972 { 1973 return bus->self && bus->self->ari_enabled; 1974 } 1975 #endif /* LINUX_PCI_H */ 1976