1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <uapi/linux/pci.h> 33 34 #include <linux/pci_ids.h> 35 36 /* 37 * The PCI interface treats multi-function devices as independent 38 * devices. The slot/function address of each device is encoded 39 * in a single byte as follows: 40 * 41 * 7:3 = slot 42 * 2:0 = function 43 * 44 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 45 * In the interest of not exposing interfaces to user-space unnecessarily, 46 * the following kernel-only defines are being added here. 47 */ 48 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 49 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 50 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 51 52 /* pci_slot represents a physical slot */ 53 struct pci_slot { 54 struct pci_bus *bus; /* The bus this slot is on */ 55 struct list_head list; /* node in list of slots on this bus */ 56 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 57 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 58 struct kobject kobj; 59 }; 60 61 static inline const char *pci_slot_name(const struct pci_slot *slot) 62 { 63 return kobject_name(&slot->kobj); 64 } 65 66 /* File state for mmap()s on /proc/bus/pci/X/Y */ 67 enum pci_mmap_state { 68 pci_mmap_io, 69 pci_mmap_mem 70 }; 71 72 /* This defines the direction arg to the DMA mapping routines. */ 73 #define PCI_DMA_BIDIRECTIONAL 0 74 #define PCI_DMA_TODEVICE 1 75 #define PCI_DMA_FROMDEVICE 2 76 #define PCI_DMA_NONE 3 77 78 /* 79 * For PCI devices, the region numbers are assigned this way: 80 */ 81 enum { 82 /* #0-5: standard PCI resources */ 83 PCI_STD_RESOURCES, 84 PCI_STD_RESOURCE_END = 5, 85 86 /* #6: expansion ROM resource */ 87 PCI_ROM_RESOURCE, 88 89 /* device specific resources */ 90 #ifdef CONFIG_PCI_IOV 91 PCI_IOV_RESOURCES, 92 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 93 #endif 94 95 /* resources assigned to buses behind the bridge */ 96 #define PCI_BRIDGE_RESOURCE_NUM 4 97 98 PCI_BRIDGE_RESOURCES, 99 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 100 PCI_BRIDGE_RESOURCE_NUM - 1, 101 102 /* total resources associated with a PCI device */ 103 PCI_NUM_RESOURCES, 104 105 /* preserve this for compatibility */ 106 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 107 }; 108 109 typedef int __bitwise pci_power_t; 110 111 #define PCI_D0 ((pci_power_t __force) 0) 112 #define PCI_D1 ((pci_power_t __force) 1) 113 #define PCI_D2 ((pci_power_t __force) 2) 114 #define PCI_D3hot ((pci_power_t __force) 3) 115 #define PCI_D3cold ((pci_power_t __force) 4) 116 #define PCI_UNKNOWN ((pci_power_t __force) 5) 117 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 118 119 /* Remember to update this when the list above changes! */ 120 extern const char *pci_power_names[]; 121 122 static inline const char *pci_power_name(pci_power_t state) 123 { 124 return pci_power_names[1 + (int) state]; 125 } 126 127 #define PCI_PM_D2_DELAY 200 128 #define PCI_PM_D3_WAIT 10 129 #define PCI_PM_D3COLD_WAIT 100 130 #define PCI_PM_BUS_WAIT 50 131 132 /** The pci_channel state describes connectivity between the CPU and 133 * the pci device. If some PCI bus between here and the pci device 134 * has crashed or locked up, this info is reflected here. 135 */ 136 typedef unsigned int __bitwise pci_channel_state_t; 137 138 enum pci_channel_state { 139 /* I/O channel is in normal state */ 140 pci_channel_io_normal = (__force pci_channel_state_t) 1, 141 142 /* I/O to channel is blocked */ 143 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 144 145 /* PCI card is dead */ 146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 147 }; 148 149 typedef unsigned int __bitwise pcie_reset_state_t; 150 151 enum pcie_reset_state { 152 /* Reset is NOT asserted (Use to deassert reset) */ 153 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 154 155 /* Use #PERST to reset PCIe device */ 156 pcie_warm_reset = (__force pcie_reset_state_t) 2, 157 158 /* Use PCIe Hot Reset to reset device */ 159 pcie_hot_reset = (__force pcie_reset_state_t) 3 160 }; 161 162 typedef unsigned short __bitwise pci_dev_flags_t; 163 enum pci_dev_flags { 164 /* INTX_DISABLE in PCI_COMMAND register disables MSI 165 * generation too. 166 */ 167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 168 /* Device configuration is irrevocably lost if disabled into D3 */ 169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 170 /* Provide indication device is assigned by a Virtual Machine Manager */ 171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 172 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 174 /* Flag to indicate the device uses dma_alias_devfn */ 175 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), 176 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 177 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 178 }; 179 180 enum pci_irq_reroute_variant { 181 INTEL_IRQ_REROUTE_VARIANT = 1, 182 MAX_IRQ_REROUTE_VARIANTS = 3 183 }; 184 185 typedef unsigned short __bitwise pci_bus_flags_t; 186 enum pci_bus_flags { 187 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 188 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 189 }; 190 191 /* These values come from the PCI Express Spec */ 192 enum pcie_link_width { 193 PCIE_LNK_WIDTH_RESRV = 0x00, 194 PCIE_LNK_X1 = 0x01, 195 PCIE_LNK_X2 = 0x02, 196 PCIE_LNK_X4 = 0x04, 197 PCIE_LNK_X8 = 0x08, 198 PCIE_LNK_X12 = 0x0C, 199 PCIE_LNK_X16 = 0x10, 200 PCIE_LNK_X32 = 0x20, 201 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 202 }; 203 204 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 205 enum pci_bus_speed { 206 PCI_SPEED_33MHz = 0x00, 207 PCI_SPEED_66MHz = 0x01, 208 PCI_SPEED_66MHz_PCIX = 0x02, 209 PCI_SPEED_100MHz_PCIX = 0x03, 210 PCI_SPEED_133MHz_PCIX = 0x04, 211 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 212 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 213 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 214 PCI_SPEED_66MHz_PCIX_266 = 0x09, 215 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 216 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 217 AGP_UNKNOWN = 0x0c, 218 AGP_1X = 0x0d, 219 AGP_2X = 0x0e, 220 AGP_4X = 0x0f, 221 AGP_8X = 0x10, 222 PCI_SPEED_66MHz_PCIX_533 = 0x11, 223 PCI_SPEED_100MHz_PCIX_533 = 0x12, 224 PCI_SPEED_133MHz_PCIX_533 = 0x13, 225 PCIE_SPEED_2_5GT = 0x14, 226 PCIE_SPEED_5_0GT = 0x15, 227 PCIE_SPEED_8_0GT = 0x16, 228 PCI_SPEED_UNKNOWN = 0xff, 229 }; 230 231 struct pci_cap_saved_data { 232 u16 cap_nr; 233 bool cap_extended; 234 unsigned int size; 235 u32 data[0]; 236 }; 237 238 struct pci_cap_saved_state { 239 struct hlist_node next; 240 struct pci_cap_saved_data cap; 241 }; 242 243 struct pcie_link_state; 244 struct pci_vpd; 245 struct pci_sriov; 246 struct pci_ats; 247 248 /* 249 * The pci_dev structure is used to describe PCI devices. 250 */ 251 struct pci_dev { 252 struct list_head bus_list; /* node in per-bus list */ 253 struct pci_bus *bus; /* bus this device is on */ 254 struct pci_bus *subordinate; /* bus this device bridges to */ 255 256 void *sysdata; /* hook for sys-specific extension */ 257 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 258 struct pci_slot *slot; /* Physical slot this device is in */ 259 260 unsigned int devfn; /* encoded device & function index */ 261 unsigned short vendor; 262 unsigned short device; 263 unsigned short subsystem_vendor; 264 unsigned short subsystem_device; 265 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 266 u8 revision; /* PCI revision, low byte of class word */ 267 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 268 u8 pcie_cap; /* PCIe capability offset */ 269 u8 msi_cap; /* MSI capability offset */ 270 u8 msix_cap; /* MSI-X capability offset */ 271 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 272 u8 rom_base_reg; /* which config register controls the ROM */ 273 u8 pin; /* which interrupt pin this device uses */ 274 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 275 u8 dma_alias_devfn;/* devfn of DMA alias, if any */ 276 277 struct pci_driver *driver; /* which driver has allocated this device */ 278 u64 dma_mask; /* Mask of the bits of bus address this 279 device implements. Normally this is 280 0xffffffff. You only need to change 281 this if your device has broken DMA 282 or supports 64-bit transfers. */ 283 284 struct device_dma_parameters dma_parms; 285 286 pci_power_t current_state; /* Current operating state. In ACPI-speak, 287 this is D0-D3, D0 being fully functional, 288 and D3 being off. */ 289 u8 pm_cap; /* PM capability offset */ 290 unsigned int pme_support:5; /* Bitmask of states from which PME# 291 can be generated */ 292 unsigned int pme_interrupt:1; 293 unsigned int pme_poll:1; /* Poll device's PME status bit */ 294 unsigned int d1_support:1; /* Low power state D1 is supported */ 295 unsigned int d2_support:1; /* Low power state D2 is supported */ 296 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 297 unsigned int no_d3cold:1; /* D3cold is forbidden */ 298 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 299 unsigned int mmio_always_on:1; /* disallow turning off io/mem 300 decoding during bar sizing */ 301 unsigned int wakeup_prepared:1; 302 unsigned int runtime_d3cold:1; /* whether go through runtime 303 D3cold, not set for devices 304 powered on/off by the 305 corresponding bridge */ 306 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 307 unsigned int d3_delay; /* D3->D0 transition time in ms */ 308 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 309 310 #ifdef CONFIG_PCIEASPM 311 struct pcie_link_state *link_state; /* ASPM link state */ 312 #endif 313 314 pci_channel_state_t error_state; /* current connectivity state */ 315 struct device dev; /* Generic device interface */ 316 317 int cfg_size; /* Size of configuration space */ 318 319 /* 320 * Instead of touching interrupt line and base address registers 321 * directly, use the values stored here. They might be different! 322 */ 323 unsigned int irq; 324 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 325 326 bool match_driver; /* Skip attaching driver */ 327 /* These fields are used by common fixups */ 328 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 329 unsigned int multifunction:1;/* Part of multi-function device */ 330 /* keep track of device state */ 331 unsigned int is_added:1; 332 unsigned int is_busmaster:1; /* device is busmaster */ 333 unsigned int no_msi:1; /* device may not use msi */ 334 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 335 unsigned int block_cfg_access:1; /* config space access is blocked */ 336 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 337 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 338 unsigned int msi_enabled:1; 339 unsigned int msix_enabled:1; 340 unsigned int ari_enabled:1; /* ARI forwarding */ 341 unsigned int is_managed:1; 342 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 343 unsigned int state_saved:1; 344 unsigned int is_physfn:1; 345 unsigned int is_virtfn:1; 346 unsigned int reset_fn:1; 347 unsigned int is_hotplug_bridge:1; 348 unsigned int __aer_firmware_first_valid:1; 349 unsigned int __aer_firmware_first:1; 350 unsigned int broken_intx_masking:1; 351 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 352 pci_dev_flags_t dev_flags; 353 atomic_t enable_cnt; /* pci_enable_device has been called */ 354 355 u32 saved_config_space[16]; /* config space saved at suspend time */ 356 struct hlist_head saved_cap_space; 357 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 358 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 359 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 360 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 361 #ifdef CONFIG_PCI_MSI 362 struct list_head msi_list; 363 const struct attribute_group **msi_irq_groups; 364 #endif 365 struct pci_vpd *vpd; 366 #ifdef CONFIG_PCI_ATS 367 union { 368 struct pci_sriov *sriov; /* SR-IOV capability related */ 369 struct pci_dev *physfn; /* the PF this VF is associated with */ 370 }; 371 struct pci_ats *ats; /* Address Translation Service */ 372 #endif 373 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 374 size_t romlen; /* Length of ROM if it's not from the BAR */ 375 char *driver_override; /* Driver name to force a match */ 376 }; 377 378 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 379 { 380 #ifdef CONFIG_PCI_IOV 381 if (dev->is_virtfn) 382 dev = dev->physfn; 383 #endif 384 return dev; 385 } 386 387 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 388 389 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 390 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 391 392 static inline int pci_channel_offline(struct pci_dev *pdev) 393 { 394 return (pdev->error_state != pci_channel_io_normal); 395 } 396 397 struct pci_host_bridge_window { 398 struct list_head list; 399 struct resource *res; /* host bridge aperture (CPU address) */ 400 resource_size_t offset; /* bus address + offset = CPU address */ 401 }; 402 403 struct pci_host_bridge { 404 struct device dev; 405 struct pci_bus *bus; /* root bus */ 406 struct list_head windows; /* pci_host_bridge_windows */ 407 void (*release_fn)(struct pci_host_bridge *); 408 void *release_data; 409 }; 410 411 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 412 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 413 void (*release_fn)(struct pci_host_bridge *), 414 void *release_data); 415 416 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 417 418 /* 419 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 420 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 421 * buses below host bridges or subtractive decode bridges) go in the list. 422 * Use pci_bus_for_each_resource() to iterate through all the resources. 423 */ 424 425 /* 426 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 427 * and there's no way to program the bridge with the details of the window. 428 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 429 * decode bit set, because they are explicit and can be programmed with _SRS. 430 */ 431 #define PCI_SUBTRACTIVE_DECODE 0x1 432 433 struct pci_bus_resource { 434 struct list_head list; 435 struct resource *res; 436 unsigned int flags; 437 }; 438 439 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 440 441 struct pci_bus { 442 struct list_head node; /* node in list of buses */ 443 struct pci_bus *parent; /* parent bus this bridge is on */ 444 struct list_head children; /* list of child buses */ 445 struct list_head devices; /* list of devices on this bus */ 446 struct pci_dev *self; /* bridge device as seen by parent */ 447 struct list_head slots; /* list of slots on this bus */ 448 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 449 struct list_head resources; /* address space routed to this bus */ 450 struct resource busn_res; /* bus numbers routed to this bus */ 451 452 struct pci_ops *ops; /* configuration access functions */ 453 struct msi_chip *msi; /* MSI controller */ 454 void *sysdata; /* hook for sys-specific extension */ 455 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 456 457 unsigned char number; /* bus number */ 458 unsigned char primary; /* number of primary bridge */ 459 unsigned char max_bus_speed; /* enum pci_bus_speed */ 460 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 461 #ifdef CONFIG_PCI_DOMAINS_GENERIC 462 int domain_nr; 463 #endif 464 465 char name[48]; 466 467 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 468 pci_bus_flags_t bus_flags; /* inherited by child buses */ 469 struct device *bridge; 470 struct device dev; 471 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 472 struct bin_attribute *legacy_mem; /* legacy mem */ 473 unsigned int is_added:1; 474 }; 475 476 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 477 478 /* 479 * Returns true if the PCI bus is root (behind host-PCI bridge), 480 * false otherwise 481 * 482 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 483 * This is incorrect because "virtual" buses added for SR-IOV (via 484 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 485 */ 486 static inline bool pci_is_root_bus(struct pci_bus *pbus) 487 { 488 return !(pbus->parent); 489 } 490 491 /** 492 * pci_is_bridge - check if the PCI device is a bridge 493 * @dev: PCI device 494 * 495 * Return true if the PCI device is bridge whether it has subordinate 496 * or not. 497 */ 498 static inline bool pci_is_bridge(struct pci_dev *dev) 499 { 500 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 501 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 502 } 503 504 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 505 { 506 dev = pci_physfn(dev); 507 if (pci_is_root_bus(dev->bus)) 508 return NULL; 509 510 return dev->bus->self; 511 } 512 513 #ifdef CONFIG_PCI_MSI 514 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 515 { 516 return pci_dev->msi_enabled || pci_dev->msix_enabled; 517 } 518 #else 519 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 520 #endif 521 522 /* 523 * Error values that may be returned by PCI functions. 524 */ 525 #define PCIBIOS_SUCCESSFUL 0x00 526 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 527 #define PCIBIOS_BAD_VENDOR_ID 0x83 528 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 529 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 530 #define PCIBIOS_SET_FAILED 0x88 531 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 532 533 /* 534 * Translate above to generic errno for passing back through non-PCI code. 535 */ 536 static inline int pcibios_err_to_errno(int err) 537 { 538 if (err <= PCIBIOS_SUCCESSFUL) 539 return err; /* Assume already errno */ 540 541 switch (err) { 542 case PCIBIOS_FUNC_NOT_SUPPORTED: 543 return -ENOENT; 544 case PCIBIOS_BAD_VENDOR_ID: 545 return -ENOTTY; 546 case PCIBIOS_DEVICE_NOT_FOUND: 547 return -ENODEV; 548 case PCIBIOS_BAD_REGISTER_NUMBER: 549 return -EFAULT; 550 case PCIBIOS_SET_FAILED: 551 return -EIO; 552 case PCIBIOS_BUFFER_TOO_SMALL: 553 return -ENOSPC; 554 } 555 556 return -ERANGE; 557 } 558 559 /* Low-level architecture-dependent routines */ 560 561 struct pci_ops { 562 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 563 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 564 }; 565 566 /* 567 * ACPI needs to be able to access PCI config space before we've done a 568 * PCI bus scan and created pci_bus structures. 569 */ 570 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 571 int reg, int len, u32 *val); 572 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 573 int reg, int len, u32 val); 574 575 struct pci_bus_region { 576 dma_addr_t start; 577 dma_addr_t end; 578 }; 579 580 struct pci_dynids { 581 spinlock_t lock; /* protects list, index */ 582 struct list_head list; /* for IDs added at runtime */ 583 }; 584 585 586 /* 587 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 588 * a set of callbacks in struct pci_error_handlers, that device driver 589 * will be notified of PCI bus errors, and will be driven to recovery 590 * when an error occurs. 591 */ 592 593 typedef unsigned int __bitwise pci_ers_result_t; 594 595 enum pci_ers_result { 596 /* no result/none/not supported in device driver */ 597 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 598 599 /* Device driver can recover without slot reset */ 600 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 601 602 /* Device driver wants slot to be reset. */ 603 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 604 605 /* Device has completely failed, is unrecoverable */ 606 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 607 608 /* Device driver is fully recovered and operational */ 609 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 610 611 /* No AER capabilities registered for the driver */ 612 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 613 }; 614 615 /* PCI bus error event callbacks */ 616 struct pci_error_handlers { 617 /* PCI bus error detected on this device */ 618 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 619 enum pci_channel_state error); 620 621 /* MMIO has been re-enabled, but not DMA */ 622 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 623 624 /* PCI Express link has been reset */ 625 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 626 627 /* PCI slot has been reset */ 628 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 629 630 /* PCI function reset prepare or completed */ 631 void (*reset_notify)(struct pci_dev *dev, bool prepare); 632 633 /* Device driver may resume normal operations */ 634 void (*resume)(struct pci_dev *dev); 635 }; 636 637 638 struct module; 639 struct pci_driver { 640 struct list_head node; 641 const char *name; 642 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 643 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 644 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 645 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 646 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 647 int (*resume_early) (struct pci_dev *dev); 648 int (*resume) (struct pci_dev *dev); /* Device woken up */ 649 void (*shutdown) (struct pci_dev *dev); 650 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 651 const struct pci_error_handlers *err_handler; 652 struct device_driver driver; 653 struct pci_dynids dynids; 654 }; 655 656 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 657 658 /** 659 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 660 * @_table: device table name 661 * 662 * This macro is deprecated and should not be used in new code. 663 */ 664 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 665 const struct pci_device_id _table[] 666 667 /** 668 * PCI_DEVICE - macro used to describe a specific pci device 669 * @vend: the 16 bit PCI Vendor ID 670 * @dev: the 16 bit PCI Device ID 671 * 672 * This macro is used to create a struct pci_device_id that matches a 673 * specific device. The subvendor and subdevice fields will be set to 674 * PCI_ANY_ID. 675 */ 676 #define PCI_DEVICE(vend,dev) \ 677 .vendor = (vend), .device = (dev), \ 678 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 679 680 /** 681 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 682 * @vend: the 16 bit PCI Vendor ID 683 * @dev: the 16 bit PCI Device ID 684 * @subvend: the 16 bit PCI Subvendor ID 685 * @subdev: the 16 bit PCI Subdevice ID 686 * 687 * This macro is used to create a struct pci_device_id that matches a 688 * specific device with subsystem information. 689 */ 690 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 691 .vendor = (vend), .device = (dev), \ 692 .subvendor = (subvend), .subdevice = (subdev) 693 694 /** 695 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 696 * @dev_class: the class, subclass, prog-if triple for this device 697 * @dev_class_mask: the class mask for this device 698 * 699 * This macro is used to create a struct pci_device_id that matches a 700 * specific PCI class. The vendor, device, subvendor, and subdevice 701 * fields will be set to PCI_ANY_ID. 702 */ 703 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 704 .class = (dev_class), .class_mask = (dev_class_mask), \ 705 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 706 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 707 708 /** 709 * PCI_VDEVICE - macro used to describe a specific pci device in short form 710 * @vend: the vendor name 711 * @dev: the 16 bit PCI Device ID 712 * 713 * This macro is used to create a struct pci_device_id that matches a 714 * specific PCI device. The subvendor, and subdevice fields will be set 715 * to PCI_ANY_ID. The macro allows the next field to follow as the device 716 * private data. 717 */ 718 719 #define PCI_VDEVICE(vend, dev) \ 720 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 721 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 722 723 /* these external functions are only available when PCI support is enabled */ 724 #ifdef CONFIG_PCI 725 726 void pcie_bus_configure_settings(struct pci_bus *bus); 727 728 enum pcie_bus_config_types { 729 PCIE_BUS_TUNE_OFF, 730 PCIE_BUS_SAFE, 731 PCIE_BUS_PERFORMANCE, 732 PCIE_BUS_PEER2PEER, 733 }; 734 735 extern enum pcie_bus_config_types pcie_bus_config; 736 737 extern struct bus_type pci_bus_type; 738 739 /* Do NOT directly access these two variables, unless you are arch-specific PCI 740 * code, or PCI core code. */ 741 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 742 /* Some device drivers need know if PCI is initiated */ 743 int no_pci_devices(void); 744 745 void pcibios_resource_survey_bus(struct pci_bus *bus); 746 void pcibios_add_bus(struct pci_bus *bus); 747 void pcibios_remove_bus(struct pci_bus *bus); 748 void pcibios_fixup_bus(struct pci_bus *); 749 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 750 /* Architecture-specific versions may override this (weak) */ 751 char *pcibios_setup(char *str); 752 753 /* Used only when drivers/pci/setup.c is used */ 754 resource_size_t pcibios_align_resource(void *, const struct resource *, 755 resource_size_t, 756 resource_size_t); 757 void pcibios_update_irq(struct pci_dev *, int irq); 758 759 /* Weak but can be overriden by arch */ 760 void pci_fixup_cardbus(struct pci_bus *); 761 762 /* Generic PCI functions used internally */ 763 764 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 765 struct resource *res); 766 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 767 struct pci_bus_region *region); 768 void pcibios_scan_specific_bus(int busn); 769 struct pci_bus *pci_find_bus(int domain, int busnr); 770 void pci_bus_add_devices(const struct pci_bus *bus); 771 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, 772 struct pci_ops *ops, void *sysdata); 773 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 774 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 775 struct pci_ops *ops, void *sysdata, 776 struct list_head *resources); 777 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 778 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 779 void pci_bus_release_busn_res(struct pci_bus *b); 780 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 781 struct pci_ops *ops, void *sysdata, 782 struct list_head *resources); 783 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 784 int busnr); 785 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 786 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 787 const char *name, 788 struct hotplug_slot *hotplug); 789 void pci_destroy_slot(struct pci_slot *slot); 790 int pci_scan_slot(struct pci_bus *bus, int devfn); 791 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 792 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 793 unsigned int pci_scan_child_bus(struct pci_bus *bus); 794 void pci_bus_add_device(struct pci_dev *dev); 795 void pci_read_bridge_bases(struct pci_bus *child); 796 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 797 struct resource *res); 798 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 799 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 800 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 801 struct pci_dev *pci_dev_get(struct pci_dev *dev); 802 void pci_dev_put(struct pci_dev *dev); 803 void pci_remove_bus(struct pci_bus *b); 804 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 805 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 806 void pci_stop_root_bus(struct pci_bus *bus); 807 void pci_remove_root_bus(struct pci_bus *bus); 808 void pci_setup_cardbus(struct pci_bus *bus); 809 void pci_sort_breadthfirst(void); 810 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 811 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 812 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 813 814 /* Generic PCI functions exported to card drivers */ 815 816 enum pci_lost_interrupt_reason { 817 PCI_LOST_IRQ_NO_INFORMATION = 0, 818 PCI_LOST_IRQ_DISABLE_MSI, 819 PCI_LOST_IRQ_DISABLE_MSIX, 820 PCI_LOST_IRQ_DISABLE_ACPI, 821 }; 822 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 823 int pci_find_capability(struct pci_dev *dev, int cap); 824 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 825 int pci_find_ext_capability(struct pci_dev *dev, int cap); 826 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 827 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 828 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 829 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 830 831 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 832 struct pci_dev *from); 833 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 834 unsigned int ss_vendor, unsigned int ss_device, 835 struct pci_dev *from); 836 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 837 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 838 unsigned int devfn); 839 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 840 unsigned int devfn) 841 { 842 return pci_get_domain_bus_and_slot(0, bus, devfn); 843 } 844 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 845 int pci_dev_present(const struct pci_device_id *ids); 846 847 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 848 int where, u8 *val); 849 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 850 int where, u16 *val); 851 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 852 int where, u32 *val); 853 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 854 int where, u8 val); 855 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 856 int where, u16 val); 857 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 858 int where, u32 val); 859 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 860 861 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 862 { 863 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 864 } 865 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 866 { 867 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 868 } 869 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 870 u32 *val) 871 { 872 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 873 } 874 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 875 { 876 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 877 } 878 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 879 { 880 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 881 } 882 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 883 u32 val) 884 { 885 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 886 } 887 888 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 889 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 890 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 891 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 892 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 893 u16 clear, u16 set); 894 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 895 u32 clear, u32 set); 896 897 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 898 u16 set) 899 { 900 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 901 } 902 903 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 904 u32 set) 905 { 906 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 907 } 908 909 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 910 u16 clear) 911 { 912 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 913 } 914 915 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 916 u32 clear) 917 { 918 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 919 } 920 921 /* user-space driven config access */ 922 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 923 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 924 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 925 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 926 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 927 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 928 929 int __must_check pci_enable_device(struct pci_dev *dev); 930 int __must_check pci_enable_device_io(struct pci_dev *dev); 931 int __must_check pci_enable_device_mem(struct pci_dev *dev); 932 int __must_check pci_reenable_device(struct pci_dev *); 933 int __must_check pcim_enable_device(struct pci_dev *pdev); 934 void pcim_pin_device(struct pci_dev *pdev); 935 936 static inline int pci_is_enabled(struct pci_dev *pdev) 937 { 938 return (atomic_read(&pdev->enable_cnt) > 0); 939 } 940 941 static inline int pci_is_managed(struct pci_dev *pdev) 942 { 943 return pdev->is_managed; 944 } 945 946 void pci_disable_device(struct pci_dev *dev); 947 948 extern unsigned int pcibios_max_latency; 949 void pci_set_master(struct pci_dev *dev); 950 void pci_clear_master(struct pci_dev *dev); 951 952 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 953 int pci_set_cacheline_size(struct pci_dev *dev); 954 #define HAVE_PCI_SET_MWI 955 int __must_check pci_set_mwi(struct pci_dev *dev); 956 int pci_try_set_mwi(struct pci_dev *dev); 957 void pci_clear_mwi(struct pci_dev *dev); 958 void pci_intx(struct pci_dev *dev, int enable); 959 bool pci_intx_mask_supported(struct pci_dev *dev); 960 bool pci_check_and_mask_intx(struct pci_dev *dev); 961 bool pci_check_and_unmask_intx(struct pci_dev *dev); 962 void pci_msi_off(struct pci_dev *dev); 963 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 964 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 965 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 966 int pci_wait_for_pending_transaction(struct pci_dev *dev); 967 int pcix_get_max_mmrbc(struct pci_dev *dev); 968 int pcix_get_mmrbc(struct pci_dev *dev); 969 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 970 int pcie_get_readrq(struct pci_dev *dev); 971 int pcie_set_readrq(struct pci_dev *dev, int rq); 972 int pcie_get_mps(struct pci_dev *dev); 973 int pcie_set_mps(struct pci_dev *dev, int mps); 974 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 975 enum pcie_link_width *width); 976 int __pci_reset_function(struct pci_dev *dev); 977 int __pci_reset_function_locked(struct pci_dev *dev); 978 int pci_reset_function(struct pci_dev *dev); 979 int pci_try_reset_function(struct pci_dev *dev); 980 int pci_probe_reset_slot(struct pci_slot *slot); 981 int pci_reset_slot(struct pci_slot *slot); 982 int pci_try_reset_slot(struct pci_slot *slot); 983 int pci_probe_reset_bus(struct pci_bus *bus); 984 int pci_reset_bus(struct pci_bus *bus); 985 int pci_try_reset_bus(struct pci_bus *bus); 986 void pci_reset_secondary_bus(struct pci_dev *dev); 987 void pcibios_reset_secondary_bus(struct pci_dev *dev); 988 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 989 void pci_update_resource(struct pci_dev *dev, int resno); 990 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 991 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 992 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 993 bool pci_device_is_present(struct pci_dev *pdev); 994 995 /* ROM control related routines */ 996 int pci_enable_rom(struct pci_dev *pdev); 997 void pci_disable_rom(struct pci_dev *pdev); 998 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 999 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1000 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1001 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1002 1003 /* Power management related routines */ 1004 int pci_save_state(struct pci_dev *dev); 1005 void pci_restore_state(struct pci_dev *dev); 1006 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1007 int pci_load_and_free_saved_state(struct pci_dev *dev, 1008 struct pci_saved_state **state); 1009 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1010 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1011 u16 cap); 1012 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1013 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1014 u16 cap, unsigned int size); 1015 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1016 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1017 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1018 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1019 void pci_pme_active(struct pci_dev *dev, bool enable); 1020 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1021 bool runtime, bool enable); 1022 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1023 int pci_prepare_to_sleep(struct pci_dev *dev); 1024 int pci_back_from_sleep(struct pci_dev *dev); 1025 bool pci_dev_run_wake(struct pci_dev *dev); 1026 bool pci_check_pme_status(struct pci_dev *dev); 1027 void pci_pme_wakeup_bus(struct pci_bus *bus); 1028 1029 static inline void pci_ignore_hotplug(struct pci_dev *dev) 1030 { 1031 dev->ignore_hotplug = 1; 1032 } 1033 1034 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1035 bool enable) 1036 { 1037 return __pci_enable_wake(dev, state, false, enable); 1038 } 1039 1040 /* PCI Virtual Channel */ 1041 int pci_save_vc_state(struct pci_dev *dev); 1042 void pci_restore_vc_state(struct pci_dev *dev); 1043 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1044 1045 /* For use by arch with custom probe code */ 1046 void set_pcie_port_type(struct pci_dev *pdev); 1047 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1048 1049 /* Functions for PCI Hotplug drivers to use */ 1050 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1051 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1052 unsigned int pci_rescan_bus(struct pci_bus *bus); 1053 void pci_lock_rescan_remove(void); 1054 void pci_unlock_rescan_remove(void); 1055 1056 /* Vital product data routines */ 1057 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1058 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1059 1060 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1061 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1062 void pci_bus_assign_resources(const struct pci_bus *bus); 1063 void pci_bus_size_bridges(struct pci_bus *bus); 1064 int pci_claim_resource(struct pci_dev *, int); 1065 void pci_assign_unassigned_resources(void); 1066 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1067 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1068 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1069 void pdev_enable_device(struct pci_dev *); 1070 int pci_enable_resources(struct pci_dev *, int mask); 1071 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1072 int (*)(const struct pci_dev *, u8, u8)); 1073 #define HAVE_PCI_REQ_REGIONS 2 1074 int __must_check pci_request_regions(struct pci_dev *, const char *); 1075 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1076 void pci_release_regions(struct pci_dev *); 1077 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1078 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1079 void pci_release_region(struct pci_dev *, int); 1080 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1081 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1082 void pci_release_selected_regions(struct pci_dev *, int); 1083 1084 /* drivers/pci/bus.c */ 1085 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1086 void pci_bus_put(struct pci_bus *bus); 1087 void pci_add_resource(struct list_head *resources, struct resource *res); 1088 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1089 resource_size_t offset); 1090 void pci_free_resource_list(struct list_head *resources); 1091 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1092 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1093 void pci_bus_remove_resources(struct pci_bus *bus); 1094 1095 #define pci_bus_for_each_resource(bus, res, i) \ 1096 for (i = 0; \ 1097 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1098 i++) 1099 1100 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1101 struct resource *res, resource_size_t size, 1102 resource_size_t align, resource_size_t min, 1103 unsigned long type_mask, 1104 resource_size_t (*alignf)(void *, 1105 const struct resource *, 1106 resource_size_t, 1107 resource_size_t), 1108 void *alignf_data); 1109 1110 1111 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1112 1113 static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1114 { 1115 struct pci_bus_region region; 1116 1117 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1118 return region.start; 1119 } 1120 1121 /* Proper probing supporting hot-pluggable devices */ 1122 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1123 const char *mod_name); 1124 1125 /* 1126 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1127 */ 1128 #define pci_register_driver(driver) \ 1129 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1130 1131 void pci_unregister_driver(struct pci_driver *dev); 1132 1133 /** 1134 * module_pci_driver() - Helper macro for registering a PCI driver 1135 * @__pci_driver: pci_driver struct 1136 * 1137 * Helper macro for PCI drivers which do not do anything special in module 1138 * init/exit. This eliminates a lot of boilerplate. Each module may only 1139 * use this macro once, and calling it replaces module_init() and module_exit() 1140 */ 1141 #define module_pci_driver(__pci_driver) \ 1142 module_driver(__pci_driver, pci_register_driver, \ 1143 pci_unregister_driver) 1144 1145 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1146 int pci_add_dynid(struct pci_driver *drv, 1147 unsigned int vendor, unsigned int device, 1148 unsigned int subvendor, unsigned int subdevice, 1149 unsigned int class, unsigned int class_mask, 1150 unsigned long driver_data); 1151 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1152 struct pci_dev *dev); 1153 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1154 int pass); 1155 1156 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1157 void *userdata); 1158 int pci_cfg_space_size(struct pci_dev *dev); 1159 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1160 void pci_setup_bridge(struct pci_bus *bus); 1161 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1162 unsigned long type); 1163 1164 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1165 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1166 1167 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1168 unsigned int command_bits, u32 flags); 1169 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1170 1171 #include <linux/pci-dma.h> 1172 #include <linux/dmapool.h> 1173 1174 #define pci_pool dma_pool 1175 #define pci_pool_create(name, pdev, size, align, allocation) \ 1176 dma_pool_create(name, &pdev->dev, size, align, allocation) 1177 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1178 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1179 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1180 1181 enum pci_dma_burst_strategy { 1182 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, 1183 strategy_parameter is N/A */ 1184 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter 1185 byte boundaries */ 1186 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of 1187 strategy_parameter byte boundaries */ 1188 }; 1189 1190 struct msix_entry { 1191 u32 vector; /* kernel uses to write allocated vector */ 1192 u16 entry; /* driver uses to specify entry, OS writes */ 1193 }; 1194 1195 1196 #ifdef CONFIG_PCI_MSI 1197 int pci_msi_vec_count(struct pci_dev *dev); 1198 void pci_msi_shutdown(struct pci_dev *dev); 1199 void pci_disable_msi(struct pci_dev *dev); 1200 int pci_msix_vec_count(struct pci_dev *dev); 1201 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1202 void pci_msix_shutdown(struct pci_dev *dev); 1203 void pci_disable_msix(struct pci_dev *dev); 1204 void pci_restore_msi_state(struct pci_dev *dev); 1205 int pci_msi_enabled(void); 1206 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1207 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1208 { 1209 int rc = pci_enable_msi_range(dev, nvec, nvec); 1210 if (rc < 0) 1211 return rc; 1212 return 0; 1213 } 1214 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1215 int minvec, int maxvec); 1216 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1217 struct msix_entry *entries, int nvec) 1218 { 1219 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1220 if (rc < 0) 1221 return rc; 1222 return 0; 1223 } 1224 #else 1225 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1226 static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1227 static inline void pci_disable_msi(struct pci_dev *dev) { } 1228 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1229 static inline int pci_enable_msix(struct pci_dev *dev, 1230 struct msix_entry *entries, int nvec) 1231 { return -ENOSYS; } 1232 static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1233 static inline void pci_disable_msix(struct pci_dev *dev) { } 1234 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1235 static inline int pci_msi_enabled(void) { return 0; } 1236 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1237 int maxvec) 1238 { return -ENOSYS; } 1239 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1240 { return -ENOSYS; } 1241 static inline int pci_enable_msix_range(struct pci_dev *dev, 1242 struct msix_entry *entries, int minvec, int maxvec) 1243 { return -ENOSYS; } 1244 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1245 struct msix_entry *entries, int nvec) 1246 { return -ENOSYS; } 1247 #endif 1248 1249 #ifdef CONFIG_PCIEPORTBUS 1250 extern bool pcie_ports_disabled; 1251 extern bool pcie_ports_auto; 1252 #else 1253 #define pcie_ports_disabled true 1254 #define pcie_ports_auto false 1255 #endif 1256 1257 #ifdef CONFIG_PCIEASPM 1258 bool pcie_aspm_support_enabled(void); 1259 #else 1260 static inline bool pcie_aspm_support_enabled(void) { return false; } 1261 #endif 1262 1263 #ifdef CONFIG_PCIEAER 1264 void pci_no_aer(void); 1265 bool pci_aer_available(void); 1266 #else 1267 static inline void pci_no_aer(void) { } 1268 static inline bool pci_aer_available(void) { return false; } 1269 #endif 1270 1271 #ifdef CONFIG_PCIE_ECRC 1272 void pcie_set_ecrc_checking(struct pci_dev *dev); 1273 void pcie_ecrc_get_policy(char *str); 1274 #else 1275 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1276 static inline void pcie_ecrc_get_policy(char *str) { } 1277 #endif 1278 1279 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) 1280 1281 #ifdef CONFIG_HT_IRQ 1282 /* The functions a driver should call */ 1283 int ht_create_irq(struct pci_dev *dev, int idx); 1284 void ht_destroy_irq(unsigned int irq); 1285 #endif /* CONFIG_HT_IRQ */ 1286 1287 void pci_cfg_access_lock(struct pci_dev *dev); 1288 bool pci_cfg_access_trylock(struct pci_dev *dev); 1289 void pci_cfg_access_unlock(struct pci_dev *dev); 1290 1291 /* 1292 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1293 * a PCI domain is defined to be a set of PCI buses which share 1294 * configuration space. 1295 */ 1296 #ifdef CONFIG_PCI_DOMAINS 1297 extern int pci_domains_supported; 1298 int pci_get_new_domain_nr(void); 1299 #else 1300 enum { pci_domains_supported = 0 }; 1301 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1302 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1303 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1304 #endif /* CONFIG_PCI_DOMAINS */ 1305 1306 /* 1307 * Generic implementation for PCI domain support. If your 1308 * architecture does not need custom management of PCI 1309 * domains then this implementation will be used 1310 */ 1311 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1312 static inline int pci_domain_nr(struct pci_bus *bus) 1313 { 1314 return bus->domain_nr; 1315 } 1316 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); 1317 #else 1318 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, 1319 struct device *parent) 1320 { 1321 } 1322 #endif 1323 1324 /* some architectures require additional setup to direct VGA traffic */ 1325 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1326 unsigned int command_bits, u32 flags); 1327 void pci_register_set_vga_state(arch_set_vga_state_t func); 1328 1329 #else /* CONFIG_PCI is not enabled */ 1330 1331 /* 1332 * If the system does not have PCI, clearly these return errors. Define 1333 * these as simple inline functions to avoid hair in drivers. 1334 */ 1335 1336 #define _PCI_NOP(o, s, t) \ 1337 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1338 int where, t val) \ 1339 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1340 1341 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1342 _PCI_NOP(o, word, u16 x) \ 1343 _PCI_NOP(o, dword, u32 x) 1344 _PCI_NOP_ALL(read, *) 1345 _PCI_NOP_ALL(write,) 1346 1347 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1348 unsigned int device, 1349 struct pci_dev *from) 1350 { return NULL; } 1351 1352 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1353 unsigned int device, 1354 unsigned int ss_vendor, 1355 unsigned int ss_device, 1356 struct pci_dev *from) 1357 { return NULL; } 1358 1359 static inline struct pci_dev *pci_get_class(unsigned int class, 1360 struct pci_dev *from) 1361 { return NULL; } 1362 1363 #define pci_dev_present(ids) (0) 1364 #define no_pci_devices() (1) 1365 #define pci_dev_put(dev) do { } while (0) 1366 1367 static inline void pci_set_master(struct pci_dev *dev) { } 1368 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1369 static inline void pci_disable_device(struct pci_dev *dev) { } 1370 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1371 { return -EIO; } 1372 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1373 { return -EIO; } 1374 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1375 unsigned int size) 1376 { return -EIO; } 1377 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1378 unsigned long mask) 1379 { return -EIO; } 1380 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1381 { return -EBUSY; } 1382 static inline int __pci_register_driver(struct pci_driver *drv, 1383 struct module *owner) 1384 { return 0; } 1385 static inline int pci_register_driver(struct pci_driver *drv) 1386 { return 0; } 1387 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1388 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1389 { return 0; } 1390 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1391 int cap) 1392 { return 0; } 1393 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1394 { return 0; } 1395 1396 /* Power management related routines */ 1397 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1398 static inline void pci_restore_state(struct pci_dev *dev) { } 1399 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1400 { return 0; } 1401 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1402 { return 0; } 1403 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1404 pm_message_t state) 1405 { return PCI_D0; } 1406 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1407 int enable) 1408 { return 0; } 1409 1410 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1411 { return -EIO; } 1412 static inline void pci_release_regions(struct pci_dev *dev) { } 1413 1414 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 1415 1416 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1417 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1418 { return 0; } 1419 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1420 1421 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1422 { return NULL; } 1423 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1424 unsigned int devfn) 1425 { return NULL; } 1426 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1427 unsigned int devfn) 1428 { return NULL; } 1429 1430 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1431 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1432 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1433 1434 #define dev_is_pci(d) (false) 1435 #define dev_is_pf(d) (false) 1436 #define dev_num_vf(d) (0) 1437 #endif /* CONFIG_PCI */ 1438 1439 /* Include architecture-dependent settings and functions */ 1440 1441 #include <asm/pci.h> 1442 1443 /* these helpers provide future and backwards compatibility 1444 * for accessing popular PCI BAR info */ 1445 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1446 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1447 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1448 #define pci_resource_len(dev,bar) \ 1449 ((pci_resource_start((dev), (bar)) == 0 && \ 1450 pci_resource_end((dev), (bar)) == \ 1451 pci_resource_start((dev), (bar))) ? 0 : \ 1452 \ 1453 (pci_resource_end((dev), (bar)) - \ 1454 pci_resource_start((dev), (bar)) + 1)) 1455 1456 /* Similar to the helpers above, these manipulate per-pci_dev 1457 * driver-specific data. They are really just a wrapper around 1458 * the generic device structure functions of these calls. 1459 */ 1460 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1461 { 1462 return dev_get_drvdata(&pdev->dev); 1463 } 1464 1465 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1466 { 1467 dev_set_drvdata(&pdev->dev, data); 1468 } 1469 1470 /* If you want to know what to call your pci_dev, ask this function. 1471 * Again, it's a wrapper around the generic device. 1472 */ 1473 static inline const char *pci_name(const struct pci_dev *pdev) 1474 { 1475 return dev_name(&pdev->dev); 1476 } 1477 1478 1479 /* Some archs don't want to expose struct resource to userland as-is 1480 * in sysfs and /proc 1481 */ 1482 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1483 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1484 const struct resource *rsrc, resource_size_t *start, 1485 resource_size_t *end) 1486 { 1487 *start = rsrc->start; 1488 *end = rsrc->end; 1489 } 1490 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1491 1492 1493 /* 1494 * The world is not perfect and supplies us with broken PCI devices. 1495 * For at least a part of these bugs we need a work-around, so both 1496 * generic (drivers/pci/quirks.c) and per-architecture code can define 1497 * fixup hooks to be called for particular buggy devices. 1498 */ 1499 1500 struct pci_fixup { 1501 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1502 u16 device; /* You can use PCI_ANY_ID here of course */ 1503 u32 class; /* You can use PCI_ANY_ID here too */ 1504 unsigned int class_shift; /* should be 0, 8, 16 */ 1505 void (*hook)(struct pci_dev *dev); 1506 }; 1507 1508 enum pci_fixup_pass { 1509 pci_fixup_early, /* Before probing BARs */ 1510 pci_fixup_header, /* After reading configuration header */ 1511 pci_fixup_final, /* Final phase of device fixups */ 1512 pci_fixup_enable, /* pci_enable_device() time */ 1513 pci_fixup_resume, /* pci_device_resume() */ 1514 pci_fixup_suspend, /* pci_device_suspend() */ 1515 pci_fixup_resume_early, /* pci_device_resume_early() */ 1516 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1517 }; 1518 1519 /* Anonymous variables would be nice... */ 1520 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1521 class_shift, hook) \ 1522 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1523 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1524 = { vendor, device, class, class_shift, hook }; 1525 1526 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1527 class_shift, hook) \ 1528 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1529 hook, vendor, device, class, class_shift, hook) 1530 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1531 class_shift, hook) \ 1532 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1533 hook, vendor, device, class, class_shift, hook) 1534 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1535 class_shift, hook) \ 1536 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1537 hook, vendor, device, class, class_shift, hook) 1538 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1539 class_shift, hook) \ 1540 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1541 hook, vendor, device, class, class_shift, hook) 1542 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1543 class_shift, hook) \ 1544 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1545 resume##hook, vendor, device, class, \ 1546 class_shift, hook) 1547 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1548 class_shift, hook) \ 1549 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1550 resume_early##hook, vendor, device, \ 1551 class, class_shift, hook) 1552 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1553 class_shift, hook) \ 1554 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1555 suspend##hook, vendor, device, class, \ 1556 class_shift, hook) 1557 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1558 class_shift, hook) \ 1559 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1560 suspend_late##hook, vendor, device, \ 1561 class, class_shift, hook) 1562 1563 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1564 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1565 hook, vendor, device, PCI_ANY_ID, 0, hook) 1566 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1567 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1568 hook, vendor, device, PCI_ANY_ID, 0, hook) 1569 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1570 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1571 hook, vendor, device, PCI_ANY_ID, 0, hook) 1572 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1573 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1574 hook, vendor, device, PCI_ANY_ID, 0, hook) 1575 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1576 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1577 resume##hook, vendor, device, \ 1578 PCI_ANY_ID, 0, hook) 1579 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1580 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1581 resume_early##hook, vendor, device, \ 1582 PCI_ANY_ID, 0, hook) 1583 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1584 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1585 suspend##hook, vendor, device, \ 1586 PCI_ANY_ID, 0, hook) 1587 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1588 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1589 suspend_late##hook, vendor, device, \ 1590 PCI_ANY_ID, 0, hook) 1591 1592 #ifdef CONFIG_PCI_QUIRKS 1593 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1594 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1595 void pci_dev_specific_enable_acs(struct pci_dev *dev); 1596 #else 1597 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1598 struct pci_dev *dev) { } 1599 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1600 u16 acs_flags) 1601 { 1602 return -ENOTTY; 1603 } 1604 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } 1605 #endif 1606 1607 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1608 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1609 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1610 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1611 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1612 const char *name); 1613 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1614 1615 extern int pci_pci_problems; 1616 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1617 #define PCIPCI_TRITON 2 1618 #define PCIPCI_NATOMA 4 1619 #define PCIPCI_VIAETBF 8 1620 #define PCIPCI_VSFX 16 1621 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1622 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1623 1624 extern unsigned long pci_cardbus_io_size; 1625 extern unsigned long pci_cardbus_mem_size; 1626 extern u8 pci_dfl_cache_line_size; 1627 extern u8 pci_cache_line_size; 1628 1629 extern unsigned long pci_hotplug_io_size; 1630 extern unsigned long pci_hotplug_mem_size; 1631 1632 /* Architecture-specific versions may override these (weak) */ 1633 void pcibios_disable_device(struct pci_dev *dev); 1634 void pcibios_set_master(struct pci_dev *dev); 1635 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1636 enum pcie_reset_state state); 1637 int pcibios_add_device(struct pci_dev *dev); 1638 void pcibios_release_device(struct pci_dev *dev); 1639 void pcibios_penalize_isa_irq(int irq, int active); 1640 1641 #ifdef CONFIG_HIBERNATE_CALLBACKS 1642 extern struct dev_pm_ops pcibios_pm_ops; 1643 #endif 1644 1645 #ifdef CONFIG_PCI_MMCONFIG 1646 void __init pci_mmcfg_early_init(void); 1647 void __init pci_mmcfg_late_init(void); 1648 #else 1649 static inline void pci_mmcfg_early_init(void) { } 1650 static inline void pci_mmcfg_late_init(void) { } 1651 #endif 1652 1653 int pci_ext_cfg_avail(void); 1654 1655 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1656 1657 #ifdef CONFIG_PCI_IOV 1658 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1659 void pci_disable_sriov(struct pci_dev *dev); 1660 int pci_num_vf(struct pci_dev *dev); 1661 int pci_vfs_assigned(struct pci_dev *dev); 1662 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1663 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1664 #else 1665 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1666 { return -ENODEV; } 1667 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1668 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1669 static inline int pci_vfs_assigned(struct pci_dev *dev) 1670 { return 0; } 1671 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1672 { return 0; } 1673 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1674 { return 0; } 1675 #endif 1676 1677 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1678 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1679 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1680 #endif 1681 1682 /** 1683 * pci_pcie_cap - get the saved PCIe capability offset 1684 * @dev: PCI device 1685 * 1686 * PCIe capability offset is calculated at PCI device initialization 1687 * time and saved in the data structure. This function returns saved 1688 * PCIe capability offset. Using this instead of pci_find_capability() 1689 * reduces unnecessary search in the PCI configuration space. If you 1690 * need to calculate PCIe capability offset from raw device for some 1691 * reasons, please use pci_find_capability() instead. 1692 */ 1693 static inline int pci_pcie_cap(struct pci_dev *dev) 1694 { 1695 return dev->pcie_cap; 1696 } 1697 1698 /** 1699 * pci_is_pcie - check if the PCI device is PCI Express capable 1700 * @dev: PCI device 1701 * 1702 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1703 */ 1704 static inline bool pci_is_pcie(struct pci_dev *dev) 1705 { 1706 return pci_pcie_cap(dev); 1707 } 1708 1709 /** 1710 * pcie_caps_reg - get the PCIe Capabilities Register 1711 * @dev: PCI device 1712 */ 1713 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1714 { 1715 return dev->pcie_flags_reg; 1716 } 1717 1718 /** 1719 * pci_pcie_type - get the PCIe device/port type 1720 * @dev: PCI device 1721 */ 1722 static inline int pci_pcie_type(const struct pci_dev *dev) 1723 { 1724 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1725 } 1726 1727 void pci_request_acs(void); 1728 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1729 bool pci_acs_path_enabled(struct pci_dev *start, 1730 struct pci_dev *end, u16 acs_flags); 1731 1732 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1733 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1734 1735 /* Large Resource Data Type Tag Item Names */ 1736 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1737 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1738 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1739 1740 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1741 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1742 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1743 1744 /* Small Resource Data Type Tag Item Names */ 1745 #define PCI_VPD_STIN_END 0x78 /* End */ 1746 1747 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1748 1749 #define PCI_VPD_SRDT_TIN_MASK 0x78 1750 #define PCI_VPD_SRDT_LEN_MASK 0x07 1751 1752 #define PCI_VPD_LRDT_TAG_SIZE 3 1753 #define PCI_VPD_SRDT_TAG_SIZE 1 1754 1755 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1756 1757 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1758 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1759 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1760 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1761 1762 /** 1763 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1764 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1765 * 1766 * Returns the extracted Large Resource Data Type length. 1767 */ 1768 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1769 { 1770 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1771 } 1772 1773 /** 1774 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1775 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1776 * 1777 * Returns the extracted Small Resource Data Type length. 1778 */ 1779 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1780 { 1781 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1782 } 1783 1784 /** 1785 * pci_vpd_info_field_size - Extracts the information field length 1786 * @lrdt: Pointer to the beginning of an information field header 1787 * 1788 * Returns the extracted information field length. 1789 */ 1790 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1791 { 1792 return info_field[2]; 1793 } 1794 1795 /** 1796 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1797 * @buf: Pointer to buffered vpd data 1798 * @off: The offset into the buffer at which to begin the search 1799 * @len: The length of the vpd buffer 1800 * @rdt: The Resource Data Type to search for 1801 * 1802 * Returns the index where the Resource Data Type was found or 1803 * -ENOENT otherwise. 1804 */ 1805 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1806 1807 /** 1808 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1809 * @buf: Pointer to buffered vpd data 1810 * @off: The offset into the buffer at which to begin the search 1811 * @len: The length of the buffer area, relative to off, in which to search 1812 * @kw: The keyword to search for 1813 * 1814 * Returns the index where the information field keyword was found or 1815 * -ENOENT otherwise. 1816 */ 1817 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1818 unsigned int len, const char *kw); 1819 1820 /* PCI <-> OF binding helpers */ 1821 #ifdef CONFIG_OF 1822 struct device_node; 1823 void pci_set_of_node(struct pci_dev *dev); 1824 void pci_release_of_node(struct pci_dev *dev); 1825 void pci_set_bus_of_node(struct pci_bus *bus); 1826 void pci_release_bus_of_node(struct pci_bus *bus); 1827 1828 /* Arch may override this (weak) */ 1829 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1830 1831 static inline struct device_node * 1832 pci_device_to_OF_node(const struct pci_dev *pdev) 1833 { 1834 return pdev ? pdev->dev.of_node : NULL; 1835 } 1836 1837 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1838 { 1839 return bus ? bus->dev.of_node : NULL; 1840 } 1841 1842 #else /* CONFIG_OF */ 1843 static inline void pci_set_of_node(struct pci_dev *dev) { } 1844 static inline void pci_release_of_node(struct pci_dev *dev) { } 1845 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1846 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1847 #endif /* CONFIG_OF */ 1848 1849 #ifdef CONFIG_EEH 1850 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1851 { 1852 return pdev->dev.archdata.edev; 1853 } 1854 #endif 1855 1856 int pci_for_each_dma_alias(struct pci_dev *pdev, 1857 int (*fn)(struct pci_dev *pdev, 1858 u16 alias, void *data), void *data); 1859 1860 /* helper functions for operation of device flag */ 1861 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 1862 { 1863 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 1864 } 1865 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 1866 { 1867 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 1868 } 1869 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 1870 { 1871 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 1872 } 1873 #endif /* LINUX_PCI_H */ 1874