1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/interrupt.h> 32 #include <linux/io.h> 33 #include <linux/resource_ext.h> 34 #include <uapi/linux/pci.h> 35 36 #include <linux/pci_ids.h> 37 38 /* 39 * The PCI interface treats multi-function devices as independent 40 * devices. The slot/function address of each device is encoded 41 * in a single byte as follows: 42 * 43 * 7:3 = slot 44 * 2:0 = function 45 * 46 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 47 * In the interest of not exposing interfaces to user-space unnecessarily, 48 * the following kernel-only defines are being added here. 49 */ 50 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 51 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 52 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 53 54 /* pci_slot represents a physical slot */ 55 struct pci_slot { 56 struct pci_bus *bus; /* The bus this slot is on */ 57 struct list_head list; /* node in list of slots on this bus */ 58 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 59 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 60 struct kobject kobj; 61 }; 62 63 static inline const char *pci_slot_name(const struct pci_slot *slot) 64 { 65 return kobject_name(&slot->kobj); 66 } 67 68 /* File state for mmap()s on /proc/bus/pci/X/Y */ 69 enum pci_mmap_state { 70 pci_mmap_io, 71 pci_mmap_mem 72 }; 73 74 /* 75 * For PCI devices, the region numbers are assigned this way: 76 */ 77 enum { 78 /* #0-5: standard PCI resources */ 79 PCI_STD_RESOURCES, 80 PCI_STD_RESOURCE_END = 5, 81 82 /* #6: expansion ROM resource */ 83 PCI_ROM_RESOURCE, 84 85 /* device specific resources */ 86 #ifdef CONFIG_PCI_IOV 87 PCI_IOV_RESOURCES, 88 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 89 #endif 90 91 /* resources assigned to buses behind the bridge */ 92 #define PCI_BRIDGE_RESOURCE_NUM 4 93 94 PCI_BRIDGE_RESOURCES, 95 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 96 PCI_BRIDGE_RESOURCE_NUM - 1, 97 98 /* total resources associated with a PCI device */ 99 PCI_NUM_RESOURCES, 100 101 /* preserve this for compatibility */ 102 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 103 }; 104 105 /* 106 * pci_power_t values must match the bits in the Capabilities PME_Support 107 * and Control/Status PowerState fields in the Power Management capability. 108 */ 109 typedef int __bitwise pci_power_t; 110 111 #define PCI_D0 ((pci_power_t __force) 0) 112 #define PCI_D1 ((pci_power_t __force) 1) 113 #define PCI_D2 ((pci_power_t __force) 2) 114 #define PCI_D3hot ((pci_power_t __force) 3) 115 #define PCI_D3cold ((pci_power_t __force) 4) 116 #define PCI_UNKNOWN ((pci_power_t __force) 5) 117 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 118 119 /* Remember to update this when the list above changes! */ 120 extern const char *pci_power_names[]; 121 122 static inline const char *pci_power_name(pci_power_t state) 123 { 124 return pci_power_names[1 + (__force int) state]; 125 } 126 127 #define PCI_PM_D2_DELAY 200 128 #define PCI_PM_D3_WAIT 10 129 #define PCI_PM_D3COLD_WAIT 100 130 #define PCI_PM_BUS_WAIT 50 131 132 /** The pci_channel state describes connectivity between the CPU and 133 * the pci device. If some PCI bus between here and the pci device 134 * has crashed or locked up, this info is reflected here. 135 */ 136 typedef unsigned int __bitwise pci_channel_state_t; 137 138 enum pci_channel_state { 139 /* I/O channel is in normal state */ 140 pci_channel_io_normal = (__force pci_channel_state_t) 1, 141 142 /* I/O to channel is blocked */ 143 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 144 145 /* PCI card is dead */ 146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 147 }; 148 149 typedef unsigned int __bitwise pcie_reset_state_t; 150 151 enum pcie_reset_state { 152 /* Reset is NOT asserted (Use to deassert reset) */ 153 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 154 155 /* Use #PERST to reset PCIe device */ 156 pcie_warm_reset = (__force pcie_reset_state_t) 2, 157 158 /* Use PCIe Hot Reset to reset device */ 159 pcie_hot_reset = (__force pcie_reset_state_t) 3 160 }; 161 162 typedef unsigned short __bitwise pci_dev_flags_t; 163 enum pci_dev_flags { 164 /* INTX_DISABLE in PCI_COMMAND register disables MSI 165 * generation too. 166 */ 167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 168 /* Device configuration is irrevocably lost if disabled into D3 */ 169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 170 /* Provide indication device is assigned by a Virtual Machine Manager */ 171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 172 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 174 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 175 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 176 /* Do not use bus resets for device */ 177 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 178 /* Do not use PM reset even if device advertises NoSoftRst- */ 179 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 180 /* Get VPD from function 0 VPD */ 181 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 182 /* a non-root bridge where translation occurs, stop alias search here */ 183 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 184 /* Do not use FLR even if device advertises PCI_AF_CAP */ 185 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 186 /* 187 * Resume before calling the driver's system suspend hooks, disabling 188 * the direct_complete optimization. 189 */ 190 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11), 191 }; 192 193 enum pci_irq_reroute_variant { 194 INTEL_IRQ_REROUTE_VARIANT = 1, 195 MAX_IRQ_REROUTE_VARIANTS = 3 196 }; 197 198 typedef unsigned short __bitwise pci_bus_flags_t; 199 enum pci_bus_flags { 200 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 201 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 202 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 203 }; 204 205 /* These values come from the PCI Express Spec */ 206 enum pcie_link_width { 207 PCIE_LNK_WIDTH_RESRV = 0x00, 208 PCIE_LNK_X1 = 0x01, 209 PCIE_LNK_X2 = 0x02, 210 PCIE_LNK_X4 = 0x04, 211 PCIE_LNK_X8 = 0x08, 212 PCIE_LNK_X12 = 0x0C, 213 PCIE_LNK_X16 = 0x10, 214 PCIE_LNK_X32 = 0x20, 215 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 216 }; 217 218 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 219 enum pci_bus_speed { 220 PCI_SPEED_33MHz = 0x00, 221 PCI_SPEED_66MHz = 0x01, 222 PCI_SPEED_66MHz_PCIX = 0x02, 223 PCI_SPEED_100MHz_PCIX = 0x03, 224 PCI_SPEED_133MHz_PCIX = 0x04, 225 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 226 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 227 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 228 PCI_SPEED_66MHz_PCIX_266 = 0x09, 229 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 230 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 231 AGP_UNKNOWN = 0x0c, 232 AGP_1X = 0x0d, 233 AGP_2X = 0x0e, 234 AGP_4X = 0x0f, 235 AGP_8X = 0x10, 236 PCI_SPEED_66MHz_PCIX_533 = 0x11, 237 PCI_SPEED_100MHz_PCIX_533 = 0x12, 238 PCI_SPEED_133MHz_PCIX_533 = 0x13, 239 PCIE_SPEED_2_5GT = 0x14, 240 PCIE_SPEED_5_0GT = 0x15, 241 PCIE_SPEED_8_0GT = 0x16, 242 PCI_SPEED_UNKNOWN = 0xff, 243 }; 244 245 struct pci_cap_saved_data { 246 u16 cap_nr; 247 bool cap_extended; 248 unsigned int size; 249 u32 data[0]; 250 }; 251 252 struct pci_cap_saved_state { 253 struct hlist_node next; 254 struct pci_cap_saved_data cap; 255 }; 256 257 struct irq_affinity; 258 struct pcie_link_state; 259 struct pci_vpd; 260 struct pci_sriov; 261 struct pci_ats; 262 263 /* 264 * The pci_dev structure is used to describe PCI devices. 265 */ 266 struct pci_dev { 267 struct list_head bus_list; /* node in per-bus list */ 268 struct pci_bus *bus; /* bus this device is on */ 269 struct pci_bus *subordinate; /* bus this device bridges to */ 270 271 void *sysdata; /* hook for sys-specific extension */ 272 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 273 struct pci_slot *slot; /* Physical slot this device is in */ 274 275 unsigned int devfn; /* encoded device & function index */ 276 unsigned short vendor; 277 unsigned short device; 278 unsigned short subsystem_vendor; 279 unsigned short subsystem_device; 280 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 281 u8 revision; /* PCI revision, low byte of class word */ 282 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 283 #ifdef CONFIG_PCIEAER 284 u16 aer_cap; /* AER capability offset */ 285 #endif 286 u8 pcie_cap; /* PCIe capability offset */ 287 u8 msi_cap; /* MSI capability offset */ 288 u8 msix_cap; /* MSI-X capability offset */ 289 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 290 u8 rom_base_reg; /* which config register controls the ROM */ 291 u8 pin; /* which interrupt pin this device uses */ 292 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 293 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */ 294 295 struct pci_driver *driver; /* which driver has allocated this device */ 296 u64 dma_mask; /* Mask of the bits of bus address this 297 device implements. Normally this is 298 0xffffffff. You only need to change 299 this if your device has broken DMA 300 or supports 64-bit transfers. */ 301 302 struct device_dma_parameters dma_parms; 303 304 pci_power_t current_state; /* Current operating state. In ACPI-speak, 305 this is D0-D3, D0 being fully functional, 306 and D3 being off. */ 307 u8 pm_cap; /* PM capability offset */ 308 unsigned int pme_support:5; /* Bitmask of states from which PME# 309 can be generated */ 310 unsigned int pme_poll:1; /* Poll device's PME status bit */ 311 unsigned int d1_support:1; /* Low power state D1 is supported */ 312 unsigned int d2_support:1; /* Low power state D2 is supported */ 313 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 314 unsigned int no_d3cold:1; /* D3cold is forbidden */ 315 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 316 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 317 unsigned int mmio_always_on:1; /* disallow turning off io/mem 318 decoding during bar sizing */ 319 unsigned int wakeup_prepared:1; 320 unsigned int runtime_d3cold:1; /* whether go through runtime 321 D3cold, not set for devices 322 powered on/off by the 323 corresponding bridge */ 324 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 325 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 326 controlled exclusively by 327 user sysfs */ 328 unsigned int d3_delay; /* D3->D0 transition time in ms */ 329 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 330 331 #ifdef CONFIG_PCIEASPM 332 struct pcie_link_state *link_state; /* ASPM link state */ 333 #endif 334 335 pci_channel_state_t error_state; /* current connectivity state */ 336 struct device dev; /* Generic device interface */ 337 338 int cfg_size; /* Size of configuration space */ 339 340 /* 341 * Instead of touching interrupt line and base address registers 342 * directly, use the values stored here. They might be different! 343 */ 344 unsigned int irq; 345 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 346 347 bool match_driver; /* Skip attaching driver */ 348 /* These fields are used by common fixups */ 349 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 350 unsigned int multifunction:1;/* Part of multi-function device */ 351 /* keep track of device state */ 352 unsigned int is_added:1; 353 unsigned int is_busmaster:1; /* device is busmaster */ 354 unsigned int no_msi:1; /* device may not use msi */ 355 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 356 unsigned int block_cfg_access:1; /* config space access is blocked */ 357 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 358 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 359 unsigned int msi_enabled:1; 360 unsigned int msix_enabled:1; 361 unsigned int ari_enabled:1; /* ARI forwarding */ 362 unsigned int ats_enabled:1; /* Address Translation Service */ 363 unsigned int pasid_enabled:1; /* Process Address Space ID */ 364 unsigned int pri_enabled:1; /* Page Request Interface */ 365 unsigned int is_managed:1; 366 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 367 unsigned int state_saved:1; 368 unsigned int is_physfn:1; 369 unsigned int is_virtfn:1; 370 unsigned int reset_fn:1; 371 unsigned int is_hotplug_bridge:1; 372 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 373 unsigned int __aer_firmware_first_valid:1; 374 unsigned int __aer_firmware_first:1; 375 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 376 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 377 unsigned int irq_managed:1; 378 unsigned int has_secondary_link:1; 379 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 380 unsigned int is_probed:1; /* device probing in progress */ 381 pci_dev_flags_t dev_flags; 382 atomic_t enable_cnt; /* pci_enable_device has been called */ 383 384 u32 saved_config_space[16]; /* config space saved at suspend time */ 385 struct hlist_head saved_cap_space; 386 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 387 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 388 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 389 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 390 391 #ifdef CONFIG_PCIE_PTM 392 unsigned int ptm_root:1; 393 unsigned int ptm_enabled:1; 394 u8 ptm_granularity; 395 #endif 396 #ifdef CONFIG_PCI_MSI 397 const struct attribute_group **msi_irq_groups; 398 #endif 399 struct pci_vpd *vpd; 400 #ifdef CONFIG_PCI_ATS 401 union { 402 struct pci_sriov *sriov; /* SR-IOV capability related */ 403 struct pci_dev *physfn; /* the PF this VF is associated with */ 404 }; 405 u16 ats_cap; /* ATS Capability offset */ 406 u8 ats_stu; /* ATS Smallest Translation Unit */ 407 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 408 #endif 409 #ifdef CONFIG_PCI_PRI 410 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 411 #endif 412 #ifdef CONFIG_PCI_PASID 413 u16 pasid_features; 414 #endif 415 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 416 size_t romlen; /* Length of ROM if it's not from the BAR */ 417 char *driver_override; /* Driver name to force a match */ 418 419 unsigned long priv_flags; /* Private flags for the pci driver */ 420 }; 421 422 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 423 { 424 #ifdef CONFIG_PCI_IOV 425 if (dev->is_virtfn) 426 dev = dev->physfn; 427 #endif 428 return dev; 429 } 430 431 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 432 433 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 434 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 435 436 static inline int pci_channel_offline(struct pci_dev *pdev) 437 { 438 return (pdev->error_state != pci_channel_io_normal); 439 } 440 441 struct pci_host_bridge { 442 struct device dev; 443 struct pci_bus *bus; /* root bus */ 444 struct pci_ops *ops; 445 void *sysdata; 446 int busnr; 447 struct list_head windows; /* resource_entry */ 448 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */ 449 int (*map_irq)(const struct pci_dev *, u8, u8); 450 void (*release_fn)(struct pci_host_bridge *); 451 void *release_data; 452 struct msi_controller *msi; 453 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 454 /* Resource alignment requirements */ 455 resource_size_t (*align_resource)(struct pci_dev *dev, 456 const struct resource *res, 457 resource_size_t start, 458 resource_size_t size, 459 resource_size_t align); 460 unsigned long private[0] ____cacheline_aligned; 461 }; 462 463 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 464 465 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 466 { 467 return (void *)bridge->private; 468 } 469 470 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 471 { 472 return container_of(priv, struct pci_host_bridge, private); 473 } 474 475 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 476 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 477 size_t priv); 478 void pci_free_host_bridge(struct pci_host_bridge *bridge); 479 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 480 481 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 482 void (*release_fn)(struct pci_host_bridge *), 483 void *release_data); 484 485 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 486 487 /* 488 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 489 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 490 * buses below host bridges or subtractive decode bridges) go in the list. 491 * Use pci_bus_for_each_resource() to iterate through all the resources. 492 */ 493 494 /* 495 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 496 * and there's no way to program the bridge with the details of the window. 497 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 498 * decode bit set, because they are explicit and can be programmed with _SRS. 499 */ 500 #define PCI_SUBTRACTIVE_DECODE 0x1 501 502 struct pci_bus_resource { 503 struct list_head list; 504 struct resource *res; 505 unsigned int flags; 506 }; 507 508 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 509 510 struct pci_bus { 511 struct list_head node; /* node in list of buses */ 512 struct pci_bus *parent; /* parent bus this bridge is on */ 513 struct list_head children; /* list of child buses */ 514 struct list_head devices; /* list of devices on this bus */ 515 struct pci_dev *self; /* bridge device as seen by parent */ 516 struct list_head slots; /* list of slots on this bus; 517 protected by pci_slot_mutex */ 518 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 519 struct list_head resources; /* address space routed to this bus */ 520 struct resource busn_res; /* bus numbers routed to this bus */ 521 522 struct pci_ops *ops; /* configuration access functions */ 523 struct msi_controller *msi; /* MSI controller */ 524 void *sysdata; /* hook for sys-specific extension */ 525 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 526 527 unsigned char number; /* bus number */ 528 unsigned char primary; /* number of primary bridge */ 529 unsigned char max_bus_speed; /* enum pci_bus_speed */ 530 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 531 #ifdef CONFIG_PCI_DOMAINS_GENERIC 532 int domain_nr; 533 #endif 534 535 char name[48]; 536 537 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 538 pci_bus_flags_t bus_flags; /* inherited by child buses */ 539 struct device *bridge; 540 struct device dev; 541 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 542 struct bin_attribute *legacy_mem; /* legacy mem */ 543 unsigned int is_added:1; 544 }; 545 546 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 547 548 /* 549 * Returns true if the PCI bus is root (behind host-PCI bridge), 550 * false otherwise 551 * 552 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 553 * This is incorrect because "virtual" buses added for SR-IOV (via 554 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 555 */ 556 static inline bool pci_is_root_bus(struct pci_bus *pbus) 557 { 558 return !(pbus->parent); 559 } 560 561 /** 562 * pci_is_bridge - check if the PCI device is a bridge 563 * @dev: PCI device 564 * 565 * Return true if the PCI device is bridge whether it has subordinate 566 * or not. 567 */ 568 static inline bool pci_is_bridge(struct pci_dev *dev) 569 { 570 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 571 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 572 } 573 574 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 575 { 576 dev = pci_physfn(dev); 577 if (pci_is_root_bus(dev->bus)) 578 return NULL; 579 580 return dev->bus->self; 581 } 582 583 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 584 void pci_put_host_bridge_device(struct device *dev); 585 586 #ifdef CONFIG_PCI_MSI 587 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 588 { 589 return pci_dev->msi_enabled || pci_dev->msix_enabled; 590 } 591 #else 592 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 593 #endif 594 595 /* 596 * Error values that may be returned by PCI functions. 597 */ 598 #define PCIBIOS_SUCCESSFUL 0x00 599 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 600 #define PCIBIOS_BAD_VENDOR_ID 0x83 601 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 602 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 603 #define PCIBIOS_SET_FAILED 0x88 604 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 605 606 /* 607 * Translate above to generic errno for passing back through non-PCI code. 608 */ 609 static inline int pcibios_err_to_errno(int err) 610 { 611 if (err <= PCIBIOS_SUCCESSFUL) 612 return err; /* Assume already errno */ 613 614 switch (err) { 615 case PCIBIOS_FUNC_NOT_SUPPORTED: 616 return -ENOENT; 617 case PCIBIOS_BAD_VENDOR_ID: 618 return -ENOTTY; 619 case PCIBIOS_DEVICE_NOT_FOUND: 620 return -ENODEV; 621 case PCIBIOS_BAD_REGISTER_NUMBER: 622 return -EFAULT; 623 case PCIBIOS_SET_FAILED: 624 return -EIO; 625 case PCIBIOS_BUFFER_TOO_SMALL: 626 return -ENOSPC; 627 } 628 629 return -ERANGE; 630 } 631 632 /* Low-level architecture-dependent routines */ 633 634 struct pci_ops { 635 int (*add_bus)(struct pci_bus *bus); 636 void (*remove_bus)(struct pci_bus *bus); 637 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 638 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 639 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 640 }; 641 642 /* 643 * ACPI needs to be able to access PCI config space before we've done a 644 * PCI bus scan and created pci_bus structures. 645 */ 646 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 647 int reg, int len, u32 *val); 648 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 649 int reg, int len, u32 val); 650 651 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 652 typedef u64 pci_bus_addr_t; 653 #else 654 typedef u32 pci_bus_addr_t; 655 #endif 656 657 struct pci_bus_region { 658 pci_bus_addr_t start; 659 pci_bus_addr_t end; 660 }; 661 662 struct pci_dynids { 663 spinlock_t lock; /* protects list, index */ 664 struct list_head list; /* for IDs added at runtime */ 665 }; 666 667 668 /* 669 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 670 * a set of callbacks in struct pci_error_handlers, that device driver 671 * will be notified of PCI bus errors, and will be driven to recovery 672 * when an error occurs. 673 */ 674 675 typedef unsigned int __bitwise pci_ers_result_t; 676 677 enum pci_ers_result { 678 /* no result/none/not supported in device driver */ 679 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 680 681 /* Device driver can recover without slot reset */ 682 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 683 684 /* Device driver wants slot to be reset. */ 685 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 686 687 /* Device has completely failed, is unrecoverable */ 688 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 689 690 /* Device driver is fully recovered and operational */ 691 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 692 693 /* No AER capabilities registered for the driver */ 694 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 695 }; 696 697 /* PCI bus error event callbacks */ 698 struct pci_error_handlers { 699 /* PCI bus error detected on this device */ 700 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 701 enum pci_channel_state error); 702 703 /* MMIO has been re-enabled, but not DMA */ 704 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 705 706 /* PCI slot has been reset */ 707 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 708 709 /* PCI function reset prepare or completed */ 710 void (*reset_prepare)(struct pci_dev *dev); 711 void (*reset_done)(struct pci_dev *dev); 712 713 /* Device driver may resume normal operations */ 714 void (*resume)(struct pci_dev *dev); 715 }; 716 717 718 struct module; 719 struct pci_driver { 720 struct list_head node; 721 const char *name; 722 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 723 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 724 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 725 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 726 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 727 int (*resume_early) (struct pci_dev *dev); 728 int (*resume) (struct pci_dev *dev); /* Device woken up */ 729 void (*shutdown) (struct pci_dev *dev); 730 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 731 const struct pci_error_handlers *err_handler; 732 struct device_driver driver; 733 struct pci_dynids dynids; 734 }; 735 736 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 737 738 /** 739 * PCI_DEVICE - macro used to describe a specific pci device 740 * @vend: the 16 bit PCI Vendor ID 741 * @dev: the 16 bit PCI Device ID 742 * 743 * This macro is used to create a struct pci_device_id that matches a 744 * specific device. The subvendor and subdevice fields will be set to 745 * PCI_ANY_ID. 746 */ 747 #define PCI_DEVICE(vend,dev) \ 748 .vendor = (vend), .device = (dev), \ 749 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 750 751 /** 752 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 753 * @vend: the 16 bit PCI Vendor ID 754 * @dev: the 16 bit PCI Device ID 755 * @subvend: the 16 bit PCI Subvendor ID 756 * @subdev: the 16 bit PCI Subdevice ID 757 * 758 * This macro is used to create a struct pci_device_id that matches a 759 * specific device with subsystem information. 760 */ 761 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 762 .vendor = (vend), .device = (dev), \ 763 .subvendor = (subvend), .subdevice = (subdev) 764 765 /** 766 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 767 * @dev_class: the class, subclass, prog-if triple for this device 768 * @dev_class_mask: the class mask for this device 769 * 770 * This macro is used to create a struct pci_device_id that matches a 771 * specific PCI class. The vendor, device, subvendor, and subdevice 772 * fields will be set to PCI_ANY_ID. 773 */ 774 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 775 .class = (dev_class), .class_mask = (dev_class_mask), \ 776 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 777 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 778 779 /** 780 * PCI_VDEVICE - macro used to describe a specific pci device in short form 781 * @vend: the vendor name 782 * @dev: the 16 bit PCI Device ID 783 * 784 * This macro is used to create a struct pci_device_id that matches a 785 * specific PCI device. The subvendor, and subdevice fields will be set 786 * to PCI_ANY_ID. The macro allows the next field to follow as the device 787 * private data. 788 */ 789 790 #define PCI_VDEVICE(vend, dev) \ 791 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 792 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 793 794 enum { 795 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ 796 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ 797 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ 798 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ 799 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ 800 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 801 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ 802 }; 803 804 /* these external functions are only available when PCI support is enabled */ 805 #ifdef CONFIG_PCI 806 807 extern unsigned int pci_flags; 808 809 static inline void pci_set_flags(int flags) { pci_flags = flags; } 810 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 811 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 812 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 813 814 void pcie_bus_configure_settings(struct pci_bus *bus); 815 816 enum pcie_bus_config_types { 817 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 818 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 819 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 820 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 821 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 822 }; 823 824 extern enum pcie_bus_config_types pcie_bus_config; 825 826 extern struct bus_type pci_bus_type; 827 828 /* Do NOT directly access these two variables, unless you are arch-specific PCI 829 * code, or PCI core code. */ 830 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 831 /* Some device drivers need know if PCI is initiated */ 832 int no_pci_devices(void); 833 834 void pcibios_resource_survey_bus(struct pci_bus *bus); 835 void pcibios_bus_add_device(struct pci_dev *pdev); 836 void pcibios_add_bus(struct pci_bus *bus); 837 void pcibios_remove_bus(struct pci_bus *bus); 838 void pcibios_fixup_bus(struct pci_bus *); 839 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 840 /* Architecture-specific versions may override this (weak) */ 841 char *pcibios_setup(char *str); 842 843 /* Used only when drivers/pci/setup.c is used */ 844 resource_size_t pcibios_align_resource(void *, const struct resource *, 845 resource_size_t, 846 resource_size_t); 847 void pcibios_update_irq(struct pci_dev *, int irq); 848 849 /* Weak but can be overriden by arch */ 850 void pci_fixup_cardbus(struct pci_bus *); 851 852 /* Generic PCI functions used internally */ 853 854 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 855 struct resource *res); 856 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 857 struct pci_bus_region *region); 858 void pcibios_scan_specific_bus(int busn); 859 struct pci_bus *pci_find_bus(int domain, int busnr); 860 void pci_bus_add_devices(const struct pci_bus *bus); 861 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 862 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 863 struct pci_ops *ops, void *sysdata, 864 struct list_head *resources); 865 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 866 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 867 void pci_bus_release_busn_res(struct pci_bus *b); 868 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 869 struct pci_ops *ops, void *sysdata, 870 struct list_head *resources); 871 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 872 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 873 int busnr); 874 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 875 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 876 const char *name, 877 struct hotplug_slot *hotplug); 878 void pci_destroy_slot(struct pci_slot *slot); 879 #ifdef CONFIG_SYSFS 880 void pci_dev_assign_slot(struct pci_dev *dev); 881 #else 882 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 883 #endif 884 int pci_scan_slot(struct pci_bus *bus, int devfn); 885 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 886 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 887 unsigned int pci_scan_child_bus(struct pci_bus *bus); 888 void pci_bus_add_device(struct pci_dev *dev); 889 void pci_read_bridge_bases(struct pci_bus *child); 890 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 891 struct resource *res); 892 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 893 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 894 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 895 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 896 struct pci_dev *pci_dev_get(struct pci_dev *dev); 897 void pci_dev_put(struct pci_dev *dev); 898 void pci_remove_bus(struct pci_bus *b); 899 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 900 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 901 void pci_stop_root_bus(struct pci_bus *bus); 902 void pci_remove_root_bus(struct pci_bus *bus); 903 void pci_setup_cardbus(struct pci_bus *bus); 904 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 905 void pci_sort_breadthfirst(void); 906 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 907 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 908 909 /* Generic PCI functions exported to card drivers */ 910 911 enum pci_lost_interrupt_reason { 912 PCI_LOST_IRQ_NO_INFORMATION = 0, 913 PCI_LOST_IRQ_DISABLE_MSI, 914 PCI_LOST_IRQ_DISABLE_MSIX, 915 PCI_LOST_IRQ_DISABLE_ACPI, 916 }; 917 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 918 int pci_find_capability(struct pci_dev *dev, int cap); 919 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 920 int pci_find_ext_capability(struct pci_dev *dev, int cap); 921 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 922 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 923 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 924 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 925 926 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 927 struct pci_dev *from); 928 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 929 unsigned int ss_vendor, unsigned int ss_device, 930 struct pci_dev *from); 931 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 932 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 933 unsigned int devfn); 934 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 935 unsigned int devfn) 936 { 937 return pci_get_domain_bus_and_slot(0, bus, devfn); 938 } 939 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 940 int pci_dev_present(const struct pci_device_id *ids); 941 942 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 943 int where, u8 *val); 944 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 945 int where, u16 *val); 946 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 947 int where, u32 *val); 948 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 949 int where, u8 val); 950 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 951 int where, u16 val); 952 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 953 int where, u32 val); 954 955 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 956 int where, int size, u32 *val); 957 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 958 int where, int size, u32 val); 959 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 960 int where, int size, u32 *val); 961 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 962 int where, int size, u32 val); 963 964 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 965 966 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 967 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 968 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 969 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 970 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 971 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 972 973 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 974 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 975 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 976 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 977 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 978 u16 clear, u16 set); 979 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 980 u32 clear, u32 set); 981 982 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 983 u16 set) 984 { 985 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 986 } 987 988 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 989 u32 set) 990 { 991 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 992 } 993 994 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 995 u16 clear) 996 { 997 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 998 } 999 1000 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1001 u32 clear) 1002 { 1003 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1004 } 1005 1006 /* user-space driven config access */ 1007 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1008 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1009 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1010 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1011 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1012 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1013 1014 int __must_check pci_enable_device(struct pci_dev *dev); 1015 int __must_check pci_enable_device_io(struct pci_dev *dev); 1016 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1017 int __must_check pci_reenable_device(struct pci_dev *); 1018 int __must_check pcim_enable_device(struct pci_dev *pdev); 1019 void pcim_pin_device(struct pci_dev *pdev); 1020 1021 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1022 { 1023 /* 1024 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1025 * writable and no quirk has marked the feature broken. 1026 */ 1027 return !pdev->broken_intx_masking; 1028 } 1029 1030 static inline int pci_is_enabled(struct pci_dev *pdev) 1031 { 1032 return (atomic_read(&pdev->enable_cnt) > 0); 1033 } 1034 1035 static inline int pci_is_managed(struct pci_dev *pdev) 1036 { 1037 return pdev->is_managed; 1038 } 1039 1040 void pci_disable_device(struct pci_dev *dev); 1041 1042 extern unsigned int pcibios_max_latency; 1043 void pci_set_master(struct pci_dev *dev); 1044 void pci_clear_master(struct pci_dev *dev); 1045 1046 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1047 int pci_set_cacheline_size(struct pci_dev *dev); 1048 #define HAVE_PCI_SET_MWI 1049 int __must_check pci_set_mwi(struct pci_dev *dev); 1050 int pci_try_set_mwi(struct pci_dev *dev); 1051 void pci_clear_mwi(struct pci_dev *dev); 1052 void pci_intx(struct pci_dev *dev, int enable); 1053 bool pci_check_and_mask_intx(struct pci_dev *dev); 1054 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1055 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1056 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1057 int pcix_get_max_mmrbc(struct pci_dev *dev); 1058 int pcix_get_mmrbc(struct pci_dev *dev); 1059 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1060 int pcie_get_readrq(struct pci_dev *dev); 1061 int pcie_set_readrq(struct pci_dev *dev, int rq); 1062 int pcie_get_mps(struct pci_dev *dev); 1063 int pcie_set_mps(struct pci_dev *dev, int mps); 1064 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1065 enum pcie_link_width *width); 1066 void pcie_flr(struct pci_dev *dev); 1067 int __pci_reset_function(struct pci_dev *dev); 1068 int __pci_reset_function_locked(struct pci_dev *dev); 1069 int pci_reset_function(struct pci_dev *dev); 1070 int pci_reset_function_locked(struct pci_dev *dev); 1071 int pci_try_reset_function(struct pci_dev *dev); 1072 int pci_probe_reset_slot(struct pci_slot *slot); 1073 int pci_reset_slot(struct pci_slot *slot); 1074 int pci_try_reset_slot(struct pci_slot *slot); 1075 int pci_probe_reset_bus(struct pci_bus *bus); 1076 int pci_reset_bus(struct pci_bus *bus); 1077 int pci_try_reset_bus(struct pci_bus *bus); 1078 void pci_reset_secondary_bus(struct pci_dev *dev); 1079 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1080 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1081 void pci_update_resource(struct pci_dev *dev, int resno); 1082 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1083 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1084 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1085 bool pci_device_is_present(struct pci_dev *pdev); 1086 void pci_ignore_hotplug(struct pci_dev *dev); 1087 1088 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1089 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1090 const char *fmt, ...); 1091 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1092 1093 /* ROM control related routines */ 1094 int pci_enable_rom(struct pci_dev *pdev); 1095 void pci_disable_rom(struct pci_dev *pdev); 1096 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1097 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1098 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1099 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1100 1101 /* Power management related routines */ 1102 int pci_save_state(struct pci_dev *dev); 1103 void pci_restore_state(struct pci_dev *dev); 1104 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1105 int pci_load_saved_state(struct pci_dev *dev, 1106 struct pci_saved_state *state); 1107 int pci_load_and_free_saved_state(struct pci_dev *dev, 1108 struct pci_saved_state **state); 1109 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1110 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1111 u16 cap); 1112 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1113 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1114 u16 cap, unsigned int size); 1115 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1116 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1117 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1118 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1119 void pci_pme_active(struct pci_dev *dev, bool enable); 1120 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1121 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1122 int pci_prepare_to_sleep(struct pci_dev *dev); 1123 int pci_back_from_sleep(struct pci_dev *dev); 1124 bool pci_dev_run_wake(struct pci_dev *dev); 1125 bool pci_check_pme_status(struct pci_dev *dev); 1126 void pci_pme_wakeup_bus(struct pci_bus *bus); 1127 void pci_d3cold_enable(struct pci_dev *dev); 1128 void pci_d3cold_disable(struct pci_dev *dev); 1129 1130 /* PCI Virtual Channel */ 1131 int pci_save_vc_state(struct pci_dev *dev); 1132 void pci_restore_vc_state(struct pci_dev *dev); 1133 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1134 1135 /* For use by arch with custom probe code */ 1136 void set_pcie_port_type(struct pci_dev *pdev); 1137 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1138 1139 /* Functions for PCI Hotplug drivers to use */ 1140 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1141 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1142 unsigned int pci_rescan_bus(struct pci_bus *bus); 1143 void pci_lock_rescan_remove(void); 1144 void pci_unlock_rescan_remove(void); 1145 1146 /* Vital product data routines */ 1147 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1148 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1149 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1150 1151 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1152 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1153 void pci_bus_assign_resources(const struct pci_bus *bus); 1154 void pci_bus_claim_resources(struct pci_bus *bus); 1155 void pci_bus_size_bridges(struct pci_bus *bus); 1156 int pci_claim_resource(struct pci_dev *, int); 1157 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1158 void pci_assign_unassigned_resources(void); 1159 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1160 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1161 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1162 void pdev_enable_device(struct pci_dev *); 1163 int pci_enable_resources(struct pci_dev *, int mask); 1164 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1165 int (*)(const struct pci_dev *, u8, u8)); 1166 void pci_assign_irq(struct pci_dev *dev); 1167 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1168 #define HAVE_PCI_REQ_REGIONS 2 1169 int __must_check pci_request_regions(struct pci_dev *, const char *); 1170 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1171 void pci_release_regions(struct pci_dev *); 1172 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1173 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1174 void pci_release_region(struct pci_dev *, int); 1175 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1176 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1177 void pci_release_selected_regions(struct pci_dev *, int); 1178 1179 /* drivers/pci/bus.c */ 1180 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1181 void pci_bus_put(struct pci_bus *bus); 1182 void pci_add_resource(struct list_head *resources, struct resource *res); 1183 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1184 resource_size_t offset); 1185 void pci_free_resource_list(struct list_head *resources); 1186 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1187 unsigned int flags); 1188 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1189 void pci_bus_remove_resources(struct pci_bus *bus); 1190 int devm_request_pci_bus_resources(struct device *dev, 1191 struct list_head *resources); 1192 1193 #define pci_bus_for_each_resource(bus, res, i) \ 1194 for (i = 0; \ 1195 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1196 i++) 1197 1198 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1199 struct resource *res, resource_size_t size, 1200 resource_size_t align, resource_size_t min, 1201 unsigned long type_mask, 1202 resource_size_t (*alignf)(void *, 1203 const struct resource *, 1204 resource_size_t, 1205 resource_size_t), 1206 void *alignf_data); 1207 1208 1209 int pci_register_io_range(phys_addr_t addr, resource_size_t size); 1210 unsigned long pci_address_to_pio(phys_addr_t addr); 1211 phys_addr_t pci_pio_to_address(unsigned long pio); 1212 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1213 void pci_unmap_iospace(struct resource *res); 1214 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1215 resource_size_t offset, 1216 resource_size_t size); 1217 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1218 struct resource *res); 1219 1220 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1221 { 1222 struct pci_bus_region region; 1223 1224 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1225 return region.start; 1226 } 1227 1228 /* Proper probing supporting hot-pluggable devices */ 1229 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1230 const char *mod_name); 1231 1232 /* 1233 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1234 */ 1235 #define pci_register_driver(driver) \ 1236 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1237 1238 void pci_unregister_driver(struct pci_driver *dev); 1239 1240 /** 1241 * module_pci_driver() - Helper macro for registering a PCI driver 1242 * @__pci_driver: pci_driver struct 1243 * 1244 * Helper macro for PCI drivers which do not do anything special in module 1245 * init/exit. This eliminates a lot of boilerplate. Each module may only 1246 * use this macro once, and calling it replaces module_init() and module_exit() 1247 */ 1248 #define module_pci_driver(__pci_driver) \ 1249 module_driver(__pci_driver, pci_register_driver, \ 1250 pci_unregister_driver) 1251 1252 /** 1253 * builtin_pci_driver() - Helper macro for registering a PCI driver 1254 * @__pci_driver: pci_driver struct 1255 * 1256 * Helper macro for PCI drivers which do not do anything special in their 1257 * init code. This eliminates a lot of boilerplate. Each driver may only 1258 * use this macro once, and calling it replaces device_initcall(...) 1259 */ 1260 #define builtin_pci_driver(__pci_driver) \ 1261 builtin_driver(__pci_driver, pci_register_driver) 1262 1263 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1264 int pci_add_dynid(struct pci_driver *drv, 1265 unsigned int vendor, unsigned int device, 1266 unsigned int subvendor, unsigned int subdevice, 1267 unsigned int class, unsigned int class_mask, 1268 unsigned long driver_data); 1269 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1270 struct pci_dev *dev); 1271 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1272 int pass); 1273 1274 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1275 void *userdata); 1276 int pci_cfg_space_size(struct pci_dev *dev); 1277 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1278 void pci_setup_bridge(struct pci_bus *bus); 1279 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1280 unsigned long type); 1281 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1282 1283 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1284 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1285 1286 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1287 unsigned int command_bits, u32 flags); 1288 1289 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ 1290 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ 1291 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ 1292 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ 1293 #define PCI_IRQ_ALL_TYPES \ 1294 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1295 1296 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1297 1298 #include <linux/pci-dma.h> 1299 #include <linux/dmapool.h> 1300 1301 #define pci_pool dma_pool 1302 #define pci_pool_create(name, pdev, size, align, allocation) \ 1303 dma_pool_create(name, &pdev->dev, size, align, allocation) 1304 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1305 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1306 #define pci_pool_zalloc(pool, flags, handle) \ 1307 dma_pool_zalloc(pool, flags, handle) 1308 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1309 1310 struct msix_entry { 1311 u32 vector; /* kernel uses to write allocated vector */ 1312 u16 entry; /* driver uses to specify entry, OS writes */ 1313 }; 1314 1315 #ifdef CONFIG_PCI_MSI 1316 int pci_msi_vec_count(struct pci_dev *dev); 1317 void pci_disable_msi(struct pci_dev *dev); 1318 int pci_msix_vec_count(struct pci_dev *dev); 1319 void pci_disable_msix(struct pci_dev *dev); 1320 void pci_restore_msi_state(struct pci_dev *dev); 1321 int pci_msi_enabled(void); 1322 int pci_enable_msi(struct pci_dev *dev); 1323 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1324 int minvec, int maxvec); 1325 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1326 struct msix_entry *entries, int nvec) 1327 { 1328 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1329 if (rc < 0) 1330 return rc; 1331 return 0; 1332 } 1333 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1334 unsigned int max_vecs, unsigned int flags, 1335 const struct irq_affinity *affd); 1336 1337 void pci_free_irq_vectors(struct pci_dev *dev); 1338 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1339 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1340 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1341 1342 #else 1343 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1344 static inline void pci_disable_msi(struct pci_dev *dev) { } 1345 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1346 static inline void pci_disable_msix(struct pci_dev *dev) { } 1347 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1348 static inline int pci_msi_enabled(void) { return 0; } 1349 static inline int pci_enable_msi(struct pci_dev *dev) 1350 { return -ENOSYS; } 1351 static inline int pci_enable_msix_range(struct pci_dev *dev, 1352 struct msix_entry *entries, int minvec, int maxvec) 1353 { return -ENOSYS; } 1354 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1355 struct msix_entry *entries, int nvec) 1356 { return -ENOSYS; } 1357 1358 static inline int 1359 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1360 unsigned int max_vecs, unsigned int flags, 1361 const struct irq_affinity *aff_desc) 1362 { 1363 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1364 return 1; 1365 return -ENOSPC; 1366 } 1367 1368 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1369 { 1370 } 1371 1372 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1373 { 1374 if (WARN_ON_ONCE(nr > 0)) 1375 return -EINVAL; 1376 return dev->irq; 1377 } 1378 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1379 int vec) 1380 { 1381 return cpu_possible_mask; 1382 } 1383 1384 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1385 { 1386 return first_online_node; 1387 } 1388 #endif 1389 1390 static inline int 1391 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1392 unsigned int max_vecs, unsigned int flags) 1393 { 1394 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1395 NULL); 1396 } 1397 1398 #ifdef CONFIG_PCIEPORTBUS 1399 extern bool pcie_ports_disabled; 1400 extern bool pcie_ports_auto; 1401 #else 1402 #define pcie_ports_disabled true 1403 #define pcie_ports_auto false 1404 #endif 1405 1406 #ifdef CONFIG_PCIEASPM 1407 bool pcie_aspm_support_enabled(void); 1408 #else 1409 static inline bool pcie_aspm_support_enabled(void) { return false; } 1410 #endif 1411 1412 #ifdef CONFIG_PCIEAER 1413 void pci_no_aer(void); 1414 bool pci_aer_available(void); 1415 int pci_aer_init(struct pci_dev *dev); 1416 #else 1417 static inline void pci_no_aer(void) { } 1418 static inline bool pci_aer_available(void) { return false; } 1419 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } 1420 #endif 1421 1422 #ifdef CONFIG_PCIE_ECRC 1423 void pcie_set_ecrc_checking(struct pci_dev *dev); 1424 void pcie_ecrc_get_policy(char *str); 1425 #else 1426 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1427 static inline void pcie_ecrc_get_policy(char *str) { } 1428 #endif 1429 1430 #ifdef CONFIG_HT_IRQ 1431 /* The functions a driver should call */ 1432 int ht_create_irq(struct pci_dev *dev, int idx); 1433 void ht_destroy_irq(unsigned int irq); 1434 #endif /* CONFIG_HT_IRQ */ 1435 1436 #ifdef CONFIG_PCI_ATS 1437 /* Address Translation Service */ 1438 void pci_ats_init(struct pci_dev *dev); 1439 int pci_enable_ats(struct pci_dev *dev, int ps); 1440 void pci_disable_ats(struct pci_dev *dev); 1441 int pci_ats_queue_depth(struct pci_dev *dev); 1442 #else 1443 static inline void pci_ats_init(struct pci_dev *d) { } 1444 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1445 static inline void pci_disable_ats(struct pci_dev *d) { } 1446 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1447 #endif 1448 1449 #ifdef CONFIG_PCIE_PTM 1450 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1451 #else 1452 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1453 { return -EINVAL; } 1454 #endif 1455 1456 void pci_cfg_access_lock(struct pci_dev *dev); 1457 bool pci_cfg_access_trylock(struct pci_dev *dev); 1458 void pci_cfg_access_unlock(struct pci_dev *dev); 1459 1460 /* 1461 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1462 * a PCI domain is defined to be a set of PCI buses which share 1463 * configuration space. 1464 */ 1465 #ifdef CONFIG_PCI_DOMAINS 1466 extern int pci_domains_supported; 1467 int pci_get_new_domain_nr(void); 1468 #else 1469 enum { pci_domains_supported = 0 }; 1470 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1471 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1472 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1473 #endif /* CONFIG_PCI_DOMAINS */ 1474 1475 /* 1476 * Generic implementation for PCI domain support. If your 1477 * architecture does not need custom management of PCI 1478 * domains then this implementation will be used 1479 */ 1480 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1481 static inline int pci_domain_nr(struct pci_bus *bus) 1482 { 1483 return bus->domain_nr; 1484 } 1485 #ifdef CONFIG_ACPI 1486 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1487 #else 1488 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1489 { return 0; } 1490 #endif 1491 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1492 #endif 1493 1494 /* some architectures require additional setup to direct VGA traffic */ 1495 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1496 unsigned int command_bits, u32 flags); 1497 void pci_register_set_vga_state(arch_set_vga_state_t func); 1498 1499 static inline int 1500 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1501 { 1502 return pci_request_selected_regions(pdev, 1503 pci_select_bars(pdev, IORESOURCE_IO), name); 1504 } 1505 1506 static inline void 1507 pci_release_io_regions(struct pci_dev *pdev) 1508 { 1509 return pci_release_selected_regions(pdev, 1510 pci_select_bars(pdev, IORESOURCE_IO)); 1511 } 1512 1513 static inline int 1514 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1515 { 1516 return pci_request_selected_regions(pdev, 1517 pci_select_bars(pdev, IORESOURCE_MEM), name); 1518 } 1519 1520 static inline void 1521 pci_release_mem_regions(struct pci_dev *pdev) 1522 { 1523 return pci_release_selected_regions(pdev, 1524 pci_select_bars(pdev, IORESOURCE_MEM)); 1525 } 1526 1527 #else /* CONFIG_PCI is not enabled */ 1528 1529 static inline void pci_set_flags(int flags) { } 1530 static inline void pci_add_flags(int flags) { } 1531 static inline void pci_clear_flags(int flags) { } 1532 static inline int pci_has_flag(int flag) { return 0; } 1533 1534 /* 1535 * If the system does not have PCI, clearly these return errors. Define 1536 * these as simple inline functions to avoid hair in drivers. 1537 */ 1538 1539 #define _PCI_NOP(o, s, t) \ 1540 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1541 int where, t val) \ 1542 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1543 1544 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1545 _PCI_NOP(o, word, u16 x) \ 1546 _PCI_NOP(o, dword, u32 x) 1547 _PCI_NOP_ALL(read, *) 1548 _PCI_NOP_ALL(write,) 1549 1550 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1551 unsigned int device, 1552 struct pci_dev *from) 1553 { return NULL; } 1554 1555 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1556 unsigned int device, 1557 unsigned int ss_vendor, 1558 unsigned int ss_device, 1559 struct pci_dev *from) 1560 { return NULL; } 1561 1562 static inline struct pci_dev *pci_get_class(unsigned int class, 1563 struct pci_dev *from) 1564 { return NULL; } 1565 1566 #define pci_dev_present(ids) (0) 1567 #define no_pci_devices() (1) 1568 #define pci_dev_put(dev) do { } while (0) 1569 1570 static inline void pci_set_master(struct pci_dev *dev) { } 1571 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1572 static inline void pci_disable_device(struct pci_dev *dev) { } 1573 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1574 { return -EBUSY; } 1575 static inline int __pci_register_driver(struct pci_driver *drv, 1576 struct module *owner) 1577 { return 0; } 1578 static inline int pci_register_driver(struct pci_driver *drv) 1579 { return 0; } 1580 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1581 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1582 { return 0; } 1583 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1584 int cap) 1585 { return 0; } 1586 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1587 { return 0; } 1588 1589 /* Power management related routines */ 1590 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1591 static inline void pci_restore_state(struct pci_dev *dev) { } 1592 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1593 { return 0; } 1594 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1595 { return 0; } 1596 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1597 pm_message_t state) 1598 { return PCI_D0; } 1599 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1600 int enable) 1601 { return 0; } 1602 1603 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1604 struct resource *res) 1605 { return NULL; } 1606 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1607 { return -EIO; } 1608 static inline void pci_release_regions(struct pci_dev *dev) { } 1609 1610 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1611 1612 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1613 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1614 { return 0; } 1615 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1616 1617 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1618 { return NULL; } 1619 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1620 unsigned int devfn) 1621 { return NULL; } 1622 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1623 unsigned int devfn) 1624 { return NULL; } 1625 1626 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1627 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1628 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1629 1630 #define dev_is_pci(d) (false) 1631 #define dev_is_pf(d) (false) 1632 #endif /* CONFIG_PCI */ 1633 1634 /* Include architecture-dependent settings and functions */ 1635 1636 #include <asm/pci.h> 1637 1638 /* These two functions provide almost identical functionality. Depennding 1639 * on the architecture, one will be implemented as a wrapper around the 1640 * other (in drivers/pci/mmap.c). 1641 * 1642 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1643 * is expected to be an offset within that region. 1644 * 1645 * pci_mmap_page_range() is the legacy architecture-specific interface, 1646 * which accepts a "user visible" resource address converted by 1647 * pci_resource_to_user(), as used in the legacy mmap() interface in 1648 * /proc/bus/pci/. 1649 */ 1650 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1651 struct vm_area_struct *vma, 1652 enum pci_mmap_state mmap_state, int write_combine); 1653 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1654 struct vm_area_struct *vma, 1655 enum pci_mmap_state mmap_state, int write_combine); 1656 1657 #ifndef arch_can_pci_mmap_wc 1658 #define arch_can_pci_mmap_wc() 0 1659 #endif 1660 1661 #ifndef arch_can_pci_mmap_io 1662 #define arch_can_pci_mmap_io() 0 1663 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1664 #else 1665 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1666 #endif 1667 1668 #ifndef pci_root_bus_fwnode 1669 #define pci_root_bus_fwnode(bus) NULL 1670 #endif 1671 1672 /* these helpers provide future and backwards compatibility 1673 * for accessing popular PCI BAR info */ 1674 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1675 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1676 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1677 #define pci_resource_len(dev,bar) \ 1678 ((pci_resource_start((dev), (bar)) == 0 && \ 1679 pci_resource_end((dev), (bar)) == \ 1680 pci_resource_start((dev), (bar))) ? 0 : \ 1681 \ 1682 (pci_resource_end((dev), (bar)) - \ 1683 pci_resource_start((dev), (bar)) + 1)) 1684 1685 /* Similar to the helpers above, these manipulate per-pci_dev 1686 * driver-specific data. They are really just a wrapper around 1687 * the generic device structure functions of these calls. 1688 */ 1689 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1690 { 1691 return dev_get_drvdata(&pdev->dev); 1692 } 1693 1694 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1695 { 1696 dev_set_drvdata(&pdev->dev, data); 1697 } 1698 1699 /* If you want to know what to call your pci_dev, ask this function. 1700 * Again, it's a wrapper around the generic device. 1701 */ 1702 static inline const char *pci_name(const struct pci_dev *pdev) 1703 { 1704 return dev_name(&pdev->dev); 1705 } 1706 1707 1708 /* Some archs don't want to expose struct resource to userland as-is 1709 * in sysfs and /proc 1710 */ 1711 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1712 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1713 const struct resource *rsrc, 1714 resource_size_t *start, resource_size_t *end); 1715 #else 1716 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1717 const struct resource *rsrc, resource_size_t *start, 1718 resource_size_t *end) 1719 { 1720 *start = rsrc->start; 1721 *end = rsrc->end; 1722 } 1723 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1724 1725 1726 /* 1727 * The world is not perfect and supplies us with broken PCI devices. 1728 * For at least a part of these bugs we need a work-around, so both 1729 * generic (drivers/pci/quirks.c) and per-architecture code can define 1730 * fixup hooks to be called for particular buggy devices. 1731 */ 1732 1733 struct pci_fixup { 1734 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1735 u16 device; /* You can use PCI_ANY_ID here of course */ 1736 u32 class; /* You can use PCI_ANY_ID here too */ 1737 unsigned int class_shift; /* should be 0, 8, 16 */ 1738 void (*hook)(struct pci_dev *dev); 1739 }; 1740 1741 enum pci_fixup_pass { 1742 pci_fixup_early, /* Before probing BARs */ 1743 pci_fixup_header, /* After reading configuration header */ 1744 pci_fixup_final, /* Final phase of device fixups */ 1745 pci_fixup_enable, /* pci_enable_device() time */ 1746 pci_fixup_resume, /* pci_device_resume() */ 1747 pci_fixup_suspend, /* pci_device_suspend() */ 1748 pci_fixup_resume_early, /* pci_device_resume_early() */ 1749 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1750 }; 1751 1752 /* Anonymous variables would be nice... */ 1753 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1754 class_shift, hook) \ 1755 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1756 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1757 = { vendor, device, class, class_shift, hook }; 1758 1759 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1760 class_shift, hook) \ 1761 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1762 hook, vendor, device, class, class_shift, hook) 1763 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1764 class_shift, hook) \ 1765 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1766 hook, vendor, device, class, class_shift, hook) 1767 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1768 class_shift, hook) \ 1769 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1770 hook, vendor, device, class, class_shift, hook) 1771 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1772 class_shift, hook) \ 1773 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1774 hook, vendor, device, class, class_shift, hook) 1775 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1776 class_shift, hook) \ 1777 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1778 resume##hook, vendor, device, class, \ 1779 class_shift, hook) 1780 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1781 class_shift, hook) \ 1782 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1783 resume_early##hook, vendor, device, \ 1784 class, class_shift, hook) 1785 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1786 class_shift, hook) \ 1787 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1788 suspend##hook, vendor, device, class, \ 1789 class_shift, hook) 1790 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1791 class_shift, hook) \ 1792 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1793 suspend_late##hook, vendor, device, \ 1794 class, class_shift, hook) 1795 1796 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1797 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1798 hook, vendor, device, PCI_ANY_ID, 0, hook) 1799 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1800 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1801 hook, vendor, device, PCI_ANY_ID, 0, hook) 1802 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1803 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1804 hook, vendor, device, PCI_ANY_ID, 0, hook) 1805 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1806 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1807 hook, vendor, device, PCI_ANY_ID, 0, hook) 1808 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1809 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1810 resume##hook, vendor, device, \ 1811 PCI_ANY_ID, 0, hook) 1812 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1813 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1814 resume_early##hook, vendor, device, \ 1815 PCI_ANY_ID, 0, hook) 1816 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1817 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1818 suspend##hook, vendor, device, \ 1819 PCI_ANY_ID, 0, hook) 1820 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1821 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1822 suspend_late##hook, vendor, device, \ 1823 PCI_ANY_ID, 0, hook) 1824 1825 #ifdef CONFIG_PCI_QUIRKS 1826 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1827 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1828 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1829 #else 1830 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1831 struct pci_dev *dev) { } 1832 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1833 u16 acs_flags) 1834 { 1835 return -ENOTTY; 1836 } 1837 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1838 { 1839 return -ENOTTY; 1840 } 1841 #endif 1842 1843 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1844 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1845 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1846 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1847 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1848 const char *name); 1849 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1850 1851 extern int pci_pci_problems; 1852 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1853 #define PCIPCI_TRITON 2 1854 #define PCIPCI_NATOMA 4 1855 #define PCIPCI_VIAETBF 8 1856 #define PCIPCI_VSFX 16 1857 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1858 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1859 1860 extern unsigned long pci_cardbus_io_size; 1861 extern unsigned long pci_cardbus_mem_size; 1862 extern u8 pci_dfl_cache_line_size; 1863 extern u8 pci_cache_line_size; 1864 1865 extern unsigned long pci_hotplug_io_size; 1866 extern unsigned long pci_hotplug_mem_size; 1867 extern unsigned long pci_hotplug_bus_size; 1868 1869 /* Architecture-specific versions may override these (weak) */ 1870 void pcibios_disable_device(struct pci_dev *dev); 1871 void pcibios_set_master(struct pci_dev *dev); 1872 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1873 enum pcie_reset_state state); 1874 int pcibios_add_device(struct pci_dev *dev); 1875 void pcibios_release_device(struct pci_dev *dev); 1876 void pcibios_penalize_isa_irq(int irq, int active); 1877 int pcibios_alloc_irq(struct pci_dev *dev); 1878 void pcibios_free_irq(struct pci_dev *dev); 1879 1880 #ifdef CONFIG_HIBERNATE_CALLBACKS 1881 extern struct dev_pm_ops pcibios_pm_ops; 1882 #endif 1883 1884 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1885 void __init pci_mmcfg_early_init(void); 1886 void __init pci_mmcfg_late_init(void); 1887 #else 1888 static inline void pci_mmcfg_early_init(void) { } 1889 static inline void pci_mmcfg_late_init(void) { } 1890 #endif 1891 1892 int pci_ext_cfg_avail(void); 1893 1894 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1895 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1896 1897 #ifdef CONFIG_PCI_IOV 1898 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1899 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1900 1901 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1902 void pci_disable_sriov(struct pci_dev *dev); 1903 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset); 1904 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset); 1905 int pci_num_vf(struct pci_dev *dev); 1906 int pci_vfs_assigned(struct pci_dev *dev); 1907 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1908 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1909 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1910 #else 1911 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1912 { 1913 return -ENOSYS; 1914 } 1915 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1916 { 1917 return -ENOSYS; 1918 } 1919 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1920 { return -ENODEV; } 1921 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset) 1922 { 1923 return -ENOSYS; 1924 } 1925 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 1926 int id, int reset) { } 1927 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1928 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1929 static inline int pci_vfs_assigned(struct pci_dev *dev) 1930 { return 0; } 1931 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1932 { return 0; } 1933 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1934 { return 0; } 1935 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1936 { return 0; } 1937 #endif 1938 1939 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1940 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1941 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1942 #endif 1943 1944 /** 1945 * pci_pcie_cap - get the saved PCIe capability offset 1946 * @dev: PCI device 1947 * 1948 * PCIe capability offset is calculated at PCI device initialization 1949 * time and saved in the data structure. This function returns saved 1950 * PCIe capability offset. Using this instead of pci_find_capability() 1951 * reduces unnecessary search in the PCI configuration space. If you 1952 * need to calculate PCIe capability offset from raw device for some 1953 * reasons, please use pci_find_capability() instead. 1954 */ 1955 static inline int pci_pcie_cap(struct pci_dev *dev) 1956 { 1957 return dev->pcie_cap; 1958 } 1959 1960 /** 1961 * pci_is_pcie - check if the PCI device is PCI Express capable 1962 * @dev: PCI device 1963 * 1964 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1965 */ 1966 static inline bool pci_is_pcie(struct pci_dev *dev) 1967 { 1968 return pci_pcie_cap(dev); 1969 } 1970 1971 /** 1972 * pcie_caps_reg - get the PCIe Capabilities Register 1973 * @dev: PCI device 1974 */ 1975 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1976 { 1977 return dev->pcie_flags_reg; 1978 } 1979 1980 /** 1981 * pci_pcie_type - get the PCIe device/port type 1982 * @dev: PCI device 1983 */ 1984 static inline int pci_pcie_type(const struct pci_dev *dev) 1985 { 1986 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1987 } 1988 1989 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 1990 { 1991 while (1) { 1992 if (!pci_is_pcie(dev)) 1993 break; 1994 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 1995 return dev; 1996 if (!dev->bus->self) 1997 break; 1998 dev = dev->bus->self; 1999 } 2000 return NULL; 2001 } 2002 2003 void pci_request_acs(void); 2004 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2005 bool pci_acs_path_enabled(struct pci_dev *start, 2006 struct pci_dev *end, u16 acs_flags); 2007 2008 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2009 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2010 2011 /* Large Resource Data Type Tag Item Names */ 2012 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2013 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2014 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2015 2016 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2017 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2018 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2019 2020 /* Small Resource Data Type Tag Item Names */ 2021 #define PCI_VPD_STIN_END 0x0f /* End */ 2022 2023 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2024 2025 #define PCI_VPD_SRDT_TIN_MASK 0x78 2026 #define PCI_VPD_SRDT_LEN_MASK 0x07 2027 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2028 2029 #define PCI_VPD_LRDT_TAG_SIZE 3 2030 #define PCI_VPD_SRDT_TAG_SIZE 1 2031 2032 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2033 2034 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2035 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2036 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2037 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2038 2039 /** 2040 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2041 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2042 * 2043 * Returns the extracted Large Resource Data Type length. 2044 */ 2045 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2046 { 2047 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2048 } 2049 2050 /** 2051 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2052 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2053 * 2054 * Returns the extracted Large Resource Data Type Tag item. 2055 */ 2056 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2057 { 2058 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2059 } 2060 2061 /** 2062 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2063 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 2064 * 2065 * Returns the extracted Small Resource Data Type length. 2066 */ 2067 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2068 { 2069 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2070 } 2071 2072 /** 2073 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2074 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 2075 * 2076 * Returns the extracted Small Resource Data Type Tag Item. 2077 */ 2078 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2079 { 2080 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2081 } 2082 2083 /** 2084 * pci_vpd_info_field_size - Extracts the information field length 2085 * @lrdt: Pointer to the beginning of an information field header 2086 * 2087 * Returns the extracted information field length. 2088 */ 2089 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2090 { 2091 return info_field[2]; 2092 } 2093 2094 /** 2095 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2096 * @buf: Pointer to buffered vpd data 2097 * @off: The offset into the buffer at which to begin the search 2098 * @len: The length of the vpd buffer 2099 * @rdt: The Resource Data Type to search for 2100 * 2101 * Returns the index where the Resource Data Type was found or 2102 * -ENOENT otherwise. 2103 */ 2104 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2105 2106 /** 2107 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2108 * @buf: Pointer to buffered vpd data 2109 * @off: The offset into the buffer at which to begin the search 2110 * @len: The length of the buffer area, relative to off, in which to search 2111 * @kw: The keyword to search for 2112 * 2113 * Returns the index where the information field keyword was found or 2114 * -ENOENT otherwise. 2115 */ 2116 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2117 unsigned int len, const char *kw); 2118 2119 /* PCI <-> OF binding helpers */ 2120 #ifdef CONFIG_OF 2121 struct device_node; 2122 struct irq_domain; 2123 void pci_set_of_node(struct pci_dev *dev); 2124 void pci_release_of_node(struct pci_dev *dev); 2125 void pci_set_bus_of_node(struct pci_bus *bus); 2126 void pci_release_bus_of_node(struct pci_bus *bus); 2127 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2128 2129 /* Arch may override this (weak) */ 2130 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2131 2132 static inline struct device_node * 2133 pci_device_to_OF_node(const struct pci_dev *pdev) 2134 { 2135 return pdev ? pdev->dev.of_node : NULL; 2136 } 2137 2138 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2139 { 2140 return bus ? bus->dev.of_node : NULL; 2141 } 2142 2143 #else /* CONFIG_OF */ 2144 static inline void pci_set_of_node(struct pci_dev *dev) { } 2145 static inline void pci_release_of_node(struct pci_dev *dev) { } 2146 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2147 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2148 static inline struct device_node * 2149 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 2150 static inline struct irq_domain * 2151 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2152 #endif /* CONFIG_OF */ 2153 2154 #ifdef CONFIG_ACPI 2155 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2156 2157 void 2158 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2159 #else 2160 static inline struct irq_domain * 2161 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2162 #endif 2163 2164 #ifdef CONFIG_EEH 2165 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2166 { 2167 return pdev->dev.archdata.edev; 2168 } 2169 #endif 2170 2171 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2172 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2173 int pci_for_each_dma_alias(struct pci_dev *pdev, 2174 int (*fn)(struct pci_dev *pdev, 2175 u16 alias, void *data), void *data); 2176 2177 /* helper functions for operation of device flag */ 2178 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2179 { 2180 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2181 } 2182 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2183 { 2184 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2185 } 2186 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2187 { 2188 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2189 } 2190 2191 /** 2192 * pci_ari_enabled - query ARI forwarding status 2193 * @bus: the PCI bus 2194 * 2195 * Returns true if ARI forwarding is enabled. 2196 */ 2197 static inline bool pci_ari_enabled(struct pci_bus *bus) 2198 { 2199 return bus->self && bus->self->ari_enabled; 2200 } 2201 2202 /** 2203 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2204 * @pdev: PCI device to check 2205 * 2206 * Walk upwards from @pdev and check for each encountered bridge if it's part 2207 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2208 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2209 */ 2210 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2211 { 2212 struct pci_dev *parent = pdev; 2213 2214 if (pdev->is_thunderbolt) 2215 return true; 2216 2217 while ((parent = pci_upstream_bridge(parent))) 2218 if (parent->is_thunderbolt) 2219 return true; 2220 2221 return false; 2222 } 2223 2224 /* provide the legacy pci_dma_* API */ 2225 #include <linux/pci-dma-compat.h> 2226 2227 #endif /* LINUX_PCI_H */ 2228