1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * For more information, please consult the following manuals (look at 10 * http://www.pcisig.com/ for how to get them): 11 * 12 * PCI BIOS Specification 13 * PCI Local Bus Specification 14 * PCI to PCI Bridge Specification 15 * PCI System Design Guide 16 */ 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 21 #include <linux/mod_devicetable.h> 22 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/list.h> 27 #include <linux/compiler.h> 28 #include <linux/errno.h> 29 #include <linux/kobject.h> 30 #include <linux/atomic.h> 31 #include <linux/device.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/resource_ext.h> 35 #include <uapi/linux/pci.h> 36 37 #include <linux/pci_ids.h> 38 39 /* 40 * The PCI interface treats multi-function devices as independent 41 * devices. The slot/function address of each device is encoded 42 * in a single byte as follows: 43 * 44 * 7:3 = slot 45 * 2:0 = function 46 * 47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 48 * In the interest of not exposing interfaces to user-space unnecessarily, 49 * the following kernel-only defines are being added here. 50 */ 51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 54 55 /* pci_slot represents a physical slot */ 56 struct pci_slot { 57 struct pci_bus *bus; /* The bus this slot is on */ 58 struct list_head list; /* node in list of slots on this bus */ 59 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 61 struct kobject kobj; 62 }; 63 64 static inline const char *pci_slot_name(const struct pci_slot *slot) 65 { 66 return kobject_name(&slot->kobj); 67 } 68 69 /* File state for mmap()s on /proc/bus/pci/X/Y */ 70 enum pci_mmap_state { 71 pci_mmap_io, 72 pci_mmap_mem 73 }; 74 75 /* 76 * For PCI devices, the region numbers are assigned this way: 77 */ 78 enum { 79 /* #0-5: standard PCI resources */ 80 PCI_STD_RESOURCES, 81 PCI_STD_RESOURCE_END = 5, 82 83 /* #6: expansion ROM resource */ 84 PCI_ROM_RESOURCE, 85 86 /* device specific resources */ 87 #ifdef CONFIG_PCI_IOV 88 PCI_IOV_RESOURCES, 89 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 90 #endif 91 92 /* resources assigned to buses behind the bridge */ 93 #define PCI_BRIDGE_RESOURCE_NUM 4 94 95 PCI_BRIDGE_RESOURCES, 96 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 97 PCI_BRIDGE_RESOURCE_NUM - 1, 98 99 /* total resources associated with a PCI device */ 100 PCI_NUM_RESOURCES, 101 102 /* preserve this for compatibility */ 103 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 104 }; 105 106 /** 107 * enum pci_interrupt_pin - PCI INTx interrupt values 108 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 109 * @PCI_INTERRUPT_INTA: PCI INTA pin 110 * @PCI_INTERRUPT_INTB: PCI INTB pin 111 * @PCI_INTERRUPT_INTC: PCI INTC pin 112 * @PCI_INTERRUPT_INTD: PCI INTD pin 113 * 114 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 115 * PCI_INTERRUPT_PIN register. 116 */ 117 enum pci_interrupt_pin { 118 PCI_INTERRUPT_UNKNOWN, 119 PCI_INTERRUPT_INTA, 120 PCI_INTERRUPT_INTB, 121 PCI_INTERRUPT_INTC, 122 PCI_INTERRUPT_INTD, 123 }; 124 125 /* The number of legacy PCI INTx interrupts */ 126 #define PCI_NUM_INTX 4 127 128 /* 129 * pci_power_t values must match the bits in the Capabilities PME_Support 130 * and Control/Status PowerState fields in the Power Management capability. 131 */ 132 typedef int __bitwise pci_power_t; 133 134 #define PCI_D0 ((pci_power_t __force) 0) 135 #define PCI_D1 ((pci_power_t __force) 1) 136 #define PCI_D2 ((pci_power_t __force) 2) 137 #define PCI_D3hot ((pci_power_t __force) 3) 138 #define PCI_D3cold ((pci_power_t __force) 4) 139 #define PCI_UNKNOWN ((pci_power_t __force) 5) 140 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 141 142 /* Remember to update this when the list above changes! */ 143 extern const char *pci_power_names[]; 144 145 static inline const char *pci_power_name(pci_power_t state) 146 { 147 return pci_power_names[1 + (__force int) state]; 148 } 149 150 #define PCI_PM_D2_DELAY 200 151 #define PCI_PM_D3_WAIT 10 152 #define PCI_PM_D3COLD_WAIT 100 153 #define PCI_PM_BUS_WAIT 50 154 155 /** The pci_channel state describes connectivity between the CPU and 156 * the pci device. If some PCI bus between here and the pci device 157 * has crashed or locked up, this info is reflected here. 158 */ 159 typedef unsigned int __bitwise pci_channel_state_t; 160 161 enum pci_channel_state { 162 /* I/O channel is in normal state */ 163 pci_channel_io_normal = (__force pci_channel_state_t) 1, 164 165 /* I/O to channel is blocked */ 166 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 167 168 /* PCI card is dead */ 169 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 170 }; 171 172 typedef unsigned int __bitwise pcie_reset_state_t; 173 174 enum pcie_reset_state { 175 /* Reset is NOT asserted (Use to deassert reset) */ 176 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 177 178 /* Use #PERST to reset PCIe device */ 179 pcie_warm_reset = (__force pcie_reset_state_t) 2, 180 181 /* Use PCIe Hot Reset to reset device */ 182 pcie_hot_reset = (__force pcie_reset_state_t) 3 183 }; 184 185 typedef unsigned short __bitwise pci_dev_flags_t; 186 enum pci_dev_flags { 187 /* INTX_DISABLE in PCI_COMMAND register disables MSI 188 * generation too. 189 */ 190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 191 /* Device configuration is irrevocably lost if disabled into D3 */ 192 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 193 /* Provide indication device is assigned by a Virtual Machine Manager */ 194 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 195 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 197 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 199 /* Do not use bus resets for device */ 200 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 201 /* Do not use PM reset even if device advertises NoSoftRst- */ 202 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 203 /* Get VPD from function 0 VPD */ 204 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 205 /* a non-root bridge where translation occurs, stop alias search here */ 206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 207 /* Do not use FLR even if device advertises PCI_AF_CAP */ 208 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 209 /* Don't use Relaxed Ordering for TLPs directed at this device */ 210 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 211 }; 212 213 enum pci_irq_reroute_variant { 214 INTEL_IRQ_REROUTE_VARIANT = 1, 215 MAX_IRQ_REROUTE_VARIANTS = 3 216 }; 217 218 typedef unsigned short __bitwise pci_bus_flags_t; 219 enum pci_bus_flags { 220 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 221 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 222 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 223 }; 224 225 /* These values come from the PCI Express Spec */ 226 enum pcie_link_width { 227 PCIE_LNK_WIDTH_RESRV = 0x00, 228 PCIE_LNK_X1 = 0x01, 229 PCIE_LNK_X2 = 0x02, 230 PCIE_LNK_X4 = 0x04, 231 PCIE_LNK_X8 = 0x08, 232 PCIE_LNK_X12 = 0x0C, 233 PCIE_LNK_X16 = 0x10, 234 PCIE_LNK_X32 = 0x20, 235 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 236 }; 237 238 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 239 enum pci_bus_speed { 240 PCI_SPEED_33MHz = 0x00, 241 PCI_SPEED_66MHz = 0x01, 242 PCI_SPEED_66MHz_PCIX = 0x02, 243 PCI_SPEED_100MHz_PCIX = 0x03, 244 PCI_SPEED_133MHz_PCIX = 0x04, 245 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 246 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 247 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 248 PCI_SPEED_66MHz_PCIX_266 = 0x09, 249 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 250 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 251 AGP_UNKNOWN = 0x0c, 252 AGP_1X = 0x0d, 253 AGP_2X = 0x0e, 254 AGP_4X = 0x0f, 255 AGP_8X = 0x10, 256 PCI_SPEED_66MHz_PCIX_533 = 0x11, 257 PCI_SPEED_100MHz_PCIX_533 = 0x12, 258 PCI_SPEED_133MHz_PCIX_533 = 0x13, 259 PCIE_SPEED_2_5GT = 0x14, 260 PCIE_SPEED_5_0GT = 0x15, 261 PCIE_SPEED_8_0GT = 0x16, 262 PCI_SPEED_UNKNOWN = 0xff, 263 }; 264 265 struct pci_cap_saved_data { 266 u16 cap_nr; 267 bool cap_extended; 268 unsigned int size; 269 u32 data[0]; 270 }; 271 272 struct pci_cap_saved_state { 273 struct hlist_node next; 274 struct pci_cap_saved_data cap; 275 }; 276 277 struct irq_affinity; 278 struct pcie_link_state; 279 struct pci_vpd; 280 struct pci_sriov; 281 struct pci_ats; 282 283 /* 284 * The pci_dev structure is used to describe PCI devices. 285 */ 286 struct pci_dev { 287 struct list_head bus_list; /* node in per-bus list */ 288 struct pci_bus *bus; /* bus this device is on */ 289 struct pci_bus *subordinate; /* bus this device bridges to */ 290 291 void *sysdata; /* hook for sys-specific extension */ 292 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 293 struct pci_slot *slot; /* Physical slot this device is in */ 294 295 unsigned int devfn; /* encoded device & function index */ 296 unsigned short vendor; 297 unsigned short device; 298 unsigned short subsystem_vendor; 299 unsigned short subsystem_device; 300 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 301 u8 revision; /* PCI revision, low byte of class word */ 302 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 303 #ifdef CONFIG_PCIEAER 304 u16 aer_cap; /* AER capability offset */ 305 #endif 306 u8 pcie_cap; /* PCIe capability offset */ 307 u8 msi_cap; /* MSI capability offset */ 308 u8 msix_cap; /* MSI-X capability offset */ 309 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 310 u8 rom_base_reg; /* which config register controls the ROM */ 311 u8 pin; /* which interrupt pin this device uses */ 312 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 313 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */ 314 315 struct pci_driver *driver; /* which driver has allocated this device */ 316 u64 dma_mask; /* Mask of the bits of bus address this 317 device implements. Normally this is 318 0xffffffff. You only need to change 319 this if your device has broken DMA 320 or supports 64-bit transfers. */ 321 322 struct device_dma_parameters dma_parms; 323 324 pci_power_t current_state; /* Current operating state. In ACPI-speak, 325 this is D0-D3, D0 being fully functional, 326 and D3 being off. */ 327 u8 pm_cap; /* PM capability offset */ 328 unsigned int pme_support:5; /* Bitmask of states from which PME# 329 can be generated */ 330 unsigned int pme_poll:1; /* Poll device's PME status bit */ 331 unsigned int d1_support:1; /* Low power state D1 is supported */ 332 unsigned int d2_support:1; /* Low power state D2 is supported */ 333 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 334 unsigned int no_d3cold:1; /* D3cold is forbidden */ 335 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 336 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 337 unsigned int mmio_always_on:1; /* disallow turning off io/mem 338 decoding during bar sizing */ 339 unsigned int wakeup_prepared:1; 340 unsigned int runtime_d3cold:1; /* whether go through runtime 341 D3cold, not set for devices 342 powered on/off by the 343 corresponding bridge */ 344 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 345 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 346 controlled exclusively by 347 user sysfs */ 348 unsigned int d3_delay; /* D3->D0 transition time in ms */ 349 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 350 351 #ifdef CONFIG_PCIEASPM 352 struct pcie_link_state *link_state; /* ASPM link state */ 353 #endif 354 355 pci_channel_state_t error_state; /* current connectivity state */ 356 struct device dev; /* Generic device interface */ 357 358 int cfg_size; /* Size of configuration space */ 359 360 /* 361 * Instead of touching interrupt line and base address registers 362 * directly, use the values stored here. They might be different! 363 */ 364 unsigned int irq; 365 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 366 367 bool match_driver; /* Skip attaching driver */ 368 /* These fields are used by common fixups */ 369 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 370 unsigned int multifunction:1;/* Part of multi-function device */ 371 /* keep track of device state */ 372 unsigned int is_added:1; 373 unsigned int is_busmaster:1; /* device is busmaster */ 374 unsigned int no_msi:1; /* device may not use msi */ 375 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 376 unsigned int block_cfg_access:1; /* config space access is blocked */ 377 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 378 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 379 unsigned int msi_enabled:1; 380 unsigned int msix_enabled:1; 381 unsigned int ari_enabled:1; /* ARI forwarding */ 382 unsigned int ats_enabled:1; /* Address Translation Service */ 383 unsigned int pasid_enabled:1; /* Process Address Space ID */ 384 unsigned int pri_enabled:1; /* Page Request Interface */ 385 unsigned int is_managed:1; 386 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 387 unsigned int state_saved:1; 388 unsigned int is_physfn:1; 389 unsigned int is_virtfn:1; 390 unsigned int reset_fn:1; 391 unsigned int is_hotplug_bridge:1; 392 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 393 unsigned int __aer_firmware_first_valid:1; 394 unsigned int __aer_firmware_first:1; 395 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 396 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 397 unsigned int irq_managed:1; 398 unsigned int has_secondary_link:1; 399 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 400 unsigned int is_probed:1; /* device probing in progress */ 401 pci_dev_flags_t dev_flags; 402 atomic_t enable_cnt; /* pci_enable_device has been called */ 403 404 u32 saved_config_space[16]; /* config space saved at suspend time */ 405 struct hlist_head saved_cap_space; 406 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 407 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 408 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 409 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 410 411 #ifdef CONFIG_PCIE_PTM 412 unsigned int ptm_root:1; 413 unsigned int ptm_enabled:1; 414 u8 ptm_granularity; 415 #endif 416 #ifdef CONFIG_PCI_MSI 417 const struct attribute_group **msi_irq_groups; 418 #endif 419 struct pci_vpd *vpd; 420 #ifdef CONFIG_PCI_ATS 421 union { 422 struct pci_sriov *sriov; /* SR-IOV capability related */ 423 struct pci_dev *physfn; /* the PF this VF is associated with */ 424 }; 425 u16 ats_cap; /* ATS Capability offset */ 426 u8 ats_stu; /* ATS Smallest Translation Unit */ 427 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 428 #endif 429 #ifdef CONFIG_PCI_PRI 430 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 431 #endif 432 #ifdef CONFIG_PCI_PASID 433 u16 pasid_features; 434 #endif 435 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 436 size_t romlen; /* Length of ROM if it's not from the BAR */ 437 char *driver_override; /* Driver name to force a match */ 438 439 unsigned long priv_flags; /* Private flags for the pci driver */ 440 }; 441 442 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 443 { 444 #ifdef CONFIG_PCI_IOV 445 if (dev->is_virtfn) 446 dev = dev->physfn; 447 #endif 448 return dev; 449 } 450 451 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 452 453 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 454 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 455 456 static inline int pci_channel_offline(struct pci_dev *pdev) 457 { 458 return (pdev->error_state != pci_channel_io_normal); 459 } 460 461 struct pci_host_bridge { 462 struct device dev; 463 struct pci_bus *bus; /* root bus */ 464 struct pci_ops *ops; 465 void *sysdata; 466 int busnr; 467 struct list_head windows; /* resource_entry */ 468 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */ 469 int (*map_irq)(const struct pci_dev *, u8, u8); 470 void (*release_fn)(struct pci_host_bridge *); 471 void *release_data; 472 struct msi_controller *msi; 473 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 474 unsigned int no_ext_tags:1; /* no Extended Tags */ 475 /* Resource alignment requirements */ 476 resource_size_t (*align_resource)(struct pci_dev *dev, 477 const struct resource *res, 478 resource_size_t start, 479 resource_size_t size, 480 resource_size_t align); 481 unsigned long private[0] ____cacheline_aligned; 482 }; 483 484 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 485 486 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 487 { 488 return (void *)bridge->private; 489 } 490 491 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 492 { 493 return container_of(priv, struct pci_host_bridge, private); 494 } 495 496 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 497 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 498 size_t priv); 499 void pci_free_host_bridge(struct pci_host_bridge *bridge); 500 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 501 502 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 503 void (*release_fn)(struct pci_host_bridge *), 504 void *release_data); 505 506 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 507 508 /* 509 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 510 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 511 * buses below host bridges or subtractive decode bridges) go in the list. 512 * Use pci_bus_for_each_resource() to iterate through all the resources. 513 */ 514 515 /* 516 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 517 * and there's no way to program the bridge with the details of the window. 518 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 519 * decode bit set, because they are explicit and can be programmed with _SRS. 520 */ 521 #define PCI_SUBTRACTIVE_DECODE 0x1 522 523 struct pci_bus_resource { 524 struct list_head list; 525 struct resource *res; 526 unsigned int flags; 527 }; 528 529 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 530 531 struct pci_bus { 532 struct list_head node; /* node in list of buses */ 533 struct pci_bus *parent; /* parent bus this bridge is on */ 534 struct list_head children; /* list of child buses */ 535 struct list_head devices; /* list of devices on this bus */ 536 struct pci_dev *self; /* bridge device as seen by parent */ 537 struct list_head slots; /* list of slots on this bus; 538 protected by pci_slot_mutex */ 539 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 540 struct list_head resources; /* address space routed to this bus */ 541 struct resource busn_res; /* bus numbers routed to this bus */ 542 543 struct pci_ops *ops; /* configuration access functions */ 544 struct msi_controller *msi; /* MSI controller */ 545 void *sysdata; /* hook for sys-specific extension */ 546 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 547 548 unsigned char number; /* bus number */ 549 unsigned char primary; /* number of primary bridge */ 550 unsigned char max_bus_speed; /* enum pci_bus_speed */ 551 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 552 #ifdef CONFIG_PCI_DOMAINS_GENERIC 553 int domain_nr; 554 #endif 555 556 char name[48]; 557 558 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 559 pci_bus_flags_t bus_flags; /* inherited by child buses */ 560 struct device *bridge; 561 struct device dev; 562 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 563 struct bin_attribute *legacy_mem; /* legacy mem */ 564 unsigned int is_added:1; 565 }; 566 567 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 568 569 /* 570 * Returns true if the PCI bus is root (behind host-PCI bridge), 571 * false otherwise 572 * 573 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 574 * This is incorrect because "virtual" buses added for SR-IOV (via 575 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 576 */ 577 static inline bool pci_is_root_bus(struct pci_bus *pbus) 578 { 579 return !(pbus->parent); 580 } 581 582 /** 583 * pci_is_bridge - check if the PCI device is a bridge 584 * @dev: PCI device 585 * 586 * Return true if the PCI device is bridge whether it has subordinate 587 * or not. 588 */ 589 static inline bool pci_is_bridge(struct pci_dev *dev) 590 { 591 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 592 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 593 } 594 595 #define for_each_pci_bridge(dev, bus) \ 596 list_for_each_entry(dev, &bus->devices, bus_list) \ 597 if (!pci_is_bridge(dev)) {} else 598 599 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 600 { 601 dev = pci_physfn(dev); 602 if (pci_is_root_bus(dev->bus)) 603 return NULL; 604 605 return dev->bus->self; 606 } 607 608 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 609 void pci_put_host_bridge_device(struct device *dev); 610 611 #ifdef CONFIG_PCI_MSI 612 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 613 { 614 return pci_dev->msi_enabled || pci_dev->msix_enabled; 615 } 616 #else 617 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 618 #endif 619 620 /* 621 * Error values that may be returned by PCI functions. 622 */ 623 #define PCIBIOS_SUCCESSFUL 0x00 624 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 625 #define PCIBIOS_BAD_VENDOR_ID 0x83 626 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 627 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 628 #define PCIBIOS_SET_FAILED 0x88 629 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 630 631 /* 632 * Translate above to generic errno for passing back through non-PCI code. 633 */ 634 static inline int pcibios_err_to_errno(int err) 635 { 636 if (err <= PCIBIOS_SUCCESSFUL) 637 return err; /* Assume already errno */ 638 639 switch (err) { 640 case PCIBIOS_FUNC_NOT_SUPPORTED: 641 return -ENOENT; 642 case PCIBIOS_BAD_VENDOR_ID: 643 return -ENOTTY; 644 case PCIBIOS_DEVICE_NOT_FOUND: 645 return -ENODEV; 646 case PCIBIOS_BAD_REGISTER_NUMBER: 647 return -EFAULT; 648 case PCIBIOS_SET_FAILED: 649 return -EIO; 650 case PCIBIOS_BUFFER_TOO_SMALL: 651 return -ENOSPC; 652 } 653 654 return -ERANGE; 655 } 656 657 /* Low-level architecture-dependent routines */ 658 659 struct pci_ops { 660 int (*add_bus)(struct pci_bus *bus); 661 void (*remove_bus)(struct pci_bus *bus); 662 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 663 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 664 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 665 }; 666 667 /* 668 * ACPI needs to be able to access PCI config space before we've done a 669 * PCI bus scan and created pci_bus structures. 670 */ 671 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 672 int reg, int len, u32 *val); 673 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 674 int reg, int len, u32 val); 675 676 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 677 typedef u64 pci_bus_addr_t; 678 #else 679 typedef u32 pci_bus_addr_t; 680 #endif 681 682 struct pci_bus_region { 683 pci_bus_addr_t start; 684 pci_bus_addr_t end; 685 }; 686 687 struct pci_dynids { 688 spinlock_t lock; /* protects list, index */ 689 struct list_head list; /* for IDs added at runtime */ 690 }; 691 692 693 /* 694 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 695 * a set of callbacks in struct pci_error_handlers, that device driver 696 * will be notified of PCI bus errors, and will be driven to recovery 697 * when an error occurs. 698 */ 699 700 typedef unsigned int __bitwise pci_ers_result_t; 701 702 enum pci_ers_result { 703 /* no result/none/not supported in device driver */ 704 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 705 706 /* Device driver can recover without slot reset */ 707 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 708 709 /* Device driver wants slot to be reset. */ 710 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 711 712 /* Device has completely failed, is unrecoverable */ 713 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 714 715 /* Device driver is fully recovered and operational */ 716 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 717 718 /* No AER capabilities registered for the driver */ 719 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 720 }; 721 722 /* PCI bus error event callbacks */ 723 struct pci_error_handlers { 724 /* PCI bus error detected on this device */ 725 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 726 enum pci_channel_state error); 727 728 /* MMIO has been re-enabled, but not DMA */ 729 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 730 731 /* PCI slot has been reset */ 732 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 733 734 /* PCI function reset prepare or completed */ 735 void (*reset_prepare)(struct pci_dev *dev); 736 void (*reset_done)(struct pci_dev *dev); 737 738 /* Device driver may resume normal operations */ 739 void (*resume)(struct pci_dev *dev); 740 }; 741 742 743 struct module; 744 struct pci_driver { 745 struct list_head node; 746 const char *name; 747 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 748 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 749 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 750 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 751 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 752 int (*resume_early) (struct pci_dev *dev); 753 int (*resume) (struct pci_dev *dev); /* Device woken up */ 754 void (*shutdown) (struct pci_dev *dev); 755 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 756 const struct pci_error_handlers *err_handler; 757 const struct attribute_group **groups; 758 struct device_driver driver; 759 struct pci_dynids dynids; 760 }; 761 762 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 763 764 /** 765 * PCI_DEVICE - macro used to describe a specific pci device 766 * @vend: the 16 bit PCI Vendor ID 767 * @dev: the 16 bit PCI Device ID 768 * 769 * This macro is used to create a struct pci_device_id that matches a 770 * specific device. The subvendor and subdevice fields will be set to 771 * PCI_ANY_ID. 772 */ 773 #define PCI_DEVICE(vend,dev) \ 774 .vendor = (vend), .device = (dev), \ 775 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 776 777 /** 778 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 779 * @vend: the 16 bit PCI Vendor ID 780 * @dev: the 16 bit PCI Device ID 781 * @subvend: the 16 bit PCI Subvendor ID 782 * @subdev: the 16 bit PCI Subdevice ID 783 * 784 * This macro is used to create a struct pci_device_id that matches a 785 * specific device with subsystem information. 786 */ 787 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 788 .vendor = (vend), .device = (dev), \ 789 .subvendor = (subvend), .subdevice = (subdev) 790 791 /** 792 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 793 * @dev_class: the class, subclass, prog-if triple for this device 794 * @dev_class_mask: the class mask for this device 795 * 796 * This macro is used to create a struct pci_device_id that matches a 797 * specific PCI class. The vendor, device, subvendor, and subdevice 798 * fields will be set to PCI_ANY_ID. 799 */ 800 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 801 .class = (dev_class), .class_mask = (dev_class_mask), \ 802 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 803 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 804 805 /** 806 * PCI_VDEVICE - macro used to describe a specific pci device in short form 807 * @vend: the vendor name 808 * @dev: the 16 bit PCI Device ID 809 * 810 * This macro is used to create a struct pci_device_id that matches a 811 * specific PCI device. The subvendor, and subdevice fields will be set 812 * to PCI_ANY_ID. The macro allows the next field to follow as the device 813 * private data. 814 */ 815 816 #define PCI_VDEVICE(vend, dev) \ 817 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 818 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 819 820 enum { 821 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ 822 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ 823 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ 824 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ 825 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ 826 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 827 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ 828 }; 829 830 /* these external functions are only available when PCI support is enabled */ 831 #ifdef CONFIG_PCI 832 833 extern unsigned int pci_flags; 834 835 static inline void pci_set_flags(int flags) { pci_flags = flags; } 836 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 837 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 838 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 839 840 void pcie_bus_configure_settings(struct pci_bus *bus); 841 842 enum pcie_bus_config_types { 843 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 844 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 845 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 846 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 847 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 848 }; 849 850 extern enum pcie_bus_config_types pcie_bus_config; 851 852 extern struct bus_type pci_bus_type; 853 854 /* Do NOT directly access these two variables, unless you are arch-specific PCI 855 * code, or PCI core code. */ 856 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 857 /* Some device drivers need know if PCI is initiated */ 858 int no_pci_devices(void); 859 860 void pcibios_resource_survey_bus(struct pci_bus *bus); 861 void pcibios_bus_add_device(struct pci_dev *pdev); 862 void pcibios_add_bus(struct pci_bus *bus); 863 void pcibios_remove_bus(struct pci_bus *bus); 864 void pcibios_fixup_bus(struct pci_bus *); 865 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 866 /* Architecture-specific versions may override this (weak) */ 867 char *pcibios_setup(char *str); 868 869 /* Used only when drivers/pci/setup.c is used */ 870 resource_size_t pcibios_align_resource(void *, const struct resource *, 871 resource_size_t, 872 resource_size_t); 873 874 /* Weak but can be overriden by arch */ 875 void pci_fixup_cardbus(struct pci_bus *); 876 877 /* Generic PCI functions used internally */ 878 879 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 880 struct resource *res); 881 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 882 struct pci_bus_region *region); 883 void pcibios_scan_specific_bus(int busn); 884 struct pci_bus *pci_find_bus(int domain, int busnr); 885 void pci_bus_add_devices(const struct pci_bus *bus); 886 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 887 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 888 struct pci_ops *ops, void *sysdata, 889 struct list_head *resources); 890 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 891 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 892 void pci_bus_release_busn_res(struct pci_bus *b); 893 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 894 struct pci_ops *ops, void *sysdata, 895 struct list_head *resources); 896 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 897 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 898 int busnr); 899 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 900 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 901 const char *name, 902 struct hotplug_slot *hotplug); 903 void pci_destroy_slot(struct pci_slot *slot); 904 #ifdef CONFIG_SYSFS 905 void pci_dev_assign_slot(struct pci_dev *dev); 906 #else 907 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 908 #endif 909 int pci_scan_slot(struct pci_bus *bus, int devfn); 910 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 911 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 912 unsigned int pci_scan_child_bus(struct pci_bus *bus); 913 void pci_bus_add_device(struct pci_dev *dev); 914 void pci_read_bridge_bases(struct pci_bus *child); 915 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 916 struct resource *res); 917 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 918 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 919 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 920 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 921 struct pci_dev *pci_dev_get(struct pci_dev *dev); 922 void pci_dev_put(struct pci_dev *dev); 923 void pci_remove_bus(struct pci_bus *b); 924 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 925 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 926 void pci_stop_root_bus(struct pci_bus *bus); 927 void pci_remove_root_bus(struct pci_bus *bus); 928 void pci_setup_cardbus(struct pci_bus *bus); 929 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 930 void pci_sort_breadthfirst(void); 931 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 932 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 933 934 /* Generic PCI functions exported to card drivers */ 935 936 enum pci_lost_interrupt_reason { 937 PCI_LOST_IRQ_NO_INFORMATION = 0, 938 PCI_LOST_IRQ_DISABLE_MSI, 939 PCI_LOST_IRQ_DISABLE_MSIX, 940 PCI_LOST_IRQ_DISABLE_ACPI, 941 }; 942 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 943 int pci_find_capability(struct pci_dev *dev, int cap); 944 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 945 int pci_find_ext_capability(struct pci_dev *dev, int cap); 946 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 947 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 948 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 949 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 950 951 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 952 struct pci_dev *from); 953 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 954 unsigned int ss_vendor, unsigned int ss_device, 955 struct pci_dev *from); 956 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 957 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 958 unsigned int devfn); 959 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 960 unsigned int devfn) 961 { 962 return pci_get_domain_bus_and_slot(0, bus, devfn); 963 } 964 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 965 int pci_dev_present(const struct pci_device_id *ids); 966 967 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 968 int where, u8 *val); 969 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 970 int where, u16 *val); 971 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 972 int where, u32 *val); 973 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 974 int where, u8 val); 975 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 976 int where, u16 val); 977 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 978 int where, u32 val); 979 980 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 981 int where, int size, u32 *val); 982 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 983 int where, int size, u32 val); 984 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 985 int where, int size, u32 *val); 986 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 987 int where, int size, u32 val); 988 989 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 990 991 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 992 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 993 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 994 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 995 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 996 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 997 998 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 999 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1000 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1001 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1002 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1003 u16 clear, u16 set); 1004 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1005 u32 clear, u32 set); 1006 1007 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1008 u16 set) 1009 { 1010 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1011 } 1012 1013 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1014 u32 set) 1015 { 1016 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1017 } 1018 1019 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1020 u16 clear) 1021 { 1022 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1023 } 1024 1025 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1026 u32 clear) 1027 { 1028 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1029 } 1030 1031 /* user-space driven config access */ 1032 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1033 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1034 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1035 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1036 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1037 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1038 1039 int __must_check pci_enable_device(struct pci_dev *dev); 1040 int __must_check pci_enable_device_io(struct pci_dev *dev); 1041 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1042 int __must_check pci_reenable_device(struct pci_dev *); 1043 int __must_check pcim_enable_device(struct pci_dev *pdev); 1044 void pcim_pin_device(struct pci_dev *pdev); 1045 1046 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1047 { 1048 /* 1049 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1050 * writable and no quirk has marked the feature broken. 1051 */ 1052 return !pdev->broken_intx_masking; 1053 } 1054 1055 static inline int pci_is_enabled(struct pci_dev *pdev) 1056 { 1057 return (atomic_read(&pdev->enable_cnt) > 0); 1058 } 1059 1060 static inline int pci_is_managed(struct pci_dev *pdev) 1061 { 1062 return pdev->is_managed; 1063 } 1064 1065 void pci_disable_device(struct pci_dev *dev); 1066 1067 extern unsigned int pcibios_max_latency; 1068 void pci_set_master(struct pci_dev *dev); 1069 void pci_clear_master(struct pci_dev *dev); 1070 1071 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1072 int pci_set_cacheline_size(struct pci_dev *dev); 1073 #define HAVE_PCI_SET_MWI 1074 int __must_check pci_set_mwi(struct pci_dev *dev); 1075 int pci_try_set_mwi(struct pci_dev *dev); 1076 void pci_clear_mwi(struct pci_dev *dev); 1077 void pci_intx(struct pci_dev *dev, int enable); 1078 bool pci_check_and_mask_intx(struct pci_dev *dev); 1079 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1080 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1081 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1082 int pcix_get_max_mmrbc(struct pci_dev *dev); 1083 int pcix_get_mmrbc(struct pci_dev *dev); 1084 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1085 int pcie_get_readrq(struct pci_dev *dev); 1086 int pcie_set_readrq(struct pci_dev *dev, int rq); 1087 int pcie_get_mps(struct pci_dev *dev); 1088 int pcie_set_mps(struct pci_dev *dev, int mps); 1089 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1090 enum pcie_link_width *width); 1091 void pcie_flr(struct pci_dev *dev); 1092 int __pci_reset_function_locked(struct pci_dev *dev); 1093 int pci_reset_function(struct pci_dev *dev); 1094 int pci_reset_function_locked(struct pci_dev *dev); 1095 int pci_try_reset_function(struct pci_dev *dev); 1096 int pci_probe_reset_slot(struct pci_slot *slot); 1097 int pci_reset_slot(struct pci_slot *slot); 1098 int pci_try_reset_slot(struct pci_slot *slot); 1099 int pci_probe_reset_bus(struct pci_bus *bus); 1100 int pci_reset_bus(struct pci_bus *bus); 1101 int pci_try_reset_bus(struct pci_bus *bus); 1102 void pci_reset_secondary_bus(struct pci_dev *dev); 1103 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1104 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1105 void pci_update_resource(struct pci_dev *dev, int resno); 1106 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1107 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1108 void pci_release_resource(struct pci_dev *dev, int resno); 1109 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1110 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1111 bool pci_device_is_present(struct pci_dev *pdev); 1112 void pci_ignore_hotplug(struct pci_dev *dev); 1113 1114 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1115 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1116 const char *fmt, ...); 1117 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1118 1119 /* ROM control related routines */ 1120 int pci_enable_rom(struct pci_dev *pdev); 1121 void pci_disable_rom(struct pci_dev *pdev); 1122 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1123 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1124 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1125 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1126 1127 /* Power management related routines */ 1128 int pci_save_state(struct pci_dev *dev); 1129 void pci_restore_state(struct pci_dev *dev); 1130 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1131 int pci_load_saved_state(struct pci_dev *dev, 1132 struct pci_saved_state *state); 1133 int pci_load_and_free_saved_state(struct pci_dev *dev, 1134 struct pci_saved_state **state); 1135 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1136 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1137 u16 cap); 1138 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1139 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1140 u16 cap, unsigned int size); 1141 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1142 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1143 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1144 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1145 void pci_pme_active(struct pci_dev *dev, bool enable); 1146 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1147 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1148 int pci_prepare_to_sleep(struct pci_dev *dev); 1149 int pci_back_from_sleep(struct pci_dev *dev); 1150 bool pci_dev_run_wake(struct pci_dev *dev); 1151 bool pci_check_pme_status(struct pci_dev *dev); 1152 void pci_pme_wakeup_bus(struct pci_bus *bus); 1153 void pci_d3cold_enable(struct pci_dev *dev); 1154 void pci_d3cold_disable(struct pci_dev *dev); 1155 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1156 1157 /* PCI Virtual Channel */ 1158 int pci_save_vc_state(struct pci_dev *dev); 1159 void pci_restore_vc_state(struct pci_dev *dev); 1160 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1161 1162 /* For use by arch with custom probe code */ 1163 void set_pcie_port_type(struct pci_dev *pdev); 1164 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1165 1166 /* Functions for PCI Hotplug drivers to use */ 1167 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1168 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1169 unsigned int pci_rescan_bus(struct pci_bus *bus); 1170 void pci_lock_rescan_remove(void); 1171 void pci_unlock_rescan_remove(void); 1172 1173 /* Vital product data routines */ 1174 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1175 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1176 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1177 1178 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1179 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1180 void pci_bus_assign_resources(const struct pci_bus *bus); 1181 void pci_bus_claim_resources(struct pci_bus *bus); 1182 void pci_bus_size_bridges(struct pci_bus *bus); 1183 int pci_claim_resource(struct pci_dev *, int); 1184 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1185 void pci_assign_unassigned_resources(void); 1186 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1187 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1188 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1189 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1190 void pdev_enable_device(struct pci_dev *); 1191 int pci_enable_resources(struct pci_dev *, int mask); 1192 void pci_assign_irq(struct pci_dev *dev); 1193 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1194 #define HAVE_PCI_REQ_REGIONS 2 1195 int __must_check pci_request_regions(struct pci_dev *, const char *); 1196 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1197 void pci_release_regions(struct pci_dev *); 1198 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1199 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1200 void pci_release_region(struct pci_dev *, int); 1201 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1202 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1203 void pci_release_selected_regions(struct pci_dev *, int); 1204 1205 /* drivers/pci/bus.c */ 1206 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1207 void pci_bus_put(struct pci_bus *bus); 1208 void pci_add_resource(struct list_head *resources, struct resource *res); 1209 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1210 resource_size_t offset); 1211 void pci_free_resource_list(struct list_head *resources); 1212 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1213 unsigned int flags); 1214 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1215 void pci_bus_remove_resources(struct pci_bus *bus); 1216 int devm_request_pci_bus_resources(struct device *dev, 1217 struct list_head *resources); 1218 1219 #define pci_bus_for_each_resource(bus, res, i) \ 1220 for (i = 0; \ 1221 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1222 i++) 1223 1224 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1225 struct resource *res, resource_size_t size, 1226 resource_size_t align, resource_size_t min, 1227 unsigned long type_mask, 1228 resource_size_t (*alignf)(void *, 1229 const struct resource *, 1230 resource_size_t, 1231 resource_size_t), 1232 void *alignf_data); 1233 1234 1235 int pci_register_io_range(phys_addr_t addr, resource_size_t size); 1236 unsigned long pci_address_to_pio(phys_addr_t addr); 1237 phys_addr_t pci_pio_to_address(unsigned long pio); 1238 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1239 void pci_unmap_iospace(struct resource *res); 1240 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1241 resource_size_t offset, 1242 resource_size_t size); 1243 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1244 struct resource *res); 1245 1246 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1247 { 1248 struct pci_bus_region region; 1249 1250 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1251 return region.start; 1252 } 1253 1254 /* Proper probing supporting hot-pluggable devices */ 1255 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1256 const char *mod_name); 1257 1258 /* 1259 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1260 */ 1261 #define pci_register_driver(driver) \ 1262 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1263 1264 void pci_unregister_driver(struct pci_driver *dev); 1265 1266 /** 1267 * module_pci_driver() - Helper macro for registering a PCI driver 1268 * @__pci_driver: pci_driver struct 1269 * 1270 * Helper macro for PCI drivers which do not do anything special in module 1271 * init/exit. This eliminates a lot of boilerplate. Each module may only 1272 * use this macro once, and calling it replaces module_init() and module_exit() 1273 */ 1274 #define module_pci_driver(__pci_driver) \ 1275 module_driver(__pci_driver, pci_register_driver, \ 1276 pci_unregister_driver) 1277 1278 /** 1279 * builtin_pci_driver() - Helper macro for registering a PCI driver 1280 * @__pci_driver: pci_driver struct 1281 * 1282 * Helper macro for PCI drivers which do not do anything special in their 1283 * init code. This eliminates a lot of boilerplate. Each driver may only 1284 * use this macro once, and calling it replaces device_initcall(...) 1285 */ 1286 #define builtin_pci_driver(__pci_driver) \ 1287 builtin_driver(__pci_driver, pci_register_driver) 1288 1289 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1290 int pci_add_dynid(struct pci_driver *drv, 1291 unsigned int vendor, unsigned int device, 1292 unsigned int subvendor, unsigned int subdevice, 1293 unsigned int class, unsigned int class_mask, 1294 unsigned long driver_data); 1295 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1296 struct pci_dev *dev); 1297 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1298 int pass); 1299 1300 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1301 void *userdata); 1302 int pci_cfg_space_size(struct pci_dev *dev); 1303 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1304 void pci_setup_bridge(struct pci_bus *bus); 1305 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1306 unsigned long type); 1307 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1308 1309 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1310 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1311 1312 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1313 unsigned int command_bits, u32 flags); 1314 1315 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ 1316 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ 1317 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ 1318 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ 1319 #define PCI_IRQ_ALL_TYPES \ 1320 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1321 1322 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1323 1324 #include <linux/pci-dma.h> 1325 #include <linux/dmapool.h> 1326 1327 #define pci_pool dma_pool 1328 #define pci_pool_create(name, pdev, size, align, allocation) \ 1329 dma_pool_create(name, &pdev->dev, size, align, allocation) 1330 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1331 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1332 #define pci_pool_zalloc(pool, flags, handle) \ 1333 dma_pool_zalloc(pool, flags, handle) 1334 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1335 1336 struct msix_entry { 1337 u32 vector; /* kernel uses to write allocated vector */ 1338 u16 entry; /* driver uses to specify entry, OS writes */ 1339 }; 1340 1341 #ifdef CONFIG_PCI_MSI 1342 int pci_msi_vec_count(struct pci_dev *dev); 1343 void pci_disable_msi(struct pci_dev *dev); 1344 int pci_msix_vec_count(struct pci_dev *dev); 1345 void pci_disable_msix(struct pci_dev *dev); 1346 void pci_restore_msi_state(struct pci_dev *dev); 1347 int pci_msi_enabled(void); 1348 int pci_enable_msi(struct pci_dev *dev); 1349 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1350 int minvec, int maxvec); 1351 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1352 struct msix_entry *entries, int nvec) 1353 { 1354 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1355 if (rc < 0) 1356 return rc; 1357 return 0; 1358 } 1359 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1360 unsigned int max_vecs, unsigned int flags, 1361 const struct irq_affinity *affd); 1362 1363 void pci_free_irq_vectors(struct pci_dev *dev); 1364 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1365 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1366 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1367 1368 #else 1369 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1370 static inline void pci_disable_msi(struct pci_dev *dev) { } 1371 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1372 static inline void pci_disable_msix(struct pci_dev *dev) { } 1373 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1374 static inline int pci_msi_enabled(void) { return 0; } 1375 static inline int pci_enable_msi(struct pci_dev *dev) 1376 { return -ENOSYS; } 1377 static inline int pci_enable_msix_range(struct pci_dev *dev, 1378 struct msix_entry *entries, int minvec, int maxvec) 1379 { return -ENOSYS; } 1380 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1381 struct msix_entry *entries, int nvec) 1382 { return -ENOSYS; } 1383 1384 static inline int 1385 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1386 unsigned int max_vecs, unsigned int flags, 1387 const struct irq_affinity *aff_desc) 1388 { 1389 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1390 return 1; 1391 return -ENOSPC; 1392 } 1393 1394 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1395 { 1396 } 1397 1398 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1399 { 1400 if (WARN_ON_ONCE(nr > 0)) 1401 return -EINVAL; 1402 return dev->irq; 1403 } 1404 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1405 int vec) 1406 { 1407 return cpu_possible_mask; 1408 } 1409 1410 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1411 { 1412 return first_online_node; 1413 } 1414 #endif 1415 1416 static inline int 1417 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1418 unsigned int max_vecs, unsigned int flags) 1419 { 1420 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1421 NULL); 1422 } 1423 1424 /** 1425 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1426 * @d: the INTx IRQ domain 1427 * @node: the DT node for the device whose interrupt we're translating 1428 * @intspec: the interrupt specifier data from the DT 1429 * @intsize: the number of entries in @intspec 1430 * @out_hwirq: pointer at which to write the hwirq number 1431 * @out_type: pointer at which to write the interrupt type 1432 * 1433 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1434 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1435 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1436 * INTx value to obtain the hwirq number. 1437 * 1438 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1439 */ 1440 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1441 struct device_node *node, 1442 const u32 *intspec, 1443 unsigned int intsize, 1444 unsigned long *out_hwirq, 1445 unsigned int *out_type) 1446 { 1447 const u32 intx = intspec[0]; 1448 1449 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1450 return -EINVAL; 1451 1452 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1453 return 0; 1454 } 1455 1456 #ifdef CONFIG_PCIEPORTBUS 1457 extern bool pcie_ports_disabled; 1458 extern bool pcie_ports_auto; 1459 #else 1460 #define pcie_ports_disabled true 1461 #define pcie_ports_auto false 1462 #endif 1463 1464 #ifdef CONFIG_PCIEASPM 1465 bool pcie_aspm_support_enabled(void); 1466 #else 1467 static inline bool pcie_aspm_support_enabled(void) { return false; } 1468 #endif 1469 1470 #ifdef CONFIG_PCIEAER 1471 void pci_no_aer(void); 1472 bool pci_aer_available(void); 1473 int pci_aer_init(struct pci_dev *dev); 1474 #else 1475 static inline void pci_no_aer(void) { } 1476 static inline bool pci_aer_available(void) { return false; } 1477 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } 1478 #endif 1479 1480 #ifdef CONFIG_PCIE_ECRC 1481 void pcie_set_ecrc_checking(struct pci_dev *dev); 1482 void pcie_ecrc_get_policy(char *str); 1483 #else 1484 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1485 static inline void pcie_ecrc_get_policy(char *str) { } 1486 #endif 1487 1488 #ifdef CONFIG_PCI_ATS 1489 /* Address Translation Service */ 1490 void pci_ats_init(struct pci_dev *dev); 1491 int pci_enable_ats(struct pci_dev *dev, int ps); 1492 void pci_disable_ats(struct pci_dev *dev); 1493 int pci_ats_queue_depth(struct pci_dev *dev); 1494 #else 1495 static inline void pci_ats_init(struct pci_dev *d) { } 1496 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1497 static inline void pci_disable_ats(struct pci_dev *d) { } 1498 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1499 #endif 1500 1501 #ifdef CONFIG_PCIE_PTM 1502 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1503 #else 1504 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1505 { return -EINVAL; } 1506 #endif 1507 1508 void pci_cfg_access_lock(struct pci_dev *dev); 1509 bool pci_cfg_access_trylock(struct pci_dev *dev); 1510 void pci_cfg_access_unlock(struct pci_dev *dev); 1511 1512 /* 1513 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1514 * a PCI domain is defined to be a set of PCI buses which share 1515 * configuration space. 1516 */ 1517 #ifdef CONFIG_PCI_DOMAINS 1518 extern int pci_domains_supported; 1519 int pci_get_new_domain_nr(void); 1520 #else 1521 enum { pci_domains_supported = 0 }; 1522 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1523 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1524 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1525 #endif /* CONFIG_PCI_DOMAINS */ 1526 1527 /* 1528 * Generic implementation for PCI domain support. If your 1529 * architecture does not need custom management of PCI 1530 * domains then this implementation will be used 1531 */ 1532 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1533 static inline int pci_domain_nr(struct pci_bus *bus) 1534 { 1535 return bus->domain_nr; 1536 } 1537 #ifdef CONFIG_ACPI 1538 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1539 #else 1540 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1541 { return 0; } 1542 #endif 1543 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1544 #endif 1545 1546 /* some architectures require additional setup to direct VGA traffic */ 1547 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1548 unsigned int command_bits, u32 flags); 1549 void pci_register_set_vga_state(arch_set_vga_state_t func); 1550 1551 static inline int 1552 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1553 { 1554 return pci_request_selected_regions(pdev, 1555 pci_select_bars(pdev, IORESOURCE_IO), name); 1556 } 1557 1558 static inline void 1559 pci_release_io_regions(struct pci_dev *pdev) 1560 { 1561 return pci_release_selected_regions(pdev, 1562 pci_select_bars(pdev, IORESOURCE_IO)); 1563 } 1564 1565 static inline int 1566 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1567 { 1568 return pci_request_selected_regions(pdev, 1569 pci_select_bars(pdev, IORESOURCE_MEM), name); 1570 } 1571 1572 static inline void 1573 pci_release_mem_regions(struct pci_dev *pdev) 1574 { 1575 return pci_release_selected_regions(pdev, 1576 pci_select_bars(pdev, IORESOURCE_MEM)); 1577 } 1578 1579 #else /* CONFIG_PCI is not enabled */ 1580 1581 static inline void pci_set_flags(int flags) { } 1582 static inline void pci_add_flags(int flags) { } 1583 static inline void pci_clear_flags(int flags) { } 1584 static inline int pci_has_flag(int flag) { return 0; } 1585 1586 /* 1587 * If the system does not have PCI, clearly these return errors. Define 1588 * these as simple inline functions to avoid hair in drivers. 1589 */ 1590 1591 #define _PCI_NOP(o, s, t) \ 1592 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1593 int where, t val) \ 1594 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1595 1596 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1597 _PCI_NOP(o, word, u16 x) \ 1598 _PCI_NOP(o, dword, u32 x) 1599 _PCI_NOP_ALL(read, *) 1600 _PCI_NOP_ALL(write,) 1601 1602 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1603 unsigned int device, 1604 struct pci_dev *from) 1605 { return NULL; } 1606 1607 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1608 unsigned int device, 1609 unsigned int ss_vendor, 1610 unsigned int ss_device, 1611 struct pci_dev *from) 1612 { return NULL; } 1613 1614 static inline struct pci_dev *pci_get_class(unsigned int class, 1615 struct pci_dev *from) 1616 { return NULL; } 1617 1618 #define pci_dev_present(ids) (0) 1619 #define no_pci_devices() (1) 1620 #define pci_dev_put(dev) do { } while (0) 1621 1622 static inline void pci_set_master(struct pci_dev *dev) { } 1623 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1624 static inline void pci_disable_device(struct pci_dev *dev) { } 1625 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1626 { return -EBUSY; } 1627 static inline int __pci_register_driver(struct pci_driver *drv, 1628 struct module *owner) 1629 { return 0; } 1630 static inline int pci_register_driver(struct pci_driver *drv) 1631 { return 0; } 1632 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1633 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1634 { return 0; } 1635 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1636 int cap) 1637 { return 0; } 1638 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1639 { return 0; } 1640 1641 /* Power management related routines */ 1642 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1643 static inline void pci_restore_state(struct pci_dev *dev) { } 1644 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1645 { return 0; } 1646 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1647 { return 0; } 1648 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1649 pm_message_t state) 1650 { return PCI_D0; } 1651 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1652 int enable) 1653 { return 0; } 1654 1655 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1656 struct resource *res) 1657 { return NULL; } 1658 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1659 { return -EIO; } 1660 static inline void pci_release_regions(struct pci_dev *dev) { } 1661 1662 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1663 1664 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1665 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1666 { return 0; } 1667 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1668 1669 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1670 { return NULL; } 1671 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1672 unsigned int devfn) 1673 { return NULL; } 1674 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1675 unsigned int devfn) 1676 { return NULL; } 1677 1678 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1679 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1680 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1681 1682 #define dev_is_pci(d) (false) 1683 #define dev_is_pf(d) (false) 1684 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1685 { return false; } 1686 #endif /* CONFIG_PCI */ 1687 1688 /* Include architecture-dependent settings and functions */ 1689 1690 #include <asm/pci.h> 1691 1692 /* These two functions provide almost identical functionality. Depennding 1693 * on the architecture, one will be implemented as a wrapper around the 1694 * other (in drivers/pci/mmap.c). 1695 * 1696 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1697 * is expected to be an offset within that region. 1698 * 1699 * pci_mmap_page_range() is the legacy architecture-specific interface, 1700 * which accepts a "user visible" resource address converted by 1701 * pci_resource_to_user(), as used in the legacy mmap() interface in 1702 * /proc/bus/pci/. 1703 */ 1704 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1705 struct vm_area_struct *vma, 1706 enum pci_mmap_state mmap_state, int write_combine); 1707 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1708 struct vm_area_struct *vma, 1709 enum pci_mmap_state mmap_state, int write_combine); 1710 1711 #ifndef arch_can_pci_mmap_wc 1712 #define arch_can_pci_mmap_wc() 0 1713 #endif 1714 1715 #ifndef arch_can_pci_mmap_io 1716 #define arch_can_pci_mmap_io() 0 1717 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1718 #else 1719 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1720 #endif 1721 1722 #ifndef pci_root_bus_fwnode 1723 #define pci_root_bus_fwnode(bus) NULL 1724 #endif 1725 1726 /* these helpers provide future and backwards compatibility 1727 * for accessing popular PCI BAR info */ 1728 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1729 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1730 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1731 #define pci_resource_len(dev,bar) \ 1732 ((pci_resource_start((dev), (bar)) == 0 && \ 1733 pci_resource_end((dev), (bar)) == \ 1734 pci_resource_start((dev), (bar))) ? 0 : \ 1735 \ 1736 (pci_resource_end((dev), (bar)) - \ 1737 pci_resource_start((dev), (bar)) + 1)) 1738 1739 /* Similar to the helpers above, these manipulate per-pci_dev 1740 * driver-specific data. They are really just a wrapper around 1741 * the generic device structure functions of these calls. 1742 */ 1743 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1744 { 1745 return dev_get_drvdata(&pdev->dev); 1746 } 1747 1748 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1749 { 1750 dev_set_drvdata(&pdev->dev, data); 1751 } 1752 1753 /* If you want to know what to call your pci_dev, ask this function. 1754 * Again, it's a wrapper around the generic device. 1755 */ 1756 static inline const char *pci_name(const struct pci_dev *pdev) 1757 { 1758 return dev_name(&pdev->dev); 1759 } 1760 1761 1762 /* Some archs don't want to expose struct resource to userland as-is 1763 * in sysfs and /proc 1764 */ 1765 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1766 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1767 const struct resource *rsrc, 1768 resource_size_t *start, resource_size_t *end); 1769 #else 1770 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1771 const struct resource *rsrc, resource_size_t *start, 1772 resource_size_t *end) 1773 { 1774 *start = rsrc->start; 1775 *end = rsrc->end; 1776 } 1777 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1778 1779 1780 /* 1781 * The world is not perfect and supplies us with broken PCI devices. 1782 * For at least a part of these bugs we need a work-around, so both 1783 * generic (drivers/pci/quirks.c) and per-architecture code can define 1784 * fixup hooks to be called for particular buggy devices. 1785 */ 1786 1787 struct pci_fixup { 1788 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1789 u16 device; /* You can use PCI_ANY_ID here of course */ 1790 u32 class; /* You can use PCI_ANY_ID here too */ 1791 unsigned int class_shift; /* should be 0, 8, 16 */ 1792 void (*hook)(struct pci_dev *dev); 1793 }; 1794 1795 enum pci_fixup_pass { 1796 pci_fixup_early, /* Before probing BARs */ 1797 pci_fixup_header, /* After reading configuration header */ 1798 pci_fixup_final, /* Final phase of device fixups */ 1799 pci_fixup_enable, /* pci_enable_device() time */ 1800 pci_fixup_resume, /* pci_device_resume() */ 1801 pci_fixup_suspend, /* pci_device_suspend() */ 1802 pci_fixup_resume_early, /* pci_device_resume_early() */ 1803 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1804 }; 1805 1806 /* Anonymous variables would be nice... */ 1807 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1808 class_shift, hook) \ 1809 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1810 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1811 = { vendor, device, class, class_shift, hook }; 1812 1813 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1814 class_shift, hook) \ 1815 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1816 hook, vendor, device, class, class_shift, hook) 1817 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1818 class_shift, hook) \ 1819 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1820 hook, vendor, device, class, class_shift, hook) 1821 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1822 class_shift, hook) \ 1823 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1824 hook, vendor, device, class, class_shift, hook) 1825 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1826 class_shift, hook) \ 1827 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1828 hook, vendor, device, class, class_shift, hook) 1829 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1830 class_shift, hook) \ 1831 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1832 resume##hook, vendor, device, class, \ 1833 class_shift, hook) 1834 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1835 class_shift, hook) \ 1836 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1837 resume_early##hook, vendor, device, \ 1838 class, class_shift, hook) 1839 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1840 class_shift, hook) \ 1841 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1842 suspend##hook, vendor, device, class, \ 1843 class_shift, hook) 1844 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1845 class_shift, hook) \ 1846 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1847 suspend_late##hook, vendor, device, \ 1848 class, class_shift, hook) 1849 1850 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1851 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1852 hook, vendor, device, PCI_ANY_ID, 0, hook) 1853 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1854 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1855 hook, vendor, device, PCI_ANY_ID, 0, hook) 1856 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1857 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1858 hook, vendor, device, PCI_ANY_ID, 0, hook) 1859 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1860 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1861 hook, vendor, device, PCI_ANY_ID, 0, hook) 1862 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1864 resume##hook, vendor, device, \ 1865 PCI_ANY_ID, 0, hook) 1866 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1868 resume_early##hook, vendor, device, \ 1869 PCI_ANY_ID, 0, hook) 1870 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1871 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1872 suspend##hook, vendor, device, \ 1873 PCI_ANY_ID, 0, hook) 1874 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1875 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1876 suspend_late##hook, vendor, device, \ 1877 PCI_ANY_ID, 0, hook) 1878 1879 #ifdef CONFIG_PCI_QUIRKS 1880 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1881 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1882 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1883 #else 1884 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1885 struct pci_dev *dev) { } 1886 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1887 u16 acs_flags) 1888 { 1889 return -ENOTTY; 1890 } 1891 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1892 { 1893 return -ENOTTY; 1894 } 1895 #endif 1896 1897 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1898 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1899 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1900 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1901 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1902 const char *name); 1903 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1904 1905 extern int pci_pci_problems; 1906 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1907 #define PCIPCI_TRITON 2 1908 #define PCIPCI_NATOMA 4 1909 #define PCIPCI_VIAETBF 8 1910 #define PCIPCI_VSFX 16 1911 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1912 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1913 1914 extern unsigned long pci_cardbus_io_size; 1915 extern unsigned long pci_cardbus_mem_size; 1916 extern u8 pci_dfl_cache_line_size; 1917 extern u8 pci_cache_line_size; 1918 1919 extern unsigned long pci_hotplug_io_size; 1920 extern unsigned long pci_hotplug_mem_size; 1921 extern unsigned long pci_hotplug_bus_size; 1922 1923 /* Architecture-specific versions may override these (weak) */ 1924 void pcibios_disable_device(struct pci_dev *dev); 1925 void pcibios_set_master(struct pci_dev *dev); 1926 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1927 enum pcie_reset_state state); 1928 int pcibios_add_device(struct pci_dev *dev); 1929 void pcibios_release_device(struct pci_dev *dev); 1930 void pcibios_penalize_isa_irq(int irq, int active); 1931 int pcibios_alloc_irq(struct pci_dev *dev); 1932 void pcibios_free_irq(struct pci_dev *dev); 1933 1934 #ifdef CONFIG_HIBERNATE_CALLBACKS 1935 extern struct dev_pm_ops pcibios_pm_ops; 1936 #endif 1937 1938 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1939 void __init pci_mmcfg_early_init(void); 1940 void __init pci_mmcfg_late_init(void); 1941 #else 1942 static inline void pci_mmcfg_early_init(void) { } 1943 static inline void pci_mmcfg_late_init(void) { } 1944 #endif 1945 1946 int pci_ext_cfg_avail(void); 1947 1948 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1949 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1950 1951 #ifdef CONFIG_PCI_IOV 1952 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1953 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1954 1955 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1956 void pci_disable_sriov(struct pci_dev *dev); 1957 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 1958 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 1959 int pci_num_vf(struct pci_dev *dev); 1960 int pci_vfs_assigned(struct pci_dev *dev); 1961 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1962 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1963 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1964 #else 1965 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1966 { 1967 return -ENOSYS; 1968 } 1969 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1970 { 1971 return -ENOSYS; 1972 } 1973 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1974 { return -ENODEV; } 1975 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 1976 { 1977 return -ENOSYS; 1978 } 1979 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 1980 int id) { } 1981 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1982 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1983 static inline int pci_vfs_assigned(struct pci_dev *dev) 1984 { return 0; } 1985 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1986 { return 0; } 1987 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1988 { return 0; } 1989 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1990 { return 0; } 1991 #endif 1992 1993 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1994 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1995 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1996 #endif 1997 1998 /** 1999 * pci_pcie_cap - get the saved PCIe capability offset 2000 * @dev: PCI device 2001 * 2002 * PCIe capability offset is calculated at PCI device initialization 2003 * time and saved in the data structure. This function returns saved 2004 * PCIe capability offset. Using this instead of pci_find_capability() 2005 * reduces unnecessary search in the PCI configuration space. If you 2006 * need to calculate PCIe capability offset from raw device for some 2007 * reasons, please use pci_find_capability() instead. 2008 */ 2009 static inline int pci_pcie_cap(struct pci_dev *dev) 2010 { 2011 return dev->pcie_cap; 2012 } 2013 2014 /** 2015 * pci_is_pcie - check if the PCI device is PCI Express capable 2016 * @dev: PCI device 2017 * 2018 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2019 */ 2020 static inline bool pci_is_pcie(struct pci_dev *dev) 2021 { 2022 return pci_pcie_cap(dev); 2023 } 2024 2025 /** 2026 * pcie_caps_reg - get the PCIe Capabilities Register 2027 * @dev: PCI device 2028 */ 2029 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2030 { 2031 return dev->pcie_flags_reg; 2032 } 2033 2034 /** 2035 * pci_pcie_type - get the PCIe device/port type 2036 * @dev: PCI device 2037 */ 2038 static inline int pci_pcie_type(const struct pci_dev *dev) 2039 { 2040 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2041 } 2042 2043 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2044 { 2045 while (1) { 2046 if (!pci_is_pcie(dev)) 2047 break; 2048 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2049 return dev; 2050 if (!dev->bus->self) 2051 break; 2052 dev = dev->bus->self; 2053 } 2054 return NULL; 2055 } 2056 2057 void pci_request_acs(void); 2058 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2059 bool pci_acs_path_enabled(struct pci_dev *start, 2060 struct pci_dev *end, u16 acs_flags); 2061 2062 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2063 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2064 2065 /* Large Resource Data Type Tag Item Names */ 2066 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2067 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2068 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2069 2070 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2071 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2072 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2073 2074 /* Small Resource Data Type Tag Item Names */ 2075 #define PCI_VPD_STIN_END 0x0f /* End */ 2076 2077 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2078 2079 #define PCI_VPD_SRDT_TIN_MASK 0x78 2080 #define PCI_VPD_SRDT_LEN_MASK 0x07 2081 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2082 2083 #define PCI_VPD_LRDT_TAG_SIZE 3 2084 #define PCI_VPD_SRDT_TAG_SIZE 1 2085 2086 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2087 2088 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2089 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2090 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2091 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2092 2093 /** 2094 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2095 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2096 * 2097 * Returns the extracted Large Resource Data Type length. 2098 */ 2099 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2100 { 2101 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2102 } 2103 2104 /** 2105 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2106 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2107 * 2108 * Returns the extracted Large Resource Data Type Tag item. 2109 */ 2110 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2111 { 2112 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2113 } 2114 2115 /** 2116 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2117 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2118 * 2119 * Returns the extracted Small Resource Data Type length. 2120 */ 2121 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2122 { 2123 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2124 } 2125 2126 /** 2127 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2128 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2129 * 2130 * Returns the extracted Small Resource Data Type Tag Item. 2131 */ 2132 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2133 { 2134 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2135 } 2136 2137 /** 2138 * pci_vpd_info_field_size - Extracts the information field length 2139 * @lrdt: Pointer to the beginning of an information field header 2140 * 2141 * Returns the extracted information field length. 2142 */ 2143 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2144 { 2145 return info_field[2]; 2146 } 2147 2148 /** 2149 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2150 * @buf: Pointer to buffered vpd data 2151 * @off: The offset into the buffer at which to begin the search 2152 * @len: The length of the vpd buffer 2153 * @rdt: The Resource Data Type to search for 2154 * 2155 * Returns the index where the Resource Data Type was found or 2156 * -ENOENT otherwise. 2157 */ 2158 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2159 2160 /** 2161 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2162 * @buf: Pointer to buffered vpd data 2163 * @off: The offset into the buffer at which to begin the search 2164 * @len: The length of the buffer area, relative to off, in which to search 2165 * @kw: The keyword to search for 2166 * 2167 * Returns the index where the information field keyword was found or 2168 * -ENOENT otherwise. 2169 */ 2170 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2171 unsigned int len, const char *kw); 2172 2173 /* PCI <-> OF binding helpers */ 2174 #ifdef CONFIG_OF 2175 struct device_node; 2176 struct irq_domain; 2177 void pci_set_of_node(struct pci_dev *dev); 2178 void pci_release_of_node(struct pci_dev *dev); 2179 void pci_set_bus_of_node(struct pci_bus *bus); 2180 void pci_release_bus_of_node(struct pci_bus *bus); 2181 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2182 2183 /* Arch may override this (weak) */ 2184 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2185 2186 static inline struct device_node * 2187 pci_device_to_OF_node(const struct pci_dev *pdev) 2188 { 2189 return pdev ? pdev->dev.of_node : NULL; 2190 } 2191 2192 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2193 { 2194 return bus ? bus->dev.of_node : NULL; 2195 } 2196 2197 #else /* CONFIG_OF */ 2198 static inline void pci_set_of_node(struct pci_dev *dev) { } 2199 static inline void pci_release_of_node(struct pci_dev *dev) { } 2200 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2201 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2202 static inline struct device_node * 2203 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 2204 static inline struct irq_domain * 2205 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2206 #endif /* CONFIG_OF */ 2207 2208 #ifdef CONFIG_ACPI 2209 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2210 2211 void 2212 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2213 #else 2214 static inline struct irq_domain * 2215 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2216 #endif 2217 2218 #ifdef CONFIG_EEH 2219 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2220 { 2221 return pdev->dev.archdata.edev; 2222 } 2223 #endif 2224 2225 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2226 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2227 int pci_for_each_dma_alias(struct pci_dev *pdev, 2228 int (*fn)(struct pci_dev *pdev, 2229 u16 alias, void *data), void *data); 2230 2231 /* helper functions for operation of device flag */ 2232 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2233 { 2234 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2235 } 2236 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2237 { 2238 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2239 } 2240 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2241 { 2242 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2243 } 2244 2245 /** 2246 * pci_ari_enabled - query ARI forwarding status 2247 * @bus: the PCI bus 2248 * 2249 * Returns true if ARI forwarding is enabled. 2250 */ 2251 static inline bool pci_ari_enabled(struct pci_bus *bus) 2252 { 2253 return bus->self && bus->self->ari_enabled; 2254 } 2255 2256 /** 2257 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2258 * @pdev: PCI device to check 2259 * 2260 * Walk upwards from @pdev and check for each encountered bridge if it's part 2261 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2262 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2263 */ 2264 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2265 { 2266 struct pci_dev *parent = pdev; 2267 2268 if (pdev->is_thunderbolt) 2269 return true; 2270 2271 while ((parent = pci_upstream_bridge(parent))) 2272 if (parent->is_thunderbolt) 2273 return true; 2274 2275 return false; 2276 } 2277 2278 /* provide the legacy pci_dma_* API */ 2279 #include <linux/pci-dma-compat.h> 2280 2281 #endif /* LINUX_PCI_H */ 2282