1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <linux/resource_ext.h> 33 #include <uapi/linux/pci.h> 34 35 #include <linux/pci_ids.h> 36 37 /* 38 * The PCI interface treats multi-function devices as independent 39 * devices. The slot/function address of each device is encoded 40 * in a single byte as follows: 41 * 42 * 7:3 = slot 43 * 2:0 = function 44 * 45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 46 * In the interest of not exposing interfaces to user-space unnecessarily, 47 * the following kernel-only defines are being added here. 48 */ 49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 52 53 /* pci_slot represents a physical slot */ 54 struct pci_slot { 55 struct pci_bus *bus; /* The bus this slot is on */ 56 struct list_head list; /* node in list of slots on this bus */ 57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 59 struct kobject kobj; 60 }; 61 62 static inline const char *pci_slot_name(const struct pci_slot *slot) 63 { 64 return kobject_name(&slot->kobj); 65 } 66 67 /* File state for mmap()s on /proc/bus/pci/X/Y */ 68 enum pci_mmap_state { 69 pci_mmap_io, 70 pci_mmap_mem 71 }; 72 73 /* 74 * For PCI devices, the region numbers are assigned this way: 75 */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* device specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 typedef int __bitwise pci_power_t; 105 106 #define PCI_D0 ((pci_power_t __force) 0) 107 #define PCI_D1 ((pci_power_t __force) 1) 108 #define PCI_D2 ((pci_power_t __force) 2) 109 #define PCI_D3hot ((pci_power_t __force) 3) 110 #define PCI_D3cold ((pci_power_t __force) 4) 111 #define PCI_UNKNOWN ((pci_power_t __force) 5) 112 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 113 114 /* Remember to update this when the list above changes! */ 115 extern const char *pci_power_names[]; 116 117 static inline const char *pci_power_name(pci_power_t state) 118 { 119 return pci_power_names[1 + (int) state]; 120 } 121 122 #define PCI_PM_D2_DELAY 200 123 #define PCI_PM_D3_WAIT 10 124 #define PCI_PM_D3COLD_WAIT 100 125 #define PCI_PM_BUS_WAIT 50 126 127 /** The pci_channel state describes connectivity between the CPU and 128 * the pci device. If some PCI bus between here and the pci device 129 * has crashed or locked up, this info is reflected here. 130 */ 131 typedef unsigned int __bitwise pci_channel_state_t; 132 133 enum pci_channel_state { 134 /* I/O channel is in normal state */ 135 pci_channel_io_normal = (__force pci_channel_state_t) 1, 136 137 /* I/O to channel is blocked */ 138 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 139 140 /* PCI card is dead */ 141 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 142 }; 143 144 typedef unsigned int __bitwise pcie_reset_state_t; 145 146 enum pcie_reset_state { 147 /* Reset is NOT asserted (Use to deassert reset) */ 148 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 149 150 /* Use #PERST to reset PCIe device */ 151 pcie_warm_reset = (__force pcie_reset_state_t) 2, 152 153 /* Use PCIe Hot Reset to reset device */ 154 pcie_hot_reset = (__force pcie_reset_state_t) 3 155 }; 156 157 typedef unsigned short __bitwise pci_dev_flags_t; 158 enum pci_dev_flags { 159 /* INTX_DISABLE in PCI_COMMAND register disables MSI 160 * generation too. 161 */ 162 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 163 /* Device configuration is irrevocably lost if disabled into D3 */ 164 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 165 /* Provide indication device is assigned by a Virtual Machine Manager */ 166 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 167 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 168 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 169 /* Flag to indicate the device uses dma_alias_devfn */ 170 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), 171 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 172 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 173 /* Do not use bus resets for device */ 174 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 175 /* Do not use PM reset even if device advertises NoSoftRst- */ 176 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 177 /* Get VPD from function 0 VPD */ 178 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 179 }; 180 181 enum pci_irq_reroute_variant { 182 INTEL_IRQ_REROUTE_VARIANT = 1, 183 MAX_IRQ_REROUTE_VARIANTS = 3 184 }; 185 186 typedef unsigned short __bitwise pci_bus_flags_t; 187 enum pci_bus_flags { 188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 190 }; 191 192 /* These values come from the PCI Express Spec */ 193 enum pcie_link_width { 194 PCIE_LNK_WIDTH_RESRV = 0x00, 195 PCIE_LNK_X1 = 0x01, 196 PCIE_LNK_X2 = 0x02, 197 PCIE_LNK_X4 = 0x04, 198 PCIE_LNK_X8 = 0x08, 199 PCIE_LNK_X12 = 0x0C, 200 PCIE_LNK_X16 = 0x10, 201 PCIE_LNK_X32 = 0x20, 202 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 203 }; 204 205 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 206 enum pci_bus_speed { 207 PCI_SPEED_33MHz = 0x00, 208 PCI_SPEED_66MHz = 0x01, 209 PCI_SPEED_66MHz_PCIX = 0x02, 210 PCI_SPEED_100MHz_PCIX = 0x03, 211 PCI_SPEED_133MHz_PCIX = 0x04, 212 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 213 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 214 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 215 PCI_SPEED_66MHz_PCIX_266 = 0x09, 216 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 217 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 218 AGP_UNKNOWN = 0x0c, 219 AGP_1X = 0x0d, 220 AGP_2X = 0x0e, 221 AGP_4X = 0x0f, 222 AGP_8X = 0x10, 223 PCI_SPEED_66MHz_PCIX_533 = 0x11, 224 PCI_SPEED_100MHz_PCIX_533 = 0x12, 225 PCI_SPEED_133MHz_PCIX_533 = 0x13, 226 PCIE_SPEED_2_5GT = 0x14, 227 PCIE_SPEED_5_0GT = 0x15, 228 PCIE_SPEED_8_0GT = 0x16, 229 PCI_SPEED_UNKNOWN = 0xff, 230 }; 231 232 struct pci_cap_saved_data { 233 u16 cap_nr; 234 bool cap_extended; 235 unsigned int size; 236 u32 data[0]; 237 }; 238 239 struct pci_cap_saved_state { 240 struct hlist_node next; 241 struct pci_cap_saved_data cap; 242 }; 243 244 struct pcie_link_state; 245 struct pci_vpd; 246 struct pci_sriov; 247 struct pci_ats; 248 249 /* 250 * The pci_dev structure is used to describe PCI devices. 251 */ 252 struct pci_dev { 253 struct list_head bus_list; /* node in per-bus list */ 254 struct pci_bus *bus; /* bus this device is on */ 255 struct pci_bus *subordinate; /* bus this device bridges to */ 256 257 void *sysdata; /* hook for sys-specific extension */ 258 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 259 struct pci_slot *slot; /* Physical slot this device is in */ 260 261 unsigned int devfn; /* encoded device & function index */ 262 unsigned short vendor; 263 unsigned short device; 264 unsigned short subsystem_vendor; 265 unsigned short subsystem_device; 266 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 267 u8 revision; /* PCI revision, low byte of class word */ 268 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 269 u8 pcie_cap; /* PCIe capability offset */ 270 u8 msi_cap; /* MSI capability offset */ 271 u8 msix_cap; /* MSI-X capability offset */ 272 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 273 u8 rom_base_reg; /* which config register controls the ROM */ 274 u8 pin; /* which interrupt pin this device uses */ 275 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 276 u8 dma_alias_devfn;/* devfn of DMA alias, if any */ 277 278 struct pci_driver *driver; /* which driver has allocated this device */ 279 u64 dma_mask; /* Mask of the bits of bus address this 280 device implements. Normally this is 281 0xffffffff. You only need to change 282 this if your device has broken DMA 283 or supports 64-bit transfers. */ 284 285 struct device_dma_parameters dma_parms; 286 287 pci_power_t current_state; /* Current operating state. In ACPI-speak, 288 this is D0-D3, D0 being fully functional, 289 and D3 being off. */ 290 u8 pm_cap; /* PM capability offset */ 291 unsigned int pme_support:5; /* Bitmask of states from which PME# 292 can be generated */ 293 unsigned int pme_interrupt:1; 294 unsigned int pme_poll:1; /* Poll device's PME status bit */ 295 unsigned int d1_support:1; /* Low power state D1 is supported */ 296 unsigned int d2_support:1; /* Low power state D2 is supported */ 297 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 298 unsigned int no_d3cold:1; /* D3cold is forbidden */ 299 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 300 unsigned int mmio_always_on:1; /* disallow turning off io/mem 301 decoding during bar sizing */ 302 unsigned int wakeup_prepared:1; 303 unsigned int runtime_d3cold:1; /* whether go through runtime 304 D3cold, not set for devices 305 powered on/off by the 306 corresponding bridge */ 307 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 308 unsigned int d3_delay; /* D3->D0 transition time in ms */ 309 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 310 311 #ifdef CONFIG_PCIEASPM 312 struct pcie_link_state *link_state; /* ASPM link state */ 313 #endif 314 315 pci_channel_state_t error_state; /* current connectivity state */ 316 struct device dev; /* Generic device interface */ 317 318 int cfg_size; /* Size of configuration space */ 319 320 /* 321 * Instead of touching interrupt line and base address registers 322 * directly, use the values stored here. They might be different! 323 */ 324 unsigned int irq; 325 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 326 327 bool match_driver; /* Skip attaching driver */ 328 /* These fields are used by common fixups */ 329 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 330 unsigned int multifunction:1;/* Part of multi-function device */ 331 /* keep track of device state */ 332 unsigned int is_added:1; 333 unsigned int is_busmaster:1; /* device is busmaster */ 334 unsigned int no_msi:1; /* device may not use msi */ 335 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 336 unsigned int block_cfg_access:1; /* config space access is blocked */ 337 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 338 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 339 unsigned int msi_enabled:1; 340 unsigned int msix_enabled:1; 341 unsigned int ari_enabled:1; /* ARI forwarding */ 342 unsigned int ats_enabled:1; /* Address Translation Service */ 343 unsigned int is_managed:1; 344 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 345 unsigned int state_saved:1; 346 unsigned int is_physfn:1; 347 unsigned int is_virtfn:1; 348 unsigned int reset_fn:1; 349 unsigned int is_hotplug_bridge:1; 350 unsigned int __aer_firmware_first_valid:1; 351 unsigned int __aer_firmware_first:1; 352 unsigned int broken_intx_masking:1; 353 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 354 unsigned int irq_managed:1; 355 unsigned int has_secondary_link:1; 356 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 357 pci_dev_flags_t dev_flags; 358 atomic_t enable_cnt; /* pci_enable_device has been called */ 359 360 u32 saved_config_space[16]; /* config space saved at suspend time */ 361 struct hlist_head saved_cap_space; 362 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 363 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 364 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 365 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 366 #ifdef CONFIG_PCI_MSI 367 const struct attribute_group **msi_irq_groups; 368 #endif 369 struct pci_vpd *vpd; 370 #ifdef CONFIG_PCI_ATS 371 union { 372 struct pci_sriov *sriov; /* SR-IOV capability related */ 373 struct pci_dev *physfn; /* the PF this VF is associated with */ 374 }; 375 u16 ats_cap; /* ATS Capability offset */ 376 u8 ats_stu; /* ATS Smallest Translation Unit */ 377 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 378 #endif 379 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 380 size_t romlen; /* Length of ROM if it's not from the BAR */ 381 char *driver_override; /* Driver name to force a match */ 382 }; 383 384 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 385 { 386 #ifdef CONFIG_PCI_IOV 387 if (dev->is_virtfn) 388 dev = dev->physfn; 389 #endif 390 return dev; 391 } 392 393 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 394 395 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 396 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 397 398 static inline int pci_channel_offline(struct pci_dev *pdev) 399 { 400 return (pdev->error_state != pci_channel_io_normal); 401 } 402 403 struct pci_host_bridge { 404 struct device dev; 405 struct pci_bus *bus; /* root bus */ 406 struct list_head windows; /* resource_entry */ 407 void (*release_fn)(struct pci_host_bridge *); 408 void *release_data; 409 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 410 /* Resource alignment requirements */ 411 resource_size_t (*align_resource)(struct pci_dev *dev, 412 const struct resource *res, 413 resource_size_t start, 414 resource_size_t size, 415 resource_size_t align); 416 }; 417 418 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 419 420 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 421 422 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 423 void (*release_fn)(struct pci_host_bridge *), 424 void *release_data); 425 426 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 427 428 /* 429 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 430 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 431 * buses below host bridges or subtractive decode bridges) go in the list. 432 * Use pci_bus_for_each_resource() to iterate through all the resources. 433 */ 434 435 /* 436 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 437 * and there's no way to program the bridge with the details of the window. 438 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 439 * decode bit set, because they are explicit and can be programmed with _SRS. 440 */ 441 #define PCI_SUBTRACTIVE_DECODE 0x1 442 443 struct pci_bus_resource { 444 struct list_head list; 445 struct resource *res; 446 unsigned int flags; 447 }; 448 449 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 450 451 struct pci_bus { 452 struct list_head node; /* node in list of buses */ 453 struct pci_bus *parent; /* parent bus this bridge is on */ 454 struct list_head children; /* list of child buses */ 455 struct list_head devices; /* list of devices on this bus */ 456 struct pci_dev *self; /* bridge device as seen by parent */ 457 struct list_head slots; /* list of slots on this bus; 458 protected by pci_slot_mutex */ 459 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 460 struct list_head resources; /* address space routed to this bus */ 461 struct resource busn_res; /* bus numbers routed to this bus */ 462 463 struct pci_ops *ops; /* configuration access functions */ 464 struct msi_controller *msi; /* MSI controller */ 465 void *sysdata; /* hook for sys-specific extension */ 466 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 467 468 unsigned char number; /* bus number */ 469 unsigned char primary; /* number of primary bridge */ 470 unsigned char max_bus_speed; /* enum pci_bus_speed */ 471 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 472 #ifdef CONFIG_PCI_DOMAINS_GENERIC 473 int domain_nr; 474 #endif 475 476 char name[48]; 477 478 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 479 pci_bus_flags_t bus_flags; /* inherited by child buses */ 480 struct device *bridge; 481 struct device dev; 482 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 483 struct bin_attribute *legacy_mem; /* legacy mem */ 484 unsigned int is_added:1; 485 }; 486 487 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 488 489 /* 490 * Returns true if the PCI bus is root (behind host-PCI bridge), 491 * false otherwise 492 * 493 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 494 * This is incorrect because "virtual" buses added for SR-IOV (via 495 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 496 */ 497 static inline bool pci_is_root_bus(struct pci_bus *pbus) 498 { 499 return !(pbus->parent); 500 } 501 502 /** 503 * pci_is_bridge - check if the PCI device is a bridge 504 * @dev: PCI device 505 * 506 * Return true if the PCI device is bridge whether it has subordinate 507 * or not. 508 */ 509 static inline bool pci_is_bridge(struct pci_dev *dev) 510 { 511 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 512 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 513 } 514 515 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 516 { 517 dev = pci_physfn(dev); 518 if (pci_is_root_bus(dev->bus)) 519 return NULL; 520 521 return dev->bus->self; 522 } 523 524 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 525 void pci_put_host_bridge_device(struct device *dev); 526 527 #ifdef CONFIG_PCI_MSI 528 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 529 { 530 return pci_dev->msi_enabled || pci_dev->msix_enabled; 531 } 532 #else 533 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 534 #endif 535 536 /* 537 * Error values that may be returned by PCI functions. 538 */ 539 #define PCIBIOS_SUCCESSFUL 0x00 540 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 541 #define PCIBIOS_BAD_VENDOR_ID 0x83 542 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 543 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 544 #define PCIBIOS_SET_FAILED 0x88 545 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 546 547 /* 548 * Translate above to generic errno for passing back through non-PCI code. 549 */ 550 static inline int pcibios_err_to_errno(int err) 551 { 552 if (err <= PCIBIOS_SUCCESSFUL) 553 return err; /* Assume already errno */ 554 555 switch (err) { 556 case PCIBIOS_FUNC_NOT_SUPPORTED: 557 return -ENOENT; 558 case PCIBIOS_BAD_VENDOR_ID: 559 return -ENOTTY; 560 case PCIBIOS_DEVICE_NOT_FOUND: 561 return -ENODEV; 562 case PCIBIOS_BAD_REGISTER_NUMBER: 563 return -EFAULT; 564 case PCIBIOS_SET_FAILED: 565 return -EIO; 566 case PCIBIOS_BUFFER_TOO_SMALL: 567 return -ENOSPC; 568 } 569 570 return -ERANGE; 571 } 572 573 /* Low-level architecture-dependent routines */ 574 575 struct pci_ops { 576 int (*add_bus)(struct pci_bus *bus); 577 void (*remove_bus)(struct pci_bus *bus); 578 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 579 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 580 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 581 }; 582 583 /* 584 * ACPI needs to be able to access PCI config space before we've done a 585 * PCI bus scan and created pci_bus structures. 586 */ 587 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 588 int reg, int len, u32 *val); 589 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 590 int reg, int len, u32 val); 591 592 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 593 typedef u64 pci_bus_addr_t; 594 #else 595 typedef u32 pci_bus_addr_t; 596 #endif 597 598 struct pci_bus_region { 599 pci_bus_addr_t start; 600 pci_bus_addr_t end; 601 }; 602 603 struct pci_dynids { 604 spinlock_t lock; /* protects list, index */ 605 struct list_head list; /* for IDs added at runtime */ 606 }; 607 608 609 /* 610 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 611 * a set of callbacks in struct pci_error_handlers, that device driver 612 * will be notified of PCI bus errors, and will be driven to recovery 613 * when an error occurs. 614 */ 615 616 typedef unsigned int __bitwise pci_ers_result_t; 617 618 enum pci_ers_result { 619 /* no result/none/not supported in device driver */ 620 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 621 622 /* Device driver can recover without slot reset */ 623 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 624 625 /* Device driver wants slot to be reset. */ 626 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 627 628 /* Device has completely failed, is unrecoverable */ 629 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 630 631 /* Device driver is fully recovered and operational */ 632 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 633 634 /* No AER capabilities registered for the driver */ 635 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 636 }; 637 638 /* PCI bus error event callbacks */ 639 struct pci_error_handlers { 640 /* PCI bus error detected on this device */ 641 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 642 enum pci_channel_state error); 643 644 /* MMIO has been re-enabled, but not DMA */ 645 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 646 647 /* PCI Express link has been reset */ 648 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 649 650 /* PCI slot has been reset */ 651 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 652 653 /* PCI function reset prepare or completed */ 654 void (*reset_notify)(struct pci_dev *dev, bool prepare); 655 656 /* Device driver may resume normal operations */ 657 void (*resume)(struct pci_dev *dev); 658 }; 659 660 661 struct module; 662 struct pci_driver { 663 struct list_head node; 664 const char *name; 665 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 666 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 667 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 668 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 669 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 670 int (*resume_early) (struct pci_dev *dev); 671 int (*resume) (struct pci_dev *dev); /* Device woken up */ 672 void (*shutdown) (struct pci_dev *dev); 673 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 674 const struct pci_error_handlers *err_handler; 675 struct device_driver driver; 676 struct pci_dynids dynids; 677 }; 678 679 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 680 681 /** 682 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 683 * @_table: device table name 684 * 685 * This macro is deprecated and should not be used in new code. 686 */ 687 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 688 const struct pci_device_id _table[] 689 690 /** 691 * PCI_DEVICE - macro used to describe a specific pci device 692 * @vend: the 16 bit PCI Vendor ID 693 * @dev: the 16 bit PCI Device ID 694 * 695 * This macro is used to create a struct pci_device_id that matches a 696 * specific device. The subvendor and subdevice fields will be set to 697 * PCI_ANY_ID. 698 */ 699 #define PCI_DEVICE(vend,dev) \ 700 .vendor = (vend), .device = (dev), \ 701 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 702 703 /** 704 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 705 * @vend: the 16 bit PCI Vendor ID 706 * @dev: the 16 bit PCI Device ID 707 * @subvend: the 16 bit PCI Subvendor ID 708 * @subdev: the 16 bit PCI Subdevice ID 709 * 710 * This macro is used to create a struct pci_device_id that matches a 711 * specific device with subsystem information. 712 */ 713 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 714 .vendor = (vend), .device = (dev), \ 715 .subvendor = (subvend), .subdevice = (subdev) 716 717 /** 718 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 719 * @dev_class: the class, subclass, prog-if triple for this device 720 * @dev_class_mask: the class mask for this device 721 * 722 * This macro is used to create a struct pci_device_id that matches a 723 * specific PCI class. The vendor, device, subvendor, and subdevice 724 * fields will be set to PCI_ANY_ID. 725 */ 726 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 727 .class = (dev_class), .class_mask = (dev_class_mask), \ 728 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 729 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 730 731 /** 732 * PCI_VDEVICE - macro used to describe a specific pci device in short form 733 * @vend: the vendor name 734 * @dev: the 16 bit PCI Device ID 735 * 736 * This macro is used to create a struct pci_device_id that matches a 737 * specific PCI device. The subvendor, and subdevice fields will be set 738 * to PCI_ANY_ID. The macro allows the next field to follow as the device 739 * private data. 740 */ 741 742 #define PCI_VDEVICE(vend, dev) \ 743 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 744 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 745 746 enum { 747 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ 748 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ 749 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ 750 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ 751 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ 752 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 753 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ 754 }; 755 756 /* these external functions are only available when PCI support is enabled */ 757 #ifdef CONFIG_PCI 758 759 extern unsigned int pci_flags; 760 761 static inline void pci_set_flags(int flags) { pci_flags = flags; } 762 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 763 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 764 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 765 766 void pcie_bus_configure_settings(struct pci_bus *bus); 767 768 enum pcie_bus_config_types { 769 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 770 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 771 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 772 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 773 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 774 }; 775 776 extern enum pcie_bus_config_types pcie_bus_config; 777 778 extern struct bus_type pci_bus_type; 779 780 /* Do NOT directly access these two variables, unless you are arch-specific PCI 781 * code, or PCI core code. */ 782 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 783 /* Some device drivers need know if PCI is initiated */ 784 int no_pci_devices(void); 785 786 void pcibios_resource_survey_bus(struct pci_bus *bus); 787 void pcibios_bus_add_device(struct pci_dev *pdev); 788 void pcibios_add_bus(struct pci_bus *bus); 789 void pcibios_remove_bus(struct pci_bus *bus); 790 void pcibios_fixup_bus(struct pci_bus *); 791 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 792 /* Architecture-specific versions may override this (weak) */ 793 char *pcibios_setup(char *str); 794 795 /* Used only when drivers/pci/setup.c is used */ 796 resource_size_t pcibios_align_resource(void *, const struct resource *, 797 resource_size_t, 798 resource_size_t); 799 void pcibios_update_irq(struct pci_dev *, int irq); 800 801 /* Weak but can be overriden by arch */ 802 void pci_fixup_cardbus(struct pci_bus *); 803 804 /* Generic PCI functions used internally */ 805 806 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 807 struct resource *res); 808 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 809 struct pci_bus_region *region); 810 void pcibios_scan_specific_bus(int busn); 811 struct pci_bus *pci_find_bus(int domain, int busnr); 812 void pci_bus_add_devices(const struct pci_bus *bus); 813 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 814 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 815 struct pci_ops *ops, void *sysdata, 816 struct list_head *resources); 817 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 818 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 819 void pci_bus_release_busn_res(struct pci_bus *b); 820 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, 821 struct pci_ops *ops, void *sysdata, 822 struct list_head *resources, 823 struct msi_controller *msi); 824 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 825 struct pci_ops *ops, void *sysdata, 826 struct list_head *resources); 827 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 828 int busnr); 829 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 830 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 831 const char *name, 832 struct hotplug_slot *hotplug); 833 void pci_destroy_slot(struct pci_slot *slot); 834 #ifdef CONFIG_SYSFS 835 void pci_dev_assign_slot(struct pci_dev *dev); 836 #else 837 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 838 #endif 839 int pci_scan_slot(struct pci_bus *bus, int devfn); 840 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 841 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 842 unsigned int pci_scan_child_bus(struct pci_bus *bus); 843 void pci_bus_add_device(struct pci_dev *dev); 844 void pci_read_bridge_bases(struct pci_bus *child); 845 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 846 struct resource *res); 847 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 848 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 849 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 850 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 851 struct pci_dev *pci_dev_get(struct pci_dev *dev); 852 void pci_dev_put(struct pci_dev *dev); 853 void pci_remove_bus(struct pci_bus *b); 854 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 855 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 856 void pci_stop_root_bus(struct pci_bus *bus); 857 void pci_remove_root_bus(struct pci_bus *bus); 858 void pci_setup_cardbus(struct pci_bus *bus); 859 void pci_sort_breadthfirst(void); 860 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 861 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 862 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 863 864 /* Generic PCI functions exported to card drivers */ 865 866 enum pci_lost_interrupt_reason { 867 PCI_LOST_IRQ_NO_INFORMATION = 0, 868 PCI_LOST_IRQ_DISABLE_MSI, 869 PCI_LOST_IRQ_DISABLE_MSIX, 870 PCI_LOST_IRQ_DISABLE_ACPI, 871 }; 872 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 873 int pci_find_capability(struct pci_dev *dev, int cap); 874 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 875 int pci_find_ext_capability(struct pci_dev *dev, int cap); 876 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 877 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 878 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 879 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 880 881 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 882 struct pci_dev *from); 883 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 884 unsigned int ss_vendor, unsigned int ss_device, 885 struct pci_dev *from); 886 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 887 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 888 unsigned int devfn); 889 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 890 unsigned int devfn) 891 { 892 return pci_get_domain_bus_and_slot(0, bus, devfn); 893 } 894 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 895 int pci_dev_present(const struct pci_device_id *ids); 896 897 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 898 int where, u8 *val); 899 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 900 int where, u16 *val); 901 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 902 int where, u32 *val); 903 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 904 int where, u8 val); 905 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 906 int where, u16 val); 907 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 908 int where, u32 val); 909 910 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 911 int where, int size, u32 *val); 912 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 913 int where, int size, u32 val); 914 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 915 int where, int size, u32 *val); 916 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 917 int where, int size, u32 val); 918 919 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 920 921 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 922 { 923 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 924 } 925 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 926 { 927 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 928 } 929 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 930 u32 *val) 931 { 932 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 933 } 934 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 935 { 936 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 937 } 938 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 939 { 940 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 941 } 942 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 943 u32 val) 944 { 945 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 946 } 947 948 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 949 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 950 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 951 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 952 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 953 u16 clear, u16 set); 954 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 955 u32 clear, u32 set); 956 957 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 958 u16 set) 959 { 960 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 961 } 962 963 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 964 u32 set) 965 { 966 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 967 } 968 969 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 970 u16 clear) 971 { 972 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 973 } 974 975 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 976 u32 clear) 977 { 978 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 979 } 980 981 /* user-space driven config access */ 982 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 983 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 984 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 985 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 986 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 987 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 988 989 int __must_check pci_enable_device(struct pci_dev *dev); 990 int __must_check pci_enable_device_io(struct pci_dev *dev); 991 int __must_check pci_enable_device_mem(struct pci_dev *dev); 992 int __must_check pci_reenable_device(struct pci_dev *); 993 int __must_check pcim_enable_device(struct pci_dev *pdev); 994 void pcim_pin_device(struct pci_dev *pdev); 995 996 static inline int pci_is_enabled(struct pci_dev *pdev) 997 { 998 return (atomic_read(&pdev->enable_cnt) > 0); 999 } 1000 1001 static inline int pci_is_managed(struct pci_dev *pdev) 1002 { 1003 return pdev->is_managed; 1004 } 1005 1006 void pci_disable_device(struct pci_dev *dev); 1007 1008 extern unsigned int pcibios_max_latency; 1009 void pci_set_master(struct pci_dev *dev); 1010 void pci_clear_master(struct pci_dev *dev); 1011 1012 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1013 int pci_set_cacheline_size(struct pci_dev *dev); 1014 #define HAVE_PCI_SET_MWI 1015 int __must_check pci_set_mwi(struct pci_dev *dev); 1016 int pci_try_set_mwi(struct pci_dev *dev); 1017 void pci_clear_mwi(struct pci_dev *dev); 1018 void pci_intx(struct pci_dev *dev, int enable); 1019 bool pci_intx_mask_supported(struct pci_dev *dev); 1020 bool pci_check_and_mask_intx(struct pci_dev *dev); 1021 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1022 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1023 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1024 int pcix_get_max_mmrbc(struct pci_dev *dev); 1025 int pcix_get_mmrbc(struct pci_dev *dev); 1026 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1027 int pcie_get_readrq(struct pci_dev *dev); 1028 int pcie_set_readrq(struct pci_dev *dev, int rq); 1029 int pcie_get_mps(struct pci_dev *dev); 1030 int pcie_set_mps(struct pci_dev *dev, int mps); 1031 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1032 enum pcie_link_width *width); 1033 int __pci_reset_function(struct pci_dev *dev); 1034 int __pci_reset_function_locked(struct pci_dev *dev); 1035 int pci_reset_function(struct pci_dev *dev); 1036 int pci_try_reset_function(struct pci_dev *dev); 1037 int pci_probe_reset_slot(struct pci_slot *slot); 1038 int pci_reset_slot(struct pci_slot *slot); 1039 int pci_try_reset_slot(struct pci_slot *slot); 1040 int pci_probe_reset_bus(struct pci_bus *bus); 1041 int pci_reset_bus(struct pci_bus *bus); 1042 int pci_try_reset_bus(struct pci_bus *bus); 1043 void pci_reset_secondary_bus(struct pci_dev *dev); 1044 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1045 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1046 void pci_update_resource(struct pci_dev *dev, int resno); 1047 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1048 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1049 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1050 bool pci_device_is_present(struct pci_dev *pdev); 1051 void pci_ignore_hotplug(struct pci_dev *dev); 1052 1053 /* ROM control related routines */ 1054 int pci_enable_rom(struct pci_dev *pdev); 1055 void pci_disable_rom(struct pci_dev *pdev); 1056 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1057 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1058 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1059 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1060 1061 /* Power management related routines */ 1062 int pci_save_state(struct pci_dev *dev); 1063 void pci_restore_state(struct pci_dev *dev); 1064 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1065 int pci_load_saved_state(struct pci_dev *dev, 1066 struct pci_saved_state *state); 1067 int pci_load_and_free_saved_state(struct pci_dev *dev, 1068 struct pci_saved_state **state); 1069 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1070 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1071 u16 cap); 1072 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1073 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1074 u16 cap, unsigned int size); 1075 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1076 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1077 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1078 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1079 void pci_pme_active(struct pci_dev *dev, bool enable); 1080 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1081 bool runtime, bool enable); 1082 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1083 int pci_prepare_to_sleep(struct pci_dev *dev); 1084 int pci_back_from_sleep(struct pci_dev *dev); 1085 bool pci_dev_run_wake(struct pci_dev *dev); 1086 bool pci_check_pme_status(struct pci_dev *dev); 1087 void pci_pme_wakeup_bus(struct pci_bus *bus); 1088 1089 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1090 bool enable) 1091 { 1092 return __pci_enable_wake(dev, state, false, enable); 1093 } 1094 1095 /* PCI Virtual Channel */ 1096 int pci_save_vc_state(struct pci_dev *dev); 1097 void pci_restore_vc_state(struct pci_dev *dev); 1098 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1099 1100 /* For use by arch with custom probe code */ 1101 void set_pcie_port_type(struct pci_dev *pdev); 1102 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1103 1104 /* Functions for PCI Hotplug drivers to use */ 1105 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1106 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1107 unsigned int pci_rescan_bus(struct pci_bus *bus); 1108 void pci_lock_rescan_remove(void); 1109 void pci_unlock_rescan_remove(void); 1110 1111 /* Vital product data routines */ 1112 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1113 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1114 1115 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1116 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1117 void pci_bus_assign_resources(const struct pci_bus *bus); 1118 void pci_bus_size_bridges(struct pci_bus *bus); 1119 int pci_claim_resource(struct pci_dev *, int); 1120 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1121 void pci_assign_unassigned_resources(void); 1122 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1123 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1124 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1125 void pdev_enable_device(struct pci_dev *); 1126 int pci_enable_resources(struct pci_dev *, int mask); 1127 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1128 int (*)(const struct pci_dev *, u8, u8)); 1129 #define HAVE_PCI_REQ_REGIONS 2 1130 int __must_check pci_request_regions(struct pci_dev *, const char *); 1131 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1132 void pci_release_regions(struct pci_dev *); 1133 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1134 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1135 void pci_release_region(struct pci_dev *, int); 1136 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1137 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1138 void pci_release_selected_regions(struct pci_dev *, int); 1139 1140 /* drivers/pci/bus.c */ 1141 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1142 void pci_bus_put(struct pci_bus *bus); 1143 void pci_add_resource(struct list_head *resources, struct resource *res); 1144 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1145 resource_size_t offset); 1146 void pci_free_resource_list(struct list_head *resources); 1147 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1148 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1149 void pci_bus_remove_resources(struct pci_bus *bus); 1150 1151 #define pci_bus_for_each_resource(bus, res, i) \ 1152 for (i = 0; \ 1153 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1154 i++) 1155 1156 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1157 struct resource *res, resource_size_t size, 1158 resource_size_t align, resource_size_t min, 1159 unsigned long type_mask, 1160 resource_size_t (*alignf)(void *, 1161 const struct resource *, 1162 resource_size_t, 1163 resource_size_t), 1164 void *alignf_data); 1165 1166 1167 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1168 1169 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1170 { 1171 struct pci_bus_region region; 1172 1173 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1174 return region.start; 1175 } 1176 1177 /* Proper probing supporting hot-pluggable devices */ 1178 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1179 const char *mod_name); 1180 1181 /* 1182 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1183 */ 1184 #define pci_register_driver(driver) \ 1185 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1186 1187 void pci_unregister_driver(struct pci_driver *dev); 1188 1189 /** 1190 * module_pci_driver() - Helper macro for registering a PCI driver 1191 * @__pci_driver: pci_driver struct 1192 * 1193 * Helper macro for PCI drivers which do not do anything special in module 1194 * init/exit. This eliminates a lot of boilerplate. Each module may only 1195 * use this macro once, and calling it replaces module_init() and module_exit() 1196 */ 1197 #define module_pci_driver(__pci_driver) \ 1198 module_driver(__pci_driver, pci_register_driver, \ 1199 pci_unregister_driver) 1200 1201 /** 1202 * builtin_pci_driver() - Helper macro for registering a PCI driver 1203 * @__pci_driver: pci_driver struct 1204 * 1205 * Helper macro for PCI drivers which do not do anything special in their 1206 * init code. This eliminates a lot of boilerplate. Each driver may only 1207 * use this macro once, and calling it replaces device_initcall(...) 1208 */ 1209 #define builtin_pci_driver(__pci_driver) \ 1210 builtin_driver(__pci_driver, pci_register_driver) 1211 1212 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1213 int pci_add_dynid(struct pci_driver *drv, 1214 unsigned int vendor, unsigned int device, 1215 unsigned int subvendor, unsigned int subdevice, 1216 unsigned int class, unsigned int class_mask, 1217 unsigned long driver_data); 1218 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1219 struct pci_dev *dev); 1220 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1221 int pass); 1222 1223 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1224 void *userdata); 1225 int pci_cfg_space_size(struct pci_dev *dev); 1226 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1227 void pci_setup_bridge(struct pci_bus *bus); 1228 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1229 unsigned long type); 1230 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1231 1232 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1233 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1234 1235 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1236 unsigned int command_bits, u32 flags); 1237 1238 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1239 1240 #include <linux/pci-dma.h> 1241 #include <linux/dmapool.h> 1242 1243 #define pci_pool dma_pool 1244 #define pci_pool_create(name, pdev, size, align, allocation) \ 1245 dma_pool_create(name, &pdev->dev, size, align, allocation) 1246 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1247 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1248 #define pci_pool_zalloc(pool, flags, handle) \ 1249 dma_pool_zalloc(pool, flags, handle) 1250 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1251 1252 struct msix_entry { 1253 u32 vector; /* kernel uses to write allocated vector */ 1254 u16 entry; /* driver uses to specify entry, OS writes */ 1255 }; 1256 1257 #ifdef CONFIG_PCI_MSI 1258 int pci_msi_vec_count(struct pci_dev *dev); 1259 void pci_msi_shutdown(struct pci_dev *dev); 1260 void pci_disable_msi(struct pci_dev *dev); 1261 int pci_msix_vec_count(struct pci_dev *dev); 1262 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1263 void pci_msix_shutdown(struct pci_dev *dev); 1264 void pci_disable_msix(struct pci_dev *dev); 1265 void pci_restore_msi_state(struct pci_dev *dev); 1266 int pci_msi_enabled(void); 1267 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1268 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1269 { 1270 int rc = pci_enable_msi_range(dev, nvec, nvec); 1271 if (rc < 0) 1272 return rc; 1273 return 0; 1274 } 1275 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1276 int minvec, int maxvec); 1277 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1278 struct msix_entry *entries, int nvec) 1279 { 1280 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1281 if (rc < 0) 1282 return rc; 1283 return 0; 1284 } 1285 #else 1286 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1287 static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1288 static inline void pci_disable_msi(struct pci_dev *dev) { } 1289 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1290 static inline int pci_enable_msix(struct pci_dev *dev, 1291 struct msix_entry *entries, int nvec) 1292 { return -ENOSYS; } 1293 static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1294 static inline void pci_disable_msix(struct pci_dev *dev) { } 1295 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1296 static inline int pci_msi_enabled(void) { return 0; } 1297 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1298 int maxvec) 1299 { return -ENOSYS; } 1300 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1301 { return -ENOSYS; } 1302 static inline int pci_enable_msix_range(struct pci_dev *dev, 1303 struct msix_entry *entries, int minvec, int maxvec) 1304 { return -ENOSYS; } 1305 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1306 struct msix_entry *entries, int nvec) 1307 { return -ENOSYS; } 1308 #endif 1309 1310 #ifdef CONFIG_PCIEPORTBUS 1311 extern bool pcie_ports_disabled; 1312 extern bool pcie_ports_auto; 1313 #else 1314 #define pcie_ports_disabled true 1315 #define pcie_ports_auto false 1316 #endif 1317 1318 #ifdef CONFIG_PCIEASPM 1319 bool pcie_aspm_support_enabled(void); 1320 #else 1321 static inline bool pcie_aspm_support_enabled(void) { return false; } 1322 #endif 1323 1324 #ifdef CONFIG_PCIEAER 1325 void pci_no_aer(void); 1326 bool pci_aer_available(void); 1327 #else 1328 static inline void pci_no_aer(void) { } 1329 static inline bool pci_aer_available(void) { return false; } 1330 #endif 1331 1332 #ifdef CONFIG_PCIE_ECRC 1333 void pcie_set_ecrc_checking(struct pci_dev *dev); 1334 void pcie_ecrc_get_policy(char *str); 1335 #else 1336 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1337 static inline void pcie_ecrc_get_policy(char *str) { } 1338 #endif 1339 1340 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) 1341 1342 #ifdef CONFIG_HT_IRQ 1343 /* The functions a driver should call */ 1344 int ht_create_irq(struct pci_dev *dev, int idx); 1345 void ht_destroy_irq(unsigned int irq); 1346 #endif /* CONFIG_HT_IRQ */ 1347 1348 #ifdef CONFIG_PCI_ATS 1349 /* Address Translation Service */ 1350 void pci_ats_init(struct pci_dev *dev); 1351 int pci_enable_ats(struct pci_dev *dev, int ps); 1352 void pci_disable_ats(struct pci_dev *dev); 1353 int pci_ats_queue_depth(struct pci_dev *dev); 1354 #else 1355 static inline void pci_ats_init(struct pci_dev *d) { } 1356 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1357 static inline void pci_disable_ats(struct pci_dev *d) { } 1358 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1359 #endif 1360 1361 void pci_cfg_access_lock(struct pci_dev *dev); 1362 bool pci_cfg_access_trylock(struct pci_dev *dev); 1363 void pci_cfg_access_unlock(struct pci_dev *dev); 1364 1365 /* 1366 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1367 * a PCI domain is defined to be a set of PCI buses which share 1368 * configuration space. 1369 */ 1370 #ifdef CONFIG_PCI_DOMAINS 1371 extern int pci_domains_supported; 1372 int pci_get_new_domain_nr(void); 1373 #else 1374 enum { pci_domains_supported = 0 }; 1375 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1376 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1377 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1378 #endif /* CONFIG_PCI_DOMAINS */ 1379 1380 /* 1381 * Generic implementation for PCI domain support. If your 1382 * architecture does not need custom management of PCI 1383 * domains then this implementation will be used 1384 */ 1385 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1386 static inline int pci_domain_nr(struct pci_bus *bus) 1387 { 1388 return bus->domain_nr; 1389 } 1390 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); 1391 #else 1392 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, 1393 struct device *parent) 1394 { 1395 } 1396 #endif 1397 1398 /* some architectures require additional setup to direct VGA traffic */ 1399 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1400 unsigned int command_bits, u32 flags); 1401 void pci_register_set_vga_state(arch_set_vga_state_t func); 1402 1403 #else /* CONFIG_PCI is not enabled */ 1404 1405 static inline void pci_set_flags(int flags) { } 1406 static inline void pci_add_flags(int flags) { } 1407 static inline void pci_clear_flags(int flags) { } 1408 static inline int pci_has_flag(int flag) { return 0; } 1409 1410 /* 1411 * If the system does not have PCI, clearly these return errors. Define 1412 * these as simple inline functions to avoid hair in drivers. 1413 */ 1414 1415 #define _PCI_NOP(o, s, t) \ 1416 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1417 int where, t val) \ 1418 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1419 1420 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1421 _PCI_NOP(o, word, u16 x) \ 1422 _PCI_NOP(o, dword, u32 x) 1423 _PCI_NOP_ALL(read, *) 1424 _PCI_NOP_ALL(write,) 1425 1426 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1427 unsigned int device, 1428 struct pci_dev *from) 1429 { return NULL; } 1430 1431 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1432 unsigned int device, 1433 unsigned int ss_vendor, 1434 unsigned int ss_device, 1435 struct pci_dev *from) 1436 { return NULL; } 1437 1438 static inline struct pci_dev *pci_get_class(unsigned int class, 1439 struct pci_dev *from) 1440 { return NULL; } 1441 1442 #define pci_dev_present(ids) (0) 1443 #define no_pci_devices() (1) 1444 #define pci_dev_put(dev) do { } while (0) 1445 1446 static inline void pci_set_master(struct pci_dev *dev) { } 1447 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1448 static inline void pci_disable_device(struct pci_dev *dev) { } 1449 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1450 { return -EBUSY; } 1451 static inline int __pci_register_driver(struct pci_driver *drv, 1452 struct module *owner) 1453 { return 0; } 1454 static inline int pci_register_driver(struct pci_driver *drv) 1455 { return 0; } 1456 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1457 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1458 { return 0; } 1459 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1460 int cap) 1461 { return 0; } 1462 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1463 { return 0; } 1464 1465 /* Power management related routines */ 1466 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1467 static inline void pci_restore_state(struct pci_dev *dev) { } 1468 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1469 { return 0; } 1470 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1471 { return 0; } 1472 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1473 pm_message_t state) 1474 { return PCI_D0; } 1475 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1476 int enable) 1477 { return 0; } 1478 1479 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1480 { return -EIO; } 1481 static inline void pci_release_regions(struct pci_dev *dev) { } 1482 1483 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1484 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1485 { return 0; } 1486 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1487 1488 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1489 { return NULL; } 1490 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1491 unsigned int devfn) 1492 { return NULL; } 1493 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1494 unsigned int devfn) 1495 { return NULL; } 1496 1497 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1498 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1499 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1500 1501 #define dev_is_pci(d) (false) 1502 #define dev_is_pf(d) (false) 1503 #define dev_num_vf(d) (0) 1504 #endif /* CONFIG_PCI */ 1505 1506 /* Include architecture-dependent settings and functions */ 1507 1508 #include <asm/pci.h> 1509 1510 #ifndef pci_root_bus_fwnode 1511 #define pci_root_bus_fwnode(bus) NULL 1512 #endif 1513 1514 /* these helpers provide future and backwards compatibility 1515 * for accessing popular PCI BAR info */ 1516 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1517 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1518 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1519 #define pci_resource_len(dev,bar) \ 1520 ((pci_resource_start((dev), (bar)) == 0 && \ 1521 pci_resource_end((dev), (bar)) == \ 1522 pci_resource_start((dev), (bar))) ? 0 : \ 1523 \ 1524 (pci_resource_end((dev), (bar)) - \ 1525 pci_resource_start((dev), (bar)) + 1)) 1526 1527 /* Similar to the helpers above, these manipulate per-pci_dev 1528 * driver-specific data. They are really just a wrapper around 1529 * the generic device structure functions of these calls. 1530 */ 1531 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1532 { 1533 return dev_get_drvdata(&pdev->dev); 1534 } 1535 1536 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1537 { 1538 dev_set_drvdata(&pdev->dev, data); 1539 } 1540 1541 /* If you want to know what to call your pci_dev, ask this function. 1542 * Again, it's a wrapper around the generic device. 1543 */ 1544 static inline const char *pci_name(const struct pci_dev *pdev) 1545 { 1546 return dev_name(&pdev->dev); 1547 } 1548 1549 1550 /* Some archs don't want to expose struct resource to userland as-is 1551 * in sysfs and /proc 1552 */ 1553 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1554 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1555 const struct resource *rsrc, resource_size_t *start, 1556 resource_size_t *end) 1557 { 1558 *start = rsrc->start; 1559 *end = rsrc->end; 1560 } 1561 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1562 1563 1564 /* 1565 * The world is not perfect and supplies us with broken PCI devices. 1566 * For at least a part of these bugs we need a work-around, so both 1567 * generic (drivers/pci/quirks.c) and per-architecture code can define 1568 * fixup hooks to be called for particular buggy devices. 1569 */ 1570 1571 struct pci_fixup { 1572 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1573 u16 device; /* You can use PCI_ANY_ID here of course */ 1574 u32 class; /* You can use PCI_ANY_ID here too */ 1575 unsigned int class_shift; /* should be 0, 8, 16 */ 1576 void (*hook)(struct pci_dev *dev); 1577 }; 1578 1579 enum pci_fixup_pass { 1580 pci_fixup_early, /* Before probing BARs */ 1581 pci_fixup_header, /* After reading configuration header */ 1582 pci_fixup_final, /* Final phase of device fixups */ 1583 pci_fixup_enable, /* pci_enable_device() time */ 1584 pci_fixup_resume, /* pci_device_resume() */ 1585 pci_fixup_suspend, /* pci_device_suspend() */ 1586 pci_fixup_resume_early, /* pci_device_resume_early() */ 1587 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1588 }; 1589 1590 /* Anonymous variables would be nice... */ 1591 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1592 class_shift, hook) \ 1593 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1594 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1595 = { vendor, device, class, class_shift, hook }; 1596 1597 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1598 class_shift, hook) \ 1599 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1600 hook, vendor, device, class, class_shift, hook) 1601 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1602 class_shift, hook) \ 1603 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1604 hook, vendor, device, class, class_shift, hook) 1605 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1606 class_shift, hook) \ 1607 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1608 hook, vendor, device, class, class_shift, hook) 1609 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1610 class_shift, hook) \ 1611 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1612 hook, vendor, device, class, class_shift, hook) 1613 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1614 class_shift, hook) \ 1615 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1616 resume##hook, vendor, device, class, \ 1617 class_shift, hook) 1618 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1619 class_shift, hook) \ 1620 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1621 resume_early##hook, vendor, device, \ 1622 class, class_shift, hook) 1623 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1624 class_shift, hook) \ 1625 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1626 suspend##hook, vendor, device, class, \ 1627 class_shift, hook) 1628 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1629 class_shift, hook) \ 1630 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1631 suspend_late##hook, vendor, device, \ 1632 class, class_shift, hook) 1633 1634 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1635 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1636 hook, vendor, device, PCI_ANY_ID, 0, hook) 1637 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1638 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1639 hook, vendor, device, PCI_ANY_ID, 0, hook) 1640 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1641 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1642 hook, vendor, device, PCI_ANY_ID, 0, hook) 1643 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1644 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1645 hook, vendor, device, PCI_ANY_ID, 0, hook) 1646 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1647 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1648 resume##hook, vendor, device, \ 1649 PCI_ANY_ID, 0, hook) 1650 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1651 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1652 resume_early##hook, vendor, device, \ 1653 PCI_ANY_ID, 0, hook) 1654 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1655 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1656 suspend##hook, vendor, device, \ 1657 PCI_ANY_ID, 0, hook) 1658 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1659 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1660 suspend_late##hook, vendor, device, \ 1661 PCI_ANY_ID, 0, hook) 1662 1663 #ifdef CONFIG_PCI_QUIRKS 1664 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1665 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1666 void pci_dev_specific_enable_acs(struct pci_dev *dev); 1667 #else 1668 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1669 struct pci_dev *dev) { } 1670 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1671 u16 acs_flags) 1672 { 1673 return -ENOTTY; 1674 } 1675 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } 1676 #endif 1677 1678 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1679 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1680 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1681 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1682 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1683 const char *name); 1684 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1685 1686 extern int pci_pci_problems; 1687 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1688 #define PCIPCI_TRITON 2 1689 #define PCIPCI_NATOMA 4 1690 #define PCIPCI_VIAETBF 8 1691 #define PCIPCI_VSFX 16 1692 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1693 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1694 1695 extern unsigned long pci_cardbus_io_size; 1696 extern unsigned long pci_cardbus_mem_size; 1697 extern u8 pci_dfl_cache_line_size; 1698 extern u8 pci_cache_line_size; 1699 1700 extern unsigned long pci_hotplug_io_size; 1701 extern unsigned long pci_hotplug_mem_size; 1702 1703 /* Architecture-specific versions may override these (weak) */ 1704 void pcibios_disable_device(struct pci_dev *dev); 1705 void pcibios_set_master(struct pci_dev *dev); 1706 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1707 enum pcie_reset_state state); 1708 int pcibios_add_device(struct pci_dev *dev); 1709 void pcibios_release_device(struct pci_dev *dev); 1710 void pcibios_penalize_isa_irq(int irq, int active); 1711 int pcibios_alloc_irq(struct pci_dev *dev); 1712 void pcibios_free_irq(struct pci_dev *dev); 1713 1714 #ifdef CONFIG_HIBERNATE_CALLBACKS 1715 extern struct dev_pm_ops pcibios_pm_ops; 1716 #endif 1717 1718 #ifdef CONFIG_PCI_MMCONFIG 1719 void __init pci_mmcfg_early_init(void); 1720 void __init pci_mmcfg_late_init(void); 1721 #else 1722 static inline void pci_mmcfg_early_init(void) { } 1723 static inline void pci_mmcfg_late_init(void) { } 1724 #endif 1725 1726 int pci_ext_cfg_avail(void); 1727 1728 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1729 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1730 1731 #ifdef CONFIG_PCI_IOV 1732 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1733 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1734 1735 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1736 void pci_disable_sriov(struct pci_dev *dev); 1737 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset); 1738 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset); 1739 int pci_num_vf(struct pci_dev *dev); 1740 int pci_vfs_assigned(struct pci_dev *dev); 1741 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1742 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1743 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1744 #else 1745 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1746 { 1747 return -ENOSYS; 1748 } 1749 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1750 { 1751 return -ENOSYS; 1752 } 1753 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1754 { return -ENODEV; } 1755 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset) 1756 { 1757 return -ENOSYS; 1758 } 1759 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 1760 int id, int reset) { } 1761 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1762 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1763 static inline int pci_vfs_assigned(struct pci_dev *dev) 1764 { return 0; } 1765 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1766 { return 0; } 1767 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1768 { return 0; } 1769 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1770 { return 0; } 1771 #endif 1772 1773 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1774 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1775 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1776 #endif 1777 1778 /** 1779 * pci_pcie_cap - get the saved PCIe capability offset 1780 * @dev: PCI device 1781 * 1782 * PCIe capability offset is calculated at PCI device initialization 1783 * time and saved in the data structure. This function returns saved 1784 * PCIe capability offset. Using this instead of pci_find_capability() 1785 * reduces unnecessary search in the PCI configuration space. If you 1786 * need to calculate PCIe capability offset from raw device for some 1787 * reasons, please use pci_find_capability() instead. 1788 */ 1789 static inline int pci_pcie_cap(struct pci_dev *dev) 1790 { 1791 return dev->pcie_cap; 1792 } 1793 1794 /** 1795 * pci_is_pcie - check if the PCI device is PCI Express capable 1796 * @dev: PCI device 1797 * 1798 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1799 */ 1800 static inline bool pci_is_pcie(struct pci_dev *dev) 1801 { 1802 return pci_pcie_cap(dev); 1803 } 1804 1805 /** 1806 * pcie_caps_reg - get the PCIe Capabilities Register 1807 * @dev: PCI device 1808 */ 1809 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1810 { 1811 return dev->pcie_flags_reg; 1812 } 1813 1814 /** 1815 * pci_pcie_type - get the PCIe device/port type 1816 * @dev: PCI device 1817 */ 1818 static inline int pci_pcie_type(const struct pci_dev *dev) 1819 { 1820 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1821 } 1822 1823 void pci_request_acs(void); 1824 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1825 bool pci_acs_path_enabled(struct pci_dev *start, 1826 struct pci_dev *end, u16 acs_flags); 1827 1828 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1829 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1830 1831 /* Large Resource Data Type Tag Item Names */ 1832 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1833 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1834 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1835 1836 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1837 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1838 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1839 1840 /* Small Resource Data Type Tag Item Names */ 1841 #define PCI_VPD_STIN_END 0x0f /* End */ 1842 1843 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 1844 1845 #define PCI_VPD_SRDT_TIN_MASK 0x78 1846 #define PCI_VPD_SRDT_LEN_MASK 0x07 1847 #define PCI_VPD_LRDT_TIN_MASK 0x7f 1848 1849 #define PCI_VPD_LRDT_TAG_SIZE 3 1850 #define PCI_VPD_SRDT_TAG_SIZE 1 1851 1852 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1853 1854 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1855 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1856 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1857 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1858 1859 /** 1860 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1861 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1862 * 1863 * Returns the extracted Large Resource Data Type length. 1864 */ 1865 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1866 { 1867 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1868 } 1869 1870 /** 1871 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 1872 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1873 * 1874 * Returns the extracted Large Resource Data Type Tag item. 1875 */ 1876 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 1877 { 1878 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 1879 } 1880 1881 /** 1882 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1883 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1884 * 1885 * Returns the extracted Small Resource Data Type length. 1886 */ 1887 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1888 { 1889 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1890 } 1891 1892 /** 1893 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 1894 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1895 * 1896 * Returns the extracted Small Resource Data Type Tag Item. 1897 */ 1898 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 1899 { 1900 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 1901 } 1902 1903 /** 1904 * pci_vpd_info_field_size - Extracts the information field length 1905 * @lrdt: Pointer to the beginning of an information field header 1906 * 1907 * Returns the extracted information field length. 1908 */ 1909 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1910 { 1911 return info_field[2]; 1912 } 1913 1914 /** 1915 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1916 * @buf: Pointer to buffered vpd data 1917 * @off: The offset into the buffer at which to begin the search 1918 * @len: The length of the vpd buffer 1919 * @rdt: The Resource Data Type to search for 1920 * 1921 * Returns the index where the Resource Data Type was found or 1922 * -ENOENT otherwise. 1923 */ 1924 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1925 1926 /** 1927 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1928 * @buf: Pointer to buffered vpd data 1929 * @off: The offset into the buffer at which to begin the search 1930 * @len: The length of the buffer area, relative to off, in which to search 1931 * @kw: The keyword to search for 1932 * 1933 * Returns the index where the information field keyword was found or 1934 * -ENOENT otherwise. 1935 */ 1936 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1937 unsigned int len, const char *kw); 1938 1939 /* PCI <-> OF binding helpers */ 1940 #ifdef CONFIG_OF 1941 struct device_node; 1942 struct irq_domain; 1943 void pci_set_of_node(struct pci_dev *dev); 1944 void pci_release_of_node(struct pci_dev *dev); 1945 void pci_set_bus_of_node(struct pci_bus *bus); 1946 void pci_release_bus_of_node(struct pci_bus *bus); 1947 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 1948 1949 /* Arch may override this (weak) */ 1950 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1951 1952 static inline struct device_node * 1953 pci_device_to_OF_node(const struct pci_dev *pdev) 1954 { 1955 return pdev ? pdev->dev.of_node : NULL; 1956 } 1957 1958 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1959 { 1960 return bus ? bus->dev.of_node : NULL; 1961 } 1962 1963 #else /* CONFIG_OF */ 1964 static inline void pci_set_of_node(struct pci_dev *dev) { } 1965 static inline void pci_release_of_node(struct pci_dev *dev) { } 1966 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1967 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1968 static inline struct device_node * 1969 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 1970 static inline struct irq_domain * 1971 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 1972 #endif /* CONFIG_OF */ 1973 1974 #ifdef CONFIG_ACPI 1975 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 1976 1977 void 1978 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 1979 #else 1980 static inline struct irq_domain * 1981 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 1982 #endif 1983 1984 #ifdef CONFIG_EEH 1985 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1986 { 1987 return pdev->dev.archdata.edev; 1988 } 1989 #endif 1990 1991 int pci_for_each_dma_alias(struct pci_dev *pdev, 1992 int (*fn)(struct pci_dev *pdev, 1993 u16 alias, void *data), void *data); 1994 1995 /* helper functions for operation of device flag */ 1996 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 1997 { 1998 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 1999 } 2000 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2001 { 2002 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2003 } 2004 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2005 { 2006 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2007 } 2008 2009 /** 2010 * pci_ari_enabled - query ARI forwarding status 2011 * @bus: the PCI bus 2012 * 2013 * Returns true if ARI forwarding is enabled. 2014 */ 2015 static inline bool pci_ari_enabled(struct pci_bus *bus) 2016 { 2017 return bus->self && bus->self->ari_enabled; 2018 } 2019 2020 /* provide the legacy pci_dma_* API */ 2021 #include <linux/pci-dma-compat.h> 2022 2023 #endif /* LINUX_PCI_H */ 2024