1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 46 PCI_STATUS_SIG_SYSTEM_ERROR | \ 47 PCI_STATUS_REC_MASTER_ABORT | \ 48 PCI_STATUS_REC_TARGET_ABORT | \ 49 PCI_STATUS_SIG_TARGET_ABORT | \ 50 PCI_STATUS_PARITY) 51 52 /* 53 * The PCI interface treats multi-function devices as independent 54 * devices. The slot/function address of each device is encoded 55 * in a single byte as follows: 56 * 57 * 7:3 = slot 58 * 2:0 = function 59 * 60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 61 * In the interest of not exposing interfaces to user-space unnecessarily, 62 * the following kernel-only defines are being added here. 63 */ 64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 67 68 /* pci_slot represents a physical slot */ 69 struct pci_slot { 70 struct pci_bus *bus; /* Bus this slot is on */ 71 struct list_head list; /* Node in list of slots */ 72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 74 struct kobject kobj; 75 }; 76 77 static inline const char *pci_slot_name(const struct pci_slot *slot) 78 { 79 return kobject_name(&slot->kobj); 80 } 81 82 /* File state for mmap()s on /proc/bus/pci/X/Y */ 83 enum pci_mmap_state { 84 pci_mmap_io, 85 pci_mmap_mem 86 }; 87 88 /* For PCI devices, the region numbers are assigned this way: */ 89 enum { 90 /* #0-5: standard PCI resources */ 91 PCI_STD_RESOURCES, 92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 93 94 /* #6: expansion ROM resource */ 95 PCI_ROM_RESOURCE, 96 97 /* Device-specific resources */ 98 #ifdef CONFIG_PCI_IOV 99 PCI_IOV_RESOURCES, 100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 101 #endif 102 103 /* Resources assigned to buses behind the bridge */ 104 #define PCI_BRIDGE_RESOURCE_NUM 4 105 106 PCI_BRIDGE_RESOURCES, 107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 108 PCI_BRIDGE_RESOURCE_NUM - 1, 109 110 /* Total resources associated with a PCI device */ 111 PCI_NUM_RESOURCES, 112 113 /* Preserve this for compatibility */ 114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 115 }; 116 117 /** 118 * enum pci_interrupt_pin - PCI INTx interrupt values 119 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 120 * @PCI_INTERRUPT_INTA: PCI INTA pin 121 * @PCI_INTERRUPT_INTB: PCI INTB pin 122 * @PCI_INTERRUPT_INTC: PCI INTC pin 123 * @PCI_INTERRUPT_INTD: PCI INTD pin 124 * 125 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 126 * PCI_INTERRUPT_PIN register. 127 */ 128 enum pci_interrupt_pin { 129 PCI_INTERRUPT_UNKNOWN, 130 PCI_INTERRUPT_INTA, 131 PCI_INTERRUPT_INTB, 132 PCI_INTERRUPT_INTC, 133 PCI_INTERRUPT_INTD, 134 }; 135 136 /* The number of legacy PCI INTx interrupts */ 137 #define PCI_NUM_INTX 4 138 139 /* 140 * pci_power_t values must match the bits in the Capabilities PME_Support 141 * and Control/Status PowerState fields in the Power Management capability. 142 */ 143 typedef int __bitwise pci_power_t; 144 145 #define PCI_D0 ((pci_power_t __force) 0) 146 #define PCI_D1 ((pci_power_t __force) 1) 147 #define PCI_D2 ((pci_power_t __force) 2) 148 #define PCI_D3hot ((pci_power_t __force) 3) 149 #define PCI_D3cold ((pci_power_t __force) 4) 150 #define PCI_UNKNOWN ((pci_power_t __force) 5) 151 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 152 153 /* Remember to update this when the list above changes! */ 154 extern const char *pci_power_names[]; 155 156 static inline const char *pci_power_name(pci_power_t state) 157 { 158 return pci_power_names[1 + (__force int) state]; 159 } 160 161 /** 162 * typedef pci_channel_state_t 163 * 164 * The pci_channel state describes connectivity between the CPU and 165 * the PCI device. If some PCI bus between here and the PCI device 166 * has crashed or locked up, this info is reflected here. 167 */ 168 typedef unsigned int __bitwise pci_channel_state_t; 169 170 enum pci_channel_state { 171 /* I/O channel is in normal state */ 172 pci_channel_io_normal = (__force pci_channel_state_t) 1, 173 174 /* I/O to channel is blocked */ 175 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 176 177 /* PCI card is dead */ 178 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 179 }; 180 181 typedef unsigned int __bitwise pcie_reset_state_t; 182 183 enum pcie_reset_state { 184 /* Reset is NOT asserted (Use to deassert reset) */ 185 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 186 187 /* Use #PERST to reset PCIe device */ 188 pcie_warm_reset = (__force pcie_reset_state_t) 2, 189 190 /* Use PCIe Hot Reset to reset device */ 191 pcie_hot_reset = (__force pcie_reset_state_t) 3 192 }; 193 194 typedef unsigned short __bitwise pci_dev_flags_t; 195 enum pci_dev_flags { 196 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 197 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 198 /* Device configuration is irrevocably lost if disabled into D3 */ 199 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 200 /* Provide indication device is assigned by a Virtual Machine Manager */ 201 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 202 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 203 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 204 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 205 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 206 /* Do not use bus resets for device */ 207 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 208 /* Do not use PM reset even if device advertises NoSoftRst- */ 209 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 210 /* Get VPD from function 0 VPD */ 211 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 212 /* A non-root bridge where translation occurs, stop alias search here */ 213 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 214 /* Do not use FLR even if device advertises PCI_AF_CAP */ 215 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 216 /* Don't use Relaxed Ordering for TLPs directed at this device */ 217 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 218 }; 219 220 enum pci_irq_reroute_variant { 221 INTEL_IRQ_REROUTE_VARIANT = 1, 222 MAX_IRQ_REROUTE_VARIANTS = 3 223 }; 224 225 typedef unsigned short __bitwise pci_bus_flags_t; 226 enum pci_bus_flags { 227 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 228 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 229 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 230 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 231 }; 232 233 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 234 enum pcie_link_width { 235 PCIE_LNK_WIDTH_RESRV = 0x00, 236 PCIE_LNK_X1 = 0x01, 237 PCIE_LNK_X2 = 0x02, 238 PCIE_LNK_X4 = 0x04, 239 PCIE_LNK_X8 = 0x08, 240 PCIE_LNK_X12 = 0x0c, 241 PCIE_LNK_X16 = 0x10, 242 PCIE_LNK_X32 = 0x20, 243 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 244 }; 245 246 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 247 enum pci_bus_speed { 248 PCI_SPEED_33MHz = 0x00, 249 PCI_SPEED_66MHz = 0x01, 250 PCI_SPEED_66MHz_PCIX = 0x02, 251 PCI_SPEED_100MHz_PCIX = 0x03, 252 PCI_SPEED_133MHz_PCIX = 0x04, 253 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 254 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 255 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 256 PCI_SPEED_66MHz_PCIX_266 = 0x09, 257 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 258 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 259 AGP_UNKNOWN = 0x0c, 260 AGP_1X = 0x0d, 261 AGP_2X = 0x0e, 262 AGP_4X = 0x0f, 263 AGP_8X = 0x10, 264 PCI_SPEED_66MHz_PCIX_533 = 0x11, 265 PCI_SPEED_100MHz_PCIX_533 = 0x12, 266 PCI_SPEED_133MHz_PCIX_533 = 0x13, 267 PCIE_SPEED_2_5GT = 0x14, 268 PCIE_SPEED_5_0GT = 0x15, 269 PCIE_SPEED_8_0GT = 0x16, 270 PCIE_SPEED_16_0GT = 0x17, 271 PCIE_SPEED_32_0GT = 0x18, 272 PCI_SPEED_UNKNOWN = 0xff, 273 }; 274 275 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 276 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 277 278 struct pci_cap_saved_data { 279 u16 cap_nr; 280 bool cap_extended; 281 unsigned int size; 282 u32 data[0]; 283 }; 284 285 struct pci_cap_saved_state { 286 struct hlist_node next; 287 struct pci_cap_saved_data cap; 288 }; 289 290 struct irq_affinity; 291 struct pcie_link_state; 292 struct pci_vpd; 293 struct pci_sriov; 294 struct pci_p2pdma; 295 296 /* The pci_dev structure describes PCI devices */ 297 struct pci_dev { 298 struct list_head bus_list; /* Node in per-bus list */ 299 struct pci_bus *bus; /* Bus this device is on */ 300 struct pci_bus *subordinate; /* Bus this device bridges to */ 301 302 void *sysdata; /* Hook for sys-specific extension */ 303 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 304 struct pci_slot *slot; /* Physical slot this device is in */ 305 306 unsigned int devfn; /* Encoded device & function index */ 307 unsigned short vendor; 308 unsigned short device; 309 unsigned short subsystem_vendor; 310 unsigned short subsystem_device; 311 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 312 u8 revision; /* PCI revision, low byte of class word */ 313 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 314 #ifdef CONFIG_PCIEAER 315 u16 aer_cap; /* AER capability offset */ 316 struct aer_stats *aer_stats; /* AER stats for this device */ 317 #endif 318 u8 pcie_cap; /* PCIe capability offset */ 319 u8 msi_cap; /* MSI capability offset */ 320 u8 msix_cap; /* MSI-X capability offset */ 321 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 322 u8 rom_base_reg; /* Config register controlling ROM */ 323 u8 pin; /* Interrupt pin this device uses */ 324 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 325 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 326 327 struct pci_driver *driver; /* Driver bound to this device */ 328 u64 dma_mask; /* Mask of the bits of bus address this 329 device implements. Normally this is 330 0xffffffff. You only need to change 331 this if your device has broken DMA 332 or supports 64-bit transfers. */ 333 334 struct device_dma_parameters dma_parms; 335 336 pci_power_t current_state; /* Current operating state. In ACPI, 337 this is D0-D3, D0 being fully 338 functional, and D3 being off. */ 339 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 340 u8 pm_cap; /* PM capability offset */ 341 unsigned int pme_support:5; /* Bitmask of states from which PME# 342 can be generated */ 343 unsigned int pme_poll:1; /* Poll device's PME status bit */ 344 unsigned int d1_support:1; /* Low power state D1 is supported */ 345 unsigned int d2_support:1; /* Low power state D2 is supported */ 346 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 347 unsigned int no_d3cold:1; /* D3cold is forbidden */ 348 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 349 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 350 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 351 decoding during BAR sizing */ 352 unsigned int wakeup_prepared:1; 353 unsigned int runtime_d3cold:1; /* Whether go through runtime 354 D3cold, not set for devices 355 powered on/off by the 356 corresponding bridge */ 357 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 358 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 359 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 360 controlled exclusively by 361 user sysfs */ 362 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 363 bit manually */ 364 unsigned int d3_delay; /* D3->D0 transition time in ms */ 365 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 366 367 #ifdef CONFIG_PCIEASPM 368 struct pcie_link_state *link_state; /* ASPM link state */ 369 unsigned int ltr_path:1; /* Latency Tolerance Reporting 370 supported from root to here */ 371 #endif 372 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 373 374 pci_channel_state_t error_state; /* Current connectivity state */ 375 struct device dev; /* Generic device interface */ 376 377 int cfg_size; /* Size of config space */ 378 379 /* 380 * Instead of touching interrupt line and base address registers 381 * directly, use the values stored here. They might be different! 382 */ 383 unsigned int irq; 384 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 385 386 bool match_driver; /* Skip attaching driver */ 387 388 unsigned int transparent:1; /* Subtractive decode bridge */ 389 unsigned int io_window:1; /* Bridge has I/O window */ 390 unsigned int pref_window:1; /* Bridge has pref mem window */ 391 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 392 unsigned int multifunction:1; /* Multi-function device */ 393 394 unsigned int is_busmaster:1; /* Is busmaster */ 395 unsigned int no_msi:1; /* May not use MSI */ 396 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 397 unsigned int block_cfg_access:1; /* Config space access blocked */ 398 unsigned int broken_parity_status:1; /* Generates false positive parity */ 399 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 400 unsigned int msi_enabled:1; 401 unsigned int msix_enabled:1; 402 unsigned int ari_enabled:1; /* ARI forwarding */ 403 unsigned int ats_enabled:1; /* Address Translation Svc */ 404 unsigned int pasid_enabled:1; /* Process Address Space ID */ 405 unsigned int pri_enabled:1; /* Page Request Interface */ 406 unsigned int is_managed:1; 407 unsigned int needs_freset:1; /* Requires fundamental reset */ 408 unsigned int state_saved:1; 409 unsigned int is_physfn:1; 410 unsigned int is_virtfn:1; 411 unsigned int reset_fn:1; 412 unsigned int is_hotplug_bridge:1; 413 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 414 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 415 /* 416 * Devices marked being untrusted are the ones that can potentially 417 * execute DMA attacks and similar. They are typically connected 418 * through external ports such as Thunderbolt but not limited to 419 * that. When an IOMMU is enabled they should be getting full 420 * mappings to make sure they cannot access arbitrary memory. 421 */ 422 unsigned int untrusted:1; 423 unsigned int __aer_firmware_first_valid:1; 424 unsigned int __aer_firmware_first:1; 425 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 426 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 427 unsigned int irq_managed:1; 428 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 429 unsigned int is_probed:1; /* Device probing in progress */ 430 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 431 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 432 pci_dev_flags_t dev_flags; 433 atomic_t enable_cnt; /* pci_enable_device has been called */ 434 435 u32 saved_config_space[16]; /* Config space saved at suspend time */ 436 struct hlist_head saved_cap_space; 437 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 438 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 439 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 440 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 441 442 #ifdef CONFIG_HOTPLUG_PCI_PCIE 443 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 444 #endif 445 #ifdef CONFIG_PCIE_PTM 446 unsigned int ptm_root:1; 447 unsigned int ptm_enabled:1; 448 u8 ptm_granularity; 449 #endif 450 #ifdef CONFIG_PCI_MSI 451 const struct attribute_group **msi_irq_groups; 452 #endif 453 struct pci_vpd *vpd; 454 #ifdef CONFIG_PCI_ATS 455 union { 456 struct pci_sriov *sriov; /* PF: SR-IOV info */ 457 struct pci_dev *physfn; /* VF: related PF */ 458 }; 459 u16 ats_cap; /* ATS Capability offset */ 460 u8 ats_stu; /* ATS Smallest Translation Unit */ 461 #endif 462 #ifdef CONFIG_PCI_PRI 463 u16 pri_cap; /* PRI Capability offset */ 464 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 465 unsigned int pasid_required:1; /* PRG Response PASID Required */ 466 #endif 467 #ifdef CONFIG_PCI_PASID 468 u16 pasid_cap; /* PASID Capability offset */ 469 u16 pasid_features; 470 #endif 471 #ifdef CONFIG_PCI_P2PDMA 472 struct pci_p2pdma *p2pdma; 473 #endif 474 phys_addr_t rom; /* Physical address if not from BAR */ 475 size_t romlen; /* Length if not from BAR */ 476 char *driver_override; /* Driver name to force a match */ 477 478 unsigned long priv_flags; /* Private flags for the PCI driver */ 479 }; 480 481 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 482 { 483 #ifdef CONFIG_PCI_IOV 484 if (dev->is_virtfn) 485 dev = dev->physfn; 486 #endif 487 return dev; 488 } 489 490 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 491 492 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 493 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 494 495 static inline int pci_channel_offline(struct pci_dev *pdev) 496 { 497 return (pdev->error_state != pci_channel_io_normal); 498 } 499 500 struct pci_host_bridge { 501 struct device dev; 502 struct pci_bus *bus; /* Root bus */ 503 struct pci_ops *ops; 504 void *sysdata; 505 int busnr; 506 struct list_head windows; /* resource_entry */ 507 struct list_head dma_ranges; /* dma ranges resource list */ 508 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 509 int (*map_irq)(const struct pci_dev *, u8, u8); 510 void (*release_fn)(struct pci_host_bridge *); 511 void *release_data; 512 struct msi_controller *msi; 513 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 514 unsigned int no_ext_tags:1; /* No Extended Tags */ 515 unsigned int native_aer:1; /* OS may use PCIe AER */ 516 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 517 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 518 unsigned int native_pme:1; /* OS may use PCIe PME */ 519 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 520 unsigned int preserve_config:1; /* Preserve FW resource setup */ 521 522 /* Resource alignment requirements */ 523 resource_size_t (*align_resource)(struct pci_dev *dev, 524 const struct resource *res, 525 resource_size_t start, 526 resource_size_t size, 527 resource_size_t align); 528 unsigned long private[0] ____cacheline_aligned; 529 }; 530 531 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 532 533 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 534 { 535 return (void *)bridge->private; 536 } 537 538 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 539 { 540 return container_of(priv, struct pci_host_bridge, private); 541 } 542 543 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 544 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 545 size_t priv); 546 void pci_free_host_bridge(struct pci_host_bridge *bridge); 547 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 548 549 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 550 void (*release_fn)(struct pci_host_bridge *), 551 void *release_data); 552 553 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 554 555 /* 556 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 557 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 558 * buses below host bridges or subtractive decode bridges) go in the list. 559 * Use pci_bus_for_each_resource() to iterate through all the resources. 560 */ 561 562 /* 563 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 564 * and there's no way to program the bridge with the details of the window. 565 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 566 * decode bit set, because they are explicit and can be programmed with _SRS. 567 */ 568 #define PCI_SUBTRACTIVE_DECODE 0x1 569 570 struct pci_bus_resource { 571 struct list_head list; 572 struct resource *res; 573 unsigned int flags; 574 }; 575 576 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 577 578 struct pci_bus { 579 struct list_head node; /* Node in list of buses */ 580 struct pci_bus *parent; /* Parent bus this bridge is on */ 581 struct list_head children; /* List of child buses */ 582 struct list_head devices; /* List of devices on this bus */ 583 struct pci_dev *self; /* Bridge device as seen by parent */ 584 struct list_head slots; /* List of slots on this bus; 585 protected by pci_slot_mutex */ 586 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 587 struct list_head resources; /* Address space routed to this bus */ 588 struct resource busn_res; /* Bus numbers routed to this bus */ 589 590 struct pci_ops *ops; /* Configuration access functions */ 591 struct msi_controller *msi; /* MSI controller */ 592 void *sysdata; /* Hook for sys-specific extension */ 593 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 594 595 unsigned char number; /* Bus number */ 596 unsigned char primary; /* Number of primary bridge */ 597 unsigned char max_bus_speed; /* enum pci_bus_speed */ 598 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 599 #ifdef CONFIG_PCI_DOMAINS_GENERIC 600 int domain_nr; 601 #endif 602 603 char name[48]; 604 605 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 606 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 607 struct device *bridge; 608 struct device dev; 609 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 610 struct bin_attribute *legacy_mem; /* Legacy mem */ 611 unsigned int is_added:1; 612 }; 613 614 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 615 616 static inline u16 pci_dev_id(struct pci_dev *dev) 617 { 618 return PCI_DEVID(dev->bus->number, dev->devfn); 619 } 620 621 /* 622 * Returns true if the PCI bus is root (behind host-PCI bridge), 623 * false otherwise 624 * 625 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 626 * This is incorrect because "virtual" buses added for SR-IOV (via 627 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 628 */ 629 static inline bool pci_is_root_bus(struct pci_bus *pbus) 630 { 631 return !(pbus->parent); 632 } 633 634 /** 635 * pci_is_bridge - check if the PCI device is a bridge 636 * @dev: PCI device 637 * 638 * Return true if the PCI device is bridge whether it has subordinate 639 * or not. 640 */ 641 static inline bool pci_is_bridge(struct pci_dev *dev) 642 { 643 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 644 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 645 } 646 647 #define for_each_pci_bridge(dev, bus) \ 648 list_for_each_entry(dev, &bus->devices, bus_list) \ 649 if (!pci_is_bridge(dev)) {} else 650 651 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 652 { 653 dev = pci_physfn(dev); 654 if (pci_is_root_bus(dev->bus)) 655 return NULL; 656 657 return dev->bus->self; 658 } 659 660 #ifdef CONFIG_PCI_MSI 661 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 662 { 663 return pci_dev->msi_enabled || pci_dev->msix_enabled; 664 } 665 #else 666 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 667 #endif 668 669 /* Error values that may be returned by PCI functions */ 670 #define PCIBIOS_SUCCESSFUL 0x00 671 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 672 #define PCIBIOS_BAD_VENDOR_ID 0x83 673 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 674 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 675 #define PCIBIOS_SET_FAILED 0x88 676 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 677 678 /* Translate above to generic errno for passing back through non-PCI code */ 679 static inline int pcibios_err_to_errno(int err) 680 { 681 if (err <= PCIBIOS_SUCCESSFUL) 682 return err; /* Assume already errno */ 683 684 switch (err) { 685 case PCIBIOS_FUNC_NOT_SUPPORTED: 686 return -ENOENT; 687 case PCIBIOS_BAD_VENDOR_ID: 688 return -ENOTTY; 689 case PCIBIOS_DEVICE_NOT_FOUND: 690 return -ENODEV; 691 case PCIBIOS_BAD_REGISTER_NUMBER: 692 return -EFAULT; 693 case PCIBIOS_SET_FAILED: 694 return -EIO; 695 case PCIBIOS_BUFFER_TOO_SMALL: 696 return -ENOSPC; 697 } 698 699 return -ERANGE; 700 } 701 702 /* Low-level architecture-dependent routines */ 703 704 struct pci_ops { 705 int (*add_bus)(struct pci_bus *bus); 706 void (*remove_bus)(struct pci_bus *bus); 707 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 708 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 709 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 710 }; 711 712 /* 713 * ACPI needs to be able to access PCI config space before we've done a 714 * PCI bus scan and created pci_bus structures. 715 */ 716 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 717 int reg, int len, u32 *val); 718 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 719 int reg, int len, u32 val); 720 721 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 722 typedef u64 pci_bus_addr_t; 723 #else 724 typedef u32 pci_bus_addr_t; 725 #endif 726 727 struct pci_bus_region { 728 pci_bus_addr_t start; 729 pci_bus_addr_t end; 730 }; 731 732 struct pci_dynids { 733 spinlock_t lock; /* Protects list, index */ 734 struct list_head list; /* For IDs added at runtime */ 735 }; 736 737 738 /* 739 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 740 * a set of callbacks in struct pci_error_handlers, that device driver 741 * will be notified of PCI bus errors, and will be driven to recovery 742 * when an error occurs. 743 */ 744 745 typedef unsigned int __bitwise pci_ers_result_t; 746 747 enum pci_ers_result { 748 /* No result/none/not supported in device driver */ 749 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 750 751 /* Device driver can recover without slot reset */ 752 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 753 754 /* Device driver wants slot to be reset */ 755 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 756 757 /* Device has completely failed, is unrecoverable */ 758 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 759 760 /* Device driver is fully recovered and operational */ 761 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 762 763 /* No AER capabilities registered for the driver */ 764 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 765 }; 766 767 /* PCI bus error event callbacks */ 768 struct pci_error_handlers { 769 /* PCI bus error detected on this device */ 770 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 771 enum pci_channel_state error); 772 773 /* MMIO has been re-enabled, but not DMA */ 774 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 775 776 /* PCI slot has been reset */ 777 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 778 779 /* PCI function reset prepare or completed */ 780 void (*reset_prepare)(struct pci_dev *dev); 781 void (*reset_done)(struct pci_dev *dev); 782 783 /* Device driver may resume normal operations */ 784 void (*resume)(struct pci_dev *dev); 785 }; 786 787 788 struct module; 789 790 /** 791 * struct pci_driver - PCI driver structure 792 * @node: List of driver structures. 793 * @name: Driver name. 794 * @id_table: Pointer to table of device IDs the driver is 795 * interested in. Most drivers should export this 796 * table using MODULE_DEVICE_TABLE(pci,...). 797 * @probe: This probing function gets called (during execution 798 * of pci_register_driver() for already existing 799 * devices or later if a new device gets inserted) for 800 * all PCI devices which match the ID table and are not 801 * "owned" by the other drivers yet. This function gets 802 * passed a "struct pci_dev \*" for each device whose 803 * entry in the ID table matches the device. The probe 804 * function returns zero when the driver chooses to 805 * take "ownership" of the device or an error code 806 * (negative number) otherwise. 807 * The probe function always gets called from process 808 * context, so it can sleep. 809 * @remove: The remove() function gets called whenever a device 810 * being handled by this driver is removed (either during 811 * deregistration of the driver or when it's manually 812 * pulled out of a hot-pluggable slot). 813 * The remove function always gets called from process 814 * context, so it can sleep. 815 * @suspend: Put device into low power state. 816 * @resume: Wake device from low power state. 817 * (Please see Documentation/power/pci.rst for descriptions 818 * of PCI Power Management and the related functions.) 819 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 820 * Intended to stop any idling DMA operations. 821 * Useful for enabling wake-on-lan (NIC) or changing 822 * the power state of a device before reboot. 823 * e.g. drivers/net/e100.c. 824 * @sriov_configure: Optional driver callback to allow configuration of 825 * number of VFs to enable via sysfs "sriov_numvfs" file. 826 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 827 * @groups: Sysfs attribute groups. 828 * @driver: Driver model structure. 829 * @dynids: List of dynamically added device IDs. 830 */ 831 struct pci_driver { 832 struct list_head node; 833 const char *name; 834 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 835 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 836 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 837 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 838 int (*resume)(struct pci_dev *dev); /* Device woken up */ 839 void (*shutdown)(struct pci_dev *dev); 840 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 841 const struct pci_error_handlers *err_handler; 842 const struct attribute_group **groups; 843 struct device_driver driver; 844 struct pci_dynids dynids; 845 }; 846 847 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 848 849 /** 850 * PCI_DEVICE - macro used to describe a specific PCI device 851 * @vend: the 16 bit PCI Vendor ID 852 * @dev: the 16 bit PCI Device ID 853 * 854 * This macro is used to create a struct pci_device_id that matches a 855 * specific device. The subvendor and subdevice fields will be set to 856 * PCI_ANY_ID. 857 */ 858 #define PCI_DEVICE(vend,dev) \ 859 .vendor = (vend), .device = (dev), \ 860 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 861 862 /** 863 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 864 * @vend: the 16 bit PCI Vendor ID 865 * @dev: the 16 bit PCI Device ID 866 * @subvend: the 16 bit PCI Subvendor ID 867 * @subdev: the 16 bit PCI Subdevice ID 868 * 869 * This macro is used to create a struct pci_device_id that matches a 870 * specific device with subsystem information. 871 */ 872 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 873 .vendor = (vend), .device = (dev), \ 874 .subvendor = (subvend), .subdevice = (subdev) 875 876 /** 877 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 878 * @dev_class: the class, subclass, prog-if triple for this device 879 * @dev_class_mask: the class mask for this device 880 * 881 * This macro is used to create a struct pci_device_id that matches a 882 * specific PCI class. The vendor, device, subvendor, and subdevice 883 * fields will be set to PCI_ANY_ID. 884 */ 885 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 886 .class = (dev_class), .class_mask = (dev_class_mask), \ 887 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 888 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 889 890 /** 891 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 892 * @vend: the vendor name 893 * @dev: the 16 bit PCI Device ID 894 * 895 * This macro is used to create a struct pci_device_id that matches a 896 * specific PCI device. The subvendor, and subdevice fields will be set 897 * to PCI_ANY_ID. The macro allows the next field to follow as the device 898 * private data. 899 */ 900 #define PCI_VDEVICE(vend, dev) \ 901 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 902 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 903 904 /** 905 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 906 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 907 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 908 * @data: the driver data to be filled 909 * 910 * This macro is used to create a struct pci_device_id that matches a 911 * specific PCI device. The subvendor, and subdevice fields will be set 912 * to PCI_ANY_ID. 913 */ 914 #define PCI_DEVICE_DATA(vend, dev, data) \ 915 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 916 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 917 .driver_data = (kernel_ulong_t)(data) 918 919 enum { 920 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 921 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 922 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 923 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 924 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 925 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 926 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 927 }; 928 929 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 930 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 931 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 932 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 933 934 /* These external functions are only available when PCI support is enabled */ 935 #ifdef CONFIG_PCI 936 937 extern unsigned int pci_flags; 938 939 static inline void pci_set_flags(int flags) { pci_flags = flags; } 940 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 941 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 942 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 943 944 void pcie_bus_configure_settings(struct pci_bus *bus); 945 946 enum pcie_bus_config_types { 947 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 948 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 949 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 950 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 951 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 952 }; 953 954 extern enum pcie_bus_config_types pcie_bus_config; 955 956 extern struct bus_type pci_bus_type; 957 958 /* Do NOT directly access these two variables, unless you are arch-specific PCI 959 * code, or PCI core code. */ 960 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 961 /* Some device drivers need know if PCI is initiated */ 962 int no_pci_devices(void); 963 964 void pcibios_resource_survey_bus(struct pci_bus *bus); 965 void pcibios_bus_add_device(struct pci_dev *pdev); 966 void pcibios_add_bus(struct pci_bus *bus); 967 void pcibios_remove_bus(struct pci_bus *bus); 968 void pcibios_fixup_bus(struct pci_bus *); 969 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 970 /* Architecture-specific versions may override this (weak) */ 971 char *pcibios_setup(char *str); 972 973 /* Used only when drivers/pci/setup.c is used */ 974 resource_size_t pcibios_align_resource(void *, const struct resource *, 975 resource_size_t, 976 resource_size_t); 977 978 /* Weak but can be overridden by arch */ 979 void pci_fixup_cardbus(struct pci_bus *); 980 981 /* Generic PCI functions used internally */ 982 983 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 984 struct resource *res); 985 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 986 struct pci_bus_region *region); 987 void pcibios_scan_specific_bus(int busn); 988 struct pci_bus *pci_find_bus(int domain, int busnr); 989 void pci_bus_add_devices(const struct pci_bus *bus); 990 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 991 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 992 struct pci_ops *ops, void *sysdata, 993 struct list_head *resources); 994 int pci_host_probe(struct pci_host_bridge *bridge); 995 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 996 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 997 void pci_bus_release_busn_res(struct pci_bus *b); 998 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 999 struct pci_ops *ops, void *sysdata, 1000 struct list_head *resources); 1001 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1002 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1003 int busnr); 1004 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1005 const char *name, 1006 struct hotplug_slot *hotplug); 1007 void pci_destroy_slot(struct pci_slot *slot); 1008 #ifdef CONFIG_SYSFS 1009 void pci_dev_assign_slot(struct pci_dev *dev); 1010 #else 1011 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1012 #endif 1013 int pci_scan_slot(struct pci_bus *bus, int devfn); 1014 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1015 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1016 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1017 void pci_bus_add_device(struct pci_dev *dev); 1018 void pci_read_bridge_bases(struct pci_bus *child); 1019 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1020 struct resource *res); 1021 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 1022 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1023 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1024 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1025 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1026 void pci_dev_put(struct pci_dev *dev); 1027 void pci_remove_bus(struct pci_bus *b); 1028 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1029 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1030 void pci_stop_root_bus(struct pci_bus *bus); 1031 void pci_remove_root_bus(struct pci_bus *bus); 1032 void pci_setup_cardbus(struct pci_bus *bus); 1033 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1034 void pci_sort_breadthfirst(void); 1035 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1036 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1037 1038 /* Generic PCI functions exported to card drivers */ 1039 1040 enum pci_lost_interrupt_reason { 1041 PCI_LOST_IRQ_NO_INFORMATION = 0, 1042 PCI_LOST_IRQ_DISABLE_MSI, 1043 PCI_LOST_IRQ_DISABLE_MSIX, 1044 PCI_LOST_IRQ_DISABLE_ACPI, 1045 }; 1046 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 1047 int pci_find_capability(struct pci_dev *dev, int cap); 1048 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1049 int pci_find_ext_capability(struct pci_dev *dev, int cap); 1050 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 1051 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1052 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 1053 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1054 1055 u64 pci_get_dsn(struct pci_dev *dev); 1056 1057 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1058 struct pci_dev *from); 1059 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1060 unsigned int ss_vendor, unsigned int ss_device, 1061 struct pci_dev *from); 1062 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1063 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1064 unsigned int devfn); 1065 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1066 int pci_dev_present(const struct pci_device_id *ids); 1067 1068 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1069 int where, u8 *val); 1070 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1071 int where, u16 *val); 1072 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1073 int where, u32 *val); 1074 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1075 int where, u8 val); 1076 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1077 int where, u16 val); 1078 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1079 int where, u32 val); 1080 1081 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1082 int where, int size, u32 *val); 1083 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1084 int where, int size, u32 val); 1085 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1086 int where, int size, u32 *val); 1087 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1088 int where, int size, u32 val); 1089 1090 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1091 1092 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1093 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1094 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1095 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1096 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1097 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1098 1099 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1100 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1101 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1102 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1103 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1104 u16 clear, u16 set); 1105 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1106 u32 clear, u32 set); 1107 1108 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1109 u16 set) 1110 { 1111 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1112 } 1113 1114 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1115 u32 set) 1116 { 1117 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1118 } 1119 1120 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1121 u16 clear) 1122 { 1123 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1124 } 1125 1126 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1127 u32 clear) 1128 { 1129 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1130 } 1131 1132 /* User-space driven config access */ 1133 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1134 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1135 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1136 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1137 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1138 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1139 1140 int __must_check pci_enable_device(struct pci_dev *dev); 1141 int __must_check pci_enable_device_io(struct pci_dev *dev); 1142 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1143 int __must_check pci_reenable_device(struct pci_dev *); 1144 int __must_check pcim_enable_device(struct pci_dev *pdev); 1145 void pcim_pin_device(struct pci_dev *pdev); 1146 1147 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1148 { 1149 /* 1150 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1151 * writable and no quirk has marked the feature broken. 1152 */ 1153 return !pdev->broken_intx_masking; 1154 } 1155 1156 static inline int pci_is_enabled(struct pci_dev *pdev) 1157 { 1158 return (atomic_read(&pdev->enable_cnt) > 0); 1159 } 1160 1161 static inline int pci_is_managed(struct pci_dev *pdev) 1162 { 1163 return pdev->is_managed; 1164 } 1165 1166 void pci_disable_device(struct pci_dev *dev); 1167 1168 extern unsigned int pcibios_max_latency; 1169 void pci_set_master(struct pci_dev *dev); 1170 void pci_clear_master(struct pci_dev *dev); 1171 1172 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1173 int pci_set_cacheline_size(struct pci_dev *dev); 1174 #define HAVE_PCI_SET_MWI 1175 int __must_check pci_set_mwi(struct pci_dev *dev); 1176 int __must_check pcim_set_mwi(struct pci_dev *dev); 1177 int pci_try_set_mwi(struct pci_dev *dev); 1178 void pci_clear_mwi(struct pci_dev *dev); 1179 void pci_intx(struct pci_dev *dev, int enable); 1180 bool pci_check_and_mask_intx(struct pci_dev *dev); 1181 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1182 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1183 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1184 int pcix_get_max_mmrbc(struct pci_dev *dev); 1185 int pcix_get_mmrbc(struct pci_dev *dev); 1186 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1187 int pcie_get_readrq(struct pci_dev *dev); 1188 int pcie_set_readrq(struct pci_dev *dev, int rq); 1189 int pcie_get_mps(struct pci_dev *dev); 1190 int pcie_set_mps(struct pci_dev *dev, int mps); 1191 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1192 enum pci_bus_speed *speed, 1193 enum pcie_link_width *width); 1194 void pcie_print_link_status(struct pci_dev *dev); 1195 bool pcie_has_flr(struct pci_dev *dev); 1196 int pcie_flr(struct pci_dev *dev); 1197 int __pci_reset_function_locked(struct pci_dev *dev); 1198 int pci_reset_function(struct pci_dev *dev); 1199 int pci_reset_function_locked(struct pci_dev *dev); 1200 int pci_try_reset_function(struct pci_dev *dev); 1201 int pci_probe_reset_slot(struct pci_slot *slot); 1202 int pci_probe_reset_bus(struct pci_bus *bus); 1203 int pci_reset_bus(struct pci_dev *dev); 1204 void pci_reset_secondary_bus(struct pci_dev *dev); 1205 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1206 void pci_update_resource(struct pci_dev *dev, int resno); 1207 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1208 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1209 void pci_release_resource(struct pci_dev *dev, int resno); 1210 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1211 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1212 bool pci_device_is_present(struct pci_dev *pdev); 1213 void pci_ignore_hotplug(struct pci_dev *dev); 1214 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1215 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1216 1217 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1218 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1219 const char *fmt, ...); 1220 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1221 1222 /* ROM control related routines */ 1223 int pci_enable_rom(struct pci_dev *pdev); 1224 void pci_disable_rom(struct pci_dev *pdev); 1225 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1226 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1227 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1228 1229 /* Power management related routines */ 1230 int pci_save_state(struct pci_dev *dev); 1231 void pci_restore_state(struct pci_dev *dev); 1232 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1233 int pci_load_saved_state(struct pci_dev *dev, 1234 struct pci_saved_state *state); 1235 int pci_load_and_free_saved_state(struct pci_dev *dev, 1236 struct pci_saved_state **state); 1237 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1238 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1239 u16 cap); 1240 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1241 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1242 u16 cap, unsigned int size); 1243 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1244 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1245 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1246 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1247 void pci_pme_active(struct pci_dev *dev, bool enable); 1248 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1249 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1250 int pci_prepare_to_sleep(struct pci_dev *dev); 1251 int pci_back_from_sleep(struct pci_dev *dev); 1252 bool pci_dev_run_wake(struct pci_dev *dev); 1253 void pci_d3cold_enable(struct pci_dev *dev); 1254 void pci_d3cold_disable(struct pci_dev *dev); 1255 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1256 void pci_wakeup_bus(struct pci_bus *bus); 1257 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1258 1259 /* For use by arch with custom probe code */ 1260 void set_pcie_port_type(struct pci_dev *pdev); 1261 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1262 1263 /* Functions for PCI Hotplug drivers to use */ 1264 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1265 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1266 unsigned int pci_rescan_bus(struct pci_bus *bus); 1267 void pci_lock_rescan_remove(void); 1268 void pci_unlock_rescan_remove(void); 1269 1270 /* Vital Product Data routines */ 1271 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1272 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1273 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1274 1275 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1276 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1277 void pci_bus_assign_resources(const struct pci_bus *bus); 1278 void pci_bus_claim_resources(struct pci_bus *bus); 1279 void pci_bus_size_bridges(struct pci_bus *bus); 1280 int pci_claim_resource(struct pci_dev *, int); 1281 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1282 void pci_assign_unassigned_resources(void); 1283 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1284 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1285 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1286 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1287 void pdev_enable_device(struct pci_dev *); 1288 int pci_enable_resources(struct pci_dev *, int mask); 1289 void pci_assign_irq(struct pci_dev *dev); 1290 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1291 #define HAVE_PCI_REQ_REGIONS 2 1292 int __must_check pci_request_regions(struct pci_dev *, const char *); 1293 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1294 void pci_release_regions(struct pci_dev *); 1295 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1296 void pci_release_region(struct pci_dev *, int); 1297 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1298 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1299 void pci_release_selected_regions(struct pci_dev *, int); 1300 1301 /* drivers/pci/bus.c */ 1302 void pci_add_resource(struct list_head *resources, struct resource *res); 1303 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1304 resource_size_t offset); 1305 void pci_free_resource_list(struct list_head *resources); 1306 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1307 unsigned int flags); 1308 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1309 void pci_bus_remove_resources(struct pci_bus *bus); 1310 int devm_request_pci_bus_resources(struct device *dev, 1311 struct list_head *resources); 1312 1313 /* Temporary until new and working PCI SBR API in place */ 1314 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1315 1316 #define pci_bus_for_each_resource(bus, res, i) \ 1317 for (i = 0; \ 1318 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1319 i++) 1320 1321 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1322 struct resource *res, resource_size_t size, 1323 resource_size_t align, resource_size_t min, 1324 unsigned long type_mask, 1325 resource_size_t (*alignf)(void *, 1326 const struct resource *, 1327 resource_size_t, 1328 resource_size_t), 1329 void *alignf_data); 1330 1331 1332 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1333 resource_size_t size); 1334 unsigned long pci_address_to_pio(phys_addr_t addr); 1335 phys_addr_t pci_pio_to_address(unsigned long pio); 1336 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1337 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1338 phys_addr_t phys_addr); 1339 void pci_unmap_iospace(struct resource *res); 1340 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1341 resource_size_t offset, 1342 resource_size_t size); 1343 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1344 struct resource *res); 1345 1346 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1347 { 1348 struct pci_bus_region region; 1349 1350 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1351 return region.start; 1352 } 1353 1354 /* Proper probing supporting hot-pluggable devices */ 1355 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1356 const char *mod_name); 1357 1358 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1359 #define pci_register_driver(driver) \ 1360 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1361 1362 void pci_unregister_driver(struct pci_driver *dev); 1363 1364 /** 1365 * module_pci_driver() - Helper macro for registering a PCI driver 1366 * @__pci_driver: pci_driver struct 1367 * 1368 * Helper macro for PCI drivers which do not do anything special in module 1369 * init/exit. This eliminates a lot of boilerplate. Each module may only 1370 * use this macro once, and calling it replaces module_init() and module_exit() 1371 */ 1372 #define module_pci_driver(__pci_driver) \ 1373 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1374 1375 /** 1376 * builtin_pci_driver() - Helper macro for registering a PCI driver 1377 * @__pci_driver: pci_driver struct 1378 * 1379 * Helper macro for PCI drivers which do not do anything special in their 1380 * init code. This eliminates a lot of boilerplate. Each driver may only 1381 * use this macro once, and calling it replaces device_initcall(...) 1382 */ 1383 #define builtin_pci_driver(__pci_driver) \ 1384 builtin_driver(__pci_driver, pci_register_driver) 1385 1386 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1387 int pci_add_dynid(struct pci_driver *drv, 1388 unsigned int vendor, unsigned int device, 1389 unsigned int subvendor, unsigned int subdevice, 1390 unsigned int class, unsigned int class_mask, 1391 unsigned long driver_data); 1392 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1393 struct pci_dev *dev); 1394 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1395 int pass); 1396 1397 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1398 void *userdata); 1399 int pci_cfg_space_size(struct pci_dev *dev); 1400 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1401 void pci_setup_bridge(struct pci_bus *bus); 1402 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1403 unsigned long type); 1404 1405 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1406 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1407 1408 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1409 unsigned int command_bits, u32 flags); 1410 1411 /* 1412 * Virtual interrupts allow for more interrupts to be allocated 1413 * than the device has interrupts for. These are not programmed 1414 * into the device's MSI-X table and must be handled by some 1415 * other driver means. 1416 */ 1417 #define PCI_IRQ_VIRTUAL (1 << 4) 1418 1419 #define PCI_IRQ_ALL_TYPES \ 1420 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1421 1422 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1423 1424 #include <linux/dmapool.h> 1425 1426 #define pci_pool dma_pool 1427 #define pci_pool_create(name, pdev, size, align, allocation) \ 1428 dma_pool_create(name, &pdev->dev, size, align, allocation) 1429 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1430 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1431 #define pci_pool_zalloc(pool, flags, handle) \ 1432 dma_pool_zalloc(pool, flags, handle) 1433 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1434 1435 struct msix_entry { 1436 u32 vector; /* Kernel uses to write allocated vector */ 1437 u16 entry; /* Driver uses to specify entry, OS writes */ 1438 }; 1439 1440 #ifdef CONFIG_PCI_MSI 1441 int pci_msi_vec_count(struct pci_dev *dev); 1442 void pci_disable_msi(struct pci_dev *dev); 1443 int pci_msix_vec_count(struct pci_dev *dev); 1444 void pci_disable_msix(struct pci_dev *dev); 1445 void pci_restore_msi_state(struct pci_dev *dev); 1446 int pci_msi_enabled(void); 1447 int pci_enable_msi(struct pci_dev *dev); 1448 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1449 int minvec, int maxvec); 1450 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1451 struct msix_entry *entries, int nvec) 1452 { 1453 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1454 if (rc < 0) 1455 return rc; 1456 return 0; 1457 } 1458 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1459 unsigned int max_vecs, unsigned int flags, 1460 struct irq_affinity *affd); 1461 1462 void pci_free_irq_vectors(struct pci_dev *dev); 1463 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1464 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1465 1466 #else 1467 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1468 static inline void pci_disable_msi(struct pci_dev *dev) { } 1469 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1470 static inline void pci_disable_msix(struct pci_dev *dev) { } 1471 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1472 static inline int pci_msi_enabled(void) { return 0; } 1473 static inline int pci_enable_msi(struct pci_dev *dev) 1474 { return -ENOSYS; } 1475 static inline int pci_enable_msix_range(struct pci_dev *dev, 1476 struct msix_entry *entries, int minvec, int maxvec) 1477 { return -ENOSYS; } 1478 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1479 struct msix_entry *entries, int nvec) 1480 { return -ENOSYS; } 1481 1482 static inline int 1483 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1484 unsigned int max_vecs, unsigned int flags, 1485 struct irq_affinity *aff_desc) 1486 { 1487 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1488 return 1; 1489 return -ENOSPC; 1490 } 1491 1492 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1493 { 1494 } 1495 1496 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1497 { 1498 if (WARN_ON_ONCE(nr > 0)) 1499 return -EINVAL; 1500 return dev->irq; 1501 } 1502 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1503 int vec) 1504 { 1505 return cpu_possible_mask; 1506 } 1507 #endif 1508 1509 /** 1510 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1511 * @d: the INTx IRQ domain 1512 * @node: the DT node for the device whose interrupt we're translating 1513 * @intspec: the interrupt specifier data from the DT 1514 * @intsize: the number of entries in @intspec 1515 * @out_hwirq: pointer at which to write the hwirq number 1516 * @out_type: pointer at which to write the interrupt type 1517 * 1518 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1519 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1520 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1521 * INTx value to obtain the hwirq number. 1522 * 1523 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1524 */ 1525 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1526 struct device_node *node, 1527 const u32 *intspec, 1528 unsigned int intsize, 1529 unsigned long *out_hwirq, 1530 unsigned int *out_type) 1531 { 1532 const u32 intx = intspec[0]; 1533 1534 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1535 return -EINVAL; 1536 1537 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1538 return 0; 1539 } 1540 1541 #ifdef CONFIG_PCIEPORTBUS 1542 extern bool pcie_ports_disabled; 1543 extern bool pcie_ports_native; 1544 #else 1545 #define pcie_ports_disabled true 1546 #define pcie_ports_native false 1547 #endif 1548 1549 #define PCIE_LINK_STATE_L0S BIT(0) 1550 #define PCIE_LINK_STATE_L1 BIT(1) 1551 #define PCIE_LINK_STATE_CLKPM BIT(2) 1552 #define PCIE_LINK_STATE_L1_1 BIT(3) 1553 #define PCIE_LINK_STATE_L1_2 BIT(4) 1554 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1555 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1556 1557 #ifdef CONFIG_PCIEASPM 1558 int pci_disable_link_state(struct pci_dev *pdev, int state); 1559 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1560 void pcie_no_aspm(void); 1561 bool pcie_aspm_support_enabled(void); 1562 bool pcie_aspm_enabled(struct pci_dev *pdev); 1563 #else 1564 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1565 { return 0; } 1566 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1567 { return 0; } 1568 static inline void pcie_no_aspm(void) { } 1569 static inline bool pcie_aspm_support_enabled(void) { return false; } 1570 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1571 #endif 1572 1573 #ifdef CONFIG_PCIEAER 1574 bool pci_aer_available(void); 1575 #else 1576 static inline bool pci_aer_available(void) { return false; } 1577 #endif 1578 1579 bool pci_ats_disabled(void); 1580 1581 void pci_cfg_access_lock(struct pci_dev *dev); 1582 bool pci_cfg_access_trylock(struct pci_dev *dev); 1583 void pci_cfg_access_unlock(struct pci_dev *dev); 1584 1585 /* 1586 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1587 * a PCI domain is defined to be a set of PCI buses which share 1588 * configuration space. 1589 */ 1590 #ifdef CONFIG_PCI_DOMAINS 1591 extern int pci_domains_supported; 1592 #else 1593 enum { pci_domains_supported = 0 }; 1594 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1595 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1596 #endif /* CONFIG_PCI_DOMAINS */ 1597 1598 /* 1599 * Generic implementation for PCI domain support. If your 1600 * architecture does not need custom management of PCI 1601 * domains then this implementation will be used 1602 */ 1603 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1604 static inline int pci_domain_nr(struct pci_bus *bus) 1605 { 1606 return bus->domain_nr; 1607 } 1608 #ifdef CONFIG_ACPI 1609 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1610 #else 1611 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1612 { return 0; } 1613 #endif 1614 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1615 #endif 1616 1617 /* Some architectures require additional setup to direct VGA traffic */ 1618 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1619 unsigned int command_bits, u32 flags); 1620 void pci_register_set_vga_state(arch_set_vga_state_t func); 1621 1622 static inline int 1623 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1624 { 1625 return pci_request_selected_regions(pdev, 1626 pci_select_bars(pdev, IORESOURCE_IO), name); 1627 } 1628 1629 static inline void 1630 pci_release_io_regions(struct pci_dev *pdev) 1631 { 1632 return pci_release_selected_regions(pdev, 1633 pci_select_bars(pdev, IORESOURCE_IO)); 1634 } 1635 1636 static inline int 1637 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1638 { 1639 return pci_request_selected_regions(pdev, 1640 pci_select_bars(pdev, IORESOURCE_MEM), name); 1641 } 1642 1643 static inline void 1644 pci_release_mem_regions(struct pci_dev *pdev) 1645 { 1646 return pci_release_selected_regions(pdev, 1647 pci_select_bars(pdev, IORESOURCE_MEM)); 1648 } 1649 1650 #else /* CONFIG_PCI is not enabled */ 1651 1652 static inline void pci_set_flags(int flags) { } 1653 static inline void pci_add_flags(int flags) { } 1654 static inline void pci_clear_flags(int flags) { } 1655 static inline int pci_has_flag(int flag) { return 0; } 1656 1657 /* 1658 * If the system does not have PCI, clearly these return errors. Define 1659 * these as simple inline functions to avoid hair in drivers. 1660 */ 1661 #define _PCI_NOP(o, s, t) \ 1662 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1663 int where, t val) \ 1664 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1665 1666 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1667 _PCI_NOP(o, word, u16 x) \ 1668 _PCI_NOP(o, dword, u32 x) 1669 _PCI_NOP_ALL(read, *) 1670 _PCI_NOP_ALL(write,) 1671 1672 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1673 unsigned int device, 1674 struct pci_dev *from) 1675 { return NULL; } 1676 1677 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1678 unsigned int device, 1679 unsigned int ss_vendor, 1680 unsigned int ss_device, 1681 struct pci_dev *from) 1682 { return NULL; } 1683 1684 static inline struct pci_dev *pci_get_class(unsigned int class, 1685 struct pci_dev *from) 1686 { return NULL; } 1687 1688 #define pci_dev_present(ids) (0) 1689 #define no_pci_devices() (1) 1690 #define pci_dev_put(dev) do { } while (0) 1691 1692 static inline void pci_set_master(struct pci_dev *dev) { } 1693 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1694 static inline void pci_disable_device(struct pci_dev *dev) { } 1695 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1696 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1697 { return -EBUSY; } 1698 static inline int __pci_register_driver(struct pci_driver *drv, 1699 struct module *owner) 1700 { return 0; } 1701 static inline int pci_register_driver(struct pci_driver *drv) 1702 { return 0; } 1703 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1704 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1705 { return 0; } 1706 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1707 int cap) 1708 { return 0; } 1709 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1710 { return 0; } 1711 1712 static inline u64 pci_get_dsn(struct pci_dev *dev) 1713 { return 0; } 1714 1715 /* Power management related routines */ 1716 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1717 static inline void pci_restore_state(struct pci_dev *dev) { } 1718 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1719 { return 0; } 1720 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1721 { return 0; } 1722 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1723 pm_message_t state) 1724 { return PCI_D0; } 1725 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1726 int enable) 1727 { return 0; } 1728 1729 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1730 struct resource *res) 1731 { return NULL; } 1732 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1733 { return -EIO; } 1734 static inline void pci_release_regions(struct pci_dev *dev) { } 1735 1736 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1737 1738 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1739 { return NULL; } 1740 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1741 unsigned int devfn) 1742 { return NULL; } 1743 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1744 unsigned int bus, unsigned int devfn) 1745 { return NULL; } 1746 1747 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1748 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1749 1750 #define dev_is_pci(d) (false) 1751 #define dev_is_pf(d) (false) 1752 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1753 { return false; } 1754 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1755 struct device_node *node, 1756 const u32 *intspec, 1757 unsigned int intsize, 1758 unsigned long *out_hwirq, 1759 unsigned int *out_type) 1760 { return -EINVAL; } 1761 1762 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1763 struct pci_dev *dev) 1764 { return NULL; } 1765 static inline bool pci_ats_disabled(void) { return true; } 1766 1767 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1768 { 1769 return -EINVAL; 1770 } 1771 1772 static inline int 1773 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1774 unsigned int max_vecs, unsigned int flags, 1775 struct irq_affinity *aff_desc) 1776 { 1777 return -ENOSPC; 1778 } 1779 #endif /* CONFIG_PCI */ 1780 1781 static inline int 1782 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1783 unsigned int max_vecs, unsigned int flags) 1784 { 1785 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1786 NULL); 1787 } 1788 1789 /* Include architecture-dependent settings and functions */ 1790 1791 #include <asm/pci.h> 1792 1793 /* These two functions provide almost identical functionality. Depending 1794 * on the architecture, one will be implemented as a wrapper around the 1795 * other (in drivers/pci/mmap.c). 1796 * 1797 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1798 * is expected to be an offset within that region. 1799 * 1800 * pci_mmap_page_range() is the legacy architecture-specific interface, 1801 * which accepts a "user visible" resource address converted by 1802 * pci_resource_to_user(), as used in the legacy mmap() interface in 1803 * /proc/bus/pci/. 1804 */ 1805 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1806 struct vm_area_struct *vma, 1807 enum pci_mmap_state mmap_state, int write_combine); 1808 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1809 struct vm_area_struct *vma, 1810 enum pci_mmap_state mmap_state, int write_combine); 1811 1812 #ifndef arch_can_pci_mmap_wc 1813 #define arch_can_pci_mmap_wc() 0 1814 #endif 1815 1816 #ifndef arch_can_pci_mmap_io 1817 #define arch_can_pci_mmap_io() 0 1818 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1819 #else 1820 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1821 #endif 1822 1823 #ifndef pci_root_bus_fwnode 1824 #define pci_root_bus_fwnode(bus) NULL 1825 #endif 1826 1827 /* 1828 * These helpers provide future and backwards compatibility 1829 * for accessing popular PCI BAR info 1830 */ 1831 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1832 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1833 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1834 #define pci_resource_len(dev,bar) \ 1835 ((pci_resource_start((dev), (bar)) == 0 && \ 1836 pci_resource_end((dev), (bar)) == \ 1837 pci_resource_start((dev), (bar))) ? 0 : \ 1838 \ 1839 (pci_resource_end((dev), (bar)) - \ 1840 pci_resource_start((dev), (bar)) + 1)) 1841 1842 /* 1843 * Similar to the helpers above, these manipulate per-pci_dev 1844 * driver-specific data. They are really just a wrapper around 1845 * the generic device structure functions of these calls. 1846 */ 1847 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1848 { 1849 return dev_get_drvdata(&pdev->dev); 1850 } 1851 1852 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1853 { 1854 dev_set_drvdata(&pdev->dev, data); 1855 } 1856 1857 static inline const char *pci_name(const struct pci_dev *pdev) 1858 { 1859 return dev_name(&pdev->dev); 1860 } 1861 1862 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1863 const struct resource *rsrc, 1864 resource_size_t *start, resource_size_t *end); 1865 1866 /* 1867 * The world is not perfect and supplies us with broken PCI devices. 1868 * For at least a part of these bugs we need a work-around, so both 1869 * generic (drivers/pci/quirks.c) and per-architecture code can define 1870 * fixup hooks to be called for particular buggy devices. 1871 */ 1872 1873 struct pci_fixup { 1874 u16 vendor; /* Or PCI_ANY_ID */ 1875 u16 device; /* Or PCI_ANY_ID */ 1876 u32 class; /* Or PCI_ANY_ID */ 1877 unsigned int class_shift; /* should be 0, 8, 16 */ 1878 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1879 int hook_offset; 1880 #else 1881 void (*hook)(struct pci_dev *dev); 1882 #endif 1883 }; 1884 1885 enum pci_fixup_pass { 1886 pci_fixup_early, /* Before probing BARs */ 1887 pci_fixup_header, /* After reading configuration header */ 1888 pci_fixup_final, /* Final phase of device fixups */ 1889 pci_fixup_enable, /* pci_enable_device() time */ 1890 pci_fixup_resume, /* pci_device_resume() */ 1891 pci_fixup_suspend, /* pci_device_suspend() */ 1892 pci_fixup_resume_early, /* pci_device_resume_early() */ 1893 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1894 }; 1895 1896 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1897 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1898 class_shift, hook) \ 1899 __ADDRESSABLE(hook) \ 1900 asm(".section " #sec ", \"a\" \n" \ 1901 ".balign 16 \n" \ 1902 ".short " #vendor ", " #device " \n" \ 1903 ".long " #class ", " #class_shift " \n" \ 1904 ".long " #hook " - . \n" \ 1905 ".previous \n"); 1906 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1907 class_shift, hook) \ 1908 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1909 class_shift, hook) 1910 #else 1911 /* Anonymous variables would be nice... */ 1912 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1913 class_shift, hook) \ 1914 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1915 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1916 = { vendor, device, class, class_shift, hook }; 1917 #endif 1918 1919 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1920 class_shift, hook) \ 1921 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1922 hook, vendor, device, class, class_shift, hook) 1923 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1924 class_shift, hook) \ 1925 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1926 hook, vendor, device, class, class_shift, hook) 1927 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1928 class_shift, hook) \ 1929 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1930 hook, vendor, device, class, class_shift, hook) 1931 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1932 class_shift, hook) \ 1933 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1934 hook, vendor, device, class, class_shift, hook) 1935 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1936 class_shift, hook) \ 1937 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1938 resume##hook, vendor, device, class, class_shift, hook) 1939 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1940 class_shift, hook) \ 1941 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1942 resume_early##hook, vendor, device, class, class_shift, hook) 1943 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1944 class_shift, hook) \ 1945 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1946 suspend##hook, vendor, device, class, class_shift, hook) 1947 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1948 class_shift, hook) \ 1949 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1950 suspend_late##hook, vendor, device, class, class_shift, hook) 1951 1952 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1953 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1954 hook, vendor, device, PCI_ANY_ID, 0, hook) 1955 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1956 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1957 hook, vendor, device, PCI_ANY_ID, 0, hook) 1958 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1959 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1960 hook, vendor, device, PCI_ANY_ID, 0, hook) 1961 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1962 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1963 hook, vendor, device, PCI_ANY_ID, 0, hook) 1964 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1965 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1966 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1967 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1968 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1969 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1970 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1971 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1972 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1973 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1974 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1975 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1976 1977 #ifdef CONFIG_PCI_QUIRKS 1978 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1979 #else 1980 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1981 struct pci_dev *dev) { } 1982 #endif 1983 1984 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1985 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1986 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1987 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1988 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1989 const char *name); 1990 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1991 1992 extern int pci_pci_problems; 1993 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1994 #define PCIPCI_TRITON 2 1995 #define PCIPCI_NATOMA 4 1996 #define PCIPCI_VIAETBF 8 1997 #define PCIPCI_VSFX 16 1998 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1999 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2000 2001 extern unsigned long pci_cardbus_io_size; 2002 extern unsigned long pci_cardbus_mem_size; 2003 extern u8 pci_dfl_cache_line_size; 2004 extern u8 pci_cache_line_size; 2005 2006 /* Architecture-specific versions may override these (weak) */ 2007 void pcibios_disable_device(struct pci_dev *dev); 2008 void pcibios_set_master(struct pci_dev *dev); 2009 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2010 enum pcie_reset_state state); 2011 int pcibios_add_device(struct pci_dev *dev); 2012 void pcibios_release_device(struct pci_dev *dev); 2013 #ifdef CONFIG_PCI 2014 void pcibios_penalize_isa_irq(int irq, int active); 2015 #else 2016 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2017 #endif 2018 int pcibios_alloc_irq(struct pci_dev *dev); 2019 void pcibios_free_irq(struct pci_dev *dev); 2020 resource_size_t pcibios_default_alignment(void); 2021 2022 #ifdef CONFIG_HIBERNATE_CALLBACKS 2023 extern struct dev_pm_ops pcibios_pm_ops; 2024 #endif 2025 2026 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2027 void __init pci_mmcfg_early_init(void); 2028 void __init pci_mmcfg_late_init(void); 2029 #else 2030 static inline void pci_mmcfg_early_init(void) { } 2031 static inline void pci_mmcfg_late_init(void) { } 2032 #endif 2033 2034 int pci_ext_cfg_avail(void); 2035 2036 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2037 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2038 2039 #ifdef CONFIG_PCI_IOV 2040 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2041 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2042 2043 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2044 void pci_disable_sriov(struct pci_dev *dev); 2045 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2046 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2047 int pci_num_vf(struct pci_dev *dev); 2048 int pci_vfs_assigned(struct pci_dev *dev); 2049 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2050 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2051 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2052 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2053 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2054 2055 /* Arch may override these (weak) */ 2056 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2057 int pcibios_sriov_disable(struct pci_dev *pdev); 2058 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2059 #else 2060 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2061 { 2062 return -ENOSYS; 2063 } 2064 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2065 { 2066 return -ENOSYS; 2067 } 2068 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2069 { return -ENODEV; } 2070 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2071 { 2072 return -ENOSYS; 2073 } 2074 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2075 int id) { } 2076 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2077 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2078 static inline int pci_vfs_assigned(struct pci_dev *dev) 2079 { return 0; } 2080 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2081 { return 0; } 2082 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2083 { return 0; } 2084 #define pci_sriov_configure_simple NULL 2085 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2086 { return 0; } 2087 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2088 #endif 2089 2090 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2091 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2092 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2093 #endif 2094 2095 /** 2096 * pci_pcie_cap - get the saved PCIe capability offset 2097 * @dev: PCI device 2098 * 2099 * PCIe capability offset is calculated at PCI device initialization 2100 * time and saved in the data structure. This function returns saved 2101 * PCIe capability offset. Using this instead of pci_find_capability() 2102 * reduces unnecessary search in the PCI configuration space. If you 2103 * need to calculate PCIe capability offset from raw device for some 2104 * reasons, please use pci_find_capability() instead. 2105 */ 2106 static inline int pci_pcie_cap(struct pci_dev *dev) 2107 { 2108 return dev->pcie_cap; 2109 } 2110 2111 /** 2112 * pci_is_pcie - check if the PCI device is PCI Express capable 2113 * @dev: PCI device 2114 * 2115 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2116 */ 2117 static inline bool pci_is_pcie(struct pci_dev *dev) 2118 { 2119 return pci_pcie_cap(dev); 2120 } 2121 2122 /** 2123 * pcie_caps_reg - get the PCIe Capabilities Register 2124 * @dev: PCI device 2125 */ 2126 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2127 { 2128 return dev->pcie_flags_reg; 2129 } 2130 2131 /** 2132 * pci_pcie_type - get the PCIe device/port type 2133 * @dev: PCI device 2134 */ 2135 static inline int pci_pcie_type(const struct pci_dev *dev) 2136 { 2137 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2138 } 2139 2140 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2141 { 2142 while (1) { 2143 if (!pci_is_pcie(dev)) 2144 break; 2145 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2146 return dev; 2147 if (!dev->bus->self) 2148 break; 2149 dev = dev->bus->self; 2150 } 2151 return NULL; 2152 } 2153 2154 void pci_request_acs(void); 2155 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2156 bool pci_acs_path_enabled(struct pci_dev *start, 2157 struct pci_dev *end, u16 acs_flags); 2158 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2159 2160 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2161 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2162 2163 /* Large Resource Data Type Tag Item Names */ 2164 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2165 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2166 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2167 2168 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2169 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2170 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2171 2172 /* Small Resource Data Type Tag Item Names */ 2173 #define PCI_VPD_STIN_END 0x0f /* End */ 2174 2175 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2176 2177 #define PCI_VPD_SRDT_TIN_MASK 0x78 2178 #define PCI_VPD_SRDT_LEN_MASK 0x07 2179 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2180 2181 #define PCI_VPD_LRDT_TAG_SIZE 3 2182 #define PCI_VPD_SRDT_TAG_SIZE 1 2183 2184 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2185 2186 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2187 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2188 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2189 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2190 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2191 2192 /** 2193 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2194 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2195 * 2196 * Returns the extracted Large Resource Data Type length. 2197 */ 2198 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2199 { 2200 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2201 } 2202 2203 /** 2204 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2205 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2206 * 2207 * Returns the extracted Large Resource Data Type Tag item. 2208 */ 2209 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2210 { 2211 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2212 } 2213 2214 /** 2215 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2216 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2217 * 2218 * Returns the extracted Small Resource Data Type length. 2219 */ 2220 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2221 { 2222 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2223 } 2224 2225 /** 2226 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2227 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2228 * 2229 * Returns the extracted Small Resource Data Type Tag Item. 2230 */ 2231 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2232 { 2233 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2234 } 2235 2236 /** 2237 * pci_vpd_info_field_size - Extracts the information field length 2238 * @info_field: Pointer to the beginning of an information field header 2239 * 2240 * Returns the extracted information field length. 2241 */ 2242 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2243 { 2244 return info_field[2]; 2245 } 2246 2247 /** 2248 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2249 * @buf: Pointer to buffered vpd data 2250 * @off: The offset into the buffer at which to begin the search 2251 * @len: The length of the vpd buffer 2252 * @rdt: The Resource Data Type to search for 2253 * 2254 * Returns the index where the Resource Data Type was found or 2255 * -ENOENT otherwise. 2256 */ 2257 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2258 2259 /** 2260 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2261 * @buf: Pointer to buffered vpd data 2262 * @off: The offset into the buffer at which to begin the search 2263 * @len: The length of the buffer area, relative to off, in which to search 2264 * @kw: The keyword to search for 2265 * 2266 * Returns the index where the information field keyword was found or 2267 * -ENOENT otherwise. 2268 */ 2269 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2270 unsigned int len, const char *kw); 2271 2272 /* PCI <-> OF binding helpers */ 2273 #ifdef CONFIG_OF 2274 struct device_node; 2275 struct irq_domain; 2276 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2277 int pci_parse_request_of_pci_ranges(struct device *dev, 2278 struct list_head *resources, 2279 struct list_head *ib_resources, 2280 struct resource **bus_range); 2281 2282 /* Arch may override this (weak) */ 2283 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2284 2285 #else /* CONFIG_OF */ 2286 static inline struct irq_domain * 2287 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2288 static inline int 2289 pci_parse_request_of_pci_ranges(struct device *dev, 2290 struct list_head *resources, 2291 struct list_head *ib_resources, 2292 struct resource **bus_range) 2293 { 2294 return -EINVAL; 2295 } 2296 #endif /* CONFIG_OF */ 2297 2298 static inline struct device_node * 2299 pci_device_to_OF_node(const struct pci_dev *pdev) 2300 { 2301 return pdev ? pdev->dev.of_node : NULL; 2302 } 2303 2304 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2305 { 2306 return bus ? bus->dev.of_node : NULL; 2307 } 2308 2309 #ifdef CONFIG_ACPI 2310 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2311 2312 void 2313 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2314 bool pci_pr3_present(struct pci_dev *pdev); 2315 #else 2316 static inline struct irq_domain * 2317 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2318 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2319 #endif 2320 2321 #ifdef CONFIG_EEH 2322 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2323 { 2324 return pdev->dev.archdata.edev; 2325 } 2326 #endif 2327 2328 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2329 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2330 int pci_for_each_dma_alias(struct pci_dev *pdev, 2331 int (*fn)(struct pci_dev *pdev, 2332 u16 alias, void *data), void *data); 2333 2334 /* Helper functions for operation of device flag */ 2335 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2336 { 2337 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2338 } 2339 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2340 { 2341 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2342 } 2343 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2344 { 2345 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2346 } 2347 2348 /** 2349 * pci_ari_enabled - query ARI forwarding status 2350 * @bus: the PCI bus 2351 * 2352 * Returns true if ARI forwarding is enabled. 2353 */ 2354 static inline bool pci_ari_enabled(struct pci_bus *bus) 2355 { 2356 return bus->self && bus->self->ari_enabled; 2357 } 2358 2359 /** 2360 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2361 * @pdev: PCI device to check 2362 * 2363 * Walk upwards from @pdev and check for each encountered bridge if it's part 2364 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2365 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2366 */ 2367 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2368 { 2369 struct pci_dev *parent = pdev; 2370 2371 if (pdev->is_thunderbolt) 2372 return true; 2373 2374 while ((parent = pci_upstream_bridge(parent))) 2375 if (parent->is_thunderbolt) 2376 return true; 2377 2378 return false; 2379 } 2380 2381 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2382 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2383 #endif 2384 2385 /* Provide the legacy pci_dma_* API */ 2386 #include <linux/pci-dma-compat.h> 2387 2388 #define pci_printk(level, pdev, fmt, arg...) \ 2389 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2390 2391 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2392 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2393 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2394 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2395 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2396 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2397 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2398 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2399 2400 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2401 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2402 2403 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2404 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2405 2406 #define pci_WARN(pdev, condition, fmt, arg...) \ 2407 WARN(condition, "%s %s: " fmt, \ 2408 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2409 2410 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2411 WARN_ONCE(condition, "%s %s: " fmt, \ 2412 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2413 2414 #endif /* LINUX_PCI_H */ 2415