1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 46 PCI_STATUS_SIG_SYSTEM_ERROR | \ 47 PCI_STATUS_REC_MASTER_ABORT | \ 48 PCI_STATUS_REC_TARGET_ABORT | \ 49 PCI_STATUS_SIG_TARGET_ABORT | \ 50 PCI_STATUS_PARITY) 51 52 /* 53 * The PCI interface treats multi-function devices as independent 54 * devices. The slot/function address of each device is encoded 55 * in a single byte as follows: 56 * 57 * 7:3 = slot 58 * 2:0 = function 59 * 60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 61 * In the interest of not exposing interfaces to user-space unnecessarily, 62 * the following kernel-only defines are being added here. 63 */ 64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 67 68 /* pci_slot represents a physical slot */ 69 struct pci_slot { 70 struct pci_bus *bus; /* Bus this slot is on */ 71 struct list_head list; /* Node in list of slots */ 72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 74 struct kobject kobj; 75 }; 76 77 static inline const char *pci_slot_name(const struct pci_slot *slot) 78 { 79 return kobject_name(&slot->kobj); 80 } 81 82 /* File state for mmap()s on /proc/bus/pci/X/Y */ 83 enum pci_mmap_state { 84 pci_mmap_io, 85 pci_mmap_mem 86 }; 87 88 /* For PCI devices, the region numbers are assigned this way: */ 89 enum { 90 /* #0-5: standard PCI resources */ 91 PCI_STD_RESOURCES, 92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 93 94 /* #6: expansion ROM resource */ 95 PCI_ROM_RESOURCE, 96 97 /* Device-specific resources */ 98 #ifdef CONFIG_PCI_IOV 99 PCI_IOV_RESOURCES, 100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 101 #endif 102 103 /* PCI-to-PCI (P2P) bridge windows */ 104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 107 108 /* CardBus bridge windows */ 109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 113 114 /* Total number of bridge resources for P2P and CardBus */ 115 #define PCI_BRIDGE_RESOURCE_NUM 4 116 117 /* Resources assigned to buses behind the bridge */ 118 PCI_BRIDGE_RESOURCES, 119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 120 PCI_BRIDGE_RESOURCE_NUM - 1, 121 122 /* Total resources associated with a PCI device */ 123 PCI_NUM_RESOURCES, 124 125 /* Preserve this for compatibility */ 126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 127 }; 128 129 /** 130 * enum pci_interrupt_pin - PCI INTx interrupt values 131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 132 * @PCI_INTERRUPT_INTA: PCI INTA pin 133 * @PCI_INTERRUPT_INTB: PCI INTB pin 134 * @PCI_INTERRUPT_INTC: PCI INTC pin 135 * @PCI_INTERRUPT_INTD: PCI INTD pin 136 * 137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 138 * PCI_INTERRUPT_PIN register. 139 */ 140 enum pci_interrupt_pin { 141 PCI_INTERRUPT_UNKNOWN, 142 PCI_INTERRUPT_INTA, 143 PCI_INTERRUPT_INTB, 144 PCI_INTERRUPT_INTC, 145 PCI_INTERRUPT_INTD, 146 }; 147 148 /* The number of legacy PCI INTx interrupts */ 149 #define PCI_NUM_INTX 4 150 151 /* 152 * pci_power_t values must match the bits in the Capabilities PME_Support 153 * and Control/Status PowerState fields in the Power Management capability. 154 */ 155 typedef int __bitwise pci_power_t; 156 157 #define PCI_D0 ((pci_power_t __force) 0) 158 #define PCI_D1 ((pci_power_t __force) 1) 159 #define PCI_D2 ((pci_power_t __force) 2) 160 #define PCI_D3hot ((pci_power_t __force) 3) 161 #define PCI_D3cold ((pci_power_t __force) 4) 162 #define PCI_UNKNOWN ((pci_power_t __force) 5) 163 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 164 165 /* Remember to update this when the list above changes! */ 166 extern const char *pci_power_names[]; 167 168 static inline const char *pci_power_name(pci_power_t state) 169 { 170 return pci_power_names[1 + (__force int) state]; 171 } 172 173 /** 174 * typedef pci_channel_state_t 175 * 176 * The pci_channel state describes connectivity between the CPU and 177 * the PCI device. If some PCI bus between here and the PCI device 178 * has crashed or locked up, this info is reflected here. 179 */ 180 typedef unsigned int __bitwise pci_channel_state_t; 181 182 enum { 183 /* I/O channel is in normal state */ 184 pci_channel_io_normal = (__force pci_channel_state_t) 1, 185 186 /* I/O to channel is blocked */ 187 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 188 189 /* PCI card is dead */ 190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 191 }; 192 193 typedef unsigned int __bitwise pcie_reset_state_t; 194 195 enum pcie_reset_state { 196 /* Reset is NOT asserted (Use to deassert reset) */ 197 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 198 199 /* Use #PERST to reset PCIe device */ 200 pcie_warm_reset = (__force pcie_reset_state_t) 2, 201 202 /* Use PCIe Hot Reset to reset device */ 203 pcie_hot_reset = (__force pcie_reset_state_t) 3 204 }; 205 206 typedef unsigned short __bitwise pci_dev_flags_t; 207 enum pci_dev_flags { 208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 210 /* Device configuration is irrevocably lost if disabled into D3 */ 211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 212 /* Provide indication device is assigned by a Virtual Machine Manager */ 213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 214 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 218 /* Do not use bus resets for device */ 219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 220 /* Do not use PM reset even if device advertises NoSoftRst- */ 221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 222 /* Get VPD from function 0 VPD */ 223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 224 /* A non-root bridge where translation occurs, stop alias search here */ 225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 226 /* Do not use FLR even if device advertises PCI_AF_CAP */ 227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 228 /* Don't use Relaxed Ordering for TLPs directed at this device */ 229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 230 }; 231 232 enum pci_irq_reroute_variant { 233 INTEL_IRQ_REROUTE_VARIANT = 1, 234 MAX_IRQ_REROUTE_VARIANTS = 3 235 }; 236 237 typedef unsigned short __bitwise pci_bus_flags_t; 238 enum pci_bus_flags { 239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 243 }; 244 245 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 246 enum pcie_link_width { 247 PCIE_LNK_WIDTH_RESRV = 0x00, 248 PCIE_LNK_X1 = 0x01, 249 PCIE_LNK_X2 = 0x02, 250 PCIE_LNK_X4 = 0x04, 251 PCIE_LNK_X8 = 0x08, 252 PCIE_LNK_X12 = 0x0c, 253 PCIE_LNK_X16 = 0x10, 254 PCIE_LNK_X32 = 0x20, 255 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 256 }; 257 258 /* See matching string table in pci_speed_string() */ 259 enum pci_bus_speed { 260 PCI_SPEED_33MHz = 0x00, 261 PCI_SPEED_66MHz = 0x01, 262 PCI_SPEED_66MHz_PCIX = 0x02, 263 PCI_SPEED_100MHz_PCIX = 0x03, 264 PCI_SPEED_133MHz_PCIX = 0x04, 265 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 266 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 267 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 268 PCI_SPEED_66MHz_PCIX_266 = 0x09, 269 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 270 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 271 AGP_UNKNOWN = 0x0c, 272 AGP_1X = 0x0d, 273 AGP_2X = 0x0e, 274 AGP_4X = 0x0f, 275 AGP_8X = 0x10, 276 PCI_SPEED_66MHz_PCIX_533 = 0x11, 277 PCI_SPEED_100MHz_PCIX_533 = 0x12, 278 PCI_SPEED_133MHz_PCIX_533 = 0x13, 279 PCIE_SPEED_2_5GT = 0x14, 280 PCIE_SPEED_5_0GT = 0x15, 281 PCIE_SPEED_8_0GT = 0x16, 282 PCIE_SPEED_16_0GT = 0x17, 283 PCIE_SPEED_32_0GT = 0x18, 284 PCIE_SPEED_64_0GT = 0x19, 285 PCI_SPEED_UNKNOWN = 0xff, 286 }; 287 288 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 289 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 290 291 struct pci_cap_saved_data { 292 u16 cap_nr; 293 bool cap_extended; 294 unsigned int size; 295 u32 data[]; 296 }; 297 298 struct pci_cap_saved_state { 299 struct hlist_node next; 300 struct pci_cap_saved_data cap; 301 }; 302 303 struct irq_affinity; 304 struct pcie_link_state; 305 struct pci_vpd; 306 struct pci_sriov; 307 struct pci_p2pdma; 308 struct rcec_ea; 309 310 /* The pci_dev structure describes PCI devices */ 311 struct pci_dev { 312 struct list_head bus_list; /* Node in per-bus list */ 313 struct pci_bus *bus; /* Bus this device is on */ 314 struct pci_bus *subordinate; /* Bus this device bridges to */ 315 316 void *sysdata; /* Hook for sys-specific extension */ 317 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 318 struct pci_slot *slot; /* Physical slot this device is in */ 319 320 unsigned int devfn; /* Encoded device & function index */ 321 unsigned short vendor; 322 unsigned short device; 323 unsigned short subsystem_vendor; 324 unsigned short subsystem_device; 325 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 326 u8 revision; /* PCI revision, low byte of class word */ 327 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 328 #ifdef CONFIG_PCIEAER 329 u16 aer_cap; /* AER capability offset */ 330 struct aer_stats *aer_stats; /* AER stats for this device */ 331 #endif 332 #ifdef CONFIG_PCIEPORTBUS 333 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 334 struct pci_dev *rcec; /* Associated RCEC device */ 335 #endif 336 u8 pcie_cap; /* PCIe capability offset */ 337 u8 msi_cap; /* MSI capability offset */ 338 u8 msix_cap; /* MSI-X capability offset */ 339 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 340 u8 rom_base_reg; /* Config register controlling ROM */ 341 u8 pin; /* Interrupt pin this device uses */ 342 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 343 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 344 345 struct pci_driver *driver; /* Driver bound to this device */ 346 u64 dma_mask; /* Mask of the bits of bus address this 347 device implements. Normally this is 348 0xffffffff. You only need to change 349 this if your device has broken DMA 350 or supports 64-bit transfers. */ 351 352 struct device_dma_parameters dma_parms; 353 354 pci_power_t current_state; /* Current operating state. In ACPI, 355 this is D0-D3, D0 being fully 356 functional, and D3 being off. */ 357 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 358 u8 pm_cap; /* PM capability offset */ 359 unsigned int pme_support:5; /* Bitmask of states from which PME# 360 can be generated */ 361 unsigned int pme_poll:1; /* Poll device's PME status bit */ 362 unsigned int d1_support:1; /* Low power state D1 is supported */ 363 unsigned int d2_support:1; /* Low power state D2 is supported */ 364 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 365 unsigned int no_d3cold:1; /* D3cold is forbidden */ 366 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 367 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 368 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 369 decoding during BAR sizing */ 370 unsigned int wakeup_prepared:1; 371 unsigned int runtime_d3cold:1; /* Whether go through runtime 372 D3cold, not set for devices 373 powered on/off by the 374 corresponding bridge */ 375 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 376 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 377 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 378 controlled exclusively by 379 user sysfs */ 380 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 381 bit manually */ 382 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 383 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 384 385 #ifdef CONFIG_PCIEASPM 386 struct pcie_link_state *link_state; /* ASPM link state */ 387 unsigned int ltr_path:1; /* Latency Tolerance Reporting 388 supported from root to here */ 389 u16 l1ss; /* L1SS Capability pointer */ 390 #endif 391 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 392 393 pci_channel_state_t error_state; /* Current connectivity state */ 394 struct device dev; /* Generic device interface */ 395 396 int cfg_size; /* Size of config space */ 397 398 /* 399 * Instead of touching interrupt line and base address registers 400 * directly, use the values stored here. They might be different! 401 */ 402 unsigned int irq; 403 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 404 405 bool match_driver; /* Skip attaching driver */ 406 407 unsigned int transparent:1; /* Subtractive decode bridge */ 408 unsigned int io_window:1; /* Bridge has I/O window */ 409 unsigned int pref_window:1; /* Bridge has pref mem window */ 410 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 411 unsigned int multifunction:1; /* Multi-function device */ 412 413 unsigned int is_busmaster:1; /* Is busmaster */ 414 unsigned int no_msi:1; /* May not use MSI */ 415 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 416 unsigned int block_cfg_access:1; /* Config space access blocked */ 417 unsigned int broken_parity_status:1; /* Generates false positive parity */ 418 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 419 unsigned int msi_enabled:1; 420 unsigned int msix_enabled:1; 421 unsigned int ari_enabled:1; /* ARI forwarding */ 422 unsigned int ats_enabled:1; /* Address Translation Svc */ 423 unsigned int pasid_enabled:1; /* Process Address Space ID */ 424 unsigned int pri_enabled:1; /* Page Request Interface */ 425 unsigned int is_managed:1; 426 unsigned int needs_freset:1; /* Requires fundamental reset */ 427 unsigned int state_saved:1; 428 unsigned int is_physfn:1; 429 unsigned int is_virtfn:1; 430 unsigned int reset_fn:1; 431 unsigned int is_hotplug_bridge:1; 432 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 433 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 434 /* 435 * Devices marked being untrusted are the ones that can potentially 436 * execute DMA attacks and similar. They are typically connected 437 * through external ports such as Thunderbolt but not limited to 438 * that. When an IOMMU is enabled they should be getting full 439 * mappings to make sure they cannot access arbitrary memory. 440 */ 441 unsigned int untrusted:1; 442 /* 443 * Info from the platform, e.g., ACPI or device tree, may mark a 444 * device as "external-facing". An external-facing device is 445 * itself internal but devices downstream from it are external. 446 */ 447 unsigned int external_facing:1; 448 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 449 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 450 unsigned int irq_managed:1; 451 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 452 unsigned int is_probed:1; /* Device probing in progress */ 453 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 454 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 455 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 456 pci_dev_flags_t dev_flags; 457 atomic_t enable_cnt; /* pci_enable_device has been called */ 458 459 u32 saved_config_space[16]; /* Config space saved at suspend time */ 460 struct hlist_head saved_cap_space; 461 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 462 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 463 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 464 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 465 466 #ifdef CONFIG_HOTPLUG_PCI_PCIE 467 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 468 #endif 469 #ifdef CONFIG_PCIE_PTM 470 unsigned int ptm_root:1; 471 unsigned int ptm_enabled:1; 472 u8 ptm_granularity; 473 #endif 474 #ifdef CONFIG_PCI_MSI 475 const struct attribute_group **msi_irq_groups; 476 #endif 477 struct pci_vpd *vpd; 478 #ifdef CONFIG_PCIE_DPC 479 u16 dpc_cap; 480 unsigned int dpc_rp_extensions:1; 481 u8 dpc_rp_log_size; 482 #endif 483 #ifdef CONFIG_PCI_ATS 484 union { 485 struct pci_sriov *sriov; /* PF: SR-IOV info */ 486 struct pci_dev *physfn; /* VF: related PF */ 487 }; 488 u16 ats_cap; /* ATS Capability offset */ 489 u8 ats_stu; /* ATS Smallest Translation Unit */ 490 #endif 491 #ifdef CONFIG_PCI_PRI 492 u16 pri_cap; /* PRI Capability offset */ 493 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 494 unsigned int pasid_required:1; /* PRG Response PASID Required */ 495 #endif 496 #ifdef CONFIG_PCI_PASID 497 u16 pasid_cap; /* PASID Capability offset */ 498 u16 pasid_features; 499 #endif 500 #ifdef CONFIG_PCI_P2PDMA 501 struct pci_p2pdma *p2pdma; 502 #endif 503 u16 acs_cap; /* ACS Capability offset */ 504 phys_addr_t rom; /* Physical address if not from BAR */ 505 size_t romlen; /* Length if not from BAR */ 506 char *driver_override; /* Driver name to force a match */ 507 508 unsigned long priv_flags; /* Private flags for the PCI driver */ 509 }; 510 511 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 512 { 513 #ifdef CONFIG_PCI_IOV 514 if (dev->is_virtfn) 515 dev = dev->physfn; 516 #endif 517 return dev; 518 } 519 520 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 521 522 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 523 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 524 525 static inline int pci_channel_offline(struct pci_dev *pdev) 526 { 527 return (pdev->error_state != pci_channel_io_normal); 528 } 529 530 struct pci_host_bridge { 531 struct device dev; 532 struct pci_bus *bus; /* Root bus */ 533 struct pci_ops *ops; 534 struct pci_ops *child_ops; 535 void *sysdata; 536 int busnr; 537 struct list_head windows; /* resource_entry */ 538 struct list_head dma_ranges; /* dma ranges resource list */ 539 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 540 int (*map_irq)(const struct pci_dev *, u8, u8); 541 void (*release_fn)(struct pci_host_bridge *); 542 void *release_data; 543 struct msi_controller *msi; 544 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 545 unsigned int no_ext_tags:1; /* No Extended Tags */ 546 unsigned int native_aer:1; /* OS may use PCIe AER */ 547 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 548 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 549 unsigned int native_pme:1; /* OS may use PCIe PME */ 550 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 551 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 552 unsigned int preserve_config:1; /* Preserve FW resource setup */ 553 unsigned int size_windows:1; /* Enable root bus sizing */ 554 555 /* Resource alignment requirements */ 556 resource_size_t (*align_resource)(struct pci_dev *dev, 557 const struct resource *res, 558 resource_size_t start, 559 resource_size_t size, 560 resource_size_t align); 561 unsigned long private[] ____cacheline_aligned; 562 }; 563 564 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 565 566 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 567 { 568 return (void *)bridge->private; 569 } 570 571 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 572 { 573 return container_of(priv, struct pci_host_bridge, private); 574 } 575 576 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 577 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 578 size_t priv); 579 void pci_free_host_bridge(struct pci_host_bridge *bridge); 580 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 581 582 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 583 void (*release_fn)(struct pci_host_bridge *), 584 void *release_data); 585 586 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 587 588 /* 589 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 590 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 591 * buses below host bridges or subtractive decode bridges) go in the list. 592 * Use pci_bus_for_each_resource() to iterate through all the resources. 593 */ 594 595 /* 596 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 597 * and there's no way to program the bridge with the details of the window. 598 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 599 * decode bit set, because they are explicit and can be programmed with _SRS. 600 */ 601 #define PCI_SUBTRACTIVE_DECODE 0x1 602 603 struct pci_bus_resource { 604 struct list_head list; 605 struct resource *res; 606 unsigned int flags; 607 }; 608 609 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 610 611 struct pci_bus { 612 struct list_head node; /* Node in list of buses */ 613 struct pci_bus *parent; /* Parent bus this bridge is on */ 614 struct list_head children; /* List of child buses */ 615 struct list_head devices; /* List of devices on this bus */ 616 struct pci_dev *self; /* Bridge device as seen by parent */ 617 struct list_head slots; /* List of slots on this bus; 618 protected by pci_slot_mutex */ 619 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 620 struct list_head resources; /* Address space routed to this bus */ 621 struct resource busn_res; /* Bus numbers routed to this bus */ 622 623 struct pci_ops *ops; /* Configuration access functions */ 624 struct msi_controller *msi; /* MSI controller */ 625 void *sysdata; /* Hook for sys-specific extension */ 626 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 627 628 unsigned char number; /* Bus number */ 629 unsigned char primary; /* Number of primary bridge */ 630 unsigned char max_bus_speed; /* enum pci_bus_speed */ 631 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 632 #ifdef CONFIG_PCI_DOMAINS_GENERIC 633 int domain_nr; 634 #endif 635 636 char name[48]; 637 638 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 639 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 640 struct device *bridge; 641 struct device dev; 642 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 643 struct bin_attribute *legacy_mem; /* Legacy mem */ 644 unsigned int is_added:1; 645 }; 646 647 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 648 649 static inline u16 pci_dev_id(struct pci_dev *dev) 650 { 651 return PCI_DEVID(dev->bus->number, dev->devfn); 652 } 653 654 /* 655 * Returns true if the PCI bus is root (behind host-PCI bridge), 656 * false otherwise 657 * 658 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 659 * This is incorrect because "virtual" buses added for SR-IOV (via 660 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 661 */ 662 static inline bool pci_is_root_bus(struct pci_bus *pbus) 663 { 664 return !(pbus->parent); 665 } 666 667 /** 668 * pci_is_bridge - check if the PCI device is a bridge 669 * @dev: PCI device 670 * 671 * Return true if the PCI device is bridge whether it has subordinate 672 * or not. 673 */ 674 static inline bool pci_is_bridge(struct pci_dev *dev) 675 { 676 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 677 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 678 } 679 680 #define for_each_pci_bridge(dev, bus) \ 681 list_for_each_entry(dev, &bus->devices, bus_list) \ 682 if (!pci_is_bridge(dev)) {} else 683 684 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 685 { 686 dev = pci_physfn(dev); 687 if (pci_is_root_bus(dev->bus)) 688 return NULL; 689 690 return dev->bus->self; 691 } 692 693 #ifdef CONFIG_PCI_MSI 694 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 695 { 696 return pci_dev->msi_enabled || pci_dev->msix_enabled; 697 } 698 #else 699 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 700 #endif 701 702 /* Error values that may be returned by PCI functions */ 703 #define PCIBIOS_SUCCESSFUL 0x00 704 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 705 #define PCIBIOS_BAD_VENDOR_ID 0x83 706 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 707 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 708 #define PCIBIOS_SET_FAILED 0x88 709 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 710 711 /* Translate above to generic errno for passing back through non-PCI code */ 712 static inline int pcibios_err_to_errno(int err) 713 { 714 if (err <= PCIBIOS_SUCCESSFUL) 715 return err; /* Assume already errno */ 716 717 switch (err) { 718 case PCIBIOS_FUNC_NOT_SUPPORTED: 719 return -ENOENT; 720 case PCIBIOS_BAD_VENDOR_ID: 721 return -ENOTTY; 722 case PCIBIOS_DEVICE_NOT_FOUND: 723 return -ENODEV; 724 case PCIBIOS_BAD_REGISTER_NUMBER: 725 return -EFAULT; 726 case PCIBIOS_SET_FAILED: 727 return -EIO; 728 case PCIBIOS_BUFFER_TOO_SMALL: 729 return -ENOSPC; 730 } 731 732 return -ERANGE; 733 } 734 735 /* Low-level architecture-dependent routines */ 736 737 struct pci_ops { 738 int (*add_bus)(struct pci_bus *bus); 739 void (*remove_bus)(struct pci_bus *bus); 740 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 741 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 742 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 743 }; 744 745 /* 746 * ACPI needs to be able to access PCI config space before we've done a 747 * PCI bus scan and created pci_bus structures. 748 */ 749 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 750 int reg, int len, u32 *val); 751 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 752 int reg, int len, u32 val); 753 754 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 755 typedef u64 pci_bus_addr_t; 756 #else 757 typedef u32 pci_bus_addr_t; 758 #endif 759 760 struct pci_bus_region { 761 pci_bus_addr_t start; 762 pci_bus_addr_t end; 763 }; 764 765 struct pci_dynids { 766 spinlock_t lock; /* Protects list, index */ 767 struct list_head list; /* For IDs added at runtime */ 768 }; 769 770 771 /* 772 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 773 * a set of callbacks in struct pci_error_handlers, that device driver 774 * will be notified of PCI bus errors, and will be driven to recovery 775 * when an error occurs. 776 */ 777 778 typedef unsigned int __bitwise pci_ers_result_t; 779 780 enum pci_ers_result { 781 /* No result/none/not supported in device driver */ 782 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 783 784 /* Device driver can recover without slot reset */ 785 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 786 787 /* Device driver wants slot to be reset */ 788 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 789 790 /* Device has completely failed, is unrecoverable */ 791 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 792 793 /* Device driver is fully recovered and operational */ 794 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 795 796 /* No AER capabilities registered for the driver */ 797 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 798 }; 799 800 /* PCI bus error event callbacks */ 801 struct pci_error_handlers { 802 /* PCI bus error detected on this device */ 803 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 804 pci_channel_state_t error); 805 806 /* MMIO has been re-enabled, but not DMA */ 807 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 808 809 /* PCI slot has been reset */ 810 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 811 812 /* PCI function reset prepare or completed */ 813 void (*reset_prepare)(struct pci_dev *dev); 814 void (*reset_done)(struct pci_dev *dev); 815 816 /* Device driver may resume normal operations */ 817 void (*resume)(struct pci_dev *dev); 818 }; 819 820 821 struct module; 822 823 /** 824 * struct pci_driver - PCI driver structure 825 * @node: List of driver structures. 826 * @name: Driver name. 827 * @id_table: Pointer to table of device IDs the driver is 828 * interested in. Most drivers should export this 829 * table using MODULE_DEVICE_TABLE(pci,...). 830 * @probe: This probing function gets called (during execution 831 * of pci_register_driver() for already existing 832 * devices or later if a new device gets inserted) for 833 * all PCI devices which match the ID table and are not 834 * "owned" by the other drivers yet. This function gets 835 * passed a "struct pci_dev \*" for each device whose 836 * entry in the ID table matches the device. The probe 837 * function returns zero when the driver chooses to 838 * take "ownership" of the device or an error code 839 * (negative number) otherwise. 840 * The probe function always gets called from process 841 * context, so it can sleep. 842 * @remove: The remove() function gets called whenever a device 843 * being handled by this driver is removed (either during 844 * deregistration of the driver or when it's manually 845 * pulled out of a hot-pluggable slot). 846 * The remove function always gets called from process 847 * context, so it can sleep. 848 * @suspend: Put device into low power state. 849 * @resume: Wake device from low power state. 850 * (Please see Documentation/power/pci.rst for descriptions 851 * of PCI Power Management and the related functions.) 852 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 853 * Intended to stop any idling DMA operations. 854 * Useful for enabling wake-on-lan (NIC) or changing 855 * the power state of a device before reboot. 856 * e.g. drivers/net/e100.c. 857 * @sriov_configure: Optional driver callback to allow configuration of 858 * number of VFs to enable via sysfs "sriov_numvfs" file. 859 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 860 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 861 * This will change MSI-X Table Size in the VF Message Control 862 * registers. 863 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 864 * MSI-X vectors available for distribution to the VFs. 865 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 866 * @groups: Sysfs attribute groups. 867 * @driver: Driver model structure. 868 * @dynids: List of dynamically added device IDs. 869 */ 870 struct pci_driver { 871 struct list_head node; 872 const char *name; 873 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 874 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 875 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 876 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 877 int (*resume)(struct pci_dev *dev); /* Device woken up */ 878 void (*shutdown)(struct pci_dev *dev); 879 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 880 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 881 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 882 const struct pci_error_handlers *err_handler; 883 const struct attribute_group **groups; 884 struct device_driver driver; 885 struct pci_dynids dynids; 886 }; 887 888 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 889 890 /** 891 * PCI_DEVICE - macro used to describe a specific PCI device 892 * @vend: the 16 bit PCI Vendor ID 893 * @dev: the 16 bit PCI Device ID 894 * 895 * This macro is used to create a struct pci_device_id that matches a 896 * specific device. The subvendor and subdevice fields will be set to 897 * PCI_ANY_ID. 898 */ 899 #define PCI_DEVICE(vend,dev) \ 900 .vendor = (vend), .device = (dev), \ 901 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 902 903 /** 904 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 905 * @vend: the 16 bit PCI Vendor ID 906 * @dev: the 16 bit PCI Device ID 907 * @subvend: the 16 bit PCI Subvendor ID 908 * @subdev: the 16 bit PCI Subdevice ID 909 * 910 * This macro is used to create a struct pci_device_id that matches a 911 * specific device with subsystem information. 912 */ 913 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 914 .vendor = (vend), .device = (dev), \ 915 .subvendor = (subvend), .subdevice = (subdev) 916 917 /** 918 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 919 * @dev_class: the class, subclass, prog-if triple for this device 920 * @dev_class_mask: the class mask for this device 921 * 922 * This macro is used to create a struct pci_device_id that matches a 923 * specific PCI class. The vendor, device, subvendor, and subdevice 924 * fields will be set to PCI_ANY_ID. 925 */ 926 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 927 .class = (dev_class), .class_mask = (dev_class_mask), \ 928 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 929 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 930 931 /** 932 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 933 * @vend: the vendor name 934 * @dev: the 16 bit PCI Device ID 935 * 936 * This macro is used to create a struct pci_device_id that matches a 937 * specific PCI device. The subvendor, and subdevice fields will be set 938 * to PCI_ANY_ID. The macro allows the next field to follow as the device 939 * private data. 940 */ 941 #define PCI_VDEVICE(vend, dev) \ 942 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 943 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 944 945 /** 946 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 947 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 948 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 949 * @data: the driver data to be filled 950 * 951 * This macro is used to create a struct pci_device_id that matches a 952 * specific PCI device. The subvendor, and subdevice fields will be set 953 * to PCI_ANY_ID. 954 */ 955 #define PCI_DEVICE_DATA(vend, dev, data) \ 956 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 957 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 958 .driver_data = (kernel_ulong_t)(data) 959 960 enum { 961 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 962 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 963 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 964 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 965 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 966 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 967 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 968 }; 969 970 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 971 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 972 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 973 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 974 975 /* These external functions are only available when PCI support is enabled */ 976 #ifdef CONFIG_PCI 977 978 extern unsigned int pci_flags; 979 980 static inline void pci_set_flags(int flags) { pci_flags = flags; } 981 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 982 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 983 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 984 985 void pcie_bus_configure_settings(struct pci_bus *bus); 986 987 enum pcie_bus_config_types { 988 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 989 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 990 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 991 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 992 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 993 }; 994 995 extern enum pcie_bus_config_types pcie_bus_config; 996 997 extern struct bus_type pci_bus_type; 998 999 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1000 * code, or PCI core code. */ 1001 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1002 /* Some device drivers need know if PCI is initiated */ 1003 int no_pci_devices(void); 1004 1005 void pcibios_resource_survey_bus(struct pci_bus *bus); 1006 void pcibios_bus_add_device(struct pci_dev *pdev); 1007 void pcibios_add_bus(struct pci_bus *bus); 1008 void pcibios_remove_bus(struct pci_bus *bus); 1009 void pcibios_fixup_bus(struct pci_bus *); 1010 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1011 /* Architecture-specific versions may override this (weak) */ 1012 char *pcibios_setup(char *str); 1013 1014 /* Used only when drivers/pci/setup.c is used */ 1015 resource_size_t pcibios_align_resource(void *, const struct resource *, 1016 resource_size_t, 1017 resource_size_t); 1018 1019 /* Weak but can be overridden by arch */ 1020 void pci_fixup_cardbus(struct pci_bus *); 1021 1022 /* Generic PCI functions used internally */ 1023 1024 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1025 struct resource *res); 1026 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1027 struct pci_bus_region *region); 1028 void pcibios_scan_specific_bus(int busn); 1029 struct pci_bus *pci_find_bus(int domain, int busnr); 1030 void pci_bus_add_devices(const struct pci_bus *bus); 1031 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1032 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1033 struct pci_ops *ops, void *sysdata, 1034 struct list_head *resources); 1035 int pci_host_probe(struct pci_host_bridge *bridge); 1036 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1037 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1038 void pci_bus_release_busn_res(struct pci_bus *b); 1039 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1040 struct pci_ops *ops, void *sysdata, 1041 struct list_head *resources); 1042 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1043 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1044 int busnr); 1045 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1046 const char *name, 1047 struct hotplug_slot *hotplug); 1048 void pci_destroy_slot(struct pci_slot *slot); 1049 #ifdef CONFIG_SYSFS 1050 void pci_dev_assign_slot(struct pci_dev *dev); 1051 #else 1052 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1053 #endif 1054 int pci_scan_slot(struct pci_bus *bus, int devfn); 1055 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1056 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1057 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1058 void pci_bus_add_device(struct pci_dev *dev); 1059 void pci_read_bridge_bases(struct pci_bus *child); 1060 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1061 struct resource *res); 1062 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1063 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1064 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1065 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1066 void pci_dev_put(struct pci_dev *dev); 1067 void pci_remove_bus(struct pci_bus *b); 1068 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1069 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1070 void pci_stop_root_bus(struct pci_bus *bus); 1071 void pci_remove_root_bus(struct pci_bus *bus); 1072 void pci_setup_cardbus(struct pci_bus *bus); 1073 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1074 void pci_sort_breadthfirst(void); 1075 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1076 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1077 1078 /* Generic PCI functions exported to card drivers */ 1079 1080 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1081 u8 pci_find_capability(struct pci_dev *dev, int cap); 1082 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1083 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1084 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1085 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1086 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1087 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1088 1089 u64 pci_get_dsn(struct pci_dev *dev); 1090 1091 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1092 struct pci_dev *from); 1093 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1094 unsigned int ss_vendor, unsigned int ss_device, 1095 struct pci_dev *from); 1096 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1097 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1098 unsigned int devfn); 1099 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1100 int pci_dev_present(const struct pci_device_id *ids); 1101 1102 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1103 int where, u8 *val); 1104 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1105 int where, u16 *val); 1106 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1107 int where, u32 *val); 1108 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1109 int where, u8 val); 1110 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1111 int where, u16 val); 1112 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1113 int where, u32 val); 1114 1115 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1116 int where, int size, u32 *val); 1117 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1118 int where, int size, u32 val); 1119 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1120 int where, int size, u32 *val); 1121 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1122 int where, int size, u32 val); 1123 1124 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1125 1126 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1127 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1128 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1129 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1130 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1131 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1132 1133 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1134 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1135 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1136 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1137 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1138 u16 clear, u16 set); 1139 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1140 u32 clear, u32 set); 1141 1142 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1143 u16 set) 1144 { 1145 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1146 } 1147 1148 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1149 u32 set) 1150 { 1151 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1152 } 1153 1154 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1155 u16 clear) 1156 { 1157 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1158 } 1159 1160 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1161 u32 clear) 1162 { 1163 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1164 } 1165 1166 /* User-space driven config access */ 1167 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1168 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1169 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1170 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1171 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1172 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1173 1174 int __must_check pci_enable_device(struct pci_dev *dev); 1175 int __must_check pci_enable_device_io(struct pci_dev *dev); 1176 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1177 int __must_check pci_reenable_device(struct pci_dev *); 1178 int __must_check pcim_enable_device(struct pci_dev *pdev); 1179 void pcim_pin_device(struct pci_dev *pdev); 1180 1181 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1182 { 1183 /* 1184 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1185 * writable and no quirk has marked the feature broken. 1186 */ 1187 return !pdev->broken_intx_masking; 1188 } 1189 1190 static inline int pci_is_enabled(struct pci_dev *pdev) 1191 { 1192 return (atomic_read(&pdev->enable_cnt) > 0); 1193 } 1194 1195 static inline int pci_is_managed(struct pci_dev *pdev) 1196 { 1197 return pdev->is_managed; 1198 } 1199 1200 void pci_disable_device(struct pci_dev *dev); 1201 1202 extern unsigned int pcibios_max_latency; 1203 void pci_set_master(struct pci_dev *dev); 1204 void pci_clear_master(struct pci_dev *dev); 1205 1206 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1207 int pci_set_cacheline_size(struct pci_dev *dev); 1208 int __must_check pci_set_mwi(struct pci_dev *dev); 1209 int __must_check pcim_set_mwi(struct pci_dev *dev); 1210 int pci_try_set_mwi(struct pci_dev *dev); 1211 void pci_clear_mwi(struct pci_dev *dev); 1212 void pci_intx(struct pci_dev *dev, int enable); 1213 bool pci_check_and_mask_intx(struct pci_dev *dev); 1214 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1215 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1216 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1217 int pcix_get_max_mmrbc(struct pci_dev *dev); 1218 int pcix_get_mmrbc(struct pci_dev *dev); 1219 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1220 int pcie_get_readrq(struct pci_dev *dev); 1221 int pcie_set_readrq(struct pci_dev *dev, int rq); 1222 int pcie_get_mps(struct pci_dev *dev); 1223 int pcie_set_mps(struct pci_dev *dev, int mps); 1224 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1225 enum pci_bus_speed *speed, 1226 enum pcie_link_width *width); 1227 void pcie_print_link_status(struct pci_dev *dev); 1228 bool pcie_has_flr(struct pci_dev *dev); 1229 int pcie_flr(struct pci_dev *dev); 1230 int __pci_reset_function_locked(struct pci_dev *dev); 1231 int pci_reset_function(struct pci_dev *dev); 1232 int pci_reset_function_locked(struct pci_dev *dev); 1233 int pci_try_reset_function(struct pci_dev *dev); 1234 int pci_probe_reset_slot(struct pci_slot *slot); 1235 int pci_probe_reset_bus(struct pci_bus *bus); 1236 int pci_reset_bus(struct pci_dev *dev); 1237 void pci_reset_secondary_bus(struct pci_dev *dev); 1238 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1239 void pci_update_resource(struct pci_dev *dev, int resno); 1240 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1241 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1242 void pci_release_resource(struct pci_dev *dev, int resno); 1243 static inline int pci_rebar_bytes_to_size(u64 bytes) 1244 { 1245 bytes = roundup_pow_of_two(bytes); 1246 1247 /* Return BAR size as defined in the resizable BAR specification */ 1248 return max(ilog2(bytes), 20) - 20; 1249 } 1250 1251 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1252 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1253 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1254 bool pci_device_is_present(struct pci_dev *pdev); 1255 void pci_ignore_hotplug(struct pci_dev *dev); 1256 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1257 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1258 1259 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1260 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1261 const char *fmt, ...); 1262 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1263 1264 /* ROM control related routines */ 1265 int pci_enable_rom(struct pci_dev *pdev); 1266 void pci_disable_rom(struct pci_dev *pdev); 1267 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1268 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1269 1270 /* Power management related routines */ 1271 int pci_save_state(struct pci_dev *dev); 1272 void pci_restore_state(struct pci_dev *dev); 1273 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1274 int pci_load_saved_state(struct pci_dev *dev, 1275 struct pci_saved_state *state); 1276 int pci_load_and_free_saved_state(struct pci_dev *dev, 1277 struct pci_saved_state **state); 1278 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1279 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1280 u16 cap); 1281 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1282 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1283 u16 cap, unsigned int size); 1284 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1285 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1286 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1287 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1288 void pci_pme_active(struct pci_dev *dev, bool enable); 1289 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1290 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1291 int pci_prepare_to_sleep(struct pci_dev *dev); 1292 int pci_back_from_sleep(struct pci_dev *dev); 1293 bool pci_dev_run_wake(struct pci_dev *dev); 1294 void pci_d3cold_enable(struct pci_dev *dev); 1295 void pci_d3cold_disable(struct pci_dev *dev); 1296 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1297 void pci_resume_bus(struct pci_bus *bus); 1298 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1299 1300 /* For use by arch with custom probe code */ 1301 void set_pcie_port_type(struct pci_dev *pdev); 1302 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1303 1304 /* Functions for PCI Hotplug drivers to use */ 1305 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1306 unsigned int pci_rescan_bus(struct pci_bus *bus); 1307 void pci_lock_rescan_remove(void); 1308 void pci_unlock_rescan_remove(void); 1309 1310 /* Vital Product Data routines */ 1311 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1312 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1313 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1314 1315 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1316 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1317 void pci_bus_assign_resources(const struct pci_bus *bus); 1318 void pci_bus_claim_resources(struct pci_bus *bus); 1319 void pci_bus_size_bridges(struct pci_bus *bus); 1320 int pci_claim_resource(struct pci_dev *, int); 1321 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1322 void pci_assign_unassigned_resources(void); 1323 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1324 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1325 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1326 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1327 void pdev_enable_device(struct pci_dev *); 1328 int pci_enable_resources(struct pci_dev *, int mask); 1329 void pci_assign_irq(struct pci_dev *dev); 1330 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1331 #define HAVE_PCI_REQ_REGIONS 2 1332 int __must_check pci_request_regions(struct pci_dev *, const char *); 1333 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1334 void pci_release_regions(struct pci_dev *); 1335 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1336 void pci_release_region(struct pci_dev *, int); 1337 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1338 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1339 void pci_release_selected_regions(struct pci_dev *, int); 1340 1341 /* drivers/pci/bus.c */ 1342 void pci_add_resource(struct list_head *resources, struct resource *res); 1343 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1344 resource_size_t offset); 1345 void pci_free_resource_list(struct list_head *resources); 1346 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1347 unsigned int flags); 1348 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1349 void pci_bus_remove_resources(struct pci_bus *bus); 1350 int devm_request_pci_bus_resources(struct device *dev, 1351 struct list_head *resources); 1352 1353 /* Temporary until new and working PCI SBR API in place */ 1354 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1355 1356 #define pci_bus_for_each_resource(bus, res, i) \ 1357 for (i = 0; \ 1358 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1359 i++) 1360 1361 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1362 struct resource *res, resource_size_t size, 1363 resource_size_t align, resource_size_t min, 1364 unsigned long type_mask, 1365 resource_size_t (*alignf)(void *, 1366 const struct resource *, 1367 resource_size_t, 1368 resource_size_t), 1369 void *alignf_data); 1370 1371 1372 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1373 resource_size_t size); 1374 unsigned long pci_address_to_pio(phys_addr_t addr); 1375 phys_addr_t pci_pio_to_address(unsigned long pio); 1376 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1377 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1378 phys_addr_t phys_addr); 1379 void pci_unmap_iospace(struct resource *res); 1380 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1381 resource_size_t offset, 1382 resource_size_t size); 1383 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1384 struct resource *res); 1385 1386 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1387 { 1388 struct pci_bus_region region; 1389 1390 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1391 return region.start; 1392 } 1393 1394 /* Proper probing supporting hot-pluggable devices */ 1395 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1396 const char *mod_name); 1397 1398 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1399 #define pci_register_driver(driver) \ 1400 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1401 1402 void pci_unregister_driver(struct pci_driver *dev); 1403 1404 /** 1405 * module_pci_driver() - Helper macro for registering a PCI driver 1406 * @__pci_driver: pci_driver struct 1407 * 1408 * Helper macro for PCI drivers which do not do anything special in module 1409 * init/exit. This eliminates a lot of boilerplate. Each module may only 1410 * use this macro once, and calling it replaces module_init() and module_exit() 1411 */ 1412 #define module_pci_driver(__pci_driver) \ 1413 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1414 1415 /** 1416 * builtin_pci_driver() - Helper macro for registering a PCI driver 1417 * @__pci_driver: pci_driver struct 1418 * 1419 * Helper macro for PCI drivers which do not do anything special in their 1420 * init code. This eliminates a lot of boilerplate. Each driver may only 1421 * use this macro once, and calling it replaces device_initcall(...) 1422 */ 1423 #define builtin_pci_driver(__pci_driver) \ 1424 builtin_driver(__pci_driver, pci_register_driver) 1425 1426 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1427 int pci_add_dynid(struct pci_driver *drv, 1428 unsigned int vendor, unsigned int device, 1429 unsigned int subvendor, unsigned int subdevice, 1430 unsigned int class, unsigned int class_mask, 1431 unsigned long driver_data); 1432 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1433 struct pci_dev *dev); 1434 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1435 int pass); 1436 1437 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1438 void *userdata); 1439 int pci_cfg_space_size(struct pci_dev *dev); 1440 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1441 void pci_setup_bridge(struct pci_bus *bus); 1442 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1443 unsigned long type); 1444 1445 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1446 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1447 1448 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1449 unsigned int command_bits, u32 flags); 1450 1451 /* 1452 * Virtual interrupts allow for more interrupts to be allocated 1453 * than the device has interrupts for. These are not programmed 1454 * into the device's MSI-X table and must be handled by some 1455 * other driver means. 1456 */ 1457 #define PCI_IRQ_VIRTUAL (1 << 4) 1458 1459 #define PCI_IRQ_ALL_TYPES \ 1460 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1461 1462 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1463 1464 #include <linux/dmapool.h> 1465 1466 #define pci_pool dma_pool 1467 #define pci_pool_create(name, pdev, size, align, allocation) \ 1468 dma_pool_create(name, &pdev->dev, size, align, allocation) 1469 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1470 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1471 #define pci_pool_zalloc(pool, flags, handle) \ 1472 dma_pool_zalloc(pool, flags, handle) 1473 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1474 1475 struct msix_entry { 1476 u32 vector; /* Kernel uses to write allocated vector */ 1477 u16 entry; /* Driver uses to specify entry, OS writes */ 1478 }; 1479 1480 #ifdef CONFIG_PCI_MSI 1481 int pci_msi_vec_count(struct pci_dev *dev); 1482 void pci_disable_msi(struct pci_dev *dev); 1483 int pci_msix_vec_count(struct pci_dev *dev); 1484 void pci_disable_msix(struct pci_dev *dev); 1485 void pci_restore_msi_state(struct pci_dev *dev); 1486 int pci_msi_enabled(void); 1487 int pci_enable_msi(struct pci_dev *dev); 1488 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1489 int minvec, int maxvec); 1490 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1491 struct msix_entry *entries, int nvec) 1492 { 1493 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1494 if (rc < 0) 1495 return rc; 1496 return 0; 1497 } 1498 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1499 unsigned int max_vecs, unsigned int flags, 1500 struct irq_affinity *affd); 1501 1502 void pci_free_irq_vectors(struct pci_dev *dev); 1503 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1504 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1505 1506 #else 1507 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1508 static inline void pci_disable_msi(struct pci_dev *dev) { } 1509 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1510 static inline void pci_disable_msix(struct pci_dev *dev) { } 1511 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1512 static inline int pci_msi_enabled(void) { return 0; } 1513 static inline int pci_enable_msi(struct pci_dev *dev) 1514 { return -ENOSYS; } 1515 static inline int pci_enable_msix_range(struct pci_dev *dev, 1516 struct msix_entry *entries, int minvec, int maxvec) 1517 { return -ENOSYS; } 1518 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1519 struct msix_entry *entries, int nvec) 1520 { return -ENOSYS; } 1521 1522 static inline int 1523 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1524 unsigned int max_vecs, unsigned int flags, 1525 struct irq_affinity *aff_desc) 1526 { 1527 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1528 return 1; 1529 return -ENOSPC; 1530 } 1531 1532 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1533 { 1534 } 1535 1536 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1537 { 1538 if (WARN_ON_ONCE(nr > 0)) 1539 return -EINVAL; 1540 return dev->irq; 1541 } 1542 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1543 int vec) 1544 { 1545 return cpu_possible_mask; 1546 } 1547 #endif 1548 1549 /** 1550 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1551 * @d: the INTx IRQ domain 1552 * @node: the DT node for the device whose interrupt we're translating 1553 * @intspec: the interrupt specifier data from the DT 1554 * @intsize: the number of entries in @intspec 1555 * @out_hwirq: pointer at which to write the hwirq number 1556 * @out_type: pointer at which to write the interrupt type 1557 * 1558 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1559 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1560 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1561 * INTx value to obtain the hwirq number. 1562 * 1563 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1564 */ 1565 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1566 struct device_node *node, 1567 const u32 *intspec, 1568 unsigned int intsize, 1569 unsigned long *out_hwirq, 1570 unsigned int *out_type) 1571 { 1572 const u32 intx = intspec[0]; 1573 1574 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1575 return -EINVAL; 1576 1577 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1578 return 0; 1579 } 1580 1581 #ifdef CONFIG_PCIEPORTBUS 1582 extern bool pcie_ports_disabled; 1583 extern bool pcie_ports_native; 1584 #else 1585 #define pcie_ports_disabled true 1586 #define pcie_ports_native false 1587 #endif 1588 1589 #define PCIE_LINK_STATE_L0S BIT(0) 1590 #define PCIE_LINK_STATE_L1 BIT(1) 1591 #define PCIE_LINK_STATE_CLKPM BIT(2) 1592 #define PCIE_LINK_STATE_L1_1 BIT(3) 1593 #define PCIE_LINK_STATE_L1_2 BIT(4) 1594 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1595 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1596 1597 #ifdef CONFIG_PCIEASPM 1598 int pci_disable_link_state(struct pci_dev *pdev, int state); 1599 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1600 void pcie_no_aspm(void); 1601 bool pcie_aspm_support_enabled(void); 1602 bool pcie_aspm_enabled(struct pci_dev *pdev); 1603 #else 1604 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1605 { return 0; } 1606 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1607 { return 0; } 1608 static inline void pcie_no_aspm(void) { } 1609 static inline bool pcie_aspm_support_enabled(void) { return false; } 1610 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1611 #endif 1612 1613 #ifdef CONFIG_PCIEAER 1614 bool pci_aer_available(void); 1615 #else 1616 static inline bool pci_aer_available(void) { return false; } 1617 #endif 1618 1619 bool pci_ats_disabled(void); 1620 1621 void pci_cfg_access_lock(struct pci_dev *dev); 1622 bool pci_cfg_access_trylock(struct pci_dev *dev); 1623 void pci_cfg_access_unlock(struct pci_dev *dev); 1624 1625 /* 1626 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1627 * a PCI domain is defined to be a set of PCI buses which share 1628 * configuration space. 1629 */ 1630 #ifdef CONFIG_PCI_DOMAINS 1631 extern int pci_domains_supported; 1632 #else 1633 enum { pci_domains_supported = 0 }; 1634 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1635 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1636 #endif /* CONFIG_PCI_DOMAINS */ 1637 1638 /* 1639 * Generic implementation for PCI domain support. If your 1640 * architecture does not need custom management of PCI 1641 * domains then this implementation will be used 1642 */ 1643 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1644 static inline int pci_domain_nr(struct pci_bus *bus) 1645 { 1646 return bus->domain_nr; 1647 } 1648 #ifdef CONFIG_ACPI 1649 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1650 #else 1651 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1652 { return 0; } 1653 #endif 1654 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1655 #endif 1656 1657 /* Some architectures require additional setup to direct VGA traffic */ 1658 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1659 unsigned int command_bits, u32 flags); 1660 void pci_register_set_vga_state(arch_set_vga_state_t func); 1661 1662 static inline int 1663 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1664 { 1665 return pci_request_selected_regions(pdev, 1666 pci_select_bars(pdev, IORESOURCE_IO), name); 1667 } 1668 1669 static inline void 1670 pci_release_io_regions(struct pci_dev *pdev) 1671 { 1672 return pci_release_selected_regions(pdev, 1673 pci_select_bars(pdev, IORESOURCE_IO)); 1674 } 1675 1676 static inline int 1677 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1678 { 1679 return pci_request_selected_regions(pdev, 1680 pci_select_bars(pdev, IORESOURCE_MEM), name); 1681 } 1682 1683 static inline void 1684 pci_release_mem_regions(struct pci_dev *pdev) 1685 { 1686 return pci_release_selected_regions(pdev, 1687 pci_select_bars(pdev, IORESOURCE_MEM)); 1688 } 1689 1690 #else /* CONFIG_PCI is not enabled */ 1691 1692 static inline void pci_set_flags(int flags) { } 1693 static inline void pci_add_flags(int flags) { } 1694 static inline void pci_clear_flags(int flags) { } 1695 static inline int pci_has_flag(int flag) { return 0; } 1696 1697 /* 1698 * If the system does not have PCI, clearly these return errors. Define 1699 * these as simple inline functions to avoid hair in drivers. 1700 */ 1701 #define _PCI_NOP(o, s, t) \ 1702 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1703 int where, t val) \ 1704 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1705 1706 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1707 _PCI_NOP(o, word, u16 x) \ 1708 _PCI_NOP(o, dword, u32 x) 1709 _PCI_NOP_ALL(read, *) 1710 _PCI_NOP_ALL(write,) 1711 1712 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1713 unsigned int device, 1714 struct pci_dev *from) 1715 { return NULL; } 1716 1717 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1718 unsigned int device, 1719 unsigned int ss_vendor, 1720 unsigned int ss_device, 1721 struct pci_dev *from) 1722 { return NULL; } 1723 1724 static inline struct pci_dev *pci_get_class(unsigned int class, 1725 struct pci_dev *from) 1726 { return NULL; } 1727 1728 #define pci_dev_present(ids) (0) 1729 #define no_pci_devices() (1) 1730 #define pci_dev_put(dev) do { } while (0) 1731 1732 static inline void pci_set_master(struct pci_dev *dev) { } 1733 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1734 static inline void pci_disable_device(struct pci_dev *dev) { } 1735 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1736 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1737 { return -EBUSY; } 1738 static inline int __pci_register_driver(struct pci_driver *drv, 1739 struct module *owner) 1740 { return 0; } 1741 static inline int pci_register_driver(struct pci_driver *drv) 1742 { return 0; } 1743 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1744 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1745 { return 0; } 1746 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1747 int cap) 1748 { return 0; } 1749 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1750 { return 0; } 1751 1752 static inline u64 pci_get_dsn(struct pci_dev *dev) 1753 { return 0; } 1754 1755 /* Power management related routines */ 1756 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1757 static inline void pci_restore_state(struct pci_dev *dev) { } 1758 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1759 { return 0; } 1760 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1761 { return 0; } 1762 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1763 pm_message_t state) 1764 { return PCI_D0; } 1765 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1766 int enable) 1767 { return 0; } 1768 1769 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1770 struct resource *res) 1771 { return NULL; } 1772 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1773 { return -EIO; } 1774 static inline void pci_release_regions(struct pci_dev *dev) { } 1775 1776 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1777 1778 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1779 { return NULL; } 1780 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1781 unsigned int devfn) 1782 { return NULL; } 1783 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1784 unsigned int bus, unsigned int devfn) 1785 { return NULL; } 1786 1787 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1788 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1789 1790 #define dev_is_pci(d) (false) 1791 #define dev_is_pf(d) (false) 1792 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1793 { return false; } 1794 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1795 struct device_node *node, 1796 const u32 *intspec, 1797 unsigned int intsize, 1798 unsigned long *out_hwirq, 1799 unsigned int *out_type) 1800 { return -EINVAL; } 1801 1802 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1803 struct pci_dev *dev) 1804 { return NULL; } 1805 static inline bool pci_ats_disabled(void) { return true; } 1806 1807 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1808 { 1809 return -EINVAL; 1810 } 1811 1812 static inline int 1813 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1814 unsigned int max_vecs, unsigned int flags, 1815 struct irq_affinity *aff_desc) 1816 { 1817 return -ENOSPC; 1818 } 1819 #endif /* CONFIG_PCI */ 1820 1821 static inline int 1822 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1823 unsigned int max_vecs, unsigned int flags) 1824 { 1825 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1826 NULL); 1827 } 1828 1829 /* Include architecture-dependent settings and functions */ 1830 1831 #include <asm/pci.h> 1832 1833 /* These two functions provide almost identical functionality. Depending 1834 * on the architecture, one will be implemented as a wrapper around the 1835 * other (in drivers/pci/mmap.c). 1836 * 1837 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1838 * is expected to be an offset within that region. 1839 * 1840 * pci_mmap_page_range() is the legacy architecture-specific interface, 1841 * which accepts a "user visible" resource address converted by 1842 * pci_resource_to_user(), as used in the legacy mmap() interface in 1843 * /proc/bus/pci/. 1844 */ 1845 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1846 struct vm_area_struct *vma, 1847 enum pci_mmap_state mmap_state, int write_combine); 1848 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1849 struct vm_area_struct *vma, 1850 enum pci_mmap_state mmap_state, int write_combine); 1851 1852 #ifndef arch_can_pci_mmap_wc 1853 #define arch_can_pci_mmap_wc() 0 1854 #endif 1855 1856 #ifndef arch_can_pci_mmap_io 1857 #define arch_can_pci_mmap_io() 0 1858 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1859 #else 1860 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1861 #endif 1862 1863 #ifndef pci_root_bus_fwnode 1864 #define pci_root_bus_fwnode(bus) NULL 1865 #endif 1866 1867 /* 1868 * These helpers provide future and backwards compatibility 1869 * for accessing popular PCI BAR info 1870 */ 1871 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1872 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1873 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1874 #define pci_resource_len(dev,bar) \ 1875 ((pci_resource_start((dev), (bar)) == 0 && \ 1876 pci_resource_end((dev), (bar)) == \ 1877 pci_resource_start((dev), (bar))) ? 0 : \ 1878 \ 1879 (pci_resource_end((dev), (bar)) - \ 1880 pci_resource_start((dev), (bar)) + 1)) 1881 1882 /* 1883 * Similar to the helpers above, these manipulate per-pci_dev 1884 * driver-specific data. They are really just a wrapper around 1885 * the generic device structure functions of these calls. 1886 */ 1887 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1888 { 1889 return dev_get_drvdata(&pdev->dev); 1890 } 1891 1892 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1893 { 1894 dev_set_drvdata(&pdev->dev, data); 1895 } 1896 1897 static inline const char *pci_name(const struct pci_dev *pdev) 1898 { 1899 return dev_name(&pdev->dev); 1900 } 1901 1902 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1903 const struct resource *rsrc, 1904 resource_size_t *start, resource_size_t *end); 1905 1906 /* 1907 * The world is not perfect and supplies us with broken PCI devices. 1908 * For at least a part of these bugs we need a work-around, so both 1909 * generic (drivers/pci/quirks.c) and per-architecture code can define 1910 * fixup hooks to be called for particular buggy devices. 1911 */ 1912 1913 struct pci_fixup { 1914 u16 vendor; /* Or PCI_ANY_ID */ 1915 u16 device; /* Or PCI_ANY_ID */ 1916 u32 class; /* Or PCI_ANY_ID */ 1917 unsigned int class_shift; /* should be 0, 8, 16 */ 1918 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1919 int hook_offset; 1920 #else 1921 void (*hook)(struct pci_dev *dev); 1922 #endif 1923 }; 1924 1925 enum pci_fixup_pass { 1926 pci_fixup_early, /* Before probing BARs */ 1927 pci_fixup_header, /* After reading configuration header */ 1928 pci_fixup_final, /* Final phase of device fixups */ 1929 pci_fixup_enable, /* pci_enable_device() time */ 1930 pci_fixup_resume, /* pci_device_resume() */ 1931 pci_fixup_suspend, /* pci_device_suspend() */ 1932 pci_fixup_resume_early, /* pci_device_resume_early() */ 1933 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1934 }; 1935 1936 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1937 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1938 class_shift, hook) \ 1939 __ADDRESSABLE(hook) \ 1940 asm(".section " #sec ", \"a\" \n" \ 1941 ".balign 16 \n" \ 1942 ".short " #vendor ", " #device " \n" \ 1943 ".long " #class ", " #class_shift " \n" \ 1944 ".long " #hook " - . \n" \ 1945 ".previous \n"); 1946 1947 /* 1948 * Clang's LTO may rename static functions in C, but has no way to 1949 * handle such renamings when referenced from inline asm. To work 1950 * around this, create global C stubs for these cases. 1951 */ 1952 #ifdef CONFIG_LTO_CLANG 1953 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1954 class_shift, hook, stub) \ 1955 void __cficanonical stub(struct pci_dev *dev); \ 1956 void __cficanonical stub(struct pci_dev *dev) \ 1957 { \ 1958 hook(dev); \ 1959 } \ 1960 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1961 class_shift, stub) 1962 #else 1963 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1964 class_shift, hook, stub) \ 1965 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1966 class_shift, hook) 1967 #endif 1968 1969 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1970 class_shift, hook) \ 1971 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1972 class_shift, hook, __UNIQUE_ID(hook)) 1973 #else 1974 /* Anonymous variables would be nice... */ 1975 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1976 class_shift, hook) \ 1977 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1978 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1979 = { vendor, device, class, class_shift, hook }; 1980 #endif 1981 1982 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1983 class_shift, hook) \ 1984 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1985 hook, vendor, device, class, class_shift, hook) 1986 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1987 class_shift, hook) \ 1988 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1989 hook, vendor, device, class, class_shift, hook) 1990 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1991 class_shift, hook) \ 1992 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1993 hook, vendor, device, class, class_shift, hook) 1994 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1995 class_shift, hook) \ 1996 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1997 hook, vendor, device, class, class_shift, hook) 1998 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1999 class_shift, hook) \ 2000 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2001 resume##hook, vendor, device, class, class_shift, hook) 2002 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2003 class_shift, hook) \ 2004 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2005 resume_early##hook, vendor, device, class, class_shift, hook) 2006 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2007 class_shift, hook) \ 2008 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2009 suspend##hook, vendor, device, class, class_shift, hook) 2010 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2011 class_shift, hook) \ 2012 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2013 suspend_late##hook, vendor, device, class, class_shift, hook) 2014 2015 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2016 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2017 hook, vendor, device, PCI_ANY_ID, 0, hook) 2018 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2019 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2020 hook, vendor, device, PCI_ANY_ID, 0, hook) 2021 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2022 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2023 hook, vendor, device, PCI_ANY_ID, 0, hook) 2024 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2025 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2026 hook, vendor, device, PCI_ANY_ID, 0, hook) 2027 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2028 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2029 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2030 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2031 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2032 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2033 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2034 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2035 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2036 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2037 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2038 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2039 2040 #ifdef CONFIG_PCI_QUIRKS 2041 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2042 #else 2043 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2044 struct pci_dev *dev) { } 2045 #endif 2046 2047 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2048 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2049 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2050 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2051 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2052 const char *name); 2053 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2054 2055 extern int pci_pci_problems; 2056 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2057 #define PCIPCI_TRITON 2 2058 #define PCIPCI_NATOMA 4 2059 #define PCIPCI_VIAETBF 8 2060 #define PCIPCI_VSFX 16 2061 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2062 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2063 2064 extern unsigned long pci_cardbus_io_size; 2065 extern unsigned long pci_cardbus_mem_size; 2066 extern u8 pci_dfl_cache_line_size; 2067 extern u8 pci_cache_line_size; 2068 2069 /* Architecture-specific versions may override these (weak) */ 2070 void pcibios_disable_device(struct pci_dev *dev); 2071 void pcibios_set_master(struct pci_dev *dev); 2072 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2073 enum pcie_reset_state state); 2074 int pcibios_add_device(struct pci_dev *dev); 2075 void pcibios_release_device(struct pci_dev *dev); 2076 #ifdef CONFIG_PCI 2077 void pcibios_penalize_isa_irq(int irq, int active); 2078 #else 2079 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2080 #endif 2081 int pcibios_alloc_irq(struct pci_dev *dev); 2082 void pcibios_free_irq(struct pci_dev *dev); 2083 resource_size_t pcibios_default_alignment(void); 2084 2085 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2086 void __init pci_mmcfg_early_init(void); 2087 void __init pci_mmcfg_late_init(void); 2088 #else 2089 static inline void pci_mmcfg_early_init(void) { } 2090 static inline void pci_mmcfg_late_init(void) { } 2091 #endif 2092 2093 int pci_ext_cfg_avail(void); 2094 2095 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2096 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2097 2098 #ifdef CONFIG_PCI_IOV 2099 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2100 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2101 2102 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2103 void pci_disable_sriov(struct pci_dev *dev); 2104 2105 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2106 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2107 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2108 int pci_num_vf(struct pci_dev *dev); 2109 int pci_vfs_assigned(struct pci_dev *dev); 2110 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2111 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2112 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2113 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2114 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2115 2116 /* Arch may override these (weak) */ 2117 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2118 int pcibios_sriov_disable(struct pci_dev *pdev); 2119 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2120 #else 2121 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2122 { 2123 return -ENOSYS; 2124 } 2125 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2126 { 2127 return -ENOSYS; 2128 } 2129 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2130 { return -ENODEV; } 2131 2132 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2133 struct pci_dev *virtfn, int id) 2134 { 2135 return -ENODEV; 2136 } 2137 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2138 { 2139 return -ENOSYS; 2140 } 2141 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2142 int id) { } 2143 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2144 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2145 static inline int pci_vfs_assigned(struct pci_dev *dev) 2146 { return 0; } 2147 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2148 { return 0; } 2149 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2150 { return 0; } 2151 #define pci_sriov_configure_simple NULL 2152 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2153 { return 0; } 2154 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2155 #endif 2156 2157 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2158 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2159 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2160 #endif 2161 2162 /** 2163 * pci_pcie_cap - get the saved PCIe capability offset 2164 * @dev: PCI device 2165 * 2166 * PCIe capability offset is calculated at PCI device initialization 2167 * time and saved in the data structure. This function returns saved 2168 * PCIe capability offset. Using this instead of pci_find_capability() 2169 * reduces unnecessary search in the PCI configuration space. If you 2170 * need to calculate PCIe capability offset from raw device for some 2171 * reasons, please use pci_find_capability() instead. 2172 */ 2173 static inline int pci_pcie_cap(struct pci_dev *dev) 2174 { 2175 return dev->pcie_cap; 2176 } 2177 2178 /** 2179 * pci_is_pcie - check if the PCI device is PCI Express capable 2180 * @dev: PCI device 2181 * 2182 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2183 */ 2184 static inline bool pci_is_pcie(struct pci_dev *dev) 2185 { 2186 return pci_pcie_cap(dev); 2187 } 2188 2189 /** 2190 * pcie_caps_reg - get the PCIe Capabilities Register 2191 * @dev: PCI device 2192 */ 2193 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2194 { 2195 return dev->pcie_flags_reg; 2196 } 2197 2198 /** 2199 * pci_pcie_type - get the PCIe device/port type 2200 * @dev: PCI device 2201 */ 2202 static inline int pci_pcie_type(const struct pci_dev *dev) 2203 { 2204 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2205 } 2206 2207 /** 2208 * pcie_find_root_port - Get the PCIe root port device 2209 * @dev: PCI device 2210 * 2211 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2212 * for a given PCI/PCIe Device. 2213 */ 2214 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2215 { 2216 while (dev) { 2217 if (pci_is_pcie(dev) && 2218 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2219 return dev; 2220 dev = pci_upstream_bridge(dev); 2221 } 2222 2223 return NULL; 2224 } 2225 2226 void pci_request_acs(void); 2227 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2228 bool pci_acs_path_enabled(struct pci_dev *start, 2229 struct pci_dev *end, u16 acs_flags); 2230 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2231 2232 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2233 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2234 2235 /* Large Resource Data Type Tag Item Names */ 2236 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2237 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2238 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2239 2240 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2241 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2242 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2243 2244 /* Small Resource Data Type Tag Item Names */ 2245 #define PCI_VPD_STIN_END 0x0f /* End */ 2246 2247 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2248 2249 #define PCI_VPD_SRDT_TIN_MASK 0x78 2250 #define PCI_VPD_SRDT_LEN_MASK 0x07 2251 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2252 2253 #define PCI_VPD_LRDT_TAG_SIZE 3 2254 #define PCI_VPD_SRDT_TAG_SIZE 1 2255 2256 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2257 2258 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2259 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2260 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2261 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2262 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2263 2264 /** 2265 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2266 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2267 * 2268 * Returns the extracted Large Resource Data Type length. 2269 */ 2270 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2271 { 2272 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2273 } 2274 2275 /** 2276 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2277 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2278 * 2279 * Returns the extracted Large Resource Data Type Tag item. 2280 */ 2281 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2282 { 2283 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2284 } 2285 2286 /** 2287 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2288 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2289 * 2290 * Returns the extracted Small Resource Data Type length. 2291 */ 2292 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2293 { 2294 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2295 } 2296 2297 /** 2298 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2299 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2300 * 2301 * Returns the extracted Small Resource Data Type Tag Item. 2302 */ 2303 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2304 { 2305 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2306 } 2307 2308 /** 2309 * pci_vpd_info_field_size - Extracts the information field length 2310 * @info_field: Pointer to the beginning of an information field header 2311 * 2312 * Returns the extracted information field length. 2313 */ 2314 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2315 { 2316 return info_field[2]; 2317 } 2318 2319 /** 2320 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2321 * @buf: Pointer to buffered vpd data 2322 * @off: The offset into the buffer at which to begin the search 2323 * @len: The length of the vpd buffer 2324 * @rdt: The Resource Data Type to search for 2325 * 2326 * Returns the index where the Resource Data Type was found or 2327 * -ENOENT otherwise. 2328 */ 2329 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2330 2331 /** 2332 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2333 * @buf: Pointer to buffered vpd data 2334 * @off: The offset into the buffer at which to begin the search 2335 * @len: The length of the buffer area, relative to off, in which to search 2336 * @kw: The keyword to search for 2337 * 2338 * Returns the index where the information field keyword was found or 2339 * -ENOENT otherwise. 2340 */ 2341 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2342 unsigned int len, const char *kw); 2343 2344 /* PCI <-> OF binding helpers */ 2345 #ifdef CONFIG_OF 2346 struct device_node; 2347 struct irq_domain; 2348 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2349 2350 /* Arch may override this (weak) */ 2351 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2352 2353 #else /* CONFIG_OF */ 2354 static inline struct irq_domain * 2355 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2356 #endif /* CONFIG_OF */ 2357 2358 static inline struct device_node * 2359 pci_device_to_OF_node(const struct pci_dev *pdev) 2360 { 2361 return pdev ? pdev->dev.of_node : NULL; 2362 } 2363 2364 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2365 { 2366 return bus ? bus->dev.of_node : NULL; 2367 } 2368 2369 #ifdef CONFIG_ACPI 2370 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2371 2372 void 2373 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2374 bool pci_pr3_present(struct pci_dev *pdev); 2375 #else 2376 static inline struct irq_domain * 2377 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2378 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2379 #endif 2380 2381 #ifdef CONFIG_EEH 2382 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2383 { 2384 return pdev->dev.archdata.edev; 2385 } 2386 #endif 2387 2388 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2389 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2390 int pci_for_each_dma_alias(struct pci_dev *pdev, 2391 int (*fn)(struct pci_dev *pdev, 2392 u16 alias, void *data), void *data); 2393 2394 /* Helper functions for operation of device flag */ 2395 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2396 { 2397 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2398 } 2399 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2400 { 2401 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2402 } 2403 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2404 { 2405 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2406 } 2407 2408 /** 2409 * pci_ari_enabled - query ARI forwarding status 2410 * @bus: the PCI bus 2411 * 2412 * Returns true if ARI forwarding is enabled. 2413 */ 2414 static inline bool pci_ari_enabled(struct pci_bus *bus) 2415 { 2416 return bus->self && bus->self->ari_enabled; 2417 } 2418 2419 /** 2420 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2421 * @pdev: PCI device to check 2422 * 2423 * Walk upwards from @pdev and check for each encountered bridge if it's part 2424 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2425 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2426 */ 2427 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2428 { 2429 struct pci_dev *parent = pdev; 2430 2431 if (pdev->is_thunderbolt) 2432 return true; 2433 2434 while ((parent = pci_upstream_bridge(parent))) 2435 if (parent->is_thunderbolt) 2436 return true; 2437 2438 return false; 2439 } 2440 2441 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2442 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2443 #endif 2444 2445 /* Provide the legacy pci_dma_* API */ 2446 #include <linux/pci-dma-compat.h> 2447 2448 #define pci_printk(level, pdev, fmt, arg...) \ 2449 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2450 2451 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2452 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2453 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2454 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2455 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2456 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2457 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2458 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2459 2460 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2461 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2462 2463 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2464 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2465 2466 #define pci_WARN(pdev, condition, fmt, arg...) \ 2467 WARN(condition, "%s %s: " fmt, \ 2468 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2469 2470 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2471 WARN_ONCE(condition, "%s %s: " fmt, \ 2472 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2473 2474 #endif /* LINUX_PCI_H */ 2475