1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 46 PCI_STATUS_SIG_SYSTEM_ERROR | \ 47 PCI_STATUS_REC_MASTER_ABORT | \ 48 PCI_STATUS_REC_TARGET_ABORT | \ 49 PCI_STATUS_SIG_TARGET_ABORT | \ 50 PCI_STATUS_PARITY) 51 52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 53 #define PCI_NUM_RESET_METHODS 7 54 55 #define PCI_RESET_PROBE true 56 #define PCI_RESET_DO_RESET false 57 58 /* 59 * The PCI interface treats multi-function devices as independent 60 * devices. The slot/function address of each device is encoded 61 * in a single byte as follows: 62 * 63 * 7:3 = slot 64 * 2:0 = function 65 * 66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 67 * In the interest of not exposing interfaces to user-space unnecessarily, 68 * the following kernel-only defines are being added here. 69 */ 70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 73 74 /* pci_slot represents a physical slot */ 75 struct pci_slot { 76 struct pci_bus *bus; /* Bus this slot is on */ 77 struct list_head list; /* Node in list of slots */ 78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 80 struct kobject kobj; 81 }; 82 83 static inline const char *pci_slot_name(const struct pci_slot *slot) 84 { 85 return kobject_name(&slot->kobj); 86 } 87 88 /* File state for mmap()s on /proc/bus/pci/X/Y */ 89 enum pci_mmap_state { 90 pci_mmap_io, 91 pci_mmap_mem 92 }; 93 94 /* For PCI devices, the region numbers are assigned this way: */ 95 enum { 96 /* #0-5: standard PCI resources */ 97 PCI_STD_RESOURCES, 98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 99 100 /* #6: expansion ROM resource */ 101 PCI_ROM_RESOURCE, 102 103 /* Device-specific resources */ 104 #ifdef CONFIG_PCI_IOV 105 PCI_IOV_RESOURCES, 106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 107 #endif 108 109 /* PCI-to-PCI (P2P) bridge windows */ 110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 113 114 /* CardBus bridge windows */ 115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 119 120 /* Total number of bridge resources for P2P and CardBus */ 121 #define PCI_BRIDGE_RESOURCE_NUM 4 122 123 /* Resources assigned to buses behind the bridge */ 124 PCI_BRIDGE_RESOURCES, 125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 126 PCI_BRIDGE_RESOURCE_NUM - 1, 127 128 /* Total resources associated with a PCI device */ 129 PCI_NUM_RESOURCES, 130 131 /* Preserve this for compatibility */ 132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 133 }; 134 135 /** 136 * enum pci_interrupt_pin - PCI INTx interrupt values 137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 138 * @PCI_INTERRUPT_INTA: PCI INTA pin 139 * @PCI_INTERRUPT_INTB: PCI INTB pin 140 * @PCI_INTERRUPT_INTC: PCI INTC pin 141 * @PCI_INTERRUPT_INTD: PCI INTD pin 142 * 143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 144 * PCI_INTERRUPT_PIN register. 145 */ 146 enum pci_interrupt_pin { 147 PCI_INTERRUPT_UNKNOWN, 148 PCI_INTERRUPT_INTA, 149 PCI_INTERRUPT_INTB, 150 PCI_INTERRUPT_INTC, 151 PCI_INTERRUPT_INTD, 152 }; 153 154 /* The number of legacy PCI INTx interrupts */ 155 #define PCI_NUM_INTX 4 156 157 /* 158 * pci_power_t values must match the bits in the Capabilities PME_Support 159 * and Control/Status PowerState fields in the Power Management capability. 160 */ 161 typedef int __bitwise pci_power_t; 162 163 #define PCI_D0 ((pci_power_t __force) 0) 164 #define PCI_D1 ((pci_power_t __force) 1) 165 #define PCI_D2 ((pci_power_t __force) 2) 166 #define PCI_D3hot ((pci_power_t __force) 3) 167 #define PCI_D3cold ((pci_power_t __force) 4) 168 #define PCI_UNKNOWN ((pci_power_t __force) 5) 169 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 170 171 /* Remember to update this when the list above changes! */ 172 extern const char *pci_power_names[]; 173 174 static inline const char *pci_power_name(pci_power_t state) 175 { 176 return pci_power_names[1 + (__force int) state]; 177 } 178 179 /** 180 * typedef pci_channel_state_t 181 * 182 * The pci_channel state describes connectivity between the CPU and 183 * the PCI device. If some PCI bus between here and the PCI device 184 * has crashed or locked up, this info is reflected here. 185 */ 186 typedef unsigned int __bitwise pci_channel_state_t; 187 188 enum { 189 /* I/O channel is in normal state */ 190 pci_channel_io_normal = (__force pci_channel_state_t) 1, 191 192 /* I/O to channel is blocked */ 193 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 194 195 /* PCI card is dead */ 196 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 197 }; 198 199 typedef unsigned int __bitwise pcie_reset_state_t; 200 201 enum pcie_reset_state { 202 /* Reset is NOT asserted (Use to deassert reset) */ 203 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 204 205 /* Use #PERST to reset PCIe device */ 206 pcie_warm_reset = (__force pcie_reset_state_t) 2, 207 208 /* Use PCIe Hot Reset to reset device */ 209 pcie_hot_reset = (__force pcie_reset_state_t) 3 210 }; 211 212 typedef unsigned short __bitwise pci_dev_flags_t; 213 enum pci_dev_flags { 214 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 215 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 216 /* Device configuration is irrevocably lost if disabled into D3 */ 217 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 218 /* Provide indication device is assigned by a Virtual Machine Manager */ 219 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 220 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 221 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 222 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 223 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 224 /* Do not use bus resets for device */ 225 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 226 /* Do not use PM reset even if device advertises NoSoftRst- */ 227 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 228 /* Get VPD from function 0 VPD */ 229 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 230 /* A non-root bridge where translation occurs, stop alias search here */ 231 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 232 /* Do not use FLR even if device advertises PCI_AF_CAP */ 233 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 234 /* Don't use Relaxed Ordering for TLPs directed at this device */ 235 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 236 }; 237 238 enum pci_irq_reroute_variant { 239 INTEL_IRQ_REROUTE_VARIANT = 1, 240 MAX_IRQ_REROUTE_VARIANTS = 3 241 }; 242 243 typedef unsigned short __bitwise pci_bus_flags_t; 244 enum pci_bus_flags { 245 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 246 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 247 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 248 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 249 }; 250 251 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 252 enum pcie_link_width { 253 PCIE_LNK_WIDTH_RESRV = 0x00, 254 PCIE_LNK_X1 = 0x01, 255 PCIE_LNK_X2 = 0x02, 256 PCIE_LNK_X4 = 0x04, 257 PCIE_LNK_X8 = 0x08, 258 PCIE_LNK_X12 = 0x0c, 259 PCIE_LNK_X16 = 0x10, 260 PCIE_LNK_X32 = 0x20, 261 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 262 }; 263 264 /* See matching string table in pci_speed_string() */ 265 enum pci_bus_speed { 266 PCI_SPEED_33MHz = 0x00, 267 PCI_SPEED_66MHz = 0x01, 268 PCI_SPEED_66MHz_PCIX = 0x02, 269 PCI_SPEED_100MHz_PCIX = 0x03, 270 PCI_SPEED_133MHz_PCIX = 0x04, 271 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 272 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 273 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 274 PCI_SPEED_66MHz_PCIX_266 = 0x09, 275 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 276 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 277 AGP_UNKNOWN = 0x0c, 278 AGP_1X = 0x0d, 279 AGP_2X = 0x0e, 280 AGP_4X = 0x0f, 281 AGP_8X = 0x10, 282 PCI_SPEED_66MHz_PCIX_533 = 0x11, 283 PCI_SPEED_100MHz_PCIX_533 = 0x12, 284 PCI_SPEED_133MHz_PCIX_533 = 0x13, 285 PCIE_SPEED_2_5GT = 0x14, 286 PCIE_SPEED_5_0GT = 0x15, 287 PCIE_SPEED_8_0GT = 0x16, 288 PCIE_SPEED_16_0GT = 0x17, 289 PCIE_SPEED_32_0GT = 0x18, 290 PCIE_SPEED_64_0GT = 0x19, 291 PCI_SPEED_UNKNOWN = 0xff, 292 }; 293 294 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 295 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 296 297 struct pci_vpd { 298 struct mutex lock; 299 unsigned int len; 300 u8 cap; 301 }; 302 303 struct irq_affinity; 304 struct pcie_link_state; 305 struct pci_sriov; 306 struct pci_p2pdma; 307 struct rcec_ea; 308 309 /* The pci_dev structure describes PCI devices */ 310 struct pci_dev { 311 struct list_head bus_list; /* Node in per-bus list */ 312 struct pci_bus *bus; /* Bus this device is on */ 313 struct pci_bus *subordinate; /* Bus this device bridges to */ 314 315 void *sysdata; /* Hook for sys-specific extension */ 316 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 317 struct pci_slot *slot; /* Physical slot this device is in */ 318 319 unsigned int devfn; /* Encoded device & function index */ 320 unsigned short vendor; 321 unsigned short device; 322 unsigned short subsystem_vendor; 323 unsigned short subsystem_device; 324 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 325 u8 revision; /* PCI revision, low byte of class word */ 326 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 327 #ifdef CONFIG_PCIEAER 328 u16 aer_cap; /* AER capability offset */ 329 struct aer_stats *aer_stats; /* AER stats for this device */ 330 #endif 331 #ifdef CONFIG_PCIEPORTBUS 332 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 333 struct pci_dev *rcec; /* Associated RCEC device */ 334 #endif 335 u32 devcap; /* PCIe Device Capabilities */ 336 u8 pcie_cap; /* PCIe capability offset */ 337 u8 msi_cap; /* MSI capability offset */ 338 u8 msix_cap; /* MSI-X capability offset */ 339 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 340 u8 rom_base_reg; /* Config register controlling ROM */ 341 u8 pin; /* Interrupt pin this device uses */ 342 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 343 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 344 345 u64 dma_mask; /* Mask of the bits of bus address this 346 device implements. Normally this is 347 0xffffffff. You only need to change 348 this if your device has broken DMA 349 or supports 64-bit transfers. */ 350 351 struct device_dma_parameters dma_parms; 352 353 pci_power_t current_state; /* Current operating state. In ACPI, 354 this is D0-D3, D0 being fully 355 functional, and D3 being off. */ 356 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 357 u8 pm_cap; /* PM capability offset */ 358 unsigned int pme_support:5; /* Bitmask of states from which PME# 359 can be generated */ 360 unsigned int pme_poll:1; /* Poll device's PME status bit */ 361 unsigned int d1_support:1; /* Low power state D1 is supported */ 362 unsigned int d2_support:1; /* Low power state D2 is supported */ 363 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 364 unsigned int no_d3cold:1; /* D3cold is forbidden */ 365 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 366 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 367 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 368 decoding during BAR sizing */ 369 unsigned int wakeup_prepared:1; 370 unsigned int runtime_d3cold:1; /* Whether go through runtime 371 D3cold, not set for devices 372 powered on/off by the 373 corresponding bridge */ 374 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 375 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 376 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 377 controlled exclusively by 378 user sysfs */ 379 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 380 bit manually */ 381 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 382 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 383 384 #ifdef CONFIG_PCIEASPM 385 struct pcie_link_state *link_state; /* ASPM link state */ 386 unsigned int ltr_path:1; /* Latency Tolerance Reporting 387 supported from root to here */ 388 u16 l1ss; /* L1SS Capability pointer */ 389 #endif 390 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 391 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 392 393 pci_channel_state_t error_state; /* Current connectivity state */ 394 struct device dev; /* Generic device interface */ 395 396 int cfg_size; /* Size of config space */ 397 398 /* 399 * Instead of touching interrupt line and base address registers 400 * directly, use the values stored here. They might be different! 401 */ 402 unsigned int irq; 403 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 404 405 bool match_driver; /* Skip attaching driver */ 406 407 unsigned int transparent:1; /* Subtractive decode bridge */ 408 unsigned int io_window:1; /* Bridge has I/O window */ 409 unsigned int pref_window:1; /* Bridge has pref mem window */ 410 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 411 unsigned int multifunction:1; /* Multi-function device */ 412 413 unsigned int is_busmaster:1; /* Is busmaster */ 414 unsigned int no_msi:1; /* May not use MSI */ 415 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 416 unsigned int block_cfg_access:1; /* Config space access blocked */ 417 unsigned int broken_parity_status:1; /* Generates false positive parity */ 418 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 419 unsigned int msi_enabled:1; 420 unsigned int msix_enabled:1; 421 unsigned int ari_enabled:1; /* ARI forwarding */ 422 unsigned int ats_enabled:1; /* Address Translation Svc */ 423 unsigned int pasid_enabled:1; /* Process Address Space ID */ 424 unsigned int pri_enabled:1; /* Page Request Interface */ 425 unsigned int is_managed:1; 426 unsigned int needs_freset:1; /* Requires fundamental reset */ 427 unsigned int state_saved:1; 428 unsigned int is_physfn:1; 429 unsigned int is_virtfn:1; 430 unsigned int is_hotplug_bridge:1; 431 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 432 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 433 /* 434 * Devices marked being untrusted are the ones that can potentially 435 * execute DMA attacks and similar. They are typically connected 436 * through external ports such as Thunderbolt but not limited to 437 * that. When an IOMMU is enabled they should be getting full 438 * mappings to make sure they cannot access arbitrary memory. 439 */ 440 unsigned int untrusted:1; 441 /* 442 * Info from the platform, e.g., ACPI or device tree, may mark a 443 * device as "external-facing". An external-facing device is 444 * itself internal but devices downstream from it are external. 445 */ 446 unsigned int external_facing:1; 447 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 448 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 449 unsigned int irq_managed:1; 450 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 451 unsigned int is_probed:1; /* Device probing in progress */ 452 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 453 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 454 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 455 pci_dev_flags_t dev_flags; 456 atomic_t enable_cnt; /* pci_enable_device has been called */ 457 458 u32 saved_config_space[16]; /* Config space saved at suspend time */ 459 struct hlist_head saved_cap_space; 460 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 461 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 462 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 463 464 #ifdef CONFIG_HOTPLUG_PCI_PCIE 465 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 466 #endif 467 #ifdef CONFIG_PCIE_PTM 468 unsigned int ptm_root:1; 469 unsigned int ptm_enabled:1; 470 u8 ptm_granularity; 471 #endif 472 #ifdef CONFIG_PCI_MSI 473 const struct attribute_group **msi_irq_groups; 474 #endif 475 struct pci_vpd vpd; 476 #ifdef CONFIG_PCIE_DPC 477 u16 dpc_cap; 478 unsigned int dpc_rp_extensions:1; 479 u8 dpc_rp_log_size; 480 #endif 481 #ifdef CONFIG_PCI_ATS 482 union { 483 struct pci_sriov *sriov; /* PF: SR-IOV info */ 484 struct pci_dev *physfn; /* VF: related PF */ 485 }; 486 u16 ats_cap; /* ATS Capability offset */ 487 u8 ats_stu; /* ATS Smallest Translation Unit */ 488 #endif 489 #ifdef CONFIG_PCI_PRI 490 u16 pri_cap; /* PRI Capability offset */ 491 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 492 unsigned int pasid_required:1; /* PRG Response PASID Required */ 493 #endif 494 #ifdef CONFIG_PCI_PASID 495 u16 pasid_cap; /* PASID Capability offset */ 496 u16 pasid_features; 497 #endif 498 #ifdef CONFIG_PCI_P2PDMA 499 struct pci_p2pdma __rcu *p2pdma; 500 #endif 501 u16 acs_cap; /* ACS Capability offset */ 502 phys_addr_t rom; /* Physical address if not from BAR */ 503 size_t romlen; /* Length if not from BAR */ 504 char *driver_override; /* Driver name to force a match */ 505 506 unsigned long priv_flags; /* Private flags for the PCI driver */ 507 508 /* These methods index pci_reset_fn_methods[] */ 509 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 510 }; 511 512 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 513 { 514 #ifdef CONFIG_PCI_IOV 515 if (dev->is_virtfn) 516 dev = dev->physfn; 517 #endif 518 return dev; 519 } 520 521 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 522 523 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 524 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 525 526 static inline int pci_channel_offline(struct pci_dev *pdev) 527 { 528 return (pdev->error_state != pci_channel_io_normal); 529 } 530 531 /* 532 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 533 * Group number is limited to a 16-bit value, therefore (int)-1 is 534 * not a valid PCI domain number, and can be used as a sentinel 535 * value indicating ->domain_nr is not set by the driver (and 536 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 537 * pci_bus_find_domain_nr()). 538 */ 539 #define PCI_DOMAIN_NR_NOT_SET (-1) 540 541 struct pci_host_bridge { 542 struct device dev; 543 struct pci_bus *bus; /* Root bus */ 544 struct pci_ops *ops; 545 struct pci_ops *child_ops; 546 void *sysdata; 547 int busnr; 548 int domain_nr; 549 struct list_head windows; /* resource_entry */ 550 struct list_head dma_ranges; /* dma ranges resource list */ 551 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 552 int (*map_irq)(const struct pci_dev *, u8, u8); 553 void (*release_fn)(struct pci_host_bridge *); 554 void *release_data; 555 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 556 unsigned int no_ext_tags:1; /* No Extended Tags */ 557 unsigned int native_aer:1; /* OS may use PCIe AER */ 558 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 559 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 560 unsigned int native_pme:1; /* OS may use PCIe PME */ 561 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 562 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 563 unsigned int preserve_config:1; /* Preserve FW resource setup */ 564 unsigned int size_windows:1; /* Enable root bus sizing */ 565 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 566 567 /* Resource alignment requirements */ 568 resource_size_t (*align_resource)(struct pci_dev *dev, 569 const struct resource *res, 570 resource_size_t start, 571 resource_size_t size, 572 resource_size_t align); 573 unsigned long private[] ____cacheline_aligned; 574 }; 575 576 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 577 578 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 579 { 580 return (void *)bridge->private; 581 } 582 583 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 584 { 585 return container_of(priv, struct pci_host_bridge, private); 586 } 587 588 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 589 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 590 size_t priv); 591 void pci_free_host_bridge(struct pci_host_bridge *bridge); 592 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 593 594 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 595 void (*release_fn)(struct pci_host_bridge *), 596 void *release_data); 597 598 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 599 600 /* 601 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 602 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 603 * buses below host bridges or subtractive decode bridges) go in the list. 604 * Use pci_bus_for_each_resource() to iterate through all the resources. 605 */ 606 607 /* 608 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 609 * and there's no way to program the bridge with the details of the window. 610 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 611 * decode bit set, because they are explicit and can be programmed with _SRS. 612 */ 613 #define PCI_SUBTRACTIVE_DECODE 0x1 614 615 struct pci_bus_resource { 616 struct list_head list; 617 struct resource *res; 618 unsigned int flags; 619 }; 620 621 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 622 623 struct pci_bus { 624 struct list_head node; /* Node in list of buses */ 625 struct pci_bus *parent; /* Parent bus this bridge is on */ 626 struct list_head children; /* List of child buses */ 627 struct list_head devices; /* List of devices on this bus */ 628 struct pci_dev *self; /* Bridge device as seen by parent */ 629 struct list_head slots; /* List of slots on this bus; 630 protected by pci_slot_mutex */ 631 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 632 struct list_head resources; /* Address space routed to this bus */ 633 struct resource busn_res; /* Bus numbers routed to this bus */ 634 635 struct pci_ops *ops; /* Configuration access functions */ 636 void *sysdata; /* Hook for sys-specific extension */ 637 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 638 639 unsigned char number; /* Bus number */ 640 unsigned char primary; /* Number of primary bridge */ 641 unsigned char max_bus_speed; /* enum pci_bus_speed */ 642 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 643 #ifdef CONFIG_PCI_DOMAINS_GENERIC 644 int domain_nr; 645 #endif 646 647 char name[48]; 648 649 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 650 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 651 struct device *bridge; 652 struct device dev; 653 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 654 struct bin_attribute *legacy_mem; /* Legacy mem */ 655 unsigned int is_added:1; 656 }; 657 658 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 659 660 static inline u16 pci_dev_id(struct pci_dev *dev) 661 { 662 return PCI_DEVID(dev->bus->number, dev->devfn); 663 } 664 665 /* 666 * Returns true if the PCI bus is root (behind host-PCI bridge), 667 * false otherwise 668 * 669 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 670 * This is incorrect because "virtual" buses added for SR-IOV (via 671 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 672 */ 673 static inline bool pci_is_root_bus(struct pci_bus *pbus) 674 { 675 return !(pbus->parent); 676 } 677 678 /** 679 * pci_is_bridge - check if the PCI device is a bridge 680 * @dev: PCI device 681 * 682 * Return true if the PCI device is bridge whether it has subordinate 683 * or not. 684 */ 685 static inline bool pci_is_bridge(struct pci_dev *dev) 686 { 687 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 688 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 689 } 690 691 #define for_each_pci_bridge(dev, bus) \ 692 list_for_each_entry(dev, &bus->devices, bus_list) \ 693 if (!pci_is_bridge(dev)) {} else 694 695 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 696 { 697 dev = pci_physfn(dev); 698 if (pci_is_root_bus(dev->bus)) 699 return NULL; 700 701 return dev->bus->self; 702 } 703 704 #ifdef CONFIG_PCI_MSI 705 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 706 { 707 return pci_dev->msi_enabled || pci_dev->msix_enabled; 708 } 709 #else 710 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 711 #endif 712 713 /* Error values that may be returned by PCI functions */ 714 #define PCIBIOS_SUCCESSFUL 0x00 715 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 716 #define PCIBIOS_BAD_VENDOR_ID 0x83 717 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 718 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 719 #define PCIBIOS_SET_FAILED 0x88 720 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 721 722 /* Translate above to generic errno for passing back through non-PCI code */ 723 static inline int pcibios_err_to_errno(int err) 724 { 725 if (err <= PCIBIOS_SUCCESSFUL) 726 return err; /* Assume already errno */ 727 728 switch (err) { 729 case PCIBIOS_FUNC_NOT_SUPPORTED: 730 return -ENOENT; 731 case PCIBIOS_BAD_VENDOR_ID: 732 return -ENOTTY; 733 case PCIBIOS_DEVICE_NOT_FOUND: 734 return -ENODEV; 735 case PCIBIOS_BAD_REGISTER_NUMBER: 736 return -EFAULT; 737 case PCIBIOS_SET_FAILED: 738 return -EIO; 739 case PCIBIOS_BUFFER_TOO_SMALL: 740 return -ENOSPC; 741 } 742 743 return -ERANGE; 744 } 745 746 /* Low-level architecture-dependent routines */ 747 748 struct pci_ops { 749 int (*add_bus)(struct pci_bus *bus); 750 void (*remove_bus)(struct pci_bus *bus); 751 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 752 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 753 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 754 }; 755 756 /* 757 * ACPI needs to be able to access PCI config space before we've done a 758 * PCI bus scan and created pci_bus structures. 759 */ 760 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 761 int reg, int len, u32 *val); 762 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 763 int reg, int len, u32 val); 764 765 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 766 typedef u64 pci_bus_addr_t; 767 #else 768 typedef u32 pci_bus_addr_t; 769 #endif 770 771 struct pci_bus_region { 772 pci_bus_addr_t start; 773 pci_bus_addr_t end; 774 }; 775 776 struct pci_dynids { 777 spinlock_t lock; /* Protects list, index */ 778 struct list_head list; /* For IDs added at runtime */ 779 }; 780 781 782 /* 783 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 784 * a set of callbacks in struct pci_error_handlers, that device driver 785 * will be notified of PCI bus errors, and will be driven to recovery 786 * when an error occurs. 787 */ 788 789 typedef unsigned int __bitwise pci_ers_result_t; 790 791 enum pci_ers_result { 792 /* No result/none/not supported in device driver */ 793 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 794 795 /* Device driver can recover without slot reset */ 796 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 797 798 /* Device driver wants slot to be reset */ 799 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 800 801 /* Device has completely failed, is unrecoverable */ 802 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 803 804 /* Device driver is fully recovered and operational */ 805 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 806 807 /* No AER capabilities registered for the driver */ 808 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 809 }; 810 811 /* PCI bus error event callbacks */ 812 struct pci_error_handlers { 813 /* PCI bus error detected on this device */ 814 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 815 pci_channel_state_t error); 816 817 /* MMIO has been re-enabled, but not DMA */ 818 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 819 820 /* PCI slot has been reset */ 821 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 822 823 /* PCI function reset prepare or completed */ 824 void (*reset_prepare)(struct pci_dev *dev); 825 void (*reset_done)(struct pci_dev *dev); 826 827 /* Device driver may resume normal operations */ 828 void (*resume)(struct pci_dev *dev); 829 }; 830 831 832 struct module; 833 834 /** 835 * struct pci_driver - PCI driver structure 836 * @node: List of driver structures. 837 * @name: Driver name. 838 * @id_table: Pointer to table of device IDs the driver is 839 * interested in. Most drivers should export this 840 * table using MODULE_DEVICE_TABLE(pci,...). 841 * @probe: This probing function gets called (during execution 842 * of pci_register_driver() for already existing 843 * devices or later if a new device gets inserted) for 844 * all PCI devices which match the ID table and are not 845 * "owned" by the other drivers yet. This function gets 846 * passed a "struct pci_dev \*" for each device whose 847 * entry in the ID table matches the device. The probe 848 * function returns zero when the driver chooses to 849 * take "ownership" of the device or an error code 850 * (negative number) otherwise. 851 * The probe function always gets called from process 852 * context, so it can sleep. 853 * @remove: The remove() function gets called whenever a device 854 * being handled by this driver is removed (either during 855 * deregistration of the driver or when it's manually 856 * pulled out of a hot-pluggable slot). 857 * The remove function always gets called from process 858 * context, so it can sleep. 859 * @suspend: Put device into low power state. 860 * @resume: Wake device from low power state. 861 * (Please see Documentation/power/pci.rst for descriptions 862 * of PCI Power Management and the related functions.) 863 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 864 * Intended to stop any idling DMA operations. 865 * Useful for enabling wake-on-lan (NIC) or changing 866 * the power state of a device before reboot. 867 * e.g. drivers/net/e100.c. 868 * @sriov_configure: Optional driver callback to allow configuration of 869 * number of VFs to enable via sysfs "sriov_numvfs" file. 870 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 871 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 872 * This will change MSI-X Table Size in the VF Message Control 873 * registers. 874 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 875 * MSI-X vectors available for distribution to the VFs. 876 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 877 * @groups: Sysfs attribute groups. 878 * @dev_groups: Attributes attached to the device that will be 879 * created once it is bound to the driver. 880 * @driver: Driver model structure. 881 * @dynids: List of dynamically added device IDs. 882 */ 883 struct pci_driver { 884 struct list_head node; 885 const char *name; 886 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 887 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 888 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 889 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 890 int (*resume)(struct pci_dev *dev); /* Device woken up */ 891 void (*shutdown)(struct pci_dev *dev); 892 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 893 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 894 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 895 const struct pci_error_handlers *err_handler; 896 const struct attribute_group **groups; 897 const struct attribute_group **dev_groups; 898 struct device_driver driver; 899 struct pci_dynids dynids; 900 }; 901 902 static inline struct pci_driver *to_pci_driver(struct device_driver *drv) 903 { 904 return drv ? container_of(drv, struct pci_driver, driver) : NULL; 905 } 906 907 /** 908 * PCI_DEVICE - macro used to describe a specific PCI device 909 * @vend: the 16 bit PCI Vendor ID 910 * @dev: the 16 bit PCI Device ID 911 * 912 * This macro is used to create a struct pci_device_id that matches a 913 * specific device. The subvendor and subdevice fields will be set to 914 * PCI_ANY_ID. 915 */ 916 #define PCI_DEVICE(vend,dev) \ 917 .vendor = (vend), .device = (dev), \ 918 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 919 920 /** 921 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 922 * override_only flags. 923 * @vend: the 16 bit PCI Vendor ID 924 * @dev: the 16 bit PCI Device ID 925 * @driver_override: the 32 bit PCI Device override_only 926 * 927 * This macro is used to create a struct pci_device_id that matches only a 928 * driver_override device. The subvendor and subdevice fields will be set to 929 * PCI_ANY_ID. 930 */ 931 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 932 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 933 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 934 935 /** 936 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 937 * "driver_override" PCI device. 938 * @vend: the 16 bit PCI Vendor ID 939 * @dev: the 16 bit PCI Device ID 940 * 941 * This macro is used to create a struct pci_device_id that matches a 942 * specific device. The subvendor and subdevice fields will be set to 943 * PCI_ANY_ID and the driver_override will be set to 944 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 945 */ 946 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 947 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 948 949 /** 950 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 951 * @vend: the 16 bit PCI Vendor ID 952 * @dev: the 16 bit PCI Device ID 953 * @subvend: the 16 bit PCI Subvendor ID 954 * @subdev: the 16 bit PCI Subdevice ID 955 * 956 * This macro is used to create a struct pci_device_id that matches a 957 * specific device with subsystem information. 958 */ 959 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 960 .vendor = (vend), .device = (dev), \ 961 .subvendor = (subvend), .subdevice = (subdev) 962 963 /** 964 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 965 * @dev_class: the class, subclass, prog-if triple for this device 966 * @dev_class_mask: the class mask for this device 967 * 968 * This macro is used to create a struct pci_device_id that matches a 969 * specific PCI class. The vendor, device, subvendor, and subdevice 970 * fields will be set to PCI_ANY_ID. 971 */ 972 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 973 .class = (dev_class), .class_mask = (dev_class_mask), \ 974 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 975 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 976 977 /** 978 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 979 * @vend: the vendor name 980 * @dev: the 16 bit PCI Device ID 981 * 982 * This macro is used to create a struct pci_device_id that matches a 983 * specific PCI device. The subvendor, and subdevice fields will be set 984 * to PCI_ANY_ID. The macro allows the next field to follow as the device 985 * private data. 986 */ 987 #define PCI_VDEVICE(vend, dev) \ 988 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 989 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 990 991 /** 992 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 993 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 994 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 995 * @data: the driver data to be filled 996 * 997 * This macro is used to create a struct pci_device_id that matches a 998 * specific PCI device. The subvendor, and subdevice fields will be set 999 * to PCI_ANY_ID. 1000 */ 1001 #define PCI_DEVICE_DATA(vend, dev, data) \ 1002 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1003 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1004 .driver_data = (kernel_ulong_t)(data) 1005 1006 enum { 1007 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1008 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1009 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1010 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1011 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1012 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1013 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1014 }; 1015 1016 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1017 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1018 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1019 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1020 1021 /* These external functions are only available when PCI support is enabled */ 1022 #ifdef CONFIG_PCI 1023 1024 extern unsigned int pci_flags; 1025 1026 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1027 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1028 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1029 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1030 1031 void pcie_bus_configure_settings(struct pci_bus *bus); 1032 1033 enum pcie_bus_config_types { 1034 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1035 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1036 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1037 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1038 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1039 }; 1040 1041 extern enum pcie_bus_config_types pcie_bus_config; 1042 1043 extern struct bus_type pci_bus_type; 1044 1045 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1046 * code, or PCI core code. */ 1047 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1048 /* Some device drivers need know if PCI is initiated */ 1049 int no_pci_devices(void); 1050 1051 void pcibios_resource_survey_bus(struct pci_bus *bus); 1052 void pcibios_bus_add_device(struct pci_dev *pdev); 1053 void pcibios_add_bus(struct pci_bus *bus); 1054 void pcibios_remove_bus(struct pci_bus *bus); 1055 void pcibios_fixup_bus(struct pci_bus *); 1056 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1057 /* Architecture-specific versions may override this (weak) */ 1058 char *pcibios_setup(char *str); 1059 1060 /* Used only when drivers/pci/setup.c is used */ 1061 resource_size_t pcibios_align_resource(void *, const struct resource *, 1062 resource_size_t, 1063 resource_size_t); 1064 1065 /* Weak but can be overridden by arch */ 1066 void pci_fixup_cardbus(struct pci_bus *); 1067 1068 /* Generic PCI functions used internally */ 1069 1070 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1071 struct resource *res); 1072 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1073 struct pci_bus_region *region); 1074 void pcibios_scan_specific_bus(int busn); 1075 struct pci_bus *pci_find_bus(int domain, int busnr); 1076 void pci_bus_add_devices(const struct pci_bus *bus); 1077 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1078 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1079 struct pci_ops *ops, void *sysdata, 1080 struct list_head *resources); 1081 int pci_host_probe(struct pci_host_bridge *bridge); 1082 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1083 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1084 void pci_bus_release_busn_res(struct pci_bus *b); 1085 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1086 struct pci_ops *ops, void *sysdata, 1087 struct list_head *resources); 1088 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1089 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1090 int busnr); 1091 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1092 const char *name, 1093 struct hotplug_slot *hotplug); 1094 void pci_destroy_slot(struct pci_slot *slot); 1095 #ifdef CONFIG_SYSFS 1096 void pci_dev_assign_slot(struct pci_dev *dev); 1097 #else 1098 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1099 #endif 1100 int pci_scan_slot(struct pci_bus *bus, int devfn); 1101 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1102 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1103 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1104 void pci_bus_add_device(struct pci_dev *dev); 1105 void pci_read_bridge_bases(struct pci_bus *child); 1106 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1107 struct resource *res); 1108 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1109 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1110 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1111 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1112 void pci_dev_put(struct pci_dev *dev); 1113 void pci_remove_bus(struct pci_bus *b); 1114 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1115 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1116 void pci_stop_root_bus(struct pci_bus *bus); 1117 void pci_remove_root_bus(struct pci_bus *bus); 1118 void pci_setup_cardbus(struct pci_bus *bus); 1119 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1120 void pci_sort_breadthfirst(void); 1121 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1122 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1123 1124 /* Generic PCI functions exported to card drivers */ 1125 1126 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1127 u8 pci_find_capability(struct pci_dev *dev, int cap); 1128 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1129 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1130 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1131 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1132 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1133 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1134 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1135 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1136 1137 u64 pci_get_dsn(struct pci_dev *dev); 1138 1139 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1140 struct pci_dev *from); 1141 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1142 unsigned int ss_vendor, unsigned int ss_device, 1143 struct pci_dev *from); 1144 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1145 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1146 unsigned int devfn); 1147 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1148 int pci_dev_present(const struct pci_device_id *ids); 1149 1150 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1151 int where, u8 *val); 1152 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1153 int where, u16 *val); 1154 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1155 int where, u32 *val); 1156 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1157 int where, u8 val); 1158 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1159 int where, u16 val); 1160 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1161 int where, u32 val); 1162 1163 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1164 int where, int size, u32 *val); 1165 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1166 int where, int size, u32 val); 1167 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1168 int where, int size, u32 *val); 1169 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1170 int where, int size, u32 val); 1171 1172 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1173 1174 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1175 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1176 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1177 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1178 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1179 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1180 1181 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1182 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1183 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1184 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1185 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1186 u16 clear, u16 set); 1187 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1188 u32 clear, u32 set); 1189 1190 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1191 u16 set) 1192 { 1193 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1194 } 1195 1196 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1197 u32 set) 1198 { 1199 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1200 } 1201 1202 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1203 u16 clear) 1204 { 1205 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1206 } 1207 1208 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1209 u32 clear) 1210 { 1211 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1212 } 1213 1214 /* User-space driven config access */ 1215 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1216 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1217 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1218 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1219 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1220 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1221 1222 int __must_check pci_enable_device(struct pci_dev *dev); 1223 int __must_check pci_enable_device_io(struct pci_dev *dev); 1224 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1225 int __must_check pci_reenable_device(struct pci_dev *); 1226 int __must_check pcim_enable_device(struct pci_dev *pdev); 1227 void pcim_pin_device(struct pci_dev *pdev); 1228 1229 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1230 { 1231 /* 1232 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1233 * writable and no quirk has marked the feature broken. 1234 */ 1235 return !pdev->broken_intx_masking; 1236 } 1237 1238 static inline int pci_is_enabled(struct pci_dev *pdev) 1239 { 1240 return (atomic_read(&pdev->enable_cnt) > 0); 1241 } 1242 1243 static inline int pci_is_managed(struct pci_dev *pdev) 1244 { 1245 return pdev->is_managed; 1246 } 1247 1248 void pci_disable_device(struct pci_dev *dev); 1249 1250 extern unsigned int pcibios_max_latency; 1251 void pci_set_master(struct pci_dev *dev); 1252 void pci_clear_master(struct pci_dev *dev); 1253 1254 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1255 int pci_set_cacheline_size(struct pci_dev *dev); 1256 int __must_check pci_set_mwi(struct pci_dev *dev); 1257 int __must_check pcim_set_mwi(struct pci_dev *dev); 1258 int pci_try_set_mwi(struct pci_dev *dev); 1259 void pci_clear_mwi(struct pci_dev *dev); 1260 void pci_disable_parity(struct pci_dev *dev); 1261 void pci_intx(struct pci_dev *dev, int enable); 1262 bool pci_check_and_mask_intx(struct pci_dev *dev); 1263 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1264 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1265 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1266 int pcix_get_max_mmrbc(struct pci_dev *dev); 1267 int pcix_get_mmrbc(struct pci_dev *dev); 1268 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1269 int pcie_get_readrq(struct pci_dev *dev); 1270 int pcie_set_readrq(struct pci_dev *dev, int rq); 1271 int pcie_get_mps(struct pci_dev *dev); 1272 int pcie_set_mps(struct pci_dev *dev, int mps); 1273 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1274 enum pci_bus_speed *speed, 1275 enum pcie_link_width *width); 1276 void pcie_print_link_status(struct pci_dev *dev); 1277 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1278 int pcie_flr(struct pci_dev *dev); 1279 int __pci_reset_function_locked(struct pci_dev *dev); 1280 int pci_reset_function(struct pci_dev *dev); 1281 int pci_reset_function_locked(struct pci_dev *dev); 1282 int pci_try_reset_function(struct pci_dev *dev); 1283 int pci_probe_reset_slot(struct pci_slot *slot); 1284 int pci_probe_reset_bus(struct pci_bus *bus); 1285 int pci_reset_bus(struct pci_dev *dev); 1286 void pci_reset_secondary_bus(struct pci_dev *dev); 1287 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1288 void pci_update_resource(struct pci_dev *dev, int resno); 1289 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1290 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1291 void pci_release_resource(struct pci_dev *dev, int resno); 1292 static inline int pci_rebar_bytes_to_size(u64 bytes) 1293 { 1294 bytes = roundup_pow_of_two(bytes); 1295 1296 /* Return BAR size as defined in the resizable BAR specification */ 1297 return max(ilog2(bytes), 20) - 20; 1298 } 1299 1300 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1301 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1302 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1303 bool pci_device_is_present(struct pci_dev *pdev); 1304 void pci_ignore_hotplug(struct pci_dev *dev); 1305 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1306 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1307 1308 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1309 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1310 const char *fmt, ...); 1311 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1312 1313 /* ROM control related routines */ 1314 int pci_enable_rom(struct pci_dev *pdev); 1315 void pci_disable_rom(struct pci_dev *pdev); 1316 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1317 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1318 1319 /* Power management related routines */ 1320 int pci_save_state(struct pci_dev *dev); 1321 void pci_restore_state(struct pci_dev *dev); 1322 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1323 int pci_load_saved_state(struct pci_dev *dev, 1324 struct pci_saved_state *state); 1325 int pci_load_and_free_saved_state(struct pci_dev *dev, 1326 struct pci_saved_state **state); 1327 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1328 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1329 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1330 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1331 void pci_pme_active(struct pci_dev *dev, bool enable); 1332 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1333 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1334 int pci_prepare_to_sleep(struct pci_dev *dev); 1335 int pci_back_from_sleep(struct pci_dev *dev); 1336 bool pci_dev_run_wake(struct pci_dev *dev); 1337 void pci_d3cold_enable(struct pci_dev *dev); 1338 void pci_d3cold_disable(struct pci_dev *dev); 1339 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1340 void pci_resume_bus(struct pci_bus *bus); 1341 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1342 1343 /* For use by arch with custom probe code */ 1344 void set_pcie_port_type(struct pci_dev *pdev); 1345 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1346 1347 /* Functions for PCI Hotplug drivers to use */ 1348 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1349 unsigned int pci_rescan_bus(struct pci_bus *bus); 1350 void pci_lock_rescan_remove(void); 1351 void pci_unlock_rescan_remove(void); 1352 1353 /* Vital Product Data routines */ 1354 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1355 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1356 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1357 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1358 1359 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1360 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1361 void pci_bus_assign_resources(const struct pci_bus *bus); 1362 void pci_bus_claim_resources(struct pci_bus *bus); 1363 void pci_bus_size_bridges(struct pci_bus *bus); 1364 int pci_claim_resource(struct pci_dev *, int); 1365 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1366 void pci_assign_unassigned_resources(void); 1367 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1368 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1369 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1370 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1371 void pdev_enable_device(struct pci_dev *); 1372 int pci_enable_resources(struct pci_dev *, int mask); 1373 void pci_assign_irq(struct pci_dev *dev); 1374 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1375 #define HAVE_PCI_REQ_REGIONS 2 1376 int __must_check pci_request_regions(struct pci_dev *, const char *); 1377 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1378 void pci_release_regions(struct pci_dev *); 1379 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1380 void pci_release_region(struct pci_dev *, int); 1381 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1382 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1383 void pci_release_selected_regions(struct pci_dev *, int); 1384 1385 /* drivers/pci/bus.c */ 1386 void pci_add_resource(struct list_head *resources, struct resource *res); 1387 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1388 resource_size_t offset); 1389 void pci_free_resource_list(struct list_head *resources); 1390 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1391 unsigned int flags); 1392 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1393 void pci_bus_remove_resources(struct pci_bus *bus); 1394 int devm_request_pci_bus_resources(struct device *dev, 1395 struct list_head *resources); 1396 1397 /* Temporary until new and working PCI SBR API in place */ 1398 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1399 1400 #define pci_bus_for_each_resource(bus, res, i) \ 1401 for (i = 0; \ 1402 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1403 i++) 1404 1405 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1406 struct resource *res, resource_size_t size, 1407 resource_size_t align, resource_size_t min, 1408 unsigned long type_mask, 1409 resource_size_t (*alignf)(void *, 1410 const struct resource *, 1411 resource_size_t, 1412 resource_size_t), 1413 void *alignf_data); 1414 1415 1416 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1417 resource_size_t size); 1418 unsigned long pci_address_to_pio(phys_addr_t addr); 1419 phys_addr_t pci_pio_to_address(unsigned long pio); 1420 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1421 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1422 phys_addr_t phys_addr); 1423 void pci_unmap_iospace(struct resource *res); 1424 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1425 resource_size_t offset, 1426 resource_size_t size); 1427 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1428 struct resource *res); 1429 1430 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1431 { 1432 struct pci_bus_region region; 1433 1434 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1435 return region.start; 1436 } 1437 1438 /* Proper probing supporting hot-pluggable devices */ 1439 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1440 const char *mod_name); 1441 1442 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1443 #define pci_register_driver(driver) \ 1444 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1445 1446 void pci_unregister_driver(struct pci_driver *dev); 1447 1448 /** 1449 * module_pci_driver() - Helper macro for registering a PCI driver 1450 * @__pci_driver: pci_driver struct 1451 * 1452 * Helper macro for PCI drivers which do not do anything special in module 1453 * init/exit. This eliminates a lot of boilerplate. Each module may only 1454 * use this macro once, and calling it replaces module_init() and module_exit() 1455 */ 1456 #define module_pci_driver(__pci_driver) \ 1457 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1458 1459 /** 1460 * builtin_pci_driver() - Helper macro for registering a PCI driver 1461 * @__pci_driver: pci_driver struct 1462 * 1463 * Helper macro for PCI drivers which do not do anything special in their 1464 * init code. This eliminates a lot of boilerplate. Each driver may only 1465 * use this macro once, and calling it replaces device_initcall(...) 1466 */ 1467 #define builtin_pci_driver(__pci_driver) \ 1468 builtin_driver(__pci_driver, pci_register_driver) 1469 1470 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1471 int pci_add_dynid(struct pci_driver *drv, 1472 unsigned int vendor, unsigned int device, 1473 unsigned int subvendor, unsigned int subdevice, 1474 unsigned int class, unsigned int class_mask, 1475 unsigned long driver_data); 1476 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1477 struct pci_dev *dev); 1478 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1479 int pass); 1480 1481 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1482 void *userdata); 1483 int pci_cfg_space_size(struct pci_dev *dev); 1484 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1485 void pci_setup_bridge(struct pci_bus *bus); 1486 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1487 unsigned long type); 1488 1489 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1490 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1491 1492 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1493 unsigned int command_bits, u32 flags); 1494 1495 /* 1496 * Virtual interrupts allow for more interrupts to be allocated 1497 * than the device has interrupts for. These are not programmed 1498 * into the device's MSI-X table and must be handled by some 1499 * other driver means. 1500 */ 1501 #define PCI_IRQ_VIRTUAL (1 << 4) 1502 1503 #define PCI_IRQ_ALL_TYPES \ 1504 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1505 1506 #include <linux/dmapool.h> 1507 1508 struct msix_entry { 1509 u32 vector; /* Kernel uses to write allocated vector */ 1510 u16 entry; /* Driver uses to specify entry, OS writes */ 1511 }; 1512 1513 #ifdef CONFIG_PCI_MSI 1514 int pci_msi_vec_count(struct pci_dev *dev); 1515 void pci_disable_msi(struct pci_dev *dev); 1516 int pci_msix_vec_count(struct pci_dev *dev); 1517 void pci_disable_msix(struct pci_dev *dev); 1518 void pci_restore_msi_state(struct pci_dev *dev); 1519 int pci_msi_enabled(void); 1520 int pci_enable_msi(struct pci_dev *dev); 1521 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1522 int minvec, int maxvec); 1523 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1524 struct msix_entry *entries, int nvec) 1525 { 1526 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1527 if (rc < 0) 1528 return rc; 1529 return 0; 1530 } 1531 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1532 unsigned int max_vecs, unsigned int flags, 1533 struct irq_affinity *affd); 1534 1535 void pci_free_irq_vectors(struct pci_dev *dev); 1536 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1537 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1538 1539 #else 1540 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1541 static inline void pci_disable_msi(struct pci_dev *dev) { } 1542 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1543 static inline void pci_disable_msix(struct pci_dev *dev) { } 1544 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1545 static inline int pci_msi_enabled(void) { return 0; } 1546 static inline int pci_enable_msi(struct pci_dev *dev) 1547 { return -ENOSYS; } 1548 static inline int pci_enable_msix_range(struct pci_dev *dev, 1549 struct msix_entry *entries, int minvec, int maxvec) 1550 { return -ENOSYS; } 1551 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1552 struct msix_entry *entries, int nvec) 1553 { return -ENOSYS; } 1554 1555 static inline int 1556 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1557 unsigned int max_vecs, unsigned int flags, 1558 struct irq_affinity *aff_desc) 1559 { 1560 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1561 return 1; 1562 return -ENOSPC; 1563 } 1564 1565 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1566 { 1567 } 1568 1569 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1570 { 1571 if (WARN_ON_ONCE(nr > 0)) 1572 return -EINVAL; 1573 return dev->irq; 1574 } 1575 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1576 int vec) 1577 { 1578 return cpu_possible_mask; 1579 } 1580 #endif 1581 1582 /** 1583 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1584 * @d: the INTx IRQ domain 1585 * @node: the DT node for the device whose interrupt we're translating 1586 * @intspec: the interrupt specifier data from the DT 1587 * @intsize: the number of entries in @intspec 1588 * @out_hwirq: pointer at which to write the hwirq number 1589 * @out_type: pointer at which to write the interrupt type 1590 * 1591 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1592 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1593 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1594 * INTx value to obtain the hwirq number. 1595 * 1596 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1597 */ 1598 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1599 struct device_node *node, 1600 const u32 *intspec, 1601 unsigned int intsize, 1602 unsigned long *out_hwirq, 1603 unsigned int *out_type) 1604 { 1605 const u32 intx = intspec[0]; 1606 1607 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1608 return -EINVAL; 1609 1610 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1611 return 0; 1612 } 1613 1614 #ifdef CONFIG_PCIEPORTBUS 1615 extern bool pcie_ports_disabled; 1616 extern bool pcie_ports_native; 1617 #else 1618 #define pcie_ports_disabled true 1619 #define pcie_ports_native false 1620 #endif 1621 1622 #define PCIE_LINK_STATE_L0S BIT(0) 1623 #define PCIE_LINK_STATE_L1 BIT(1) 1624 #define PCIE_LINK_STATE_CLKPM BIT(2) 1625 #define PCIE_LINK_STATE_L1_1 BIT(3) 1626 #define PCIE_LINK_STATE_L1_2 BIT(4) 1627 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1628 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1629 1630 #ifdef CONFIG_PCIEASPM 1631 int pci_disable_link_state(struct pci_dev *pdev, int state); 1632 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1633 void pcie_no_aspm(void); 1634 bool pcie_aspm_support_enabled(void); 1635 bool pcie_aspm_enabled(struct pci_dev *pdev); 1636 #else 1637 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1638 { return 0; } 1639 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1640 { return 0; } 1641 static inline void pcie_no_aspm(void) { } 1642 static inline bool pcie_aspm_support_enabled(void) { return false; } 1643 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1644 #endif 1645 1646 #ifdef CONFIG_PCIEAER 1647 bool pci_aer_available(void); 1648 #else 1649 static inline bool pci_aer_available(void) { return false; } 1650 #endif 1651 1652 bool pci_ats_disabled(void); 1653 1654 #ifdef CONFIG_PCIE_PTM 1655 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1656 bool pcie_ptm_enabled(struct pci_dev *dev); 1657 #else 1658 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1659 { return -EINVAL; } 1660 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1661 { return false; } 1662 #endif 1663 1664 void pci_cfg_access_lock(struct pci_dev *dev); 1665 bool pci_cfg_access_trylock(struct pci_dev *dev); 1666 void pci_cfg_access_unlock(struct pci_dev *dev); 1667 1668 int pci_dev_trylock(struct pci_dev *dev); 1669 void pci_dev_unlock(struct pci_dev *dev); 1670 1671 /* 1672 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1673 * a PCI domain is defined to be a set of PCI buses which share 1674 * configuration space. 1675 */ 1676 #ifdef CONFIG_PCI_DOMAINS 1677 extern int pci_domains_supported; 1678 #else 1679 enum { pci_domains_supported = 0 }; 1680 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1681 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1682 #endif /* CONFIG_PCI_DOMAINS */ 1683 1684 /* 1685 * Generic implementation for PCI domain support. If your 1686 * architecture does not need custom management of PCI 1687 * domains then this implementation will be used 1688 */ 1689 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1690 static inline int pci_domain_nr(struct pci_bus *bus) 1691 { 1692 return bus->domain_nr; 1693 } 1694 #ifdef CONFIG_ACPI 1695 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1696 #else 1697 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1698 { return 0; } 1699 #endif 1700 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1701 #endif 1702 1703 /* Some architectures require additional setup to direct VGA traffic */ 1704 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1705 unsigned int command_bits, u32 flags); 1706 void pci_register_set_vga_state(arch_set_vga_state_t func); 1707 1708 static inline int 1709 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1710 { 1711 return pci_request_selected_regions(pdev, 1712 pci_select_bars(pdev, IORESOURCE_IO), name); 1713 } 1714 1715 static inline void 1716 pci_release_io_regions(struct pci_dev *pdev) 1717 { 1718 return pci_release_selected_regions(pdev, 1719 pci_select_bars(pdev, IORESOURCE_IO)); 1720 } 1721 1722 static inline int 1723 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1724 { 1725 return pci_request_selected_regions(pdev, 1726 pci_select_bars(pdev, IORESOURCE_MEM), name); 1727 } 1728 1729 static inline void 1730 pci_release_mem_regions(struct pci_dev *pdev) 1731 { 1732 return pci_release_selected_regions(pdev, 1733 pci_select_bars(pdev, IORESOURCE_MEM)); 1734 } 1735 1736 #else /* CONFIG_PCI is not enabled */ 1737 1738 static inline void pci_set_flags(int flags) { } 1739 static inline void pci_add_flags(int flags) { } 1740 static inline void pci_clear_flags(int flags) { } 1741 static inline int pci_has_flag(int flag) { return 0; } 1742 1743 /* 1744 * If the system does not have PCI, clearly these return errors. Define 1745 * these as simple inline functions to avoid hair in drivers. 1746 */ 1747 #define _PCI_NOP(o, s, t) \ 1748 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1749 int where, t val) \ 1750 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1751 1752 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1753 _PCI_NOP(o, word, u16 x) \ 1754 _PCI_NOP(o, dword, u32 x) 1755 _PCI_NOP_ALL(read, *) 1756 _PCI_NOP_ALL(write,) 1757 1758 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1759 unsigned int device, 1760 struct pci_dev *from) 1761 { return NULL; } 1762 1763 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1764 unsigned int device, 1765 unsigned int ss_vendor, 1766 unsigned int ss_device, 1767 struct pci_dev *from) 1768 { return NULL; } 1769 1770 static inline struct pci_dev *pci_get_class(unsigned int class, 1771 struct pci_dev *from) 1772 { return NULL; } 1773 1774 #define pci_dev_present(ids) (0) 1775 #define no_pci_devices() (1) 1776 #define pci_dev_put(dev) do { } while (0) 1777 1778 static inline void pci_set_master(struct pci_dev *dev) { } 1779 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1780 static inline void pci_disable_device(struct pci_dev *dev) { } 1781 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1782 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1783 { return -EBUSY; } 1784 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 1785 struct module *owner, 1786 const char *mod_name) 1787 { return 0; } 1788 static inline int pci_register_driver(struct pci_driver *drv) 1789 { return 0; } 1790 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1791 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1792 { return 0; } 1793 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1794 int cap) 1795 { return 0; } 1796 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1797 { return 0; } 1798 1799 static inline u64 pci_get_dsn(struct pci_dev *dev) 1800 { return 0; } 1801 1802 /* Power management related routines */ 1803 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1804 static inline void pci_restore_state(struct pci_dev *dev) { } 1805 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1806 { return 0; } 1807 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1808 { return 0; } 1809 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1810 pm_message_t state) 1811 { return PCI_D0; } 1812 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1813 int enable) 1814 { return 0; } 1815 1816 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1817 struct resource *res) 1818 { return NULL; } 1819 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1820 { return -EIO; } 1821 static inline void pci_release_regions(struct pci_dev *dev) { } 1822 1823 static inline int pci_register_io_range(struct fwnode_handle *fwnode, 1824 phys_addr_t addr, resource_size_t size) 1825 { return -EINVAL; } 1826 1827 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1828 1829 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1830 { return NULL; } 1831 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1832 unsigned int devfn) 1833 { return NULL; } 1834 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1835 unsigned int bus, unsigned int devfn) 1836 { return NULL; } 1837 1838 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1839 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1840 1841 #define dev_is_pci(d) (false) 1842 #define dev_is_pf(d) (false) 1843 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1844 { return false; } 1845 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1846 struct device_node *node, 1847 const u32 *intspec, 1848 unsigned int intsize, 1849 unsigned long *out_hwirq, 1850 unsigned int *out_type) 1851 { return -EINVAL; } 1852 1853 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1854 struct pci_dev *dev) 1855 { return NULL; } 1856 static inline bool pci_ats_disabled(void) { return true; } 1857 1858 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1859 { 1860 return -EINVAL; 1861 } 1862 1863 static inline int 1864 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1865 unsigned int max_vecs, unsigned int flags, 1866 struct irq_affinity *aff_desc) 1867 { 1868 return -ENOSPC; 1869 } 1870 #endif /* CONFIG_PCI */ 1871 1872 static inline int 1873 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1874 unsigned int max_vecs, unsigned int flags) 1875 { 1876 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1877 NULL); 1878 } 1879 1880 /* Include architecture-dependent settings and functions */ 1881 1882 #include <asm/pci.h> 1883 1884 /* These two functions provide almost identical functionality. Depending 1885 * on the architecture, one will be implemented as a wrapper around the 1886 * other (in drivers/pci/mmap.c). 1887 * 1888 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1889 * is expected to be an offset within that region. 1890 * 1891 * pci_mmap_page_range() is the legacy architecture-specific interface, 1892 * which accepts a "user visible" resource address converted by 1893 * pci_resource_to_user(), as used in the legacy mmap() interface in 1894 * /proc/bus/pci/. 1895 */ 1896 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1897 struct vm_area_struct *vma, 1898 enum pci_mmap_state mmap_state, int write_combine); 1899 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1900 struct vm_area_struct *vma, 1901 enum pci_mmap_state mmap_state, int write_combine); 1902 1903 #ifndef arch_can_pci_mmap_wc 1904 #define arch_can_pci_mmap_wc() 0 1905 #endif 1906 1907 #ifndef arch_can_pci_mmap_io 1908 #define arch_can_pci_mmap_io() 0 1909 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1910 #else 1911 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1912 #endif 1913 1914 #ifndef pci_root_bus_fwnode 1915 #define pci_root_bus_fwnode(bus) NULL 1916 #endif 1917 1918 /* 1919 * These helpers provide future and backwards compatibility 1920 * for accessing popular PCI BAR info 1921 */ 1922 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1923 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1924 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1925 #define pci_resource_len(dev,bar) \ 1926 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \ 1927 \ 1928 (pci_resource_end((dev), (bar)) - \ 1929 pci_resource_start((dev), (bar)) + 1)) 1930 1931 /* 1932 * Similar to the helpers above, these manipulate per-pci_dev 1933 * driver-specific data. They are really just a wrapper around 1934 * the generic device structure functions of these calls. 1935 */ 1936 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1937 { 1938 return dev_get_drvdata(&pdev->dev); 1939 } 1940 1941 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1942 { 1943 dev_set_drvdata(&pdev->dev, data); 1944 } 1945 1946 static inline const char *pci_name(const struct pci_dev *pdev) 1947 { 1948 return dev_name(&pdev->dev); 1949 } 1950 1951 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1952 const struct resource *rsrc, 1953 resource_size_t *start, resource_size_t *end); 1954 1955 /* 1956 * The world is not perfect and supplies us with broken PCI devices. 1957 * For at least a part of these bugs we need a work-around, so both 1958 * generic (drivers/pci/quirks.c) and per-architecture code can define 1959 * fixup hooks to be called for particular buggy devices. 1960 */ 1961 1962 struct pci_fixup { 1963 u16 vendor; /* Or PCI_ANY_ID */ 1964 u16 device; /* Or PCI_ANY_ID */ 1965 u32 class; /* Or PCI_ANY_ID */ 1966 unsigned int class_shift; /* should be 0, 8, 16 */ 1967 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1968 int hook_offset; 1969 #else 1970 void (*hook)(struct pci_dev *dev); 1971 #endif 1972 }; 1973 1974 enum pci_fixup_pass { 1975 pci_fixup_early, /* Before probing BARs */ 1976 pci_fixup_header, /* After reading configuration header */ 1977 pci_fixup_final, /* Final phase of device fixups */ 1978 pci_fixup_enable, /* pci_enable_device() time */ 1979 pci_fixup_resume, /* pci_device_resume() */ 1980 pci_fixup_suspend, /* pci_device_suspend() */ 1981 pci_fixup_resume_early, /* pci_device_resume_early() */ 1982 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1983 }; 1984 1985 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1986 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1987 class_shift, hook) \ 1988 __ADDRESSABLE(hook) \ 1989 asm(".section " #sec ", \"a\" \n" \ 1990 ".balign 16 \n" \ 1991 ".short " #vendor ", " #device " \n" \ 1992 ".long " #class ", " #class_shift " \n" \ 1993 ".long " #hook " - . \n" \ 1994 ".previous \n"); 1995 1996 /* 1997 * Clang's LTO may rename static functions in C, but has no way to 1998 * handle such renamings when referenced from inline asm. To work 1999 * around this, create global C stubs for these cases. 2000 */ 2001 #ifdef CONFIG_LTO_CLANG 2002 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2003 class_shift, hook, stub) \ 2004 void __cficanonical stub(struct pci_dev *dev); \ 2005 void __cficanonical stub(struct pci_dev *dev) \ 2006 { \ 2007 hook(dev); \ 2008 } \ 2009 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2010 class_shift, stub) 2011 #else 2012 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2013 class_shift, hook, stub) \ 2014 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2015 class_shift, hook) 2016 #endif 2017 2018 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2019 class_shift, hook) \ 2020 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2021 class_shift, hook, __UNIQUE_ID(hook)) 2022 #else 2023 /* Anonymous variables would be nice... */ 2024 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2025 class_shift, hook) \ 2026 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2027 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2028 = { vendor, device, class, class_shift, hook }; 2029 #endif 2030 2031 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2032 class_shift, hook) \ 2033 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2034 hook, vendor, device, class, class_shift, hook) 2035 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2036 class_shift, hook) \ 2037 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2038 hook, vendor, device, class, class_shift, hook) 2039 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2040 class_shift, hook) \ 2041 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2042 hook, vendor, device, class, class_shift, hook) 2043 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2044 class_shift, hook) \ 2045 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2046 hook, vendor, device, class, class_shift, hook) 2047 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2048 class_shift, hook) \ 2049 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2050 resume##hook, vendor, device, class, class_shift, hook) 2051 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2052 class_shift, hook) \ 2053 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2054 resume_early##hook, vendor, device, class, class_shift, hook) 2055 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2056 class_shift, hook) \ 2057 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2058 suspend##hook, vendor, device, class, class_shift, hook) 2059 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2060 class_shift, hook) \ 2061 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2062 suspend_late##hook, vendor, device, class, class_shift, hook) 2063 2064 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2065 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2066 hook, vendor, device, PCI_ANY_ID, 0, hook) 2067 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2068 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2069 hook, vendor, device, PCI_ANY_ID, 0, hook) 2070 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2071 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2072 hook, vendor, device, PCI_ANY_ID, 0, hook) 2073 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2074 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2075 hook, vendor, device, PCI_ANY_ID, 0, hook) 2076 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2078 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2079 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2080 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2081 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2082 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2083 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2084 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2085 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2086 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2087 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2088 2089 #ifdef CONFIG_PCI_QUIRKS 2090 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2091 #else 2092 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2093 struct pci_dev *dev) { } 2094 #endif 2095 2096 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2097 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2098 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2099 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2100 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2101 const char *name); 2102 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2103 2104 extern int pci_pci_problems; 2105 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2106 #define PCIPCI_TRITON 2 2107 #define PCIPCI_NATOMA 4 2108 #define PCIPCI_VIAETBF 8 2109 #define PCIPCI_VSFX 16 2110 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2111 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2112 2113 extern unsigned long pci_cardbus_io_size; 2114 extern unsigned long pci_cardbus_mem_size; 2115 extern u8 pci_dfl_cache_line_size; 2116 extern u8 pci_cache_line_size; 2117 2118 /* Architecture-specific versions may override these (weak) */ 2119 void pcibios_disable_device(struct pci_dev *dev); 2120 void pcibios_set_master(struct pci_dev *dev); 2121 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2122 enum pcie_reset_state state); 2123 int pcibios_device_add(struct pci_dev *dev); 2124 void pcibios_release_device(struct pci_dev *dev); 2125 #ifdef CONFIG_PCI 2126 void pcibios_penalize_isa_irq(int irq, int active); 2127 #else 2128 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2129 #endif 2130 int pcibios_alloc_irq(struct pci_dev *dev); 2131 void pcibios_free_irq(struct pci_dev *dev); 2132 resource_size_t pcibios_default_alignment(void); 2133 2134 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2135 void __init pci_mmcfg_early_init(void); 2136 void __init pci_mmcfg_late_init(void); 2137 #else 2138 static inline void pci_mmcfg_early_init(void) { } 2139 static inline void pci_mmcfg_late_init(void) { } 2140 #endif 2141 2142 int pci_ext_cfg_avail(void); 2143 2144 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2145 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2146 2147 #ifdef CONFIG_PCI_IOV 2148 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2149 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2150 2151 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2152 void pci_disable_sriov(struct pci_dev *dev); 2153 2154 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2155 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2156 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2157 int pci_num_vf(struct pci_dev *dev); 2158 int pci_vfs_assigned(struct pci_dev *dev); 2159 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2160 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2161 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2162 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2163 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2164 2165 /* Arch may override these (weak) */ 2166 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2167 int pcibios_sriov_disable(struct pci_dev *pdev); 2168 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2169 #else 2170 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2171 { 2172 return -ENOSYS; 2173 } 2174 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2175 { 2176 return -ENOSYS; 2177 } 2178 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2179 { return -ENODEV; } 2180 2181 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2182 struct pci_dev *virtfn, int id) 2183 { 2184 return -ENODEV; 2185 } 2186 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2187 { 2188 return -ENOSYS; 2189 } 2190 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2191 int id) { } 2192 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2193 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2194 static inline int pci_vfs_assigned(struct pci_dev *dev) 2195 { return 0; } 2196 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2197 { return 0; } 2198 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2199 { return 0; } 2200 #define pci_sriov_configure_simple NULL 2201 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2202 { return 0; } 2203 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2204 #endif 2205 2206 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2207 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2208 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2209 #endif 2210 2211 /** 2212 * pci_pcie_cap - get the saved PCIe capability offset 2213 * @dev: PCI device 2214 * 2215 * PCIe capability offset is calculated at PCI device initialization 2216 * time and saved in the data structure. This function returns saved 2217 * PCIe capability offset. Using this instead of pci_find_capability() 2218 * reduces unnecessary search in the PCI configuration space. If you 2219 * need to calculate PCIe capability offset from raw device for some 2220 * reasons, please use pci_find_capability() instead. 2221 */ 2222 static inline int pci_pcie_cap(struct pci_dev *dev) 2223 { 2224 return dev->pcie_cap; 2225 } 2226 2227 /** 2228 * pci_is_pcie - check if the PCI device is PCI Express capable 2229 * @dev: PCI device 2230 * 2231 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2232 */ 2233 static inline bool pci_is_pcie(struct pci_dev *dev) 2234 { 2235 return pci_pcie_cap(dev); 2236 } 2237 2238 /** 2239 * pcie_caps_reg - get the PCIe Capabilities Register 2240 * @dev: PCI device 2241 */ 2242 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2243 { 2244 return dev->pcie_flags_reg; 2245 } 2246 2247 /** 2248 * pci_pcie_type - get the PCIe device/port type 2249 * @dev: PCI device 2250 */ 2251 static inline int pci_pcie_type(const struct pci_dev *dev) 2252 { 2253 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2254 } 2255 2256 /** 2257 * pcie_find_root_port - Get the PCIe root port device 2258 * @dev: PCI device 2259 * 2260 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2261 * for a given PCI/PCIe Device. 2262 */ 2263 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2264 { 2265 while (dev) { 2266 if (pci_is_pcie(dev) && 2267 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2268 return dev; 2269 dev = pci_upstream_bridge(dev); 2270 } 2271 2272 return NULL; 2273 } 2274 2275 void pci_request_acs(void); 2276 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2277 bool pci_acs_path_enabled(struct pci_dev *start, 2278 struct pci_dev *end, u16 acs_flags); 2279 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2280 2281 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2282 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2283 2284 /* Large Resource Data Type Tag Item Names */ 2285 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2286 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2287 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2288 2289 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2290 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2291 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2292 2293 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2294 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2295 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2296 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2297 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2298 2299 /** 2300 * pci_vpd_alloc - Allocate buffer and read VPD into it 2301 * @dev: PCI device 2302 * @size: pointer to field where VPD length is returned 2303 * 2304 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2305 */ 2306 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2307 2308 /** 2309 * pci_vpd_find_id_string - Locate id string in VPD 2310 * @buf: Pointer to buffered VPD data 2311 * @len: The length of the buffer area in which to search 2312 * @size: Pointer to field where length of id string is returned 2313 * 2314 * Returns the index of the id string or -ENOENT if not found. 2315 */ 2316 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2317 2318 /** 2319 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2320 * @buf: Pointer to buffered VPD data 2321 * @len: The length of the buffer area in which to search 2322 * @kw: The keyword to search for 2323 * @size: Pointer to field where length of found keyword data is returned 2324 * 2325 * Returns the index of the information field keyword data or -ENOENT if 2326 * not found. 2327 */ 2328 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2329 const char *kw, unsigned int *size); 2330 2331 /** 2332 * pci_vpd_check_csum - Check VPD checksum 2333 * @buf: Pointer to buffered VPD data 2334 * @len: VPD size 2335 * 2336 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2337 */ 2338 int pci_vpd_check_csum(const void *buf, unsigned int len); 2339 2340 /* PCI <-> OF binding helpers */ 2341 #ifdef CONFIG_OF 2342 struct device_node; 2343 struct irq_domain; 2344 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2345 bool pci_host_of_has_msi_map(struct device *dev); 2346 2347 /* Arch may override this (weak) */ 2348 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2349 2350 #else /* CONFIG_OF */ 2351 static inline struct irq_domain * 2352 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2353 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2354 #endif /* CONFIG_OF */ 2355 2356 static inline struct device_node * 2357 pci_device_to_OF_node(const struct pci_dev *pdev) 2358 { 2359 return pdev ? pdev->dev.of_node : NULL; 2360 } 2361 2362 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2363 { 2364 return bus ? bus->dev.of_node : NULL; 2365 } 2366 2367 #ifdef CONFIG_ACPI 2368 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2369 2370 void 2371 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2372 bool pci_pr3_present(struct pci_dev *pdev); 2373 #else 2374 static inline struct irq_domain * 2375 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2376 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2377 #endif 2378 2379 #ifdef CONFIG_EEH 2380 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2381 { 2382 return pdev->dev.archdata.edev; 2383 } 2384 #endif 2385 2386 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2387 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2388 int pci_for_each_dma_alias(struct pci_dev *pdev, 2389 int (*fn)(struct pci_dev *pdev, 2390 u16 alias, void *data), void *data); 2391 2392 /* Helper functions for operation of device flag */ 2393 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2394 { 2395 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2396 } 2397 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2398 { 2399 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2400 } 2401 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2402 { 2403 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2404 } 2405 2406 /** 2407 * pci_ari_enabled - query ARI forwarding status 2408 * @bus: the PCI bus 2409 * 2410 * Returns true if ARI forwarding is enabled. 2411 */ 2412 static inline bool pci_ari_enabled(struct pci_bus *bus) 2413 { 2414 return bus->self && bus->self->ari_enabled; 2415 } 2416 2417 /** 2418 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2419 * @pdev: PCI device to check 2420 * 2421 * Walk upwards from @pdev and check for each encountered bridge if it's part 2422 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2423 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2424 */ 2425 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2426 { 2427 struct pci_dev *parent = pdev; 2428 2429 if (pdev->is_thunderbolt) 2430 return true; 2431 2432 while ((parent = pci_upstream_bridge(parent))) 2433 if (parent->is_thunderbolt) 2434 return true; 2435 2436 return false; 2437 } 2438 2439 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2440 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2441 #endif 2442 2443 /* Provide the legacy pci_dma_* API */ 2444 #include <linux/pci-dma-compat.h> 2445 2446 #define pci_printk(level, pdev, fmt, arg...) \ 2447 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2448 2449 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2450 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2451 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2452 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2453 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2454 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2455 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2456 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2457 2458 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2459 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2460 2461 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2462 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2463 2464 #define pci_WARN(pdev, condition, fmt, arg...) \ 2465 WARN(condition, "%s %s: " fmt, \ 2466 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2467 2468 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2469 WARN_ONCE(condition, "%s %s: " fmt, \ 2470 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2471 2472 #endif /* LINUX_PCI_H */ 2473