1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <linux/resource_ext.h> 33 #include <uapi/linux/pci.h> 34 35 #include <linux/pci_ids.h> 36 37 /* 38 * The PCI interface treats multi-function devices as independent 39 * devices. The slot/function address of each device is encoded 40 * in a single byte as follows: 41 * 42 * 7:3 = slot 43 * 2:0 = function 44 * 45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 46 * In the interest of not exposing interfaces to user-space unnecessarily, 47 * the following kernel-only defines are being added here. 48 */ 49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 52 53 /* pci_slot represents a physical slot */ 54 struct pci_slot { 55 struct pci_bus *bus; /* The bus this slot is on */ 56 struct list_head list; /* node in list of slots on this bus */ 57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 59 struct kobject kobj; 60 }; 61 62 static inline const char *pci_slot_name(const struct pci_slot *slot) 63 { 64 return kobject_name(&slot->kobj); 65 } 66 67 /* File state for mmap()s on /proc/bus/pci/X/Y */ 68 enum pci_mmap_state { 69 pci_mmap_io, 70 pci_mmap_mem 71 }; 72 73 /* This defines the direction arg to the DMA mapping routines. */ 74 #define PCI_DMA_BIDIRECTIONAL 0 75 #define PCI_DMA_TODEVICE 1 76 #define PCI_DMA_FROMDEVICE 2 77 #define PCI_DMA_NONE 3 78 79 /* 80 * For PCI devices, the region numbers are assigned this way: 81 */ 82 enum { 83 /* #0-5: standard PCI resources */ 84 PCI_STD_RESOURCES, 85 PCI_STD_RESOURCE_END = 5, 86 87 /* #6: expansion ROM resource */ 88 PCI_ROM_RESOURCE, 89 90 /* device specific resources */ 91 #ifdef CONFIG_PCI_IOV 92 PCI_IOV_RESOURCES, 93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 94 #endif 95 96 /* resources assigned to buses behind the bridge */ 97 #define PCI_BRIDGE_RESOURCE_NUM 4 98 99 PCI_BRIDGE_RESOURCES, 100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 101 PCI_BRIDGE_RESOURCE_NUM - 1, 102 103 /* total resources associated with a PCI device */ 104 PCI_NUM_RESOURCES, 105 106 /* preserve this for compatibility */ 107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 108 }; 109 110 typedef int __bitwise pci_power_t; 111 112 #define PCI_D0 ((pci_power_t __force) 0) 113 #define PCI_D1 ((pci_power_t __force) 1) 114 #define PCI_D2 ((pci_power_t __force) 2) 115 #define PCI_D3hot ((pci_power_t __force) 3) 116 #define PCI_D3cold ((pci_power_t __force) 4) 117 #define PCI_UNKNOWN ((pci_power_t __force) 5) 118 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 119 120 /* Remember to update this when the list above changes! */ 121 extern const char *pci_power_names[]; 122 123 static inline const char *pci_power_name(pci_power_t state) 124 { 125 return pci_power_names[1 + (int) state]; 126 } 127 128 #define PCI_PM_D2_DELAY 200 129 #define PCI_PM_D3_WAIT 10 130 #define PCI_PM_D3COLD_WAIT 100 131 #define PCI_PM_BUS_WAIT 50 132 133 /** The pci_channel state describes connectivity between the CPU and 134 * the pci device. If some PCI bus between here and the pci device 135 * has crashed or locked up, this info is reflected here. 136 */ 137 typedef unsigned int __bitwise pci_channel_state_t; 138 139 enum pci_channel_state { 140 /* I/O channel is in normal state */ 141 pci_channel_io_normal = (__force pci_channel_state_t) 1, 142 143 /* I/O to channel is blocked */ 144 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 145 146 /* PCI card is dead */ 147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 148 }; 149 150 typedef unsigned int __bitwise pcie_reset_state_t; 151 152 enum pcie_reset_state { 153 /* Reset is NOT asserted (Use to deassert reset) */ 154 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 155 156 /* Use #PERST to reset PCIe device */ 157 pcie_warm_reset = (__force pcie_reset_state_t) 2, 158 159 /* Use PCIe Hot Reset to reset device */ 160 pcie_hot_reset = (__force pcie_reset_state_t) 3 161 }; 162 163 typedef unsigned short __bitwise pci_dev_flags_t; 164 enum pci_dev_flags { 165 /* INTX_DISABLE in PCI_COMMAND register disables MSI 166 * generation too. 167 */ 168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 169 /* Device configuration is irrevocably lost if disabled into D3 */ 170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 171 /* Provide indication device is assigned by a Virtual Machine Manager */ 172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 173 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 175 /* Flag to indicate the device uses dma_alias_devfn */ 176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), 177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 179 /* Do not use bus resets for device */ 180 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 181 /* Do not use PM reset even if device advertises NoSoftRst- */ 182 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 183 /* Get VPD from function 0 VPD */ 184 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 185 }; 186 187 enum pci_irq_reroute_variant { 188 INTEL_IRQ_REROUTE_VARIANT = 1, 189 MAX_IRQ_REROUTE_VARIANTS = 3 190 }; 191 192 typedef unsigned short __bitwise pci_bus_flags_t; 193 enum pci_bus_flags { 194 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 195 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 196 }; 197 198 /* These values come from the PCI Express Spec */ 199 enum pcie_link_width { 200 PCIE_LNK_WIDTH_RESRV = 0x00, 201 PCIE_LNK_X1 = 0x01, 202 PCIE_LNK_X2 = 0x02, 203 PCIE_LNK_X4 = 0x04, 204 PCIE_LNK_X8 = 0x08, 205 PCIE_LNK_X12 = 0x0C, 206 PCIE_LNK_X16 = 0x10, 207 PCIE_LNK_X32 = 0x20, 208 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 209 }; 210 211 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 212 enum pci_bus_speed { 213 PCI_SPEED_33MHz = 0x00, 214 PCI_SPEED_66MHz = 0x01, 215 PCI_SPEED_66MHz_PCIX = 0x02, 216 PCI_SPEED_100MHz_PCIX = 0x03, 217 PCI_SPEED_133MHz_PCIX = 0x04, 218 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 219 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 220 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 221 PCI_SPEED_66MHz_PCIX_266 = 0x09, 222 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 223 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 224 AGP_UNKNOWN = 0x0c, 225 AGP_1X = 0x0d, 226 AGP_2X = 0x0e, 227 AGP_4X = 0x0f, 228 AGP_8X = 0x10, 229 PCI_SPEED_66MHz_PCIX_533 = 0x11, 230 PCI_SPEED_100MHz_PCIX_533 = 0x12, 231 PCI_SPEED_133MHz_PCIX_533 = 0x13, 232 PCIE_SPEED_2_5GT = 0x14, 233 PCIE_SPEED_5_0GT = 0x15, 234 PCIE_SPEED_8_0GT = 0x16, 235 PCI_SPEED_UNKNOWN = 0xff, 236 }; 237 238 struct pci_cap_saved_data { 239 u16 cap_nr; 240 bool cap_extended; 241 unsigned int size; 242 u32 data[0]; 243 }; 244 245 struct pci_cap_saved_state { 246 struct hlist_node next; 247 struct pci_cap_saved_data cap; 248 }; 249 250 struct pcie_link_state; 251 struct pci_vpd; 252 struct pci_sriov; 253 struct pci_ats; 254 255 /* 256 * The pci_dev structure is used to describe PCI devices. 257 */ 258 struct pci_dev { 259 struct list_head bus_list; /* node in per-bus list */ 260 struct pci_bus *bus; /* bus this device is on */ 261 struct pci_bus *subordinate; /* bus this device bridges to */ 262 263 void *sysdata; /* hook for sys-specific extension */ 264 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 265 struct pci_slot *slot; /* Physical slot this device is in */ 266 267 unsigned int devfn; /* encoded device & function index */ 268 unsigned short vendor; 269 unsigned short device; 270 unsigned short subsystem_vendor; 271 unsigned short subsystem_device; 272 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 273 u8 revision; /* PCI revision, low byte of class word */ 274 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 275 u8 pcie_cap; /* PCIe capability offset */ 276 u8 msi_cap; /* MSI capability offset */ 277 u8 msix_cap; /* MSI-X capability offset */ 278 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 279 u8 rom_base_reg; /* which config register controls the ROM */ 280 u8 pin; /* which interrupt pin this device uses */ 281 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 282 u8 dma_alias_devfn;/* devfn of DMA alias, if any */ 283 284 struct pci_driver *driver; /* which driver has allocated this device */ 285 u64 dma_mask; /* Mask of the bits of bus address this 286 device implements. Normally this is 287 0xffffffff. You only need to change 288 this if your device has broken DMA 289 or supports 64-bit transfers. */ 290 291 struct device_dma_parameters dma_parms; 292 293 pci_power_t current_state; /* Current operating state. In ACPI-speak, 294 this is D0-D3, D0 being fully functional, 295 and D3 being off. */ 296 u8 pm_cap; /* PM capability offset */ 297 unsigned int pme_support:5; /* Bitmask of states from which PME# 298 can be generated */ 299 unsigned int pme_interrupt:1; 300 unsigned int pme_poll:1; /* Poll device's PME status bit */ 301 unsigned int d1_support:1; /* Low power state D1 is supported */ 302 unsigned int d2_support:1; /* Low power state D2 is supported */ 303 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 304 unsigned int no_d3cold:1; /* D3cold is forbidden */ 305 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 306 unsigned int mmio_always_on:1; /* disallow turning off io/mem 307 decoding during bar sizing */ 308 unsigned int wakeup_prepared:1; 309 unsigned int runtime_d3cold:1; /* whether go through runtime 310 D3cold, not set for devices 311 powered on/off by the 312 corresponding bridge */ 313 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 314 unsigned int d3_delay; /* D3->D0 transition time in ms */ 315 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 316 317 #ifdef CONFIG_PCIEASPM 318 struct pcie_link_state *link_state; /* ASPM link state */ 319 #endif 320 321 pci_channel_state_t error_state; /* current connectivity state */ 322 struct device dev; /* Generic device interface */ 323 324 int cfg_size; /* Size of configuration space */ 325 326 /* 327 * Instead of touching interrupt line and base address registers 328 * directly, use the values stored here. They might be different! 329 */ 330 unsigned int irq; 331 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 332 333 bool match_driver; /* Skip attaching driver */ 334 /* These fields are used by common fixups */ 335 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 336 unsigned int multifunction:1;/* Part of multi-function device */ 337 /* keep track of device state */ 338 unsigned int is_added:1; 339 unsigned int is_busmaster:1; /* device is busmaster */ 340 unsigned int no_msi:1; /* device may not use msi */ 341 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 342 unsigned int block_cfg_access:1; /* config space access is blocked */ 343 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 344 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 345 unsigned int msi_enabled:1; 346 unsigned int msix_enabled:1; 347 unsigned int ari_enabled:1; /* ARI forwarding */ 348 unsigned int ats_enabled:1; /* Address Translation Service */ 349 unsigned int is_managed:1; 350 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 351 unsigned int state_saved:1; 352 unsigned int is_physfn:1; 353 unsigned int is_virtfn:1; 354 unsigned int reset_fn:1; 355 unsigned int is_hotplug_bridge:1; 356 unsigned int __aer_firmware_first_valid:1; 357 unsigned int __aer_firmware_first:1; 358 unsigned int broken_intx_masking:1; 359 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 360 unsigned int irq_managed:1; 361 unsigned int has_secondary_link:1; 362 pci_dev_flags_t dev_flags; 363 atomic_t enable_cnt; /* pci_enable_device has been called */ 364 365 u32 saved_config_space[16]; /* config space saved at suspend time */ 366 struct hlist_head saved_cap_space; 367 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 368 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 369 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 370 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 371 #ifdef CONFIG_PCI_MSI 372 struct list_head msi_list; 373 const struct attribute_group **msi_irq_groups; 374 #endif 375 struct pci_vpd *vpd; 376 #ifdef CONFIG_PCI_ATS 377 union { 378 struct pci_sriov *sriov; /* SR-IOV capability related */ 379 struct pci_dev *physfn; /* the PF this VF is associated with */ 380 }; 381 u16 ats_cap; /* ATS Capability offset */ 382 u8 ats_stu; /* ATS Smallest Translation Unit */ 383 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 384 #endif 385 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 386 size_t romlen; /* Length of ROM if it's not from the BAR */ 387 char *driver_override; /* Driver name to force a match */ 388 }; 389 390 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 391 { 392 #ifdef CONFIG_PCI_IOV 393 if (dev->is_virtfn) 394 dev = dev->physfn; 395 #endif 396 return dev; 397 } 398 399 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 400 401 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 402 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 403 404 static inline int pci_channel_offline(struct pci_dev *pdev) 405 { 406 return (pdev->error_state != pci_channel_io_normal); 407 } 408 409 struct pci_host_bridge { 410 struct device dev; 411 struct pci_bus *bus; /* root bus */ 412 struct list_head windows; /* resource_entry */ 413 void (*release_fn)(struct pci_host_bridge *); 414 void *release_data; 415 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 416 }; 417 418 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 419 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 420 void (*release_fn)(struct pci_host_bridge *), 421 void *release_data); 422 423 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 424 425 /* 426 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 427 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 428 * buses below host bridges or subtractive decode bridges) go in the list. 429 * Use pci_bus_for_each_resource() to iterate through all the resources. 430 */ 431 432 /* 433 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 434 * and there's no way to program the bridge with the details of the window. 435 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 436 * decode bit set, because they are explicit and can be programmed with _SRS. 437 */ 438 #define PCI_SUBTRACTIVE_DECODE 0x1 439 440 struct pci_bus_resource { 441 struct list_head list; 442 struct resource *res; 443 unsigned int flags; 444 }; 445 446 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 447 448 struct pci_bus { 449 struct list_head node; /* node in list of buses */ 450 struct pci_bus *parent; /* parent bus this bridge is on */ 451 struct list_head children; /* list of child buses */ 452 struct list_head devices; /* list of devices on this bus */ 453 struct pci_dev *self; /* bridge device as seen by parent */ 454 struct list_head slots; /* list of slots on this bus; 455 protected by pci_slot_mutex */ 456 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 457 struct list_head resources; /* address space routed to this bus */ 458 struct resource busn_res; /* bus numbers routed to this bus */ 459 460 struct pci_ops *ops; /* configuration access functions */ 461 struct msi_controller *msi; /* MSI controller */ 462 void *sysdata; /* hook for sys-specific extension */ 463 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 464 465 unsigned char number; /* bus number */ 466 unsigned char primary; /* number of primary bridge */ 467 unsigned char max_bus_speed; /* enum pci_bus_speed */ 468 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 469 #ifdef CONFIG_PCI_DOMAINS_GENERIC 470 int domain_nr; 471 #endif 472 473 char name[48]; 474 475 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 476 pci_bus_flags_t bus_flags; /* inherited by child buses */ 477 struct device *bridge; 478 struct device dev; 479 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 480 struct bin_attribute *legacy_mem; /* legacy mem */ 481 unsigned int is_added:1; 482 }; 483 484 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 485 486 /* 487 * Returns true if the PCI bus is root (behind host-PCI bridge), 488 * false otherwise 489 * 490 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 491 * This is incorrect because "virtual" buses added for SR-IOV (via 492 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 493 */ 494 static inline bool pci_is_root_bus(struct pci_bus *pbus) 495 { 496 return !(pbus->parent); 497 } 498 499 /** 500 * pci_is_bridge - check if the PCI device is a bridge 501 * @dev: PCI device 502 * 503 * Return true if the PCI device is bridge whether it has subordinate 504 * or not. 505 */ 506 static inline bool pci_is_bridge(struct pci_dev *dev) 507 { 508 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 509 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 510 } 511 512 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 513 { 514 dev = pci_physfn(dev); 515 if (pci_is_root_bus(dev->bus)) 516 return NULL; 517 518 return dev->bus->self; 519 } 520 521 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 522 void pci_put_host_bridge_device(struct device *dev); 523 524 #ifdef CONFIG_PCI_MSI 525 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 526 { 527 return pci_dev->msi_enabled || pci_dev->msix_enabled; 528 } 529 #else 530 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 531 #endif 532 533 /* 534 * Error values that may be returned by PCI functions. 535 */ 536 #define PCIBIOS_SUCCESSFUL 0x00 537 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 538 #define PCIBIOS_BAD_VENDOR_ID 0x83 539 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 540 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 541 #define PCIBIOS_SET_FAILED 0x88 542 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 543 544 /* 545 * Translate above to generic errno for passing back through non-PCI code. 546 */ 547 static inline int pcibios_err_to_errno(int err) 548 { 549 if (err <= PCIBIOS_SUCCESSFUL) 550 return err; /* Assume already errno */ 551 552 switch (err) { 553 case PCIBIOS_FUNC_NOT_SUPPORTED: 554 return -ENOENT; 555 case PCIBIOS_BAD_VENDOR_ID: 556 return -ENOTTY; 557 case PCIBIOS_DEVICE_NOT_FOUND: 558 return -ENODEV; 559 case PCIBIOS_BAD_REGISTER_NUMBER: 560 return -EFAULT; 561 case PCIBIOS_SET_FAILED: 562 return -EIO; 563 case PCIBIOS_BUFFER_TOO_SMALL: 564 return -ENOSPC; 565 } 566 567 return -ERANGE; 568 } 569 570 /* Low-level architecture-dependent routines */ 571 572 struct pci_ops { 573 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 574 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 575 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 576 }; 577 578 /* 579 * ACPI needs to be able to access PCI config space before we've done a 580 * PCI bus scan and created pci_bus structures. 581 */ 582 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 583 int reg, int len, u32 *val); 584 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 585 int reg, int len, u32 val); 586 587 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 588 typedef u64 pci_bus_addr_t; 589 #else 590 typedef u32 pci_bus_addr_t; 591 #endif 592 593 struct pci_bus_region { 594 pci_bus_addr_t start; 595 pci_bus_addr_t end; 596 }; 597 598 struct pci_dynids { 599 spinlock_t lock; /* protects list, index */ 600 struct list_head list; /* for IDs added at runtime */ 601 }; 602 603 604 /* 605 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 606 * a set of callbacks in struct pci_error_handlers, that device driver 607 * will be notified of PCI bus errors, and will be driven to recovery 608 * when an error occurs. 609 */ 610 611 typedef unsigned int __bitwise pci_ers_result_t; 612 613 enum pci_ers_result { 614 /* no result/none/not supported in device driver */ 615 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 616 617 /* Device driver can recover without slot reset */ 618 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 619 620 /* Device driver wants slot to be reset. */ 621 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 622 623 /* Device has completely failed, is unrecoverable */ 624 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 625 626 /* Device driver is fully recovered and operational */ 627 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 628 629 /* No AER capabilities registered for the driver */ 630 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 631 }; 632 633 /* PCI bus error event callbacks */ 634 struct pci_error_handlers { 635 /* PCI bus error detected on this device */ 636 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 637 enum pci_channel_state error); 638 639 /* MMIO has been re-enabled, but not DMA */ 640 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 641 642 /* PCI Express link has been reset */ 643 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 644 645 /* PCI slot has been reset */ 646 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 647 648 /* PCI function reset prepare or completed */ 649 void (*reset_notify)(struct pci_dev *dev, bool prepare); 650 651 /* Device driver may resume normal operations */ 652 void (*resume)(struct pci_dev *dev); 653 }; 654 655 656 struct module; 657 struct pci_driver { 658 struct list_head node; 659 const char *name; 660 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 661 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 662 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 663 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 664 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 665 int (*resume_early) (struct pci_dev *dev); 666 int (*resume) (struct pci_dev *dev); /* Device woken up */ 667 void (*shutdown) (struct pci_dev *dev); 668 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 669 const struct pci_error_handlers *err_handler; 670 struct device_driver driver; 671 struct pci_dynids dynids; 672 }; 673 674 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 675 676 /** 677 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 678 * @_table: device table name 679 * 680 * This macro is deprecated and should not be used in new code. 681 */ 682 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 683 const struct pci_device_id _table[] 684 685 /** 686 * PCI_DEVICE - macro used to describe a specific pci device 687 * @vend: the 16 bit PCI Vendor ID 688 * @dev: the 16 bit PCI Device ID 689 * 690 * This macro is used to create a struct pci_device_id that matches a 691 * specific device. The subvendor and subdevice fields will be set to 692 * PCI_ANY_ID. 693 */ 694 #define PCI_DEVICE(vend,dev) \ 695 .vendor = (vend), .device = (dev), \ 696 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 697 698 /** 699 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 700 * @vend: the 16 bit PCI Vendor ID 701 * @dev: the 16 bit PCI Device ID 702 * @subvend: the 16 bit PCI Subvendor ID 703 * @subdev: the 16 bit PCI Subdevice ID 704 * 705 * This macro is used to create a struct pci_device_id that matches a 706 * specific device with subsystem information. 707 */ 708 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 709 .vendor = (vend), .device = (dev), \ 710 .subvendor = (subvend), .subdevice = (subdev) 711 712 /** 713 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 714 * @dev_class: the class, subclass, prog-if triple for this device 715 * @dev_class_mask: the class mask for this device 716 * 717 * This macro is used to create a struct pci_device_id that matches a 718 * specific PCI class. The vendor, device, subvendor, and subdevice 719 * fields will be set to PCI_ANY_ID. 720 */ 721 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 722 .class = (dev_class), .class_mask = (dev_class_mask), \ 723 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 724 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 725 726 /** 727 * PCI_VDEVICE - macro used to describe a specific pci device in short form 728 * @vend: the vendor name 729 * @dev: the 16 bit PCI Device ID 730 * 731 * This macro is used to create a struct pci_device_id that matches a 732 * specific PCI device. The subvendor, and subdevice fields will be set 733 * to PCI_ANY_ID. The macro allows the next field to follow as the device 734 * private data. 735 */ 736 737 #define PCI_VDEVICE(vend, dev) \ 738 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 739 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 740 741 /* these external functions are only available when PCI support is enabled */ 742 #ifdef CONFIG_PCI 743 744 void pcie_bus_configure_settings(struct pci_bus *bus); 745 746 enum pcie_bus_config_types { 747 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 748 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 749 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 750 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 751 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 752 }; 753 754 extern enum pcie_bus_config_types pcie_bus_config; 755 756 extern struct bus_type pci_bus_type; 757 758 /* Do NOT directly access these two variables, unless you are arch-specific PCI 759 * code, or PCI core code. */ 760 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 761 /* Some device drivers need know if PCI is initiated */ 762 int no_pci_devices(void); 763 764 void pcibios_resource_survey_bus(struct pci_bus *bus); 765 void pcibios_add_bus(struct pci_bus *bus); 766 void pcibios_remove_bus(struct pci_bus *bus); 767 void pcibios_fixup_bus(struct pci_bus *); 768 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 769 /* Architecture-specific versions may override this (weak) */ 770 char *pcibios_setup(char *str); 771 772 /* Used only when drivers/pci/setup.c is used */ 773 resource_size_t pcibios_align_resource(void *, const struct resource *, 774 resource_size_t, 775 resource_size_t); 776 void pcibios_update_irq(struct pci_dev *, int irq); 777 778 /* Weak but can be overriden by arch */ 779 void pci_fixup_cardbus(struct pci_bus *); 780 781 /* Generic PCI functions used internally */ 782 783 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 784 struct resource *res); 785 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 786 struct pci_bus_region *region); 787 void pcibios_scan_specific_bus(int busn); 788 struct pci_bus *pci_find_bus(int domain, int busnr); 789 void pci_bus_add_devices(const struct pci_bus *bus); 790 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 791 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 792 struct pci_ops *ops, void *sysdata, 793 struct list_head *resources); 794 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 795 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 796 void pci_bus_release_busn_res(struct pci_bus *b); 797 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, 798 struct pci_ops *ops, void *sysdata, 799 struct list_head *resources, 800 struct msi_controller *msi); 801 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 802 struct pci_ops *ops, void *sysdata, 803 struct list_head *resources); 804 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 805 int busnr); 806 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 807 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 808 const char *name, 809 struct hotplug_slot *hotplug); 810 void pci_destroy_slot(struct pci_slot *slot); 811 #ifdef CONFIG_SYSFS 812 void pci_dev_assign_slot(struct pci_dev *dev); 813 #else 814 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 815 #endif 816 int pci_scan_slot(struct pci_bus *bus, int devfn); 817 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 818 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 819 unsigned int pci_scan_child_bus(struct pci_bus *bus); 820 void pci_bus_add_device(struct pci_dev *dev); 821 void pci_read_bridge_bases(struct pci_bus *child); 822 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 823 struct resource *res); 824 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 825 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 826 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 827 struct pci_dev *pci_dev_get(struct pci_dev *dev); 828 void pci_dev_put(struct pci_dev *dev); 829 void pci_remove_bus(struct pci_bus *b); 830 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 831 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 832 void pci_stop_root_bus(struct pci_bus *bus); 833 void pci_remove_root_bus(struct pci_bus *bus); 834 void pci_setup_cardbus(struct pci_bus *bus); 835 void pci_sort_breadthfirst(void); 836 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 837 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 838 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 839 840 /* Generic PCI functions exported to card drivers */ 841 842 enum pci_lost_interrupt_reason { 843 PCI_LOST_IRQ_NO_INFORMATION = 0, 844 PCI_LOST_IRQ_DISABLE_MSI, 845 PCI_LOST_IRQ_DISABLE_MSIX, 846 PCI_LOST_IRQ_DISABLE_ACPI, 847 }; 848 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 849 int pci_find_capability(struct pci_dev *dev, int cap); 850 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 851 int pci_find_ext_capability(struct pci_dev *dev, int cap); 852 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 853 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 854 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 855 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 856 857 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 858 struct pci_dev *from); 859 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 860 unsigned int ss_vendor, unsigned int ss_device, 861 struct pci_dev *from); 862 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 863 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 864 unsigned int devfn); 865 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 866 unsigned int devfn) 867 { 868 return pci_get_domain_bus_and_slot(0, bus, devfn); 869 } 870 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 871 int pci_dev_present(const struct pci_device_id *ids); 872 873 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 874 int where, u8 *val); 875 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 876 int where, u16 *val); 877 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 878 int where, u32 *val); 879 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 880 int where, u8 val); 881 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 882 int where, u16 val); 883 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 884 int where, u32 val); 885 886 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 887 int where, int size, u32 *val); 888 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 889 int where, int size, u32 val); 890 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 891 int where, int size, u32 *val); 892 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 893 int where, int size, u32 val); 894 895 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 896 897 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 898 { 899 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 900 } 901 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 902 { 903 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 904 } 905 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 906 u32 *val) 907 { 908 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 909 } 910 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 911 { 912 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 913 } 914 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 915 { 916 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 917 } 918 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 919 u32 val) 920 { 921 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 922 } 923 924 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 925 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 926 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 927 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 928 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 929 u16 clear, u16 set); 930 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 931 u32 clear, u32 set); 932 933 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 934 u16 set) 935 { 936 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 937 } 938 939 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 940 u32 set) 941 { 942 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 943 } 944 945 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 946 u16 clear) 947 { 948 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 949 } 950 951 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 952 u32 clear) 953 { 954 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 955 } 956 957 /* user-space driven config access */ 958 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 959 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 960 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 961 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 962 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 963 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 964 965 int __must_check pci_enable_device(struct pci_dev *dev); 966 int __must_check pci_enable_device_io(struct pci_dev *dev); 967 int __must_check pci_enable_device_mem(struct pci_dev *dev); 968 int __must_check pci_reenable_device(struct pci_dev *); 969 int __must_check pcim_enable_device(struct pci_dev *pdev); 970 void pcim_pin_device(struct pci_dev *pdev); 971 972 static inline int pci_is_enabled(struct pci_dev *pdev) 973 { 974 return (atomic_read(&pdev->enable_cnt) > 0); 975 } 976 977 static inline int pci_is_managed(struct pci_dev *pdev) 978 { 979 return pdev->is_managed; 980 } 981 982 static inline void pci_set_managed_irq(struct pci_dev *pdev, unsigned int irq) 983 { 984 pdev->irq = irq; 985 pdev->irq_managed = 1; 986 } 987 988 static inline void pci_reset_managed_irq(struct pci_dev *pdev) 989 { 990 pdev->irq = 0; 991 pdev->irq_managed = 0; 992 } 993 994 static inline bool pci_has_managed_irq(struct pci_dev *pdev) 995 { 996 return pdev->irq_managed && pdev->irq > 0; 997 } 998 999 void pci_disable_device(struct pci_dev *dev); 1000 1001 extern unsigned int pcibios_max_latency; 1002 void pci_set_master(struct pci_dev *dev); 1003 void pci_clear_master(struct pci_dev *dev); 1004 1005 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1006 int pci_set_cacheline_size(struct pci_dev *dev); 1007 #define HAVE_PCI_SET_MWI 1008 int __must_check pci_set_mwi(struct pci_dev *dev); 1009 int pci_try_set_mwi(struct pci_dev *dev); 1010 void pci_clear_mwi(struct pci_dev *dev); 1011 void pci_intx(struct pci_dev *dev, int enable); 1012 bool pci_intx_mask_supported(struct pci_dev *dev); 1013 bool pci_check_and_mask_intx(struct pci_dev *dev); 1014 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1015 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 1016 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 1017 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1018 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1019 int pcix_get_max_mmrbc(struct pci_dev *dev); 1020 int pcix_get_mmrbc(struct pci_dev *dev); 1021 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1022 int pcie_get_readrq(struct pci_dev *dev); 1023 int pcie_set_readrq(struct pci_dev *dev, int rq); 1024 int pcie_get_mps(struct pci_dev *dev); 1025 int pcie_set_mps(struct pci_dev *dev, int mps); 1026 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1027 enum pcie_link_width *width); 1028 int __pci_reset_function(struct pci_dev *dev); 1029 int __pci_reset_function_locked(struct pci_dev *dev); 1030 int pci_reset_function(struct pci_dev *dev); 1031 int pci_try_reset_function(struct pci_dev *dev); 1032 int pci_probe_reset_slot(struct pci_slot *slot); 1033 int pci_reset_slot(struct pci_slot *slot); 1034 int pci_try_reset_slot(struct pci_slot *slot); 1035 int pci_probe_reset_bus(struct pci_bus *bus); 1036 int pci_reset_bus(struct pci_bus *bus); 1037 int pci_try_reset_bus(struct pci_bus *bus); 1038 void pci_reset_secondary_bus(struct pci_dev *dev); 1039 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1040 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1041 void pci_update_resource(struct pci_dev *dev, int resno); 1042 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1043 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1044 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1045 bool pci_device_is_present(struct pci_dev *pdev); 1046 void pci_ignore_hotplug(struct pci_dev *dev); 1047 1048 /* ROM control related routines */ 1049 int pci_enable_rom(struct pci_dev *pdev); 1050 void pci_disable_rom(struct pci_dev *pdev); 1051 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1052 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1053 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1054 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1055 1056 /* Power management related routines */ 1057 int pci_save_state(struct pci_dev *dev); 1058 void pci_restore_state(struct pci_dev *dev); 1059 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1060 int pci_load_saved_state(struct pci_dev *dev, 1061 struct pci_saved_state *state); 1062 int pci_load_and_free_saved_state(struct pci_dev *dev, 1063 struct pci_saved_state **state); 1064 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1065 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1066 u16 cap); 1067 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1068 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1069 u16 cap, unsigned int size); 1070 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1071 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1072 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1073 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1074 void pci_pme_active(struct pci_dev *dev, bool enable); 1075 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1076 bool runtime, bool enable); 1077 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1078 int pci_prepare_to_sleep(struct pci_dev *dev); 1079 int pci_back_from_sleep(struct pci_dev *dev); 1080 bool pci_dev_run_wake(struct pci_dev *dev); 1081 bool pci_check_pme_status(struct pci_dev *dev); 1082 void pci_pme_wakeup_bus(struct pci_bus *bus); 1083 1084 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1085 bool enable) 1086 { 1087 return __pci_enable_wake(dev, state, false, enable); 1088 } 1089 1090 /* PCI Virtual Channel */ 1091 int pci_save_vc_state(struct pci_dev *dev); 1092 void pci_restore_vc_state(struct pci_dev *dev); 1093 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1094 1095 /* For use by arch with custom probe code */ 1096 void set_pcie_port_type(struct pci_dev *pdev); 1097 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1098 1099 /* Functions for PCI Hotplug drivers to use */ 1100 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1101 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1102 unsigned int pci_rescan_bus(struct pci_bus *bus); 1103 void pci_lock_rescan_remove(void); 1104 void pci_unlock_rescan_remove(void); 1105 1106 /* Vital product data routines */ 1107 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1108 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1109 1110 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1111 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1112 void pci_bus_assign_resources(const struct pci_bus *bus); 1113 void pci_bus_size_bridges(struct pci_bus *bus); 1114 int pci_claim_resource(struct pci_dev *, int); 1115 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1116 void pci_assign_unassigned_resources(void); 1117 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1118 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1119 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1120 void pdev_enable_device(struct pci_dev *); 1121 int pci_enable_resources(struct pci_dev *, int mask); 1122 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1123 int (*)(const struct pci_dev *, u8, u8)); 1124 #define HAVE_PCI_REQ_REGIONS 2 1125 int __must_check pci_request_regions(struct pci_dev *, const char *); 1126 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1127 void pci_release_regions(struct pci_dev *); 1128 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1129 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1130 void pci_release_region(struct pci_dev *, int); 1131 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1132 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1133 void pci_release_selected_regions(struct pci_dev *, int); 1134 1135 /* drivers/pci/bus.c */ 1136 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1137 void pci_bus_put(struct pci_bus *bus); 1138 void pci_add_resource(struct list_head *resources, struct resource *res); 1139 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1140 resource_size_t offset); 1141 void pci_free_resource_list(struct list_head *resources); 1142 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1143 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1144 void pci_bus_remove_resources(struct pci_bus *bus); 1145 1146 #define pci_bus_for_each_resource(bus, res, i) \ 1147 for (i = 0; \ 1148 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1149 i++) 1150 1151 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1152 struct resource *res, resource_size_t size, 1153 resource_size_t align, resource_size_t min, 1154 unsigned long type_mask, 1155 resource_size_t (*alignf)(void *, 1156 const struct resource *, 1157 resource_size_t, 1158 resource_size_t), 1159 void *alignf_data); 1160 1161 1162 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1163 1164 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1165 { 1166 struct pci_bus_region region; 1167 1168 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1169 return region.start; 1170 } 1171 1172 /* Proper probing supporting hot-pluggable devices */ 1173 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1174 const char *mod_name); 1175 1176 /* 1177 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1178 */ 1179 #define pci_register_driver(driver) \ 1180 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1181 1182 void pci_unregister_driver(struct pci_driver *dev); 1183 1184 /** 1185 * module_pci_driver() - Helper macro for registering a PCI driver 1186 * @__pci_driver: pci_driver struct 1187 * 1188 * Helper macro for PCI drivers which do not do anything special in module 1189 * init/exit. This eliminates a lot of boilerplate. Each module may only 1190 * use this macro once, and calling it replaces module_init() and module_exit() 1191 */ 1192 #define module_pci_driver(__pci_driver) \ 1193 module_driver(__pci_driver, pci_register_driver, \ 1194 pci_unregister_driver) 1195 1196 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1197 int pci_add_dynid(struct pci_driver *drv, 1198 unsigned int vendor, unsigned int device, 1199 unsigned int subvendor, unsigned int subdevice, 1200 unsigned int class, unsigned int class_mask, 1201 unsigned long driver_data); 1202 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1203 struct pci_dev *dev); 1204 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1205 int pass); 1206 1207 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1208 void *userdata); 1209 int pci_cfg_space_size(struct pci_dev *dev); 1210 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1211 void pci_setup_bridge(struct pci_bus *bus); 1212 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1213 unsigned long type); 1214 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1215 1216 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1217 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1218 1219 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1220 unsigned int command_bits, u32 flags); 1221 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1222 1223 #include <linux/pci-dma.h> 1224 #include <linux/dmapool.h> 1225 1226 #define pci_pool dma_pool 1227 #define pci_pool_create(name, pdev, size, align, allocation) \ 1228 dma_pool_create(name, &pdev->dev, size, align, allocation) 1229 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1230 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1231 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1232 1233 struct msix_entry { 1234 u32 vector; /* kernel uses to write allocated vector */ 1235 u16 entry; /* driver uses to specify entry, OS writes */ 1236 }; 1237 1238 void pci_msi_setup_pci_dev(struct pci_dev *dev); 1239 1240 #ifdef CONFIG_PCI_MSI 1241 int pci_msi_vec_count(struct pci_dev *dev); 1242 void pci_msi_shutdown(struct pci_dev *dev); 1243 void pci_disable_msi(struct pci_dev *dev); 1244 int pci_msix_vec_count(struct pci_dev *dev); 1245 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1246 void pci_msix_shutdown(struct pci_dev *dev); 1247 void pci_disable_msix(struct pci_dev *dev); 1248 void pci_restore_msi_state(struct pci_dev *dev); 1249 int pci_msi_enabled(void); 1250 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1251 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1252 { 1253 int rc = pci_enable_msi_range(dev, nvec, nvec); 1254 if (rc < 0) 1255 return rc; 1256 return 0; 1257 } 1258 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1259 int minvec, int maxvec); 1260 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1261 struct msix_entry *entries, int nvec) 1262 { 1263 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1264 if (rc < 0) 1265 return rc; 1266 return 0; 1267 } 1268 #else 1269 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1270 static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1271 static inline void pci_disable_msi(struct pci_dev *dev) { } 1272 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1273 static inline int pci_enable_msix(struct pci_dev *dev, 1274 struct msix_entry *entries, int nvec) 1275 { return -ENOSYS; } 1276 static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1277 static inline void pci_disable_msix(struct pci_dev *dev) { } 1278 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1279 static inline int pci_msi_enabled(void) { return 0; } 1280 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1281 int maxvec) 1282 { return -ENOSYS; } 1283 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1284 { return -ENOSYS; } 1285 static inline int pci_enable_msix_range(struct pci_dev *dev, 1286 struct msix_entry *entries, int minvec, int maxvec) 1287 { return -ENOSYS; } 1288 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1289 struct msix_entry *entries, int nvec) 1290 { return -ENOSYS; } 1291 #endif 1292 1293 #ifdef CONFIG_PCIEPORTBUS 1294 extern bool pcie_ports_disabled; 1295 extern bool pcie_ports_auto; 1296 #else 1297 #define pcie_ports_disabled true 1298 #define pcie_ports_auto false 1299 #endif 1300 1301 #ifdef CONFIG_PCIEASPM 1302 bool pcie_aspm_support_enabled(void); 1303 #else 1304 static inline bool pcie_aspm_support_enabled(void) { return false; } 1305 #endif 1306 1307 #ifdef CONFIG_PCIEAER 1308 void pci_no_aer(void); 1309 bool pci_aer_available(void); 1310 #else 1311 static inline void pci_no_aer(void) { } 1312 static inline bool pci_aer_available(void) { return false; } 1313 #endif 1314 1315 #ifdef CONFIG_PCIE_ECRC 1316 void pcie_set_ecrc_checking(struct pci_dev *dev); 1317 void pcie_ecrc_get_policy(char *str); 1318 #else 1319 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1320 static inline void pcie_ecrc_get_policy(char *str) { } 1321 #endif 1322 1323 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) 1324 1325 #ifdef CONFIG_HT_IRQ 1326 /* The functions a driver should call */ 1327 int ht_create_irq(struct pci_dev *dev, int idx); 1328 void ht_destroy_irq(unsigned int irq); 1329 #endif /* CONFIG_HT_IRQ */ 1330 1331 #ifdef CONFIG_PCI_ATS 1332 /* Address Translation Service */ 1333 void pci_ats_init(struct pci_dev *dev); 1334 int pci_enable_ats(struct pci_dev *dev, int ps); 1335 void pci_disable_ats(struct pci_dev *dev); 1336 int pci_ats_queue_depth(struct pci_dev *dev); 1337 #else 1338 static inline void pci_ats_init(struct pci_dev *d) { } 1339 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1340 static inline void pci_disable_ats(struct pci_dev *d) { } 1341 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1342 #endif 1343 1344 void pci_cfg_access_lock(struct pci_dev *dev); 1345 bool pci_cfg_access_trylock(struct pci_dev *dev); 1346 void pci_cfg_access_unlock(struct pci_dev *dev); 1347 1348 /* 1349 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1350 * a PCI domain is defined to be a set of PCI buses which share 1351 * configuration space. 1352 */ 1353 #ifdef CONFIG_PCI_DOMAINS 1354 extern int pci_domains_supported; 1355 int pci_get_new_domain_nr(void); 1356 #else 1357 enum { pci_domains_supported = 0 }; 1358 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1359 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1360 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1361 #endif /* CONFIG_PCI_DOMAINS */ 1362 1363 /* 1364 * Generic implementation for PCI domain support. If your 1365 * architecture does not need custom management of PCI 1366 * domains then this implementation will be used 1367 */ 1368 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1369 static inline int pci_domain_nr(struct pci_bus *bus) 1370 { 1371 return bus->domain_nr; 1372 } 1373 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); 1374 #else 1375 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, 1376 struct device *parent) 1377 { 1378 } 1379 #endif 1380 1381 /* some architectures require additional setup to direct VGA traffic */ 1382 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1383 unsigned int command_bits, u32 flags); 1384 void pci_register_set_vga_state(arch_set_vga_state_t func); 1385 1386 #else /* CONFIG_PCI is not enabled */ 1387 1388 /* 1389 * If the system does not have PCI, clearly these return errors. Define 1390 * these as simple inline functions to avoid hair in drivers. 1391 */ 1392 1393 #define _PCI_NOP(o, s, t) \ 1394 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1395 int where, t val) \ 1396 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1397 1398 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1399 _PCI_NOP(o, word, u16 x) \ 1400 _PCI_NOP(o, dword, u32 x) 1401 _PCI_NOP_ALL(read, *) 1402 _PCI_NOP_ALL(write,) 1403 1404 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1405 unsigned int device, 1406 struct pci_dev *from) 1407 { return NULL; } 1408 1409 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1410 unsigned int device, 1411 unsigned int ss_vendor, 1412 unsigned int ss_device, 1413 struct pci_dev *from) 1414 { return NULL; } 1415 1416 static inline struct pci_dev *pci_get_class(unsigned int class, 1417 struct pci_dev *from) 1418 { return NULL; } 1419 1420 #define pci_dev_present(ids) (0) 1421 #define no_pci_devices() (1) 1422 #define pci_dev_put(dev) do { } while (0) 1423 1424 static inline void pci_set_master(struct pci_dev *dev) { } 1425 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1426 static inline void pci_disable_device(struct pci_dev *dev) { } 1427 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1428 { return -EIO; } 1429 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1430 { return -EIO; } 1431 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1432 unsigned int size) 1433 { return -EIO; } 1434 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1435 unsigned long mask) 1436 { return -EIO; } 1437 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1438 { return -EBUSY; } 1439 static inline int __pci_register_driver(struct pci_driver *drv, 1440 struct module *owner) 1441 { return 0; } 1442 static inline int pci_register_driver(struct pci_driver *drv) 1443 { return 0; } 1444 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1445 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1446 { return 0; } 1447 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1448 int cap) 1449 { return 0; } 1450 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1451 { return 0; } 1452 1453 /* Power management related routines */ 1454 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1455 static inline void pci_restore_state(struct pci_dev *dev) { } 1456 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1457 { return 0; } 1458 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1459 { return 0; } 1460 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1461 pm_message_t state) 1462 { return PCI_D0; } 1463 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1464 int enable) 1465 { return 0; } 1466 1467 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1468 { return -EIO; } 1469 static inline void pci_release_regions(struct pci_dev *dev) { } 1470 1471 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1472 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1473 { return 0; } 1474 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1475 1476 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1477 { return NULL; } 1478 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1479 unsigned int devfn) 1480 { return NULL; } 1481 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1482 unsigned int devfn) 1483 { return NULL; } 1484 1485 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1486 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1487 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1488 1489 #define dev_is_pci(d) (false) 1490 #define dev_is_pf(d) (false) 1491 #define dev_num_vf(d) (0) 1492 #endif /* CONFIG_PCI */ 1493 1494 /* Include architecture-dependent settings and functions */ 1495 1496 #include <asm/pci.h> 1497 1498 /* these helpers provide future and backwards compatibility 1499 * for accessing popular PCI BAR info */ 1500 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1501 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1502 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1503 #define pci_resource_len(dev,bar) \ 1504 ((pci_resource_start((dev), (bar)) == 0 && \ 1505 pci_resource_end((dev), (bar)) == \ 1506 pci_resource_start((dev), (bar))) ? 0 : \ 1507 \ 1508 (pci_resource_end((dev), (bar)) - \ 1509 pci_resource_start((dev), (bar)) + 1)) 1510 1511 /* Similar to the helpers above, these manipulate per-pci_dev 1512 * driver-specific data. They are really just a wrapper around 1513 * the generic device structure functions of these calls. 1514 */ 1515 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1516 { 1517 return dev_get_drvdata(&pdev->dev); 1518 } 1519 1520 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1521 { 1522 dev_set_drvdata(&pdev->dev, data); 1523 } 1524 1525 /* If you want to know what to call your pci_dev, ask this function. 1526 * Again, it's a wrapper around the generic device. 1527 */ 1528 static inline const char *pci_name(const struct pci_dev *pdev) 1529 { 1530 return dev_name(&pdev->dev); 1531 } 1532 1533 1534 /* Some archs don't want to expose struct resource to userland as-is 1535 * in sysfs and /proc 1536 */ 1537 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1538 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1539 const struct resource *rsrc, resource_size_t *start, 1540 resource_size_t *end) 1541 { 1542 *start = rsrc->start; 1543 *end = rsrc->end; 1544 } 1545 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1546 1547 1548 /* 1549 * The world is not perfect and supplies us with broken PCI devices. 1550 * For at least a part of these bugs we need a work-around, so both 1551 * generic (drivers/pci/quirks.c) and per-architecture code can define 1552 * fixup hooks to be called for particular buggy devices. 1553 */ 1554 1555 struct pci_fixup { 1556 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1557 u16 device; /* You can use PCI_ANY_ID here of course */ 1558 u32 class; /* You can use PCI_ANY_ID here too */ 1559 unsigned int class_shift; /* should be 0, 8, 16 */ 1560 void (*hook)(struct pci_dev *dev); 1561 }; 1562 1563 enum pci_fixup_pass { 1564 pci_fixup_early, /* Before probing BARs */ 1565 pci_fixup_header, /* After reading configuration header */ 1566 pci_fixup_final, /* Final phase of device fixups */ 1567 pci_fixup_enable, /* pci_enable_device() time */ 1568 pci_fixup_resume, /* pci_device_resume() */ 1569 pci_fixup_suspend, /* pci_device_suspend() */ 1570 pci_fixup_resume_early, /* pci_device_resume_early() */ 1571 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1572 }; 1573 1574 /* Anonymous variables would be nice... */ 1575 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1576 class_shift, hook) \ 1577 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1578 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1579 = { vendor, device, class, class_shift, hook }; 1580 1581 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1582 class_shift, hook) \ 1583 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1584 hook, vendor, device, class, class_shift, hook) 1585 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1586 class_shift, hook) \ 1587 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1588 hook, vendor, device, class, class_shift, hook) 1589 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1590 class_shift, hook) \ 1591 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1592 hook, vendor, device, class, class_shift, hook) 1593 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1594 class_shift, hook) \ 1595 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1596 hook, vendor, device, class, class_shift, hook) 1597 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1598 class_shift, hook) \ 1599 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1600 resume##hook, vendor, device, class, \ 1601 class_shift, hook) 1602 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1603 class_shift, hook) \ 1604 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1605 resume_early##hook, vendor, device, \ 1606 class, class_shift, hook) 1607 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1608 class_shift, hook) \ 1609 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1610 suspend##hook, vendor, device, class, \ 1611 class_shift, hook) 1612 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1613 class_shift, hook) \ 1614 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1615 suspend_late##hook, vendor, device, \ 1616 class, class_shift, hook) 1617 1618 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1619 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1620 hook, vendor, device, PCI_ANY_ID, 0, hook) 1621 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1622 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1623 hook, vendor, device, PCI_ANY_ID, 0, hook) 1624 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1625 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1626 hook, vendor, device, PCI_ANY_ID, 0, hook) 1627 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1628 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1629 hook, vendor, device, PCI_ANY_ID, 0, hook) 1630 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1631 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1632 resume##hook, vendor, device, \ 1633 PCI_ANY_ID, 0, hook) 1634 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1635 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1636 resume_early##hook, vendor, device, \ 1637 PCI_ANY_ID, 0, hook) 1638 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1639 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1640 suspend##hook, vendor, device, \ 1641 PCI_ANY_ID, 0, hook) 1642 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1643 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1644 suspend_late##hook, vendor, device, \ 1645 PCI_ANY_ID, 0, hook) 1646 1647 #ifdef CONFIG_PCI_QUIRKS 1648 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1649 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1650 void pci_dev_specific_enable_acs(struct pci_dev *dev); 1651 #else 1652 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1653 struct pci_dev *dev) { } 1654 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1655 u16 acs_flags) 1656 { 1657 return -ENOTTY; 1658 } 1659 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } 1660 #endif 1661 1662 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1663 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1664 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1665 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1666 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1667 const char *name); 1668 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1669 1670 extern int pci_pci_problems; 1671 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1672 #define PCIPCI_TRITON 2 1673 #define PCIPCI_NATOMA 4 1674 #define PCIPCI_VIAETBF 8 1675 #define PCIPCI_VSFX 16 1676 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1677 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1678 1679 extern unsigned long pci_cardbus_io_size; 1680 extern unsigned long pci_cardbus_mem_size; 1681 extern u8 pci_dfl_cache_line_size; 1682 extern u8 pci_cache_line_size; 1683 1684 extern unsigned long pci_hotplug_io_size; 1685 extern unsigned long pci_hotplug_mem_size; 1686 1687 /* Architecture-specific versions may override these (weak) */ 1688 void pcibios_disable_device(struct pci_dev *dev); 1689 void pcibios_set_master(struct pci_dev *dev); 1690 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1691 enum pcie_reset_state state); 1692 int pcibios_add_device(struct pci_dev *dev); 1693 void pcibios_release_device(struct pci_dev *dev); 1694 void pcibios_penalize_isa_irq(int irq, int active); 1695 int pcibios_alloc_irq(struct pci_dev *dev); 1696 void pcibios_free_irq(struct pci_dev *dev); 1697 1698 #ifdef CONFIG_HIBERNATE_CALLBACKS 1699 extern struct dev_pm_ops pcibios_pm_ops; 1700 #endif 1701 1702 #ifdef CONFIG_PCI_MMCONFIG 1703 void __init pci_mmcfg_early_init(void); 1704 void __init pci_mmcfg_late_init(void); 1705 #else 1706 static inline void pci_mmcfg_early_init(void) { } 1707 static inline void pci_mmcfg_late_init(void) { } 1708 #endif 1709 1710 int pci_ext_cfg_avail(void); 1711 1712 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1713 1714 #ifdef CONFIG_PCI_IOV 1715 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1716 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1717 1718 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1719 void pci_disable_sriov(struct pci_dev *dev); 1720 int pci_num_vf(struct pci_dev *dev); 1721 int pci_vfs_assigned(struct pci_dev *dev); 1722 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1723 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1724 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1725 #else 1726 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1727 { 1728 return -ENOSYS; 1729 } 1730 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1731 { 1732 return -ENOSYS; 1733 } 1734 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1735 { return -ENODEV; } 1736 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1737 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1738 static inline int pci_vfs_assigned(struct pci_dev *dev) 1739 { return 0; } 1740 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1741 { return 0; } 1742 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1743 { return 0; } 1744 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1745 { return 0; } 1746 #endif 1747 1748 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1749 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1750 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1751 #endif 1752 1753 /** 1754 * pci_pcie_cap - get the saved PCIe capability offset 1755 * @dev: PCI device 1756 * 1757 * PCIe capability offset is calculated at PCI device initialization 1758 * time and saved in the data structure. This function returns saved 1759 * PCIe capability offset. Using this instead of pci_find_capability() 1760 * reduces unnecessary search in the PCI configuration space. If you 1761 * need to calculate PCIe capability offset from raw device for some 1762 * reasons, please use pci_find_capability() instead. 1763 */ 1764 static inline int pci_pcie_cap(struct pci_dev *dev) 1765 { 1766 return dev->pcie_cap; 1767 } 1768 1769 /** 1770 * pci_is_pcie - check if the PCI device is PCI Express capable 1771 * @dev: PCI device 1772 * 1773 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1774 */ 1775 static inline bool pci_is_pcie(struct pci_dev *dev) 1776 { 1777 return pci_pcie_cap(dev); 1778 } 1779 1780 /** 1781 * pcie_caps_reg - get the PCIe Capabilities Register 1782 * @dev: PCI device 1783 */ 1784 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1785 { 1786 return dev->pcie_flags_reg; 1787 } 1788 1789 /** 1790 * pci_pcie_type - get the PCIe device/port type 1791 * @dev: PCI device 1792 */ 1793 static inline int pci_pcie_type(const struct pci_dev *dev) 1794 { 1795 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1796 } 1797 1798 void pci_request_acs(void); 1799 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1800 bool pci_acs_path_enabled(struct pci_dev *start, 1801 struct pci_dev *end, u16 acs_flags); 1802 1803 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1804 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1805 1806 /* Large Resource Data Type Tag Item Names */ 1807 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1808 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1809 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1810 1811 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1812 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1813 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1814 1815 /* Small Resource Data Type Tag Item Names */ 1816 #define PCI_VPD_STIN_END 0x78 /* End */ 1817 1818 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1819 1820 #define PCI_VPD_SRDT_TIN_MASK 0x78 1821 #define PCI_VPD_SRDT_LEN_MASK 0x07 1822 1823 #define PCI_VPD_LRDT_TAG_SIZE 3 1824 #define PCI_VPD_SRDT_TAG_SIZE 1 1825 1826 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1827 1828 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1829 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1830 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1831 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1832 1833 /** 1834 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1835 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1836 * 1837 * Returns the extracted Large Resource Data Type length. 1838 */ 1839 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1840 { 1841 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1842 } 1843 1844 /** 1845 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1846 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1847 * 1848 * Returns the extracted Small Resource Data Type length. 1849 */ 1850 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1851 { 1852 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1853 } 1854 1855 /** 1856 * pci_vpd_info_field_size - Extracts the information field length 1857 * @lrdt: Pointer to the beginning of an information field header 1858 * 1859 * Returns the extracted information field length. 1860 */ 1861 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1862 { 1863 return info_field[2]; 1864 } 1865 1866 /** 1867 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1868 * @buf: Pointer to buffered vpd data 1869 * @off: The offset into the buffer at which to begin the search 1870 * @len: The length of the vpd buffer 1871 * @rdt: The Resource Data Type to search for 1872 * 1873 * Returns the index where the Resource Data Type was found or 1874 * -ENOENT otherwise. 1875 */ 1876 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1877 1878 /** 1879 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1880 * @buf: Pointer to buffered vpd data 1881 * @off: The offset into the buffer at which to begin the search 1882 * @len: The length of the buffer area, relative to off, in which to search 1883 * @kw: The keyword to search for 1884 * 1885 * Returns the index where the information field keyword was found or 1886 * -ENOENT otherwise. 1887 */ 1888 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1889 unsigned int len, const char *kw); 1890 1891 /* PCI <-> OF binding helpers */ 1892 #ifdef CONFIG_OF 1893 struct device_node; 1894 void pci_set_of_node(struct pci_dev *dev); 1895 void pci_release_of_node(struct pci_dev *dev); 1896 void pci_set_bus_of_node(struct pci_bus *bus); 1897 void pci_release_bus_of_node(struct pci_bus *bus); 1898 1899 /* Arch may override this (weak) */ 1900 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1901 1902 static inline struct device_node * 1903 pci_device_to_OF_node(const struct pci_dev *pdev) 1904 { 1905 return pdev ? pdev->dev.of_node : NULL; 1906 } 1907 1908 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1909 { 1910 return bus ? bus->dev.of_node : NULL; 1911 } 1912 1913 #else /* CONFIG_OF */ 1914 static inline void pci_set_of_node(struct pci_dev *dev) { } 1915 static inline void pci_release_of_node(struct pci_dev *dev) { } 1916 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1917 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1918 static inline struct device_node * 1919 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 1920 #endif /* CONFIG_OF */ 1921 1922 #ifdef CONFIG_EEH 1923 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1924 { 1925 return pdev->dev.archdata.edev; 1926 } 1927 #endif 1928 1929 int pci_for_each_dma_alias(struct pci_dev *pdev, 1930 int (*fn)(struct pci_dev *pdev, 1931 u16 alias, void *data), void *data); 1932 1933 /* helper functions for operation of device flag */ 1934 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 1935 { 1936 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 1937 } 1938 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 1939 { 1940 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 1941 } 1942 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 1943 { 1944 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 1945 } 1946 1947 /** 1948 * pci_ari_enabled - query ARI forwarding status 1949 * @bus: the PCI bus 1950 * 1951 * Returns true if ARI forwarding is enabled. 1952 */ 1953 static inline bool pci_ari_enabled(struct pci_bus *bus) 1954 { 1955 return bus->self && bus->self->ari_enabled; 1956 } 1957 #endif /* LINUX_PCI_H */ 1958