1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/interrupt.h> 32 #include <linux/io.h> 33 #include <linux/resource_ext.h> 34 #include <uapi/linux/pci.h> 35 36 #include <linux/pci_ids.h> 37 38 /* 39 * The PCI interface treats multi-function devices as independent 40 * devices. The slot/function address of each device is encoded 41 * in a single byte as follows: 42 * 43 * 7:3 = slot 44 * 2:0 = function 45 * 46 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 47 * In the interest of not exposing interfaces to user-space unnecessarily, 48 * the following kernel-only defines are being added here. 49 */ 50 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 51 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 52 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 53 54 /* pci_slot represents a physical slot */ 55 struct pci_slot { 56 struct pci_bus *bus; /* The bus this slot is on */ 57 struct list_head list; /* node in list of slots on this bus */ 58 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 59 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 60 struct kobject kobj; 61 }; 62 63 static inline const char *pci_slot_name(const struct pci_slot *slot) 64 { 65 return kobject_name(&slot->kobj); 66 } 67 68 /* File state for mmap()s on /proc/bus/pci/X/Y */ 69 enum pci_mmap_state { 70 pci_mmap_io, 71 pci_mmap_mem 72 }; 73 74 /* 75 * For PCI devices, the region numbers are assigned this way: 76 */ 77 enum { 78 /* #0-5: standard PCI resources */ 79 PCI_STD_RESOURCES, 80 PCI_STD_RESOURCE_END = 5, 81 82 /* #6: expansion ROM resource */ 83 PCI_ROM_RESOURCE, 84 85 /* device specific resources */ 86 #ifdef CONFIG_PCI_IOV 87 PCI_IOV_RESOURCES, 88 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 89 #endif 90 91 /* resources assigned to buses behind the bridge */ 92 #define PCI_BRIDGE_RESOURCE_NUM 4 93 94 PCI_BRIDGE_RESOURCES, 95 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 96 PCI_BRIDGE_RESOURCE_NUM - 1, 97 98 /* total resources associated with a PCI device */ 99 PCI_NUM_RESOURCES, 100 101 /* preserve this for compatibility */ 102 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 103 }; 104 105 /** 106 * enum pci_interrupt_pin - PCI INTx interrupt values 107 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 108 * @PCI_INTERRUPT_INTA: PCI INTA pin 109 * @PCI_INTERRUPT_INTB: PCI INTB pin 110 * @PCI_INTERRUPT_INTC: PCI INTC pin 111 * @PCI_INTERRUPT_INTD: PCI INTD pin 112 * 113 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 114 * PCI_INTERRUPT_PIN register. 115 */ 116 enum pci_interrupt_pin { 117 PCI_INTERRUPT_UNKNOWN, 118 PCI_INTERRUPT_INTA, 119 PCI_INTERRUPT_INTB, 120 PCI_INTERRUPT_INTC, 121 PCI_INTERRUPT_INTD, 122 }; 123 124 /* The number of legacy PCI INTx interrupts */ 125 #define PCI_NUM_INTX 4 126 127 /* 128 * pci_power_t values must match the bits in the Capabilities PME_Support 129 * and Control/Status PowerState fields in the Power Management capability. 130 */ 131 typedef int __bitwise pci_power_t; 132 133 #define PCI_D0 ((pci_power_t __force) 0) 134 #define PCI_D1 ((pci_power_t __force) 1) 135 #define PCI_D2 ((pci_power_t __force) 2) 136 #define PCI_D3hot ((pci_power_t __force) 3) 137 #define PCI_D3cold ((pci_power_t __force) 4) 138 #define PCI_UNKNOWN ((pci_power_t __force) 5) 139 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 140 141 /* Remember to update this when the list above changes! */ 142 extern const char *pci_power_names[]; 143 144 static inline const char *pci_power_name(pci_power_t state) 145 { 146 return pci_power_names[1 + (__force int) state]; 147 } 148 149 #define PCI_PM_D2_DELAY 200 150 #define PCI_PM_D3_WAIT 10 151 #define PCI_PM_D3COLD_WAIT 100 152 #define PCI_PM_BUS_WAIT 50 153 154 /** The pci_channel state describes connectivity between the CPU and 155 * the pci device. If some PCI bus between here and the pci device 156 * has crashed or locked up, this info is reflected here. 157 */ 158 typedef unsigned int __bitwise pci_channel_state_t; 159 160 enum pci_channel_state { 161 /* I/O channel is in normal state */ 162 pci_channel_io_normal = (__force pci_channel_state_t) 1, 163 164 /* I/O to channel is blocked */ 165 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 166 167 /* PCI card is dead */ 168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 169 }; 170 171 typedef unsigned int __bitwise pcie_reset_state_t; 172 173 enum pcie_reset_state { 174 /* Reset is NOT asserted (Use to deassert reset) */ 175 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 176 177 /* Use #PERST to reset PCIe device */ 178 pcie_warm_reset = (__force pcie_reset_state_t) 2, 179 180 /* Use PCIe Hot Reset to reset device */ 181 pcie_hot_reset = (__force pcie_reset_state_t) 3 182 }; 183 184 typedef unsigned short __bitwise pci_dev_flags_t; 185 enum pci_dev_flags { 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI 187 * generation too. 188 */ 189 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 190 /* Device configuration is irrevocably lost if disabled into D3 */ 191 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 192 /* Provide indication device is assigned by a Virtual Machine Manager */ 193 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 194 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 195 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 196 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 197 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 198 /* Do not use bus resets for device */ 199 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 200 /* Do not use PM reset even if device advertises NoSoftRst- */ 201 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 202 /* Get VPD from function 0 VPD */ 203 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 204 /* a non-root bridge where translation occurs, stop alias search here */ 205 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 206 /* Do not use FLR even if device advertises PCI_AF_CAP */ 207 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 208 /* 209 * Resume before calling the driver's system suspend hooks, disabling 210 * the direct_complete optimization. 211 */ 212 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11), 213 /* Don't use Relaxed Ordering for TLPs directed at this device */ 214 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12), 215 }; 216 217 enum pci_irq_reroute_variant { 218 INTEL_IRQ_REROUTE_VARIANT = 1, 219 MAX_IRQ_REROUTE_VARIANTS = 3 220 }; 221 222 typedef unsigned short __bitwise pci_bus_flags_t; 223 enum pci_bus_flags { 224 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 225 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 226 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 227 }; 228 229 /* These values come from the PCI Express Spec */ 230 enum pcie_link_width { 231 PCIE_LNK_WIDTH_RESRV = 0x00, 232 PCIE_LNK_X1 = 0x01, 233 PCIE_LNK_X2 = 0x02, 234 PCIE_LNK_X4 = 0x04, 235 PCIE_LNK_X8 = 0x08, 236 PCIE_LNK_X12 = 0x0C, 237 PCIE_LNK_X16 = 0x10, 238 PCIE_LNK_X32 = 0x20, 239 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 240 }; 241 242 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 243 enum pci_bus_speed { 244 PCI_SPEED_33MHz = 0x00, 245 PCI_SPEED_66MHz = 0x01, 246 PCI_SPEED_66MHz_PCIX = 0x02, 247 PCI_SPEED_100MHz_PCIX = 0x03, 248 PCI_SPEED_133MHz_PCIX = 0x04, 249 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 250 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 251 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 252 PCI_SPEED_66MHz_PCIX_266 = 0x09, 253 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 254 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 255 AGP_UNKNOWN = 0x0c, 256 AGP_1X = 0x0d, 257 AGP_2X = 0x0e, 258 AGP_4X = 0x0f, 259 AGP_8X = 0x10, 260 PCI_SPEED_66MHz_PCIX_533 = 0x11, 261 PCI_SPEED_100MHz_PCIX_533 = 0x12, 262 PCI_SPEED_133MHz_PCIX_533 = 0x13, 263 PCIE_SPEED_2_5GT = 0x14, 264 PCIE_SPEED_5_0GT = 0x15, 265 PCIE_SPEED_8_0GT = 0x16, 266 PCI_SPEED_UNKNOWN = 0xff, 267 }; 268 269 struct pci_cap_saved_data { 270 u16 cap_nr; 271 bool cap_extended; 272 unsigned int size; 273 u32 data[0]; 274 }; 275 276 struct pci_cap_saved_state { 277 struct hlist_node next; 278 struct pci_cap_saved_data cap; 279 }; 280 281 struct irq_affinity; 282 struct pcie_link_state; 283 struct pci_vpd; 284 struct pci_sriov; 285 struct pci_ats; 286 287 /* 288 * The pci_dev structure is used to describe PCI devices. 289 */ 290 struct pci_dev { 291 struct list_head bus_list; /* node in per-bus list */ 292 struct pci_bus *bus; /* bus this device is on */ 293 struct pci_bus *subordinate; /* bus this device bridges to */ 294 295 void *sysdata; /* hook for sys-specific extension */ 296 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 297 struct pci_slot *slot; /* Physical slot this device is in */ 298 299 unsigned int devfn; /* encoded device & function index */ 300 unsigned short vendor; 301 unsigned short device; 302 unsigned short subsystem_vendor; 303 unsigned short subsystem_device; 304 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 305 u8 revision; /* PCI revision, low byte of class word */ 306 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 307 #ifdef CONFIG_PCIEAER 308 u16 aer_cap; /* AER capability offset */ 309 #endif 310 u8 pcie_cap; /* PCIe capability offset */ 311 u8 msi_cap; /* MSI capability offset */ 312 u8 msix_cap; /* MSI-X capability offset */ 313 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 314 u8 rom_base_reg; /* which config register controls the ROM */ 315 u8 pin; /* which interrupt pin this device uses */ 316 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 317 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */ 318 319 struct pci_driver *driver; /* which driver has allocated this device */ 320 u64 dma_mask; /* Mask of the bits of bus address this 321 device implements. Normally this is 322 0xffffffff. You only need to change 323 this if your device has broken DMA 324 or supports 64-bit transfers. */ 325 326 struct device_dma_parameters dma_parms; 327 328 pci_power_t current_state; /* Current operating state. In ACPI-speak, 329 this is D0-D3, D0 being fully functional, 330 and D3 being off. */ 331 u8 pm_cap; /* PM capability offset */ 332 unsigned int pme_support:5; /* Bitmask of states from which PME# 333 can be generated */ 334 unsigned int pme_poll:1; /* Poll device's PME status bit */ 335 unsigned int d1_support:1; /* Low power state D1 is supported */ 336 unsigned int d2_support:1; /* Low power state D2 is supported */ 337 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 338 unsigned int no_d3cold:1; /* D3cold is forbidden */ 339 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 340 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 341 unsigned int mmio_always_on:1; /* disallow turning off io/mem 342 decoding during bar sizing */ 343 unsigned int wakeup_prepared:1; 344 unsigned int runtime_d3cold:1; /* whether go through runtime 345 D3cold, not set for devices 346 powered on/off by the 347 corresponding bridge */ 348 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 349 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 350 controlled exclusively by 351 user sysfs */ 352 unsigned int d3_delay; /* D3->D0 transition time in ms */ 353 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 354 355 #ifdef CONFIG_PCIEASPM 356 struct pcie_link_state *link_state; /* ASPM link state */ 357 #endif 358 359 pci_channel_state_t error_state; /* current connectivity state */ 360 struct device dev; /* Generic device interface */ 361 362 int cfg_size; /* Size of configuration space */ 363 364 /* 365 * Instead of touching interrupt line and base address registers 366 * directly, use the values stored here. They might be different! 367 */ 368 unsigned int irq; 369 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 370 371 bool match_driver; /* Skip attaching driver */ 372 /* These fields are used by common fixups */ 373 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 374 unsigned int multifunction:1;/* Part of multi-function device */ 375 /* keep track of device state */ 376 unsigned int is_added:1; 377 unsigned int is_busmaster:1; /* device is busmaster */ 378 unsigned int no_msi:1; /* device may not use msi */ 379 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 380 unsigned int block_cfg_access:1; /* config space access is blocked */ 381 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 382 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 383 unsigned int msi_enabled:1; 384 unsigned int msix_enabled:1; 385 unsigned int ari_enabled:1; /* ARI forwarding */ 386 unsigned int ats_enabled:1; /* Address Translation Service */ 387 unsigned int pasid_enabled:1; /* Process Address Space ID */ 388 unsigned int pri_enabled:1; /* Page Request Interface */ 389 unsigned int is_managed:1; 390 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 391 unsigned int state_saved:1; 392 unsigned int is_physfn:1; 393 unsigned int is_virtfn:1; 394 unsigned int reset_fn:1; 395 unsigned int is_hotplug_bridge:1; 396 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 397 unsigned int __aer_firmware_first_valid:1; 398 unsigned int __aer_firmware_first:1; 399 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 400 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 401 unsigned int irq_managed:1; 402 unsigned int has_secondary_link:1; 403 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 404 unsigned int is_probed:1; /* device probing in progress */ 405 pci_dev_flags_t dev_flags; 406 atomic_t enable_cnt; /* pci_enable_device has been called */ 407 408 u32 saved_config_space[16]; /* config space saved at suspend time */ 409 struct hlist_head saved_cap_space; 410 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 411 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 412 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 413 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 414 415 #ifdef CONFIG_PCIE_PTM 416 unsigned int ptm_root:1; 417 unsigned int ptm_enabled:1; 418 u8 ptm_granularity; 419 #endif 420 #ifdef CONFIG_PCI_MSI 421 const struct attribute_group **msi_irq_groups; 422 #endif 423 struct pci_vpd *vpd; 424 #ifdef CONFIG_PCI_ATS 425 union { 426 struct pci_sriov *sriov; /* SR-IOV capability related */ 427 struct pci_dev *physfn; /* the PF this VF is associated with */ 428 }; 429 u16 ats_cap; /* ATS Capability offset */ 430 u8 ats_stu; /* ATS Smallest Translation Unit */ 431 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 432 #endif 433 #ifdef CONFIG_PCI_PRI 434 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 435 #endif 436 #ifdef CONFIG_PCI_PASID 437 u16 pasid_features; 438 #endif 439 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 440 size_t romlen; /* Length of ROM if it's not from the BAR */ 441 char *driver_override; /* Driver name to force a match */ 442 443 unsigned long priv_flags; /* Private flags for the pci driver */ 444 }; 445 446 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 447 { 448 #ifdef CONFIG_PCI_IOV 449 if (dev->is_virtfn) 450 dev = dev->physfn; 451 #endif 452 return dev; 453 } 454 455 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 456 457 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 458 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 459 460 static inline int pci_channel_offline(struct pci_dev *pdev) 461 { 462 return (pdev->error_state != pci_channel_io_normal); 463 } 464 465 struct pci_host_bridge { 466 struct device dev; 467 struct pci_bus *bus; /* root bus */ 468 struct pci_ops *ops; 469 void *sysdata; 470 int busnr; 471 struct list_head windows; /* resource_entry */ 472 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */ 473 int (*map_irq)(const struct pci_dev *, u8, u8); 474 void (*release_fn)(struct pci_host_bridge *); 475 void *release_data; 476 struct msi_controller *msi; 477 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 478 unsigned int no_ext_tags:1; /* no Extended Tags */ 479 /* Resource alignment requirements */ 480 resource_size_t (*align_resource)(struct pci_dev *dev, 481 const struct resource *res, 482 resource_size_t start, 483 resource_size_t size, 484 resource_size_t align); 485 unsigned long private[0] ____cacheline_aligned; 486 }; 487 488 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 489 490 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 491 { 492 return (void *)bridge->private; 493 } 494 495 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 496 { 497 return container_of(priv, struct pci_host_bridge, private); 498 } 499 500 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 501 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 502 size_t priv); 503 void pci_free_host_bridge(struct pci_host_bridge *bridge); 504 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 505 506 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 507 void (*release_fn)(struct pci_host_bridge *), 508 void *release_data); 509 510 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 511 512 /* 513 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 514 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 515 * buses below host bridges or subtractive decode bridges) go in the list. 516 * Use pci_bus_for_each_resource() to iterate through all the resources. 517 */ 518 519 /* 520 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 521 * and there's no way to program the bridge with the details of the window. 522 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 523 * decode bit set, because they are explicit and can be programmed with _SRS. 524 */ 525 #define PCI_SUBTRACTIVE_DECODE 0x1 526 527 struct pci_bus_resource { 528 struct list_head list; 529 struct resource *res; 530 unsigned int flags; 531 }; 532 533 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 534 535 struct pci_bus { 536 struct list_head node; /* node in list of buses */ 537 struct pci_bus *parent; /* parent bus this bridge is on */ 538 struct list_head children; /* list of child buses */ 539 struct list_head devices; /* list of devices on this bus */ 540 struct pci_dev *self; /* bridge device as seen by parent */ 541 struct list_head slots; /* list of slots on this bus; 542 protected by pci_slot_mutex */ 543 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 544 struct list_head resources; /* address space routed to this bus */ 545 struct resource busn_res; /* bus numbers routed to this bus */ 546 547 struct pci_ops *ops; /* configuration access functions */ 548 struct msi_controller *msi; /* MSI controller */ 549 void *sysdata; /* hook for sys-specific extension */ 550 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 551 552 unsigned char number; /* bus number */ 553 unsigned char primary; /* number of primary bridge */ 554 unsigned char max_bus_speed; /* enum pci_bus_speed */ 555 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 556 #ifdef CONFIG_PCI_DOMAINS_GENERIC 557 int domain_nr; 558 #endif 559 560 char name[48]; 561 562 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 563 pci_bus_flags_t bus_flags; /* inherited by child buses */ 564 struct device *bridge; 565 struct device dev; 566 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 567 struct bin_attribute *legacy_mem; /* legacy mem */ 568 unsigned int is_added:1; 569 }; 570 571 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 572 573 /* 574 * Returns true if the PCI bus is root (behind host-PCI bridge), 575 * false otherwise 576 * 577 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 578 * This is incorrect because "virtual" buses added for SR-IOV (via 579 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 580 */ 581 static inline bool pci_is_root_bus(struct pci_bus *pbus) 582 { 583 return !(pbus->parent); 584 } 585 586 /** 587 * pci_is_bridge - check if the PCI device is a bridge 588 * @dev: PCI device 589 * 590 * Return true if the PCI device is bridge whether it has subordinate 591 * or not. 592 */ 593 static inline bool pci_is_bridge(struct pci_dev *dev) 594 { 595 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 596 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 597 } 598 599 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 600 { 601 dev = pci_physfn(dev); 602 if (pci_is_root_bus(dev->bus)) 603 return NULL; 604 605 return dev->bus->self; 606 } 607 608 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 609 void pci_put_host_bridge_device(struct device *dev); 610 611 #ifdef CONFIG_PCI_MSI 612 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 613 { 614 return pci_dev->msi_enabled || pci_dev->msix_enabled; 615 } 616 #else 617 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 618 #endif 619 620 /* 621 * Error values that may be returned by PCI functions. 622 */ 623 #define PCIBIOS_SUCCESSFUL 0x00 624 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 625 #define PCIBIOS_BAD_VENDOR_ID 0x83 626 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 627 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 628 #define PCIBIOS_SET_FAILED 0x88 629 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 630 631 /* 632 * Translate above to generic errno for passing back through non-PCI code. 633 */ 634 static inline int pcibios_err_to_errno(int err) 635 { 636 if (err <= PCIBIOS_SUCCESSFUL) 637 return err; /* Assume already errno */ 638 639 switch (err) { 640 case PCIBIOS_FUNC_NOT_SUPPORTED: 641 return -ENOENT; 642 case PCIBIOS_BAD_VENDOR_ID: 643 return -ENOTTY; 644 case PCIBIOS_DEVICE_NOT_FOUND: 645 return -ENODEV; 646 case PCIBIOS_BAD_REGISTER_NUMBER: 647 return -EFAULT; 648 case PCIBIOS_SET_FAILED: 649 return -EIO; 650 case PCIBIOS_BUFFER_TOO_SMALL: 651 return -ENOSPC; 652 } 653 654 return -ERANGE; 655 } 656 657 /* Low-level architecture-dependent routines */ 658 659 struct pci_ops { 660 int (*add_bus)(struct pci_bus *bus); 661 void (*remove_bus)(struct pci_bus *bus); 662 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 663 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 664 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 665 }; 666 667 /* 668 * ACPI needs to be able to access PCI config space before we've done a 669 * PCI bus scan and created pci_bus structures. 670 */ 671 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 672 int reg, int len, u32 *val); 673 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 674 int reg, int len, u32 val); 675 676 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 677 typedef u64 pci_bus_addr_t; 678 #else 679 typedef u32 pci_bus_addr_t; 680 #endif 681 682 struct pci_bus_region { 683 pci_bus_addr_t start; 684 pci_bus_addr_t end; 685 }; 686 687 struct pci_dynids { 688 spinlock_t lock; /* protects list, index */ 689 struct list_head list; /* for IDs added at runtime */ 690 }; 691 692 693 /* 694 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 695 * a set of callbacks in struct pci_error_handlers, that device driver 696 * will be notified of PCI bus errors, and will be driven to recovery 697 * when an error occurs. 698 */ 699 700 typedef unsigned int __bitwise pci_ers_result_t; 701 702 enum pci_ers_result { 703 /* no result/none/not supported in device driver */ 704 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 705 706 /* Device driver can recover without slot reset */ 707 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 708 709 /* Device driver wants slot to be reset. */ 710 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 711 712 /* Device has completely failed, is unrecoverable */ 713 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 714 715 /* Device driver is fully recovered and operational */ 716 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 717 718 /* No AER capabilities registered for the driver */ 719 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 720 }; 721 722 /* PCI bus error event callbacks */ 723 struct pci_error_handlers { 724 /* PCI bus error detected on this device */ 725 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 726 enum pci_channel_state error); 727 728 /* MMIO has been re-enabled, but not DMA */ 729 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 730 731 /* PCI slot has been reset */ 732 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 733 734 /* PCI function reset prepare or completed */ 735 void (*reset_prepare)(struct pci_dev *dev); 736 void (*reset_done)(struct pci_dev *dev); 737 738 /* Device driver may resume normal operations */ 739 void (*resume)(struct pci_dev *dev); 740 }; 741 742 743 struct module; 744 struct pci_driver { 745 struct list_head node; 746 const char *name; 747 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 748 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 749 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 750 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 751 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 752 int (*resume_early) (struct pci_dev *dev); 753 int (*resume) (struct pci_dev *dev); /* Device woken up */ 754 void (*shutdown) (struct pci_dev *dev); 755 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 756 const struct pci_error_handlers *err_handler; 757 const struct attribute_group **groups; 758 struct device_driver driver; 759 struct pci_dynids dynids; 760 }; 761 762 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 763 764 /** 765 * PCI_DEVICE - macro used to describe a specific pci device 766 * @vend: the 16 bit PCI Vendor ID 767 * @dev: the 16 bit PCI Device ID 768 * 769 * This macro is used to create a struct pci_device_id that matches a 770 * specific device. The subvendor and subdevice fields will be set to 771 * PCI_ANY_ID. 772 */ 773 #define PCI_DEVICE(vend,dev) \ 774 .vendor = (vend), .device = (dev), \ 775 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 776 777 /** 778 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 779 * @vend: the 16 bit PCI Vendor ID 780 * @dev: the 16 bit PCI Device ID 781 * @subvend: the 16 bit PCI Subvendor ID 782 * @subdev: the 16 bit PCI Subdevice ID 783 * 784 * This macro is used to create a struct pci_device_id that matches a 785 * specific device with subsystem information. 786 */ 787 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 788 .vendor = (vend), .device = (dev), \ 789 .subvendor = (subvend), .subdevice = (subdev) 790 791 /** 792 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 793 * @dev_class: the class, subclass, prog-if triple for this device 794 * @dev_class_mask: the class mask for this device 795 * 796 * This macro is used to create a struct pci_device_id that matches a 797 * specific PCI class. The vendor, device, subvendor, and subdevice 798 * fields will be set to PCI_ANY_ID. 799 */ 800 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 801 .class = (dev_class), .class_mask = (dev_class_mask), \ 802 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 803 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 804 805 /** 806 * PCI_VDEVICE - macro used to describe a specific pci device in short form 807 * @vend: the vendor name 808 * @dev: the 16 bit PCI Device ID 809 * 810 * This macro is used to create a struct pci_device_id that matches a 811 * specific PCI device. The subvendor, and subdevice fields will be set 812 * to PCI_ANY_ID. The macro allows the next field to follow as the device 813 * private data. 814 */ 815 816 #define PCI_VDEVICE(vend, dev) \ 817 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 818 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 819 820 enum { 821 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ 822 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ 823 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ 824 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ 825 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ 826 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 827 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ 828 }; 829 830 /* these external functions are only available when PCI support is enabled */ 831 #ifdef CONFIG_PCI 832 833 extern unsigned int pci_flags; 834 835 static inline void pci_set_flags(int flags) { pci_flags = flags; } 836 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 837 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 838 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 839 840 void pcie_bus_configure_settings(struct pci_bus *bus); 841 842 enum pcie_bus_config_types { 843 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 844 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 845 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 846 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 847 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 848 }; 849 850 extern enum pcie_bus_config_types pcie_bus_config; 851 852 extern struct bus_type pci_bus_type; 853 854 /* Do NOT directly access these two variables, unless you are arch-specific PCI 855 * code, or PCI core code. */ 856 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 857 /* Some device drivers need know if PCI is initiated */ 858 int no_pci_devices(void); 859 860 void pcibios_resource_survey_bus(struct pci_bus *bus); 861 void pcibios_bus_add_device(struct pci_dev *pdev); 862 void pcibios_add_bus(struct pci_bus *bus); 863 void pcibios_remove_bus(struct pci_bus *bus); 864 void pcibios_fixup_bus(struct pci_bus *); 865 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 866 /* Architecture-specific versions may override this (weak) */ 867 char *pcibios_setup(char *str); 868 869 /* Used only when drivers/pci/setup.c is used */ 870 resource_size_t pcibios_align_resource(void *, const struct resource *, 871 resource_size_t, 872 resource_size_t); 873 874 /* Weak but can be overriden by arch */ 875 void pci_fixup_cardbus(struct pci_bus *); 876 877 /* Generic PCI functions used internally */ 878 879 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 880 struct resource *res); 881 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 882 struct pci_bus_region *region); 883 void pcibios_scan_specific_bus(int busn); 884 struct pci_bus *pci_find_bus(int domain, int busnr); 885 void pci_bus_add_devices(const struct pci_bus *bus); 886 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 887 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 888 struct pci_ops *ops, void *sysdata, 889 struct list_head *resources); 890 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 891 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 892 void pci_bus_release_busn_res(struct pci_bus *b); 893 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 894 struct pci_ops *ops, void *sysdata, 895 struct list_head *resources); 896 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 897 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 898 int busnr); 899 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 900 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 901 const char *name, 902 struct hotplug_slot *hotplug); 903 void pci_destroy_slot(struct pci_slot *slot); 904 #ifdef CONFIG_SYSFS 905 void pci_dev_assign_slot(struct pci_dev *dev); 906 #else 907 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 908 #endif 909 int pci_scan_slot(struct pci_bus *bus, int devfn); 910 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 911 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 912 unsigned int pci_scan_child_bus(struct pci_bus *bus); 913 void pci_bus_add_device(struct pci_dev *dev); 914 void pci_read_bridge_bases(struct pci_bus *child); 915 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 916 struct resource *res); 917 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 918 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 919 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 920 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 921 struct pci_dev *pci_dev_get(struct pci_dev *dev); 922 void pci_dev_put(struct pci_dev *dev); 923 void pci_remove_bus(struct pci_bus *b); 924 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 925 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 926 void pci_stop_root_bus(struct pci_bus *bus); 927 void pci_remove_root_bus(struct pci_bus *bus); 928 void pci_setup_cardbus(struct pci_bus *bus); 929 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 930 void pci_sort_breadthfirst(void); 931 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 932 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 933 934 /* Generic PCI functions exported to card drivers */ 935 936 enum pci_lost_interrupt_reason { 937 PCI_LOST_IRQ_NO_INFORMATION = 0, 938 PCI_LOST_IRQ_DISABLE_MSI, 939 PCI_LOST_IRQ_DISABLE_MSIX, 940 PCI_LOST_IRQ_DISABLE_ACPI, 941 }; 942 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 943 int pci_find_capability(struct pci_dev *dev, int cap); 944 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 945 int pci_find_ext_capability(struct pci_dev *dev, int cap); 946 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 947 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 948 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 949 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 950 951 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 952 struct pci_dev *from); 953 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 954 unsigned int ss_vendor, unsigned int ss_device, 955 struct pci_dev *from); 956 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 957 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 958 unsigned int devfn); 959 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 960 unsigned int devfn) 961 { 962 return pci_get_domain_bus_and_slot(0, bus, devfn); 963 } 964 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 965 int pci_dev_present(const struct pci_device_id *ids); 966 967 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 968 int where, u8 *val); 969 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 970 int where, u16 *val); 971 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 972 int where, u32 *val); 973 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 974 int where, u8 val); 975 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 976 int where, u16 val); 977 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 978 int where, u32 val); 979 980 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 981 int where, int size, u32 *val); 982 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 983 int where, int size, u32 val); 984 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 985 int where, int size, u32 *val); 986 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 987 int where, int size, u32 val); 988 989 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 990 991 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 992 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 993 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 994 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 995 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 996 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 997 998 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 999 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1000 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1001 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1002 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1003 u16 clear, u16 set); 1004 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1005 u32 clear, u32 set); 1006 1007 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1008 u16 set) 1009 { 1010 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1011 } 1012 1013 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1014 u32 set) 1015 { 1016 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1017 } 1018 1019 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1020 u16 clear) 1021 { 1022 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1023 } 1024 1025 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1026 u32 clear) 1027 { 1028 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1029 } 1030 1031 /* user-space driven config access */ 1032 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1033 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1034 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1035 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1036 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1037 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1038 1039 int __must_check pci_enable_device(struct pci_dev *dev); 1040 int __must_check pci_enable_device_io(struct pci_dev *dev); 1041 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1042 int __must_check pci_reenable_device(struct pci_dev *); 1043 int __must_check pcim_enable_device(struct pci_dev *pdev); 1044 void pcim_pin_device(struct pci_dev *pdev); 1045 1046 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1047 { 1048 /* 1049 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1050 * writable and no quirk has marked the feature broken. 1051 */ 1052 return !pdev->broken_intx_masking; 1053 } 1054 1055 static inline int pci_is_enabled(struct pci_dev *pdev) 1056 { 1057 return (atomic_read(&pdev->enable_cnt) > 0); 1058 } 1059 1060 static inline int pci_is_managed(struct pci_dev *pdev) 1061 { 1062 return pdev->is_managed; 1063 } 1064 1065 void pci_disable_device(struct pci_dev *dev); 1066 1067 extern unsigned int pcibios_max_latency; 1068 void pci_set_master(struct pci_dev *dev); 1069 void pci_clear_master(struct pci_dev *dev); 1070 1071 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1072 int pci_set_cacheline_size(struct pci_dev *dev); 1073 #define HAVE_PCI_SET_MWI 1074 int __must_check pci_set_mwi(struct pci_dev *dev); 1075 int pci_try_set_mwi(struct pci_dev *dev); 1076 void pci_clear_mwi(struct pci_dev *dev); 1077 void pci_intx(struct pci_dev *dev, int enable); 1078 bool pci_check_and_mask_intx(struct pci_dev *dev); 1079 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1080 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1081 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1082 int pcix_get_max_mmrbc(struct pci_dev *dev); 1083 int pcix_get_mmrbc(struct pci_dev *dev); 1084 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1085 int pcie_get_readrq(struct pci_dev *dev); 1086 int pcie_set_readrq(struct pci_dev *dev, int rq); 1087 int pcie_get_mps(struct pci_dev *dev); 1088 int pcie_set_mps(struct pci_dev *dev, int mps); 1089 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1090 enum pcie_link_width *width); 1091 void pcie_flr(struct pci_dev *dev); 1092 int __pci_reset_function(struct pci_dev *dev); 1093 int __pci_reset_function_locked(struct pci_dev *dev); 1094 int pci_reset_function(struct pci_dev *dev); 1095 int pci_reset_function_locked(struct pci_dev *dev); 1096 int pci_try_reset_function(struct pci_dev *dev); 1097 int pci_probe_reset_slot(struct pci_slot *slot); 1098 int pci_reset_slot(struct pci_slot *slot); 1099 int pci_try_reset_slot(struct pci_slot *slot); 1100 int pci_probe_reset_bus(struct pci_bus *bus); 1101 int pci_reset_bus(struct pci_bus *bus); 1102 int pci_try_reset_bus(struct pci_bus *bus); 1103 void pci_reset_secondary_bus(struct pci_dev *dev); 1104 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1105 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1106 void pci_update_resource(struct pci_dev *dev, int resno); 1107 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1108 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1109 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1110 bool pci_device_is_present(struct pci_dev *pdev); 1111 void pci_ignore_hotplug(struct pci_dev *dev); 1112 1113 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1114 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1115 const char *fmt, ...); 1116 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1117 1118 /* ROM control related routines */ 1119 int pci_enable_rom(struct pci_dev *pdev); 1120 void pci_disable_rom(struct pci_dev *pdev); 1121 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1122 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1123 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1124 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1125 1126 /* Power management related routines */ 1127 int pci_save_state(struct pci_dev *dev); 1128 void pci_restore_state(struct pci_dev *dev); 1129 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1130 int pci_load_saved_state(struct pci_dev *dev, 1131 struct pci_saved_state *state); 1132 int pci_load_and_free_saved_state(struct pci_dev *dev, 1133 struct pci_saved_state **state); 1134 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1135 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1136 u16 cap); 1137 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1138 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1139 u16 cap, unsigned int size); 1140 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1141 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1142 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1143 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1144 void pci_pme_active(struct pci_dev *dev, bool enable); 1145 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1146 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1147 int pci_prepare_to_sleep(struct pci_dev *dev); 1148 int pci_back_from_sleep(struct pci_dev *dev); 1149 bool pci_dev_run_wake(struct pci_dev *dev); 1150 bool pci_check_pme_status(struct pci_dev *dev); 1151 void pci_pme_wakeup_bus(struct pci_bus *bus); 1152 void pci_d3cold_enable(struct pci_dev *dev); 1153 void pci_d3cold_disable(struct pci_dev *dev); 1154 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1155 1156 /* PCI Virtual Channel */ 1157 int pci_save_vc_state(struct pci_dev *dev); 1158 void pci_restore_vc_state(struct pci_dev *dev); 1159 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1160 1161 /* For use by arch with custom probe code */ 1162 void set_pcie_port_type(struct pci_dev *pdev); 1163 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1164 1165 /* Functions for PCI Hotplug drivers to use */ 1166 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1167 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1168 unsigned int pci_rescan_bus(struct pci_bus *bus); 1169 void pci_lock_rescan_remove(void); 1170 void pci_unlock_rescan_remove(void); 1171 1172 /* Vital product data routines */ 1173 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1174 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1175 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1176 1177 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1178 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1179 void pci_bus_assign_resources(const struct pci_bus *bus); 1180 void pci_bus_claim_resources(struct pci_bus *bus); 1181 void pci_bus_size_bridges(struct pci_bus *bus); 1182 int pci_claim_resource(struct pci_dev *, int); 1183 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1184 void pci_assign_unassigned_resources(void); 1185 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1186 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1187 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1188 void pdev_enable_device(struct pci_dev *); 1189 int pci_enable_resources(struct pci_dev *, int mask); 1190 void pci_assign_irq(struct pci_dev *dev); 1191 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1192 #define HAVE_PCI_REQ_REGIONS 2 1193 int __must_check pci_request_regions(struct pci_dev *, const char *); 1194 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1195 void pci_release_regions(struct pci_dev *); 1196 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1197 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1198 void pci_release_region(struct pci_dev *, int); 1199 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1200 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1201 void pci_release_selected_regions(struct pci_dev *, int); 1202 1203 /* drivers/pci/bus.c */ 1204 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1205 void pci_bus_put(struct pci_bus *bus); 1206 void pci_add_resource(struct list_head *resources, struct resource *res); 1207 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1208 resource_size_t offset); 1209 void pci_free_resource_list(struct list_head *resources); 1210 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1211 unsigned int flags); 1212 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1213 void pci_bus_remove_resources(struct pci_bus *bus); 1214 int devm_request_pci_bus_resources(struct device *dev, 1215 struct list_head *resources); 1216 1217 #define pci_bus_for_each_resource(bus, res, i) \ 1218 for (i = 0; \ 1219 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1220 i++) 1221 1222 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1223 struct resource *res, resource_size_t size, 1224 resource_size_t align, resource_size_t min, 1225 unsigned long type_mask, 1226 resource_size_t (*alignf)(void *, 1227 const struct resource *, 1228 resource_size_t, 1229 resource_size_t), 1230 void *alignf_data); 1231 1232 1233 int pci_register_io_range(phys_addr_t addr, resource_size_t size); 1234 unsigned long pci_address_to_pio(phys_addr_t addr); 1235 phys_addr_t pci_pio_to_address(unsigned long pio); 1236 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1237 void pci_unmap_iospace(struct resource *res); 1238 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1239 resource_size_t offset, 1240 resource_size_t size); 1241 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1242 struct resource *res); 1243 1244 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1245 { 1246 struct pci_bus_region region; 1247 1248 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1249 return region.start; 1250 } 1251 1252 /* Proper probing supporting hot-pluggable devices */ 1253 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1254 const char *mod_name); 1255 1256 /* 1257 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1258 */ 1259 #define pci_register_driver(driver) \ 1260 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1261 1262 void pci_unregister_driver(struct pci_driver *dev); 1263 1264 /** 1265 * module_pci_driver() - Helper macro for registering a PCI driver 1266 * @__pci_driver: pci_driver struct 1267 * 1268 * Helper macro for PCI drivers which do not do anything special in module 1269 * init/exit. This eliminates a lot of boilerplate. Each module may only 1270 * use this macro once, and calling it replaces module_init() and module_exit() 1271 */ 1272 #define module_pci_driver(__pci_driver) \ 1273 module_driver(__pci_driver, pci_register_driver, \ 1274 pci_unregister_driver) 1275 1276 /** 1277 * builtin_pci_driver() - Helper macro for registering a PCI driver 1278 * @__pci_driver: pci_driver struct 1279 * 1280 * Helper macro for PCI drivers which do not do anything special in their 1281 * init code. This eliminates a lot of boilerplate. Each driver may only 1282 * use this macro once, and calling it replaces device_initcall(...) 1283 */ 1284 #define builtin_pci_driver(__pci_driver) \ 1285 builtin_driver(__pci_driver, pci_register_driver) 1286 1287 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1288 int pci_add_dynid(struct pci_driver *drv, 1289 unsigned int vendor, unsigned int device, 1290 unsigned int subvendor, unsigned int subdevice, 1291 unsigned int class, unsigned int class_mask, 1292 unsigned long driver_data); 1293 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1294 struct pci_dev *dev); 1295 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1296 int pass); 1297 1298 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1299 void *userdata); 1300 int pci_cfg_space_size(struct pci_dev *dev); 1301 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1302 void pci_setup_bridge(struct pci_bus *bus); 1303 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1304 unsigned long type); 1305 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1306 1307 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1308 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1309 1310 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1311 unsigned int command_bits, u32 flags); 1312 1313 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ 1314 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ 1315 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ 1316 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ 1317 #define PCI_IRQ_ALL_TYPES \ 1318 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1319 1320 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1321 1322 #include <linux/pci-dma.h> 1323 #include <linux/dmapool.h> 1324 1325 #define pci_pool dma_pool 1326 #define pci_pool_create(name, pdev, size, align, allocation) \ 1327 dma_pool_create(name, &pdev->dev, size, align, allocation) 1328 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1329 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1330 #define pci_pool_zalloc(pool, flags, handle) \ 1331 dma_pool_zalloc(pool, flags, handle) 1332 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1333 1334 struct msix_entry { 1335 u32 vector; /* kernel uses to write allocated vector */ 1336 u16 entry; /* driver uses to specify entry, OS writes */ 1337 }; 1338 1339 #ifdef CONFIG_PCI_MSI 1340 int pci_msi_vec_count(struct pci_dev *dev); 1341 void pci_disable_msi(struct pci_dev *dev); 1342 int pci_msix_vec_count(struct pci_dev *dev); 1343 void pci_disable_msix(struct pci_dev *dev); 1344 void pci_restore_msi_state(struct pci_dev *dev); 1345 int pci_msi_enabled(void); 1346 int pci_enable_msi(struct pci_dev *dev); 1347 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1348 int minvec, int maxvec); 1349 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1350 struct msix_entry *entries, int nvec) 1351 { 1352 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1353 if (rc < 0) 1354 return rc; 1355 return 0; 1356 } 1357 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1358 unsigned int max_vecs, unsigned int flags, 1359 const struct irq_affinity *affd); 1360 1361 void pci_free_irq_vectors(struct pci_dev *dev); 1362 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1363 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1364 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1365 1366 #else 1367 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1368 static inline void pci_disable_msi(struct pci_dev *dev) { } 1369 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1370 static inline void pci_disable_msix(struct pci_dev *dev) { } 1371 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1372 static inline int pci_msi_enabled(void) { return 0; } 1373 static inline int pci_enable_msi(struct pci_dev *dev) 1374 { return -ENOSYS; } 1375 static inline int pci_enable_msix_range(struct pci_dev *dev, 1376 struct msix_entry *entries, int minvec, int maxvec) 1377 { return -ENOSYS; } 1378 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1379 struct msix_entry *entries, int nvec) 1380 { return -ENOSYS; } 1381 1382 static inline int 1383 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1384 unsigned int max_vecs, unsigned int flags, 1385 const struct irq_affinity *aff_desc) 1386 { 1387 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1388 return 1; 1389 return -ENOSPC; 1390 } 1391 1392 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1393 { 1394 } 1395 1396 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1397 { 1398 if (WARN_ON_ONCE(nr > 0)) 1399 return -EINVAL; 1400 return dev->irq; 1401 } 1402 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1403 int vec) 1404 { 1405 return cpu_possible_mask; 1406 } 1407 1408 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1409 { 1410 return first_online_node; 1411 } 1412 #endif 1413 1414 static inline int 1415 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1416 unsigned int max_vecs, unsigned int flags) 1417 { 1418 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1419 NULL); 1420 } 1421 1422 /** 1423 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1424 * @d: the INTx IRQ domain 1425 * @node: the DT node for the device whose interrupt we're translating 1426 * @intspec: the interrupt specifier data from the DT 1427 * @intsize: the number of entries in @intspec 1428 * @out_hwirq: pointer at which to write the hwirq number 1429 * @out_type: pointer at which to write the interrupt type 1430 * 1431 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1432 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1433 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1434 * INTx value to obtain the hwirq number. 1435 * 1436 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1437 */ 1438 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1439 struct device_node *node, 1440 const u32 *intspec, 1441 unsigned int intsize, 1442 unsigned long *out_hwirq, 1443 unsigned int *out_type) 1444 { 1445 const u32 intx = intspec[0]; 1446 1447 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1448 return -EINVAL; 1449 1450 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1451 return 0; 1452 } 1453 1454 #ifdef CONFIG_PCIEPORTBUS 1455 extern bool pcie_ports_disabled; 1456 extern bool pcie_ports_auto; 1457 #else 1458 #define pcie_ports_disabled true 1459 #define pcie_ports_auto false 1460 #endif 1461 1462 #ifdef CONFIG_PCIEASPM 1463 bool pcie_aspm_support_enabled(void); 1464 #else 1465 static inline bool pcie_aspm_support_enabled(void) { return false; } 1466 #endif 1467 1468 #ifdef CONFIG_PCIEAER 1469 void pci_no_aer(void); 1470 bool pci_aer_available(void); 1471 int pci_aer_init(struct pci_dev *dev); 1472 #else 1473 static inline void pci_no_aer(void) { } 1474 static inline bool pci_aer_available(void) { return false; } 1475 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } 1476 #endif 1477 1478 #ifdef CONFIG_PCIE_ECRC 1479 void pcie_set_ecrc_checking(struct pci_dev *dev); 1480 void pcie_ecrc_get_policy(char *str); 1481 #else 1482 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1483 static inline void pcie_ecrc_get_policy(char *str) { } 1484 #endif 1485 1486 #ifdef CONFIG_HT_IRQ 1487 /* The functions a driver should call */ 1488 int ht_create_irq(struct pci_dev *dev, int idx); 1489 void ht_destroy_irq(unsigned int irq); 1490 #endif /* CONFIG_HT_IRQ */ 1491 1492 #ifdef CONFIG_PCI_ATS 1493 /* Address Translation Service */ 1494 void pci_ats_init(struct pci_dev *dev); 1495 int pci_enable_ats(struct pci_dev *dev, int ps); 1496 void pci_disable_ats(struct pci_dev *dev); 1497 int pci_ats_queue_depth(struct pci_dev *dev); 1498 #else 1499 static inline void pci_ats_init(struct pci_dev *d) { } 1500 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1501 static inline void pci_disable_ats(struct pci_dev *d) { } 1502 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1503 #endif 1504 1505 #ifdef CONFIG_PCIE_PTM 1506 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1507 #else 1508 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1509 { return -EINVAL; } 1510 #endif 1511 1512 void pci_cfg_access_lock(struct pci_dev *dev); 1513 bool pci_cfg_access_trylock(struct pci_dev *dev); 1514 void pci_cfg_access_unlock(struct pci_dev *dev); 1515 1516 /* 1517 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1518 * a PCI domain is defined to be a set of PCI buses which share 1519 * configuration space. 1520 */ 1521 #ifdef CONFIG_PCI_DOMAINS 1522 extern int pci_domains_supported; 1523 int pci_get_new_domain_nr(void); 1524 #else 1525 enum { pci_domains_supported = 0 }; 1526 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1527 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1528 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1529 #endif /* CONFIG_PCI_DOMAINS */ 1530 1531 /* 1532 * Generic implementation for PCI domain support. If your 1533 * architecture does not need custom management of PCI 1534 * domains then this implementation will be used 1535 */ 1536 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1537 static inline int pci_domain_nr(struct pci_bus *bus) 1538 { 1539 return bus->domain_nr; 1540 } 1541 #ifdef CONFIG_ACPI 1542 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1543 #else 1544 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1545 { return 0; } 1546 #endif 1547 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1548 #endif 1549 1550 /* some architectures require additional setup to direct VGA traffic */ 1551 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1552 unsigned int command_bits, u32 flags); 1553 void pci_register_set_vga_state(arch_set_vga_state_t func); 1554 1555 static inline int 1556 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1557 { 1558 return pci_request_selected_regions(pdev, 1559 pci_select_bars(pdev, IORESOURCE_IO), name); 1560 } 1561 1562 static inline void 1563 pci_release_io_regions(struct pci_dev *pdev) 1564 { 1565 return pci_release_selected_regions(pdev, 1566 pci_select_bars(pdev, IORESOURCE_IO)); 1567 } 1568 1569 static inline int 1570 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1571 { 1572 return pci_request_selected_regions(pdev, 1573 pci_select_bars(pdev, IORESOURCE_MEM), name); 1574 } 1575 1576 static inline void 1577 pci_release_mem_regions(struct pci_dev *pdev) 1578 { 1579 return pci_release_selected_regions(pdev, 1580 pci_select_bars(pdev, IORESOURCE_MEM)); 1581 } 1582 1583 #else /* CONFIG_PCI is not enabled */ 1584 1585 static inline void pci_set_flags(int flags) { } 1586 static inline void pci_add_flags(int flags) { } 1587 static inline void pci_clear_flags(int flags) { } 1588 static inline int pci_has_flag(int flag) { return 0; } 1589 1590 /* 1591 * If the system does not have PCI, clearly these return errors. Define 1592 * these as simple inline functions to avoid hair in drivers. 1593 */ 1594 1595 #define _PCI_NOP(o, s, t) \ 1596 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1597 int where, t val) \ 1598 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1599 1600 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1601 _PCI_NOP(o, word, u16 x) \ 1602 _PCI_NOP(o, dword, u32 x) 1603 _PCI_NOP_ALL(read, *) 1604 _PCI_NOP_ALL(write,) 1605 1606 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1607 unsigned int device, 1608 struct pci_dev *from) 1609 { return NULL; } 1610 1611 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1612 unsigned int device, 1613 unsigned int ss_vendor, 1614 unsigned int ss_device, 1615 struct pci_dev *from) 1616 { return NULL; } 1617 1618 static inline struct pci_dev *pci_get_class(unsigned int class, 1619 struct pci_dev *from) 1620 { return NULL; } 1621 1622 #define pci_dev_present(ids) (0) 1623 #define no_pci_devices() (1) 1624 #define pci_dev_put(dev) do { } while (0) 1625 1626 static inline void pci_set_master(struct pci_dev *dev) { } 1627 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1628 static inline void pci_disable_device(struct pci_dev *dev) { } 1629 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1630 { return -EBUSY; } 1631 static inline int __pci_register_driver(struct pci_driver *drv, 1632 struct module *owner) 1633 { return 0; } 1634 static inline int pci_register_driver(struct pci_driver *drv) 1635 { return 0; } 1636 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1637 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1638 { return 0; } 1639 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1640 int cap) 1641 { return 0; } 1642 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1643 { return 0; } 1644 1645 /* Power management related routines */ 1646 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1647 static inline void pci_restore_state(struct pci_dev *dev) { } 1648 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1649 { return 0; } 1650 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1651 { return 0; } 1652 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1653 pm_message_t state) 1654 { return PCI_D0; } 1655 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1656 int enable) 1657 { return 0; } 1658 1659 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1660 struct resource *res) 1661 { return NULL; } 1662 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1663 { return -EIO; } 1664 static inline void pci_release_regions(struct pci_dev *dev) { } 1665 1666 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1667 1668 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1669 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1670 { return 0; } 1671 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1672 1673 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1674 { return NULL; } 1675 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1676 unsigned int devfn) 1677 { return NULL; } 1678 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1679 unsigned int devfn) 1680 { return NULL; } 1681 1682 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1683 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1684 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1685 1686 #define dev_is_pci(d) (false) 1687 #define dev_is_pf(d) (false) 1688 #endif /* CONFIG_PCI */ 1689 1690 /* Include architecture-dependent settings and functions */ 1691 1692 #include <asm/pci.h> 1693 1694 /* These two functions provide almost identical functionality. Depennding 1695 * on the architecture, one will be implemented as a wrapper around the 1696 * other (in drivers/pci/mmap.c). 1697 * 1698 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1699 * is expected to be an offset within that region. 1700 * 1701 * pci_mmap_page_range() is the legacy architecture-specific interface, 1702 * which accepts a "user visible" resource address converted by 1703 * pci_resource_to_user(), as used in the legacy mmap() interface in 1704 * /proc/bus/pci/. 1705 */ 1706 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1707 struct vm_area_struct *vma, 1708 enum pci_mmap_state mmap_state, int write_combine); 1709 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1710 struct vm_area_struct *vma, 1711 enum pci_mmap_state mmap_state, int write_combine); 1712 1713 #ifndef arch_can_pci_mmap_wc 1714 #define arch_can_pci_mmap_wc() 0 1715 #endif 1716 1717 #ifndef arch_can_pci_mmap_io 1718 #define arch_can_pci_mmap_io() 0 1719 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1720 #else 1721 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1722 #endif 1723 1724 #ifndef pci_root_bus_fwnode 1725 #define pci_root_bus_fwnode(bus) NULL 1726 #endif 1727 1728 /* these helpers provide future and backwards compatibility 1729 * for accessing popular PCI BAR info */ 1730 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1731 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1732 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1733 #define pci_resource_len(dev,bar) \ 1734 ((pci_resource_start((dev), (bar)) == 0 && \ 1735 pci_resource_end((dev), (bar)) == \ 1736 pci_resource_start((dev), (bar))) ? 0 : \ 1737 \ 1738 (pci_resource_end((dev), (bar)) - \ 1739 pci_resource_start((dev), (bar)) + 1)) 1740 1741 /* Similar to the helpers above, these manipulate per-pci_dev 1742 * driver-specific data. They are really just a wrapper around 1743 * the generic device structure functions of these calls. 1744 */ 1745 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1746 { 1747 return dev_get_drvdata(&pdev->dev); 1748 } 1749 1750 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1751 { 1752 dev_set_drvdata(&pdev->dev, data); 1753 } 1754 1755 /* If you want to know what to call your pci_dev, ask this function. 1756 * Again, it's a wrapper around the generic device. 1757 */ 1758 static inline const char *pci_name(const struct pci_dev *pdev) 1759 { 1760 return dev_name(&pdev->dev); 1761 } 1762 1763 1764 /* Some archs don't want to expose struct resource to userland as-is 1765 * in sysfs and /proc 1766 */ 1767 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1768 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1769 const struct resource *rsrc, 1770 resource_size_t *start, resource_size_t *end); 1771 #else 1772 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1773 const struct resource *rsrc, resource_size_t *start, 1774 resource_size_t *end) 1775 { 1776 *start = rsrc->start; 1777 *end = rsrc->end; 1778 } 1779 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1780 1781 1782 /* 1783 * The world is not perfect and supplies us with broken PCI devices. 1784 * For at least a part of these bugs we need a work-around, so both 1785 * generic (drivers/pci/quirks.c) and per-architecture code can define 1786 * fixup hooks to be called for particular buggy devices. 1787 */ 1788 1789 struct pci_fixup { 1790 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1791 u16 device; /* You can use PCI_ANY_ID here of course */ 1792 u32 class; /* You can use PCI_ANY_ID here too */ 1793 unsigned int class_shift; /* should be 0, 8, 16 */ 1794 void (*hook)(struct pci_dev *dev); 1795 }; 1796 1797 enum pci_fixup_pass { 1798 pci_fixup_early, /* Before probing BARs */ 1799 pci_fixup_header, /* After reading configuration header */ 1800 pci_fixup_final, /* Final phase of device fixups */ 1801 pci_fixup_enable, /* pci_enable_device() time */ 1802 pci_fixup_resume, /* pci_device_resume() */ 1803 pci_fixup_suspend, /* pci_device_suspend() */ 1804 pci_fixup_resume_early, /* pci_device_resume_early() */ 1805 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1806 }; 1807 1808 /* Anonymous variables would be nice... */ 1809 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1810 class_shift, hook) \ 1811 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1812 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1813 = { vendor, device, class, class_shift, hook }; 1814 1815 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1816 class_shift, hook) \ 1817 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1818 hook, vendor, device, class, class_shift, hook) 1819 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1820 class_shift, hook) \ 1821 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1822 hook, vendor, device, class, class_shift, hook) 1823 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1824 class_shift, hook) \ 1825 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1826 hook, vendor, device, class, class_shift, hook) 1827 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1828 class_shift, hook) \ 1829 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1830 hook, vendor, device, class, class_shift, hook) 1831 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1832 class_shift, hook) \ 1833 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1834 resume##hook, vendor, device, class, \ 1835 class_shift, hook) 1836 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1837 class_shift, hook) \ 1838 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1839 resume_early##hook, vendor, device, \ 1840 class, class_shift, hook) 1841 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1842 class_shift, hook) \ 1843 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1844 suspend##hook, vendor, device, class, \ 1845 class_shift, hook) 1846 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1847 class_shift, hook) \ 1848 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1849 suspend_late##hook, vendor, device, \ 1850 class, class_shift, hook) 1851 1852 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1853 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1854 hook, vendor, device, PCI_ANY_ID, 0, hook) 1855 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1856 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1857 hook, vendor, device, PCI_ANY_ID, 0, hook) 1858 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1859 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1860 hook, vendor, device, PCI_ANY_ID, 0, hook) 1861 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1862 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1863 hook, vendor, device, PCI_ANY_ID, 0, hook) 1864 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1865 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1866 resume##hook, vendor, device, \ 1867 PCI_ANY_ID, 0, hook) 1868 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1869 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1870 resume_early##hook, vendor, device, \ 1871 PCI_ANY_ID, 0, hook) 1872 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1873 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1874 suspend##hook, vendor, device, \ 1875 PCI_ANY_ID, 0, hook) 1876 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1877 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1878 suspend_late##hook, vendor, device, \ 1879 PCI_ANY_ID, 0, hook) 1880 1881 #ifdef CONFIG_PCI_QUIRKS 1882 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1883 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1884 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1885 #else 1886 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1887 struct pci_dev *dev) { } 1888 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1889 u16 acs_flags) 1890 { 1891 return -ENOTTY; 1892 } 1893 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1894 { 1895 return -ENOTTY; 1896 } 1897 #endif 1898 1899 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1900 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1901 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1902 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1903 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1904 const char *name); 1905 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1906 1907 extern int pci_pci_problems; 1908 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1909 #define PCIPCI_TRITON 2 1910 #define PCIPCI_NATOMA 4 1911 #define PCIPCI_VIAETBF 8 1912 #define PCIPCI_VSFX 16 1913 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1914 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1915 1916 extern unsigned long pci_cardbus_io_size; 1917 extern unsigned long pci_cardbus_mem_size; 1918 extern u8 pci_dfl_cache_line_size; 1919 extern u8 pci_cache_line_size; 1920 1921 extern unsigned long pci_hotplug_io_size; 1922 extern unsigned long pci_hotplug_mem_size; 1923 extern unsigned long pci_hotplug_bus_size; 1924 1925 /* Architecture-specific versions may override these (weak) */ 1926 void pcibios_disable_device(struct pci_dev *dev); 1927 void pcibios_set_master(struct pci_dev *dev); 1928 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1929 enum pcie_reset_state state); 1930 int pcibios_add_device(struct pci_dev *dev); 1931 void pcibios_release_device(struct pci_dev *dev); 1932 void pcibios_penalize_isa_irq(int irq, int active); 1933 int pcibios_alloc_irq(struct pci_dev *dev); 1934 void pcibios_free_irq(struct pci_dev *dev); 1935 1936 #ifdef CONFIG_HIBERNATE_CALLBACKS 1937 extern struct dev_pm_ops pcibios_pm_ops; 1938 #endif 1939 1940 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1941 void __init pci_mmcfg_early_init(void); 1942 void __init pci_mmcfg_late_init(void); 1943 #else 1944 static inline void pci_mmcfg_early_init(void) { } 1945 static inline void pci_mmcfg_late_init(void) { } 1946 #endif 1947 1948 int pci_ext_cfg_avail(void); 1949 1950 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1951 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1952 1953 #ifdef CONFIG_PCI_IOV 1954 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1955 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1956 1957 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1958 void pci_disable_sriov(struct pci_dev *dev); 1959 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset); 1960 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset); 1961 int pci_num_vf(struct pci_dev *dev); 1962 int pci_vfs_assigned(struct pci_dev *dev); 1963 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1964 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1965 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1966 #else 1967 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1968 { 1969 return -ENOSYS; 1970 } 1971 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1972 { 1973 return -ENOSYS; 1974 } 1975 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1976 { return -ENODEV; } 1977 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset) 1978 { 1979 return -ENOSYS; 1980 } 1981 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 1982 int id, int reset) { } 1983 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1984 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1985 static inline int pci_vfs_assigned(struct pci_dev *dev) 1986 { return 0; } 1987 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1988 { return 0; } 1989 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1990 { return 0; } 1991 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1992 { return 0; } 1993 #endif 1994 1995 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1996 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1997 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1998 #endif 1999 2000 /** 2001 * pci_pcie_cap - get the saved PCIe capability offset 2002 * @dev: PCI device 2003 * 2004 * PCIe capability offset is calculated at PCI device initialization 2005 * time and saved in the data structure. This function returns saved 2006 * PCIe capability offset. Using this instead of pci_find_capability() 2007 * reduces unnecessary search in the PCI configuration space. If you 2008 * need to calculate PCIe capability offset from raw device for some 2009 * reasons, please use pci_find_capability() instead. 2010 */ 2011 static inline int pci_pcie_cap(struct pci_dev *dev) 2012 { 2013 return dev->pcie_cap; 2014 } 2015 2016 /** 2017 * pci_is_pcie - check if the PCI device is PCI Express capable 2018 * @dev: PCI device 2019 * 2020 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2021 */ 2022 static inline bool pci_is_pcie(struct pci_dev *dev) 2023 { 2024 return pci_pcie_cap(dev); 2025 } 2026 2027 /** 2028 * pcie_caps_reg - get the PCIe Capabilities Register 2029 * @dev: PCI device 2030 */ 2031 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2032 { 2033 return dev->pcie_flags_reg; 2034 } 2035 2036 /** 2037 * pci_pcie_type - get the PCIe device/port type 2038 * @dev: PCI device 2039 */ 2040 static inline int pci_pcie_type(const struct pci_dev *dev) 2041 { 2042 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2043 } 2044 2045 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2046 { 2047 while (1) { 2048 if (!pci_is_pcie(dev)) 2049 break; 2050 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2051 return dev; 2052 if (!dev->bus->self) 2053 break; 2054 dev = dev->bus->self; 2055 } 2056 return NULL; 2057 } 2058 2059 void pci_request_acs(void); 2060 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2061 bool pci_acs_path_enabled(struct pci_dev *start, 2062 struct pci_dev *end, u16 acs_flags); 2063 2064 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2065 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2066 2067 /* Large Resource Data Type Tag Item Names */ 2068 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2069 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2070 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2071 2072 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2073 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2074 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2075 2076 /* Small Resource Data Type Tag Item Names */ 2077 #define PCI_VPD_STIN_END 0x0f /* End */ 2078 2079 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2080 2081 #define PCI_VPD_SRDT_TIN_MASK 0x78 2082 #define PCI_VPD_SRDT_LEN_MASK 0x07 2083 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2084 2085 #define PCI_VPD_LRDT_TAG_SIZE 3 2086 #define PCI_VPD_SRDT_TAG_SIZE 1 2087 2088 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2089 2090 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2091 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2092 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2093 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2094 2095 /** 2096 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2097 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2098 * 2099 * Returns the extracted Large Resource Data Type length. 2100 */ 2101 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2102 { 2103 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2104 } 2105 2106 /** 2107 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2108 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2109 * 2110 * Returns the extracted Large Resource Data Type Tag item. 2111 */ 2112 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2113 { 2114 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2115 } 2116 2117 /** 2118 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2119 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2120 * 2121 * Returns the extracted Small Resource Data Type length. 2122 */ 2123 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2124 { 2125 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2126 } 2127 2128 /** 2129 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2130 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2131 * 2132 * Returns the extracted Small Resource Data Type Tag Item. 2133 */ 2134 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2135 { 2136 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2137 } 2138 2139 /** 2140 * pci_vpd_info_field_size - Extracts the information field length 2141 * @lrdt: Pointer to the beginning of an information field header 2142 * 2143 * Returns the extracted information field length. 2144 */ 2145 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2146 { 2147 return info_field[2]; 2148 } 2149 2150 /** 2151 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2152 * @buf: Pointer to buffered vpd data 2153 * @off: The offset into the buffer at which to begin the search 2154 * @len: The length of the vpd buffer 2155 * @rdt: The Resource Data Type to search for 2156 * 2157 * Returns the index where the Resource Data Type was found or 2158 * -ENOENT otherwise. 2159 */ 2160 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2161 2162 /** 2163 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2164 * @buf: Pointer to buffered vpd data 2165 * @off: The offset into the buffer at which to begin the search 2166 * @len: The length of the buffer area, relative to off, in which to search 2167 * @kw: The keyword to search for 2168 * 2169 * Returns the index where the information field keyword was found or 2170 * -ENOENT otherwise. 2171 */ 2172 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2173 unsigned int len, const char *kw); 2174 2175 /* PCI <-> OF binding helpers */ 2176 #ifdef CONFIG_OF 2177 struct device_node; 2178 struct irq_domain; 2179 void pci_set_of_node(struct pci_dev *dev); 2180 void pci_release_of_node(struct pci_dev *dev); 2181 void pci_set_bus_of_node(struct pci_bus *bus); 2182 void pci_release_bus_of_node(struct pci_bus *bus); 2183 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2184 2185 /* Arch may override this (weak) */ 2186 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2187 2188 static inline struct device_node * 2189 pci_device_to_OF_node(const struct pci_dev *pdev) 2190 { 2191 return pdev ? pdev->dev.of_node : NULL; 2192 } 2193 2194 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2195 { 2196 return bus ? bus->dev.of_node : NULL; 2197 } 2198 2199 #else /* CONFIG_OF */ 2200 static inline void pci_set_of_node(struct pci_dev *dev) { } 2201 static inline void pci_release_of_node(struct pci_dev *dev) { } 2202 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2203 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2204 static inline struct device_node * 2205 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 2206 static inline struct irq_domain * 2207 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2208 #endif /* CONFIG_OF */ 2209 2210 #ifdef CONFIG_ACPI 2211 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2212 2213 void 2214 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2215 #else 2216 static inline struct irq_domain * 2217 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2218 #endif 2219 2220 #ifdef CONFIG_EEH 2221 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2222 { 2223 return pdev->dev.archdata.edev; 2224 } 2225 #endif 2226 2227 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2228 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2229 int pci_for_each_dma_alias(struct pci_dev *pdev, 2230 int (*fn)(struct pci_dev *pdev, 2231 u16 alias, void *data), void *data); 2232 2233 /* helper functions for operation of device flag */ 2234 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2235 { 2236 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2237 } 2238 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2239 { 2240 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2241 } 2242 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2243 { 2244 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2245 } 2246 2247 /** 2248 * pci_ari_enabled - query ARI forwarding status 2249 * @bus: the PCI bus 2250 * 2251 * Returns true if ARI forwarding is enabled. 2252 */ 2253 static inline bool pci_ari_enabled(struct pci_bus *bus) 2254 { 2255 return bus->self && bus->self->ari_enabled; 2256 } 2257 2258 /** 2259 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2260 * @pdev: PCI device to check 2261 * 2262 * Walk upwards from @pdev and check for each encountered bridge if it's part 2263 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2264 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2265 */ 2266 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2267 { 2268 struct pci_dev *parent = pdev; 2269 2270 if (pdev->is_thunderbolt) 2271 return true; 2272 2273 while ((parent = pci_upstream_bridge(parent))) 2274 if (parent->is_thunderbolt) 2275 return true; 2276 2277 return false; 2278 } 2279 2280 /* provide the legacy pci_dma_* API */ 2281 #include <linux/pci-dma-compat.h> 2282 2283 #endif /* LINUX_PCI_H */ 2284