1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * For more information, please consult the following manuals (look at 10 * http://www.pcisig.com/ for how to get them): 11 * 12 * PCI BIOS Specification 13 * PCI Local Bus Specification 14 * PCI to PCI Bridge Specification 15 * PCI System Design Guide 16 */ 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 21 #include <linux/mod_devicetable.h> 22 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/list.h> 27 #include <linux/compiler.h> 28 #include <linux/errno.h> 29 #include <linux/kobject.h> 30 #include <linux/atomic.h> 31 #include <linux/device.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/resource_ext.h> 35 #include <uapi/linux/pci.h> 36 37 #include <linux/pci_ids.h> 38 39 /* 40 * The PCI interface treats multi-function devices as independent 41 * devices. The slot/function address of each device is encoded 42 * in a single byte as follows: 43 * 44 * 7:3 = slot 45 * 2:0 = function 46 * 47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 48 * In the interest of not exposing interfaces to user-space unnecessarily, 49 * the following kernel-only defines are being added here. 50 */ 51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 54 55 /* pci_slot represents a physical slot */ 56 struct pci_slot { 57 struct pci_bus *bus; /* Bus this slot is on */ 58 struct list_head list; /* Node in list of slots */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 61 struct kobject kobj; 62 }; 63 64 static inline const char *pci_slot_name(const struct pci_slot *slot) 65 { 66 return kobject_name(&slot->kobj); 67 } 68 69 /* File state for mmap()s on /proc/bus/pci/X/Y */ 70 enum pci_mmap_state { 71 pci_mmap_io, 72 pci_mmap_mem 73 }; 74 75 /* For PCI devices, the region numbers are assigned this way: */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* Device-specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* Resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* Total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* Preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 /** 105 * enum pci_interrupt_pin - PCI INTx interrupt values 106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 107 * @PCI_INTERRUPT_INTA: PCI INTA pin 108 * @PCI_INTERRUPT_INTB: PCI INTB pin 109 * @PCI_INTERRUPT_INTC: PCI INTC pin 110 * @PCI_INTERRUPT_INTD: PCI INTD pin 111 * 112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 113 * PCI_INTERRUPT_PIN register. 114 */ 115 enum pci_interrupt_pin { 116 PCI_INTERRUPT_UNKNOWN, 117 PCI_INTERRUPT_INTA, 118 PCI_INTERRUPT_INTB, 119 PCI_INTERRUPT_INTC, 120 PCI_INTERRUPT_INTD, 121 }; 122 123 /* The number of legacy PCI INTx interrupts */ 124 #define PCI_NUM_INTX 4 125 126 /* 127 * pci_power_t values must match the bits in the Capabilities PME_Support 128 * and Control/Status PowerState fields in the Power Management capability. 129 */ 130 typedef int __bitwise pci_power_t; 131 132 #define PCI_D0 ((pci_power_t __force) 0) 133 #define PCI_D1 ((pci_power_t __force) 1) 134 #define PCI_D2 ((pci_power_t __force) 2) 135 #define PCI_D3hot ((pci_power_t __force) 3) 136 #define PCI_D3cold ((pci_power_t __force) 4) 137 #define PCI_UNKNOWN ((pci_power_t __force) 5) 138 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 139 140 /* Remember to update this when the list above changes! */ 141 extern const char *pci_power_names[]; 142 143 static inline const char *pci_power_name(pci_power_t state) 144 { 145 return pci_power_names[1 + (__force int) state]; 146 } 147 148 #define PCI_PM_D2_DELAY 200 149 #define PCI_PM_D3_WAIT 10 150 #define PCI_PM_D3COLD_WAIT 100 151 #define PCI_PM_BUS_WAIT 50 152 153 /** 154 * The pci_channel state describes connectivity between the CPU and 155 * the PCI device. If some PCI bus between here and the PCI device 156 * has crashed or locked up, this info is reflected here. 157 */ 158 typedef unsigned int __bitwise pci_channel_state_t; 159 160 enum pci_channel_state { 161 /* I/O channel is in normal state */ 162 pci_channel_io_normal = (__force pci_channel_state_t) 1, 163 164 /* I/O to channel is blocked */ 165 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 166 167 /* PCI card is dead */ 168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 169 }; 170 171 typedef unsigned int __bitwise pcie_reset_state_t; 172 173 enum pcie_reset_state { 174 /* Reset is NOT asserted (Use to deassert reset) */ 175 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 176 177 /* Use #PERST to reset PCIe device */ 178 pcie_warm_reset = (__force pcie_reset_state_t) 2, 179 180 /* Use PCIe Hot Reset to reset device */ 181 pcie_hot_reset = (__force pcie_reset_state_t) 3 182 }; 183 184 typedef unsigned short __bitwise pci_dev_flags_t; 185 enum pci_dev_flags { 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 188 /* Device configuration is irrevocably lost if disabled into D3 */ 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 190 /* Provide indication device is assigned by a Virtual Machine Manager */ 191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 192 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 196 /* Do not use bus resets for device */ 197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 198 /* Do not use PM reset even if device advertises NoSoftRst- */ 199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 200 /* Get VPD from function 0 VPD */ 201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 202 /* A non-root bridge where translation occurs, stop alias search here */ 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 204 /* Do not use FLR even if device advertises PCI_AF_CAP */ 205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 206 /* Don't use Relaxed Ordering for TLPs directed at this device */ 207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 208 }; 209 210 enum pci_irq_reroute_variant { 211 INTEL_IRQ_REROUTE_VARIANT = 1, 212 MAX_IRQ_REROUTE_VARIANTS = 3 213 }; 214 215 typedef unsigned short __bitwise pci_bus_flags_t; 216 enum pci_bus_flags { 217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 221 }; 222 223 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 224 enum pcie_link_width { 225 PCIE_LNK_WIDTH_RESRV = 0x00, 226 PCIE_LNK_X1 = 0x01, 227 PCIE_LNK_X2 = 0x02, 228 PCIE_LNK_X4 = 0x04, 229 PCIE_LNK_X8 = 0x08, 230 PCIE_LNK_X12 = 0x0c, 231 PCIE_LNK_X16 = 0x10, 232 PCIE_LNK_X32 = 0x20, 233 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 234 }; 235 236 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 237 enum pci_bus_speed { 238 PCI_SPEED_33MHz = 0x00, 239 PCI_SPEED_66MHz = 0x01, 240 PCI_SPEED_66MHz_PCIX = 0x02, 241 PCI_SPEED_100MHz_PCIX = 0x03, 242 PCI_SPEED_133MHz_PCIX = 0x04, 243 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 244 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 245 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 246 PCI_SPEED_66MHz_PCIX_266 = 0x09, 247 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 248 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 249 AGP_UNKNOWN = 0x0c, 250 AGP_1X = 0x0d, 251 AGP_2X = 0x0e, 252 AGP_4X = 0x0f, 253 AGP_8X = 0x10, 254 PCI_SPEED_66MHz_PCIX_533 = 0x11, 255 PCI_SPEED_100MHz_PCIX_533 = 0x12, 256 PCI_SPEED_133MHz_PCIX_533 = 0x13, 257 PCIE_SPEED_2_5GT = 0x14, 258 PCIE_SPEED_5_0GT = 0x15, 259 PCIE_SPEED_8_0GT = 0x16, 260 PCIE_SPEED_16_0GT = 0x17, 261 PCI_SPEED_UNKNOWN = 0xff, 262 }; 263 264 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 265 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 266 267 struct pci_cap_saved_data { 268 u16 cap_nr; 269 bool cap_extended; 270 unsigned int size; 271 u32 data[0]; 272 }; 273 274 struct pci_cap_saved_state { 275 struct hlist_node next; 276 struct pci_cap_saved_data cap; 277 }; 278 279 struct irq_affinity; 280 struct pcie_link_state; 281 struct pci_vpd; 282 struct pci_sriov; 283 struct pci_ats; 284 struct pci_p2pdma; 285 286 /* The pci_dev structure describes PCI devices */ 287 struct pci_dev { 288 struct list_head bus_list; /* Node in per-bus list */ 289 struct pci_bus *bus; /* Bus this device is on */ 290 struct pci_bus *subordinate; /* Bus this device bridges to */ 291 292 void *sysdata; /* Hook for sys-specific extension */ 293 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 294 struct pci_slot *slot; /* Physical slot this device is in */ 295 296 unsigned int devfn; /* Encoded device & function index */ 297 unsigned short vendor; 298 unsigned short device; 299 unsigned short subsystem_vendor; 300 unsigned short subsystem_device; 301 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 302 u8 revision; /* PCI revision, low byte of class word */ 303 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 304 #ifdef CONFIG_PCIEAER 305 u16 aer_cap; /* AER capability offset */ 306 struct aer_stats *aer_stats; /* AER stats for this device */ 307 #endif 308 u8 pcie_cap; /* PCIe capability offset */ 309 u8 msi_cap; /* MSI capability offset */ 310 u8 msix_cap; /* MSI-X capability offset */ 311 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 312 u8 rom_base_reg; /* Config register controlling ROM */ 313 u8 pin; /* Interrupt pin this device uses */ 314 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 315 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 316 317 struct pci_driver *driver; /* Driver bound to this device */ 318 u64 dma_mask; /* Mask of the bits of bus address this 319 device implements. Normally this is 320 0xffffffff. You only need to change 321 this if your device has broken DMA 322 or supports 64-bit transfers. */ 323 324 struct device_dma_parameters dma_parms; 325 326 pci_power_t current_state; /* Current operating state. In ACPI, 327 this is D0-D3, D0 being fully 328 functional, and D3 being off. */ 329 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 330 u8 pm_cap; /* PM capability offset */ 331 unsigned int pme_support:5; /* Bitmask of states from which PME# 332 can be generated */ 333 unsigned int pme_poll:1; /* Poll device's PME status bit */ 334 unsigned int d1_support:1; /* Low power state D1 is supported */ 335 unsigned int d2_support:1; /* Low power state D2 is supported */ 336 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 337 unsigned int no_d3cold:1; /* D3cold is forbidden */ 338 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 339 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 340 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 341 decoding during BAR sizing */ 342 unsigned int wakeup_prepared:1; 343 unsigned int runtime_d3cold:1; /* Whether go through runtime 344 D3cold, not set for devices 345 powered on/off by the 346 corresponding bridge */ 347 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 348 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 349 controlled exclusively by 350 user sysfs */ 351 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 352 bit manually */ 353 unsigned int d3_delay; /* D3->D0 transition time in ms */ 354 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 355 356 #ifdef CONFIG_PCIEASPM 357 struct pcie_link_state *link_state; /* ASPM link state */ 358 unsigned int ltr_path:1; /* Latency Tolerance Reporting 359 supported from root to here */ 360 #endif 361 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 362 363 pci_channel_state_t error_state; /* Current connectivity state */ 364 struct device dev; /* Generic device interface */ 365 366 int cfg_size; /* Size of config space */ 367 368 /* 369 * Instead of touching interrupt line and base address registers 370 * directly, use the values stored here. They might be different! 371 */ 372 unsigned int irq; 373 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 374 375 bool match_driver; /* Skip attaching driver */ 376 377 unsigned int transparent:1; /* Subtractive decode bridge */ 378 unsigned int io_window:1; /* Bridge has I/O window */ 379 unsigned int pref_window:1; /* Bridge has pref mem window */ 380 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 381 unsigned int multifunction:1; /* Multi-function device */ 382 383 unsigned int is_busmaster:1; /* Is busmaster */ 384 unsigned int no_msi:1; /* May not use MSI */ 385 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 386 unsigned int block_cfg_access:1; /* Config space access blocked */ 387 unsigned int broken_parity_status:1; /* Generates false positive parity */ 388 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 389 unsigned int msi_enabled:1; 390 unsigned int msix_enabled:1; 391 unsigned int ari_enabled:1; /* ARI forwarding */ 392 unsigned int ats_enabled:1; /* Address Translation Svc */ 393 unsigned int pasid_enabled:1; /* Process Address Space ID */ 394 unsigned int pri_enabled:1; /* Page Request Interface */ 395 unsigned int is_managed:1; 396 unsigned int needs_freset:1; /* Requires fundamental reset */ 397 unsigned int state_saved:1; 398 unsigned int is_physfn:1; 399 unsigned int is_virtfn:1; 400 unsigned int reset_fn:1; 401 unsigned int is_hotplug_bridge:1; 402 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 403 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 404 /* 405 * Devices marked being untrusted are the ones that can potentially 406 * execute DMA attacks and similar. They are typically connected 407 * through external ports such as Thunderbolt but not limited to 408 * that. When an IOMMU is enabled they should be getting full 409 * mappings to make sure they cannot access arbitrary memory. 410 */ 411 unsigned int untrusted:1; 412 unsigned int __aer_firmware_first_valid:1; 413 unsigned int __aer_firmware_first:1; 414 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 415 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 416 unsigned int irq_managed:1; 417 unsigned int has_secondary_link:1; 418 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 419 unsigned int is_probed:1; /* Device probing in progress */ 420 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 421 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 422 pci_dev_flags_t dev_flags; 423 atomic_t enable_cnt; /* pci_enable_device has been called */ 424 425 u32 saved_config_space[16]; /* Config space saved at suspend time */ 426 struct hlist_head saved_cap_space; 427 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 428 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 429 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 430 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 431 432 #ifdef CONFIG_HOTPLUG_PCI_PCIE 433 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 434 #endif 435 #ifdef CONFIG_PCIE_PTM 436 unsigned int ptm_root:1; 437 unsigned int ptm_enabled:1; 438 u8 ptm_granularity; 439 #endif 440 #ifdef CONFIG_PCI_MSI 441 const struct attribute_group **msi_irq_groups; 442 #endif 443 struct pci_vpd *vpd; 444 #ifdef CONFIG_PCI_ATS 445 union { 446 struct pci_sriov *sriov; /* PF: SR-IOV info */ 447 struct pci_dev *physfn; /* VF: related PF */ 448 }; 449 u16 ats_cap; /* ATS Capability offset */ 450 u8 ats_stu; /* ATS Smallest Translation Unit */ 451 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ 452 #endif 453 #ifdef CONFIG_PCI_PRI 454 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 455 #endif 456 #ifdef CONFIG_PCI_PASID 457 u16 pasid_features; 458 #endif 459 #ifdef CONFIG_PCI_P2PDMA 460 struct pci_p2pdma *p2pdma; 461 #endif 462 phys_addr_t rom; /* Physical address if not from BAR */ 463 size_t romlen; /* Length if not from BAR */ 464 char *driver_override; /* Driver name to force a match */ 465 466 unsigned long priv_flags; /* Private flags for the PCI driver */ 467 }; 468 469 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 470 { 471 #ifdef CONFIG_PCI_IOV 472 if (dev->is_virtfn) 473 dev = dev->physfn; 474 #endif 475 return dev; 476 } 477 478 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 479 480 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 481 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 482 483 static inline int pci_channel_offline(struct pci_dev *pdev) 484 { 485 return (pdev->error_state != pci_channel_io_normal); 486 } 487 488 struct pci_host_bridge { 489 struct device dev; 490 struct pci_bus *bus; /* Root bus */ 491 struct pci_ops *ops; 492 void *sysdata; 493 int busnr; 494 struct list_head windows; /* resource_entry */ 495 struct list_head dma_ranges; /* dma ranges resource list */ 496 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 497 int (*map_irq)(const struct pci_dev *, u8, u8); 498 void (*release_fn)(struct pci_host_bridge *); 499 void *release_data; 500 struct msi_controller *msi; 501 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 502 unsigned int no_ext_tags:1; /* No Extended Tags */ 503 unsigned int native_aer:1; /* OS may use PCIe AER */ 504 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 505 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 506 unsigned int native_pme:1; /* OS may use PCIe PME */ 507 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 508 /* Resource alignment requirements */ 509 resource_size_t (*align_resource)(struct pci_dev *dev, 510 const struct resource *res, 511 resource_size_t start, 512 resource_size_t size, 513 resource_size_t align); 514 unsigned long private[0] ____cacheline_aligned; 515 }; 516 517 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 518 519 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 520 { 521 return (void *)bridge->private; 522 } 523 524 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 525 { 526 return container_of(priv, struct pci_host_bridge, private); 527 } 528 529 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 530 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 531 size_t priv); 532 void pci_free_host_bridge(struct pci_host_bridge *bridge); 533 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 534 535 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 536 void (*release_fn)(struct pci_host_bridge *), 537 void *release_data); 538 539 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 540 541 /* 542 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 543 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 544 * buses below host bridges or subtractive decode bridges) go in the list. 545 * Use pci_bus_for_each_resource() to iterate through all the resources. 546 */ 547 548 /* 549 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 550 * and there's no way to program the bridge with the details of the window. 551 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 552 * decode bit set, because they are explicit and can be programmed with _SRS. 553 */ 554 #define PCI_SUBTRACTIVE_DECODE 0x1 555 556 struct pci_bus_resource { 557 struct list_head list; 558 struct resource *res; 559 unsigned int flags; 560 }; 561 562 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 563 564 struct pci_bus { 565 struct list_head node; /* Node in list of buses */ 566 struct pci_bus *parent; /* Parent bus this bridge is on */ 567 struct list_head children; /* List of child buses */ 568 struct list_head devices; /* List of devices on this bus */ 569 struct pci_dev *self; /* Bridge device as seen by parent */ 570 struct list_head slots; /* List of slots on this bus; 571 protected by pci_slot_mutex */ 572 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 573 struct list_head resources; /* Address space routed to this bus */ 574 struct resource busn_res; /* Bus numbers routed to this bus */ 575 576 struct pci_ops *ops; /* Configuration access functions */ 577 struct msi_controller *msi; /* MSI controller */ 578 void *sysdata; /* Hook for sys-specific extension */ 579 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 580 581 unsigned char number; /* Bus number */ 582 unsigned char primary; /* Number of primary bridge */ 583 unsigned char max_bus_speed; /* enum pci_bus_speed */ 584 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 585 #ifdef CONFIG_PCI_DOMAINS_GENERIC 586 int domain_nr; 587 #endif 588 589 char name[48]; 590 591 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 592 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 593 struct device *bridge; 594 struct device dev; 595 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 596 struct bin_attribute *legacy_mem; /* Legacy mem */ 597 unsigned int is_added:1; 598 }; 599 600 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 601 602 static inline u16 pci_dev_id(struct pci_dev *dev) 603 { 604 return PCI_DEVID(dev->bus->number, dev->devfn); 605 } 606 607 /* 608 * Returns true if the PCI bus is root (behind host-PCI bridge), 609 * false otherwise 610 * 611 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 612 * This is incorrect because "virtual" buses added for SR-IOV (via 613 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 614 */ 615 static inline bool pci_is_root_bus(struct pci_bus *pbus) 616 { 617 return !(pbus->parent); 618 } 619 620 /** 621 * pci_is_bridge - check if the PCI device is a bridge 622 * @dev: PCI device 623 * 624 * Return true if the PCI device is bridge whether it has subordinate 625 * or not. 626 */ 627 static inline bool pci_is_bridge(struct pci_dev *dev) 628 { 629 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 630 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 631 } 632 633 #define for_each_pci_bridge(dev, bus) \ 634 list_for_each_entry(dev, &bus->devices, bus_list) \ 635 if (!pci_is_bridge(dev)) {} else 636 637 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 638 { 639 dev = pci_physfn(dev); 640 if (pci_is_root_bus(dev->bus)) 641 return NULL; 642 643 return dev->bus->self; 644 } 645 646 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 647 void pci_put_host_bridge_device(struct device *dev); 648 649 #ifdef CONFIG_PCI_MSI 650 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 651 { 652 return pci_dev->msi_enabled || pci_dev->msix_enabled; 653 } 654 #else 655 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 656 #endif 657 658 /* Error values that may be returned by PCI functions */ 659 #define PCIBIOS_SUCCESSFUL 0x00 660 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 661 #define PCIBIOS_BAD_VENDOR_ID 0x83 662 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 663 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 664 #define PCIBIOS_SET_FAILED 0x88 665 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 666 667 /* Translate above to generic errno for passing back through non-PCI code */ 668 static inline int pcibios_err_to_errno(int err) 669 { 670 if (err <= PCIBIOS_SUCCESSFUL) 671 return err; /* Assume already errno */ 672 673 switch (err) { 674 case PCIBIOS_FUNC_NOT_SUPPORTED: 675 return -ENOENT; 676 case PCIBIOS_BAD_VENDOR_ID: 677 return -ENOTTY; 678 case PCIBIOS_DEVICE_NOT_FOUND: 679 return -ENODEV; 680 case PCIBIOS_BAD_REGISTER_NUMBER: 681 return -EFAULT; 682 case PCIBIOS_SET_FAILED: 683 return -EIO; 684 case PCIBIOS_BUFFER_TOO_SMALL: 685 return -ENOSPC; 686 } 687 688 return -ERANGE; 689 } 690 691 /* Low-level architecture-dependent routines */ 692 693 struct pci_ops { 694 int (*add_bus)(struct pci_bus *bus); 695 void (*remove_bus)(struct pci_bus *bus); 696 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 697 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 698 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 699 }; 700 701 /* 702 * ACPI needs to be able to access PCI config space before we've done a 703 * PCI bus scan and created pci_bus structures. 704 */ 705 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 706 int reg, int len, u32 *val); 707 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 708 int reg, int len, u32 val); 709 710 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 711 typedef u64 pci_bus_addr_t; 712 #else 713 typedef u32 pci_bus_addr_t; 714 #endif 715 716 struct pci_bus_region { 717 pci_bus_addr_t start; 718 pci_bus_addr_t end; 719 }; 720 721 struct pci_dynids { 722 spinlock_t lock; /* Protects list, index */ 723 struct list_head list; /* For IDs added at runtime */ 724 }; 725 726 727 /* 728 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 729 * a set of callbacks in struct pci_error_handlers, that device driver 730 * will be notified of PCI bus errors, and will be driven to recovery 731 * when an error occurs. 732 */ 733 734 typedef unsigned int __bitwise pci_ers_result_t; 735 736 enum pci_ers_result { 737 /* No result/none/not supported in device driver */ 738 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 739 740 /* Device driver can recover without slot reset */ 741 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 742 743 /* Device driver wants slot to be reset */ 744 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 745 746 /* Device has completely failed, is unrecoverable */ 747 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 748 749 /* Device driver is fully recovered and operational */ 750 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 751 752 /* No AER capabilities registered for the driver */ 753 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 754 }; 755 756 /* PCI bus error event callbacks */ 757 struct pci_error_handlers { 758 /* PCI bus error detected on this device */ 759 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 760 enum pci_channel_state error); 761 762 /* MMIO has been re-enabled, but not DMA */ 763 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 764 765 /* PCI slot has been reset */ 766 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 767 768 /* PCI function reset prepare or completed */ 769 void (*reset_prepare)(struct pci_dev *dev); 770 void (*reset_done)(struct pci_dev *dev); 771 772 /* Device driver may resume normal operations */ 773 void (*resume)(struct pci_dev *dev); 774 }; 775 776 777 struct module; 778 struct pci_driver { 779 struct list_head node; 780 const char *name; 781 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 782 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 783 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 784 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 785 int (*suspend_late)(struct pci_dev *dev, pm_message_t state); 786 int (*resume_early)(struct pci_dev *dev); 787 int (*resume)(struct pci_dev *dev); /* Device woken up */ 788 void (*shutdown)(struct pci_dev *dev); 789 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 790 const struct pci_error_handlers *err_handler; 791 const struct attribute_group **groups; 792 struct device_driver driver; 793 struct pci_dynids dynids; 794 }; 795 796 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 797 798 /** 799 * PCI_DEVICE - macro used to describe a specific PCI device 800 * @vend: the 16 bit PCI Vendor ID 801 * @dev: the 16 bit PCI Device ID 802 * 803 * This macro is used to create a struct pci_device_id that matches a 804 * specific device. The subvendor and subdevice fields will be set to 805 * PCI_ANY_ID. 806 */ 807 #define PCI_DEVICE(vend,dev) \ 808 .vendor = (vend), .device = (dev), \ 809 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 810 811 /** 812 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 813 * @vend: the 16 bit PCI Vendor ID 814 * @dev: the 16 bit PCI Device ID 815 * @subvend: the 16 bit PCI Subvendor ID 816 * @subdev: the 16 bit PCI Subdevice ID 817 * 818 * This macro is used to create a struct pci_device_id that matches a 819 * specific device with subsystem information. 820 */ 821 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 822 .vendor = (vend), .device = (dev), \ 823 .subvendor = (subvend), .subdevice = (subdev) 824 825 /** 826 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 827 * @dev_class: the class, subclass, prog-if triple for this device 828 * @dev_class_mask: the class mask for this device 829 * 830 * This macro is used to create a struct pci_device_id that matches a 831 * specific PCI class. The vendor, device, subvendor, and subdevice 832 * fields will be set to PCI_ANY_ID. 833 */ 834 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 835 .class = (dev_class), .class_mask = (dev_class_mask), \ 836 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 837 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 838 839 /** 840 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 841 * @vend: the vendor name 842 * @dev: the 16 bit PCI Device ID 843 * 844 * This macro is used to create a struct pci_device_id that matches a 845 * specific PCI device. The subvendor, and subdevice fields will be set 846 * to PCI_ANY_ID. The macro allows the next field to follow as the device 847 * private data. 848 */ 849 #define PCI_VDEVICE(vend, dev) \ 850 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 851 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 852 853 /** 854 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 855 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 856 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 857 * @data: the driver data to be filled 858 * 859 * This macro is used to create a struct pci_device_id that matches a 860 * specific PCI device. The subvendor, and subdevice fields will be set 861 * to PCI_ANY_ID. 862 */ 863 #define PCI_DEVICE_DATA(vend, dev, data) \ 864 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 865 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 866 .driver_data = (kernel_ulong_t)(data) 867 868 enum { 869 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 870 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 871 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 872 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 873 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 874 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 875 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 876 }; 877 878 /* These external functions are only available when PCI support is enabled */ 879 #ifdef CONFIG_PCI 880 881 extern unsigned int pci_flags; 882 883 static inline void pci_set_flags(int flags) { pci_flags = flags; } 884 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 885 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 886 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 887 888 void pcie_bus_configure_settings(struct pci_bus *bus); 889 890 enum pcie_bus_config_types { 891 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 892 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 893 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 894 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 895 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 896 }; 897 898 extern enum pcie_bus_config_types pcie_bus_config; 899 900 extern struct bus_type pci_bus_type; 901 902 /* Do NOT directly access these two variables, unless you are arch-specific PCI 903 * code, or PCI core code. */ 904 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 905 /* Some device drivers need know if PCI is initiated */ 906 int no_pci_devices(void); 907 908 void pcibios_resource_survey_bus(struct pci_bus *bus); 909 void pcibios_bus_add_device(struct pci_dev *pdev); 910 void pcibios_add_bus(struct pci_bus *bus); 911 void pcibios_remove_bus(struct pci_bus *bus); 912 void pcibios_fixup_bus(struct pci_bus *); 913 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 914 /* Architecture-specific versions may override this (weak) */ 915 char *pcibios_setup(char *str); 916 917 /* Used only when drivers/pci/setup.c is used */ 918 resource_size_t pcibios_align_resource(void *, const struct resource *, 919 resource_size_t, 920 resource_size_t); 921 922 /* Weak but can be overriden by arch */ 923 void pci_fixup_cardbus(struct pci_bus *); 924 925 /* Generic PCI functions used internally */ 926 927 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 928 struct resource *res); 929 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 930 struct pci_bus_region *region); 931 void pcibios_scan_specific_bus(int busn); 932 struct pci_bus *pci_find_bus(int domain, int busnr); 933 void pci_bus_add_devices(const struct pci_bus *bus); 934 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 935 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 936 struct pci_ops *ops, void *sysdata, 937 struct list_head *resources); 938 int pci_host_probe(struct pci_host_bridge *bridge); 939 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 940 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 941 void pci_bus_release_busn_res(struct pci_bus *b); 942 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 943 struct pci_ops *ops, void *sysdata, 944 struct list_head *resources); 945 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 946 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 947 int busnr); 948 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 949 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 950 const char *name, 951 struct hotplug_slot *hotplug); 952 void pci_destroy_slot(struct pci_slot *slot); 953 #ifdef CONFIG_SYSFS 954 void pci_dev_assign_slot(struct pci_dev *dev); 955 #else 956 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 957 #endif 958 int pci_scan_slot(struct pci_bus *bus, int devfn); 959 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 960 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 961 unsigned int pci_scan_child_bus(struct pci_bus *bus); 962 void pci_bus_add_device(struct pci_dev *dev); 963 void pci_read_bridge_bases(struct pci_bus *child); 964 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 965 struct resource *res); 966 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 967 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 968 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 969 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 970 struct pci_dev *pci_dev_get(struct pci_dev *dev); 971 void pci_dev_put(struct pci_dev *dev); 972 void pci_remove_bus(struct pci_bus *b); 973 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 974 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 975 void pci_stop_root_bus(struct pci_bus *bus); 976 void pci_remove_root_bus(struct pci_bus *bus); 977 void pci_setup_cardbus(struct pci_bus *bus); 978 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 979 void pci_sort_breadthfirst(void); 980 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 981 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 982 983 /* Generic PCI functions exported to card drivers */ 984 985 enum pci_lost_interrupt_reason { 986 PCI_LOST_IRQ_NO_INFORMATION = 0, 987 PCI_LOST_IRQ_DISABLE_MSI, 988 PCI_LOST_IRQ_DISABLE_MSIX, 989 PCI_LOST_IRQ_DISABLE_ACPI, 990 }; 991 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 992 int pci_find_capability(struct pci_dev *dev, int cap); 993 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 994 int pci_find_ext_capability(struct pci_dev *dev, int cap); 995 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 996 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 997 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 998 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 999 1000 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1001 struct pci_dev *from); 1002 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1003 unsigned int ss_vendor, unsigned int ss_device, 1004 struct pci_dev *from); 1005 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1006 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1007 unsigned int devfn); 1008 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1009 int pci_dev_present(const struct pci_device_id *ids); 1010 1011 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1012 int where, u8 *val); 1013 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1014 int where, u16 *val); 1015 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1016 int where, u32 *val); 1017 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1018 int where, u8 val); 1019 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1020 int where, u16 val); 1021 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1022 int where, u32 val); 1023 1024 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1025 int where, int size, u32 *val); 1026 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1027 int where, int size, u32 val); 1028 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1029 int where, int size, u32 *val); 1030 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1031 int where, int size, u32 val); 1032 1033 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1034 1035 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1036 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1037 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1038 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1039 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1040 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1041 1042 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1043 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1044 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1045 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1046 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1047 u16 clear, u16 set); 1048 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1049 u32 clear, u32 set); 1050 1051 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1052 u16 set) 1053 { 1054 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1055 } 1056 1057 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1058 u32 set) 1059 { 1060 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1061 } 1062 1063 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1064 u16 clear) 1065 { 1066 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1067 } 1068 1069 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1070 u32 clear) 1071 { 1072 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1073 } 1074 1075 /* User-space driven config access */ 1076 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1077 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1078 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1079 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1080 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1081 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1082 1083 int __must_check pci_enable_device(struct pci_dev *dev); 1084 int __must_check pci_enable_device_io(struct pci_dev *dev); 1085 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1086 int __must_check pci_reenable_device(struct pci_dev *); 1087 int __must_check pcim_enable_device(struct pci_dev *pdev); 1088 void pcim_pin_device(struct pci_dev *pdev); 1089 1090 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1091 { 1092 /* 1093 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1094 * writable and no quirk has marked the feature broken. 1095 */ 1096 return !pdev->broken_intx_masking; 1097 } 1098 1099 static inline int pci_is_enabled(struct pci_dev *pdev) 1100 { 1101 return (atomic_read(&pdev->enable_cnt) > 0); 1102 } 1103 1104 static inline int pci_is_managed(struct pci_dev *pdev) 1105 { 1106 return pdev->is_managed; 1107 } 1108 1109 void pci_disable_device(struct pci_dev *dev); 1110 1111 extern unsigned int pcibios_max_latency; 1112 void pci_set_master(struct pci_dev *dev); 1113 void pci_clear_master(struct pci_dev *dev); 1114 1115 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1116 int pci_set_cacheline_size(struct pci_dev *dev); 1117 #define HAVE_PCI_SET_MWI 1118 int __must_check pci_set_mwi(struct pci_dev *dev); 1119 int __must_check pcim_set_mwi(struct pci_dev *dev); 1120 int pci_try_set_mwi(struct pci_dev *dev); 1121 void pci_clear_mwi(struct pci_dev *dev); 1122 void pci_intx(struct pci_dev *dev, int enable); 1123 bool pci_check_and_mask_intx(struct pci_dev *dev); 1124 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1125 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1126 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1127 int pcix_get_max_mmrbc(struct pci_dev *dev); 1128 int pcix_get_mmrbc(struct pci_dev *dev); 1129 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1130 int pcie_get_readrq(struct pci_dev *dev); 1131 int pcie_set_readrq(struct pci_dev *dev, int rq); 1132 int pcie_get_mps(struct pci_dev *dev); 1133 int pcie_set_mps(struct pci_dev *dev, int mps); 1134 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1135 enum pci_bus_speed *speed, 1136 enum pcie_link_width *width); 1137 void pcie_print_link_status(struct pci_dev *dev); 1138 bool pcie_has_flr(struct pci_dev *dev); 1139 int pcie_flr(struct pci_dev *dev); 1140 int __pci_reset_function_locked(struct pci_dev *dev); 1141 int pci_reset_function(struct pci_dev *dev); 1142 int pci_reset_function_locked(struct pci_dev *dev); 1143 int pci_try_reset_function(struct pci_dev *dev); 1144 int pci_probe_reset_slot(struct pci_slot *slot); 1145 int pci_probe_reset_bus(struct pci_bus *bus); 1146 int pci_reset_bus(struct pci_dev *dev); 1147 void pci_reset_secondary_bus(struct pci_dev *dev); 1148 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1149 void pci_update_resource(struct pci_dev *dev, int resno); 1150 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1151 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1152 void pci_release_resource(struct pci_dev *dev, int resno); 1153 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1154 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1155 bool pci_device_is_present(struct pci_dev *pdev); 1156 void pci_ignore_hotplug(struct pci_dev *dev); 1157 1158 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1159 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1160 const char *fmt, ...); 1161 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1162 1163 /* ROM control related routines */ 1164 int pci_enable_rom(struct pci_dev *pdev); 1165 void pci_disable_rom(struct pci_dev *pdev); 1166 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1167 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1168 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1169 1170 /* Power management related routines */ 1171 int pci_save_state(struct pci_dev *dev); 1172 void pci_restore_state(struct pci_dev *dev); 1173 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1174 int pci_load_saved_state(struct pci_dev *dev, 1175 struct pci_saved_state *state); 1176 int pci_load_and_free_saved_state(struct pci_dev *dev, 1177 struct pci_saved_state **state); 1178 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1179 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1180 u16 cap); 1181 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1182 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1183 u16 cap, unsigned int size); 1184 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1185 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1186 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1187 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1188 void pci_pme_active(struct pci_dev *dev, bool enable); 1189 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1190 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1191 int pci_prepare_to_sleep(struct pci_dev *dev); 1192 int pci_back_from_sleep(struct pci_dev *dev); 1193 bool pci_dev_run_wake(struct pci_dev *dev); 1194 bool pci_check_pme_status(struct pci_dev *dev); 1195 void pci_pme_wakeup_bus(struct pci_bus *bus); 1196 void pci_d3cold_enable(struct pci_dev *dev); 1197 void pci_d3cold_disable(struct pci_dev *dev); 1198 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1199 void pci_wakeup_bus(struct pci_bus *bus); 1200 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1201 1202 /* PCI Virtual Channel */ 1203 int pci_save_vc_state(struct pci_dev *dev); 1204 void pci_restore_vc_state(struct pci_dev *dev); 1205 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1206 1207 /* For use by arch with custom probe code */ 1208 void set_pcie_port_type(struct pci_dev *pdev); 1209 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1210 1211 /* Functions for PCI Hotplug drivers to use */ 1212 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1213 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1214 unsigned int pci_rescan_bus(struct pci_bus *bus); 1215 void pci_lock_rescan_remove(void); 1216 void pci_unlock_rescan_remove(void); 1217 1218 /* Vital Product Data routines */ 1219 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1220 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1221 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1222 1223 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1224 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1225 void pci_bus_assign_resources(const struct pci_bus *bus); 1226 void pci_bus_claim_resources(struct pci_bus *bus); 1227 void pci_bus_size_bridges(struct pci_bus *bus); 1228 int pci_claim_resource(struct pci_dev *, int); 1229 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1230 void pci_assign_unassigned_resources(void); 1231 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1232 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1233 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1234 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1235 void pdev_enable_device(struct pci_dev *); 1236 int pci_enable_resources(struct pci_dev *, int mask); 1237 void pci_assign_irq(struct pci_dev *dev); 1238 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1239 #define HAVE_PCI_REQ_REGIONS 2 1240 int __must_check pci_request_regions(struct pci_dev *, const char *); 1241 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1242 void pci_release_regions(struct pci_dev *); 1243 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1244 void pci_release_region(struct pci_dev *, int); 1245 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1246 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1247 void pci_release_selected_regions(struct pci_dev *, int); 1248 1249 /* drivers/pci/bus.c */ 1250 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1251 void pci_bus_put(struct pci_bus *bus); 1252 void pci_add_resource(struct list_head *resources, struct resource *res); 1253 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1254 resource_size_t offset); 1255 void pci_free_resource_list(struct list_head *resources); 1256 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1257 unsigned int flags); 1258 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1259 void pci_bus_remove_resources(struct pci_bus *bus); 1260 int devm_request_pci_bus_resources(struct device *dev, 1261 struct list_head *resources); 1262 1263 /* Temporary until new and working PCI SBR API in place */ 1264 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1265 1266 #define pci_bus_for_each_resource(bus, res, i) \ 1267 for (i = 0; \ 1268 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1269 i++) 1270 1271 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1272 struct resource *res, resource_size_t size, 1273 resource_size_t align, resource_size_t min, 1274 unsigned long type_mask, 1275 resource_size_t (*alignf)(void *, 1276 const struct resource *, 1277 resource_size_t, 1278 resource_size_t), 1279 void *alignf_data); 1280 1281 1282 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1283 resource_size_t size); 1284 unsigned long pci_address_to_pio(phys_addr_t addr); 1285 phys_addr_t pci_pio_to_address(unsigned long pio); 1286 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1287 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1288 phys_addr_t phys_addr); 1289 void pci_unmap_iospace(struct resource *res); 1290 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1291 resource_size_t offset, 1292 resource_size_t size); 1293 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1294 struct resource *res); 1295 1296 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1297 { 1298 struct pci_bus_region region; 1299 1300 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1301 return region.start; 1302 } 1303 1304 /* Proper probing supporting hot-pluggable devices */ 1305 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1306 const char *mod_name); 1307 1308 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1309 #define pci_register_driver(driver) \ 1310 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1311 1312 void pci_unregister_driver(struct pci_driver *dev); 1313 1314 /** 1315 * module_pci_driver() - Helper macro for registering a PCI driver 1316 * @__pci_driver: pci_driver struct 1317 * 1318 * Helper macro for PCI drivers which do not do anything special in module 1319 * init/exit. This eliminates a lot of boilerplate. Each module may only 1320 * use this macro once, and calling it replaces module_init() and module_exit() 1321 */ 1322 #define module_pci_driver(__pci_driver) \ 1323 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1324 1325 /** 1326 * builtin_pci_driver() - Helper macro for registering a PCI driver 1327 * @__pci_driver: pci_driver struct 1328 * 1329 * Helper macro for PCI drivers which do not do anything special in their 1330 * init code. This eliminates a lot of boilerplate. Each driver may only 1331 * use this macro once, and calling it replaces device_initcall(...) 1332 */ 1333 #define builtin_pci_driver(__pci_driver) \ 1334 builtin_driver(__pci_driver, pci_register_driver) 1335 1336 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1337 int pci_add_dynid(struct pci_driver *drv, 1338 unsigned int vendor, unsigned int device, 1339 unsigned int subvendor, unsigned int subdevice, 1340 unsigned int class, unsigned int class_mask, 1341 unsigned long driver_data); 1342 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1343 struct pci_dev *dev); 1344 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1345 int pass); 1346 1347 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1348 void *userdata); 1349 int pci_cfg_space_size(struct pci_dev *dev); 1350 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1351 void pci_setup_bridge(struct pci_bus *bus); 1352 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1353 unsigned long type); 1354 1355 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1356 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1357 1358 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1359 unsigned int command_bits, u32 flags); 1360 1361 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1362 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1363 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1364 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1365 #define PCI_IRQ_ALL_TYPES \ 1366 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1367 1368 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1369 1370 #include <linux/dmapool.h> 1371 1372 #define pci_pool dma_pool 1373 #define pci_pool_create(name, pdev, size, align, allocation) \ 1374 dma_pool_create(name, &pdev->dev, size, align, allocation) 1375 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1376 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1377 #define pci_pool_zalloc(pool, flags, handle) \ 1378 dma_pool_zalloc(pool, flags, handle) 1379 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1380 1381 struct msix_entry { 1382 u32 vector; /* Kernel uses to write allocated vector */ 1383 u16 entry; /* Driver uses to specify entry, OS writes */ 1384 }; 1385 1386 #ifdef CONFIG_PCI_MSI 1387 int pci_msi_vec_count(struct pci_dev *dev); 1388 void pci_disable_msi(struct pci_dev *dev); 1389 int pci_msix_vec_count(struct pci_dev *dev); 1390 void pci_disable_msix(struct pci_dev *dev); 1391 void pci_restore_msi_state(struct pci_dev *dev); 1392 int pci_msi_enabled(void); 1393 int pci_enable_msi(struct pci_dev *dev); 1394 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1395 int minvec, int maxvec); 1396 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1397 struct msix_entry *entries, int nvec) 1398 { 1399 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1400 if (rc < 0) 1401 return rc; 1402 return 0; 1403 } 1404 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1405 unsigned int max_vecs, unsigned int flags, 1406 struct irq_affinity *affd); 1407 1408 void pci_free_irq_vectors(struct pci_dev *dev); 1409 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1410 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1411 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1412 1413 #else 1414 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1415 static inline void pci_disable_msi(struct pci_dev *dev) { } 1416 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1417 static inline void pci_disable_msix(struct pci_dev *dev) { } 1418 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1419 static inline int pci_msi_enabled(void) { return 0; } 1420 static inline int pci_enable_msi(struct pci_dev *dev) 1421 { return -ENOSYS; } 1422 static inline int pci_enable_msix_range(struct pci_dev *dev, 1423 struct msix_entry *entries, int minvec, int maxvec) 1424 { return -ENOSYS; } 1425 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1426 struct msix_entry *entries, int nvec) 1427 { return -ENOSYS; } 1428 1429 static inline int 1430 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1431 unsigned int max_vecs, unsigned int flags, 1432 struct irq_affinity *aff_desc) 1433 { 1434 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1435 return 1; 1436 return -ENOSPC; 1437 } 1438 1439 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1440 { 1441 } 1442 1443 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1444 { 1445 if (WARN_ON_ONCE(nr > 0)) 1446 return -EINVAL; 1447 return dev->irq; 1448 } 1449 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1450 int vec) 1451 { 1452 return cpu_possible_mask; 1453 } 1454 1455 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1456 { 1457 return first_online_node; 1458 } 1459 #endif 1460 1461 static inline int 1462 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1463 unsigned int max_vecs, unsigned int flags) 1464 { 1465 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1466 NULL); 1467 } 1468 1469 /** 1470 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1471 * @d: the INTx IRQ domain 1472 * @node: the DT node for the device whose interrupt we're translating 1473 * @intspec: the interrupt specifier data from the DT 1474 * @intsize: the number of entries in @intspec 1475 * @out_hwirq: pointer at which to write the hwirq number 1476 * @out_type: pointer at which to write the interrupt type 1477 * 1478 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1479 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1480 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1481 * INTx value to obtain the hwirq number. 1482 * 1483 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1484 */ 1485 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1486 struct device_node *node, 1487 const u32 *intspec, 1488 unsigned int intsize, 1489 unsigned long *out_hwirq, 1490 unsigned int *out_type) 1491 { 1492 const u32 intx = intspec[0]; 1493 1494 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1495 return -EINVAL; 1496 1497 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1498 return 0; 1499 } 1500 1501 #ifdef CONFIG_PCIEPORTBUS 1502 extern bool pcie_ports_disabled; 1503 extern bool pcie_ports_native; 1504 #else 1505 #define pcie_ports_disabled true 1506 #define pcie_ports_native false 1507 #endif 1508 1509 #ifdef CONFIG_PCIEASPM 1510 bool pcie_aspm_support_enabled(void); 1511 #else 1512 static inline bool pcie_aspm_support_enabled(void) { return false; } 1513 #endif 1514 1515 #ifdef CONFIG_PCIEAER 1516 bool pci_aer_available(void); 1517 #else 1518 static inline bool pci_aer_available(void) { return false; } 1519 #endif 1520 1521 #ifdef CONFIG_PCIE_ECRC 1522 void pcie_set_ecrc_checking(struct pci_dev *dev); 1523 void pcie_ecrc_get_policy(char *str); 1524 #else 1525 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1526 static inline void pcie_ecrc_get_policy(char *str) { } 1527 #endif 1528 1529 bool pci_ats_disabled(void); 1530 1531 #ifdef CONFIG_PCIE_PTM 1532 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1533 #else 1534 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1535 { return -EINVAL; } 1536 #endif 1537 1538 void pci_cfg_access_lock(struct pci_dev *dev); 1539 bool pci_cfg_access_trylock(struct pci_dev *dev); 1540 void pci_cfg_access_unlock(struct pci_dev *dev); 1541 1542 /* 1543 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1544 * a PCI domain is defined to be a set of PCI buses which share 1545 * configuration space. 1546 */ 1547 #ifdef CONFIG_PCI_DOMAINS 1548 extern int pci_domains_supported; 1549 #else 1550 enum { pci_domains_supported = 0 }; 1551 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1552 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1553 #endif /* CONFIG_PCI_DOMAINS */ 1554 1555 /* 1556 * Generic implementation for PCI domain support. If your 1557 * architecture does not need custom management of PCI 1558 * domains then this implementation will be used 1559 */ 1560 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1561 static inline int pci_domain_nr(struct pci_bus *bus) 1562 { 1563 return bus->domain_nr; 1564 } 1565 #ifdef CONFIG_ACPI 1566 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1567 #else 1568 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1569 { return 0; } 1570 #endif 1571 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1572 #endif 1573 1574 /* Some architectures require additional setup to direct VGA traffic */ 1575 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1576 unsigned int command_bits, u32 flags); 1577 void pci_register_set_vga_state(arch_set_vga_state_t func); 1578 1579 static inline int 1580 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1581 { 1582 return pci_request_selected_regions(pdev, 1583 pci_select_bars(pdev, IORESOURCE_IO), name); 1584 } 1585 1586 static inline void 1587 pci_release_io_regions(struct pci_dev *pdev) 1588 { 1589 return pci_release_selected_regions(pdev, 1590 pci_select_bars(pdev, IORESOURCE_IO)); 1591 } 1592 1593 static inline int 1594 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1595 { 1596 return pci_request_selected_regions(pdev, 1597 pci_select_bars(pdev, IORESOURCE_MEM), name); 1598 } 1599 1600 static inline void 1601 pci_release_mem_regions(struct pci_dev *pdev) 1602 { 1603 return pci_release_selected_regions(pdev, 1604 pci_select_bars(pdev, IORESOURCE_MEM)); 1605 } 1606 1607 #else /* CONFIG_PCI is not enabled */ 1608 1609 static inline void pci_set_flags(int flags) { } 1610 static inline void pci_add_flags(int flags) { } 1611 static inline void pci_clear_flags(int flags) { } 1612 static inline int pci_has_flag(int flag) { return 0; } 1613 1614 /* 1615 * If the system does not have PCI, clearly these return errors. Define 1616 * these as simple inline functions to avoid hair in drivers. 1617 */ 1618 #define _PCI_NOP(o, s, t) \ 1619 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1620 int where, t val) \ 1621 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1622 1623 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1624 _PCI_NOP(o, word, u16 x) \ 1625 _PCI_NOP(o, dword, u32 x) 1626 _PCI_NOP_ALL(read, *) 1627 _PCI_NOP_ALL(write,) 1628 1629 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1630 unsigned int device, 1631 struct pci_dev *from) 1632 { return NULL; } 1633 1634 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1635 unsigned int device, 1636 unsigned int ss_vendor, 1637 unsigned int ss_device, 1638 struct pci_dev *from) 1639 { return NULL; } 1640 1641 static inline struct pci_dev *pci_get_class(unsigned int class, 1642 struct pci_dev *from) 1643 { return NULL; } 1644 1645 #define pci_dev_present(ids) (0) 1646 #define no_pci_devices() (1) 1647 #define pci_dev_put(dev) do { } while (0) 1648 1649 static inline void pci_set_master(struct pci_dev *dev) { } 1650 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1651 static inline void pci_disable_device(struct pci_dev *dev) { } 1652 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1653 { return -EBUSY; } 1654 static inline int __pci_register_driver(struct pci_driver *drv, 1655 struct module *owner) 1656 { return 0; } 1657 static inline int pci_register_driver(struct pci_driver *drv) 1658 { return 0; } 1659 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1660 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1661 { return 0; } 1662 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1663 int cap) 1664 { return 0; } 1665 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1666 { return 0; } 1667 1668 /* Power management related routines */ 1669 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1670 static inline void pci_restore_state(struct pci_dev *dev) { } 1671 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1672 { return 0; } 1673 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1674 { return 0; } 1675 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1676 pm_message_t state) 1677 { return PCI_D0; } 1678 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1679 int enable) 1680 { return 0; } 1681 1682 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1683 struct resource *res) 1684 { return NULL; } 1685 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1686 { return -EIO; } 1687 static inline void pci_release_regions(struct pci_dev *dev) { } 1688 1689 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1690 1691 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1692 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1693 { return 0; } 1694 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1695 1696 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1697 { return NULL; } 1698 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1699 unsigned int devfn) 1700 { return NULL; } 1701 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1702 unsigned int bus, unsigned int devfn) 1703 { return NULL; } 1704 1705 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1706 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1707 1708 #define dev_is_pci(d) (false) 1709 #define dev_is_pf(d) (false) 1710 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1711 { return false; } 1712 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1713 struct device_node *node, 1714 const u32 *intspec, 1715 unsigned int intsize, 1716 unsigned long *out_hwirq, 1717 unsigned int *out_type) 1718 { return -EINVAL; } 1719 1720 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1721 struct pci_dev *dev) 1722 { return NULL; } 1723 static inline bool pci_ats_disabled(void) { return true; } 1724 #endif /* CONFIG_PCI */ 1725 1726 #ifdef CONFIG_PCI_ATS 1727 /* Address Translation Service */ 1728 void pci_ats_init(struct pci_dev *dev); 1729 int pci_enable_ats(struct pci_dev *dev, int ps); 1730 void pci_disable_ats(struct pci_dev *dev); 1731 int pci_ats_queue_depth(struct pci_dev *dev); 1732 int pci_ats_page_aligned(struct pci_dev *dev); 1733 #else 1734 static inline void pci_ats_init(struct pci_dev *d) { } 1735 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1736 static inline void pci_disable_ats(struct pci_dev *d) { } 1737 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1738 static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; } 1739 #endif 1740 1741 /* Include architecture-dependent settings and functions */ 1742 1743 #include <asm/pci.h> 1744 1745 /* These two functions provide almost identical functionality. Depennding 1746 * on the architecture, one will be implemented as a wrapper around the 1747 * other (in drivers/pci/mmap.c). 1748 * 1749 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1750 * is expected to be an offset within that region. 1751 * 1752 * pci_mmap_page_range() is the legacy architecture-specific interface, 1753 * which accepts a "user visible" resource address converted by 1754 * pci_resource_to_user(), as used in the legacy mmap() interface in 1755 * /proc/bus/pci/. 1756 */ 1757 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1758 struct vm_area_struct *vma, 1759 enum pci_mmap_state mmap_state, int write_combine); 1760 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1761 struct vm_area_struct *vma, 1762 enum pci_mmap_state mmap_state, int write_combine); 1763 1764 #ifndef arch_can_pci_mmap_wc 1765 #define arch_can_pci_mmap_wc() 0 1766 #endif 1767 1768 #ifndef arch_can_pci_mmap_io 1769 #define arch_can_pci_mmap_io() 0 1770 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1771 #else 1772 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1773 #endif 1774 1775 #ifndef pci_root_bus_fwnode 1776 #define pci_root_bus_fwnode(bus) NULL 1777 #endif 1778 1779 /* 1780 * These helpers provide future and backwards compatibility 1781 * for accessing popular PCI BAR info 1782 */ 1783 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1784 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1785 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1786 #define pci_resource_len(dev,bar) \ 1787 ((pci_resource_start((dev), (bar)) == 0 && \ 1788 pci_resource_end((dev), (bar)) == \ 1789 pci_resource_start((dev), (bar))) ? 0 : \ 1790 \ 1791 (pci_resource_end((dev), (bar)) - \ 1792 pci_resource_start((dev), (bar)) + 1)) 1793 1794 /* 1795 * Similar to the helpers above, these manipulate per-pci_dev 1796 * driver-specific data. They are really just a wrapper around 1797 * the generic device structure functions of these calls. 1798 */ 1799 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1800 { 1801 return dev_get_drvdata(&pdev->dev); 1802 } 1803 1804 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1805 { 1806 dev_set_drvdata(&pdev->dev, data); 1807 } 1808 1809 static inline const char *pci_name(const struct pci_dev *pdev) 1810 { 1811 return dev_name(&pdev->dev); 1812 } 1813 1814 1815 /* 1816 * Some archs don't want to expose struct resource to userland as-is 1817 * in sysfs and /proc 1818 */ 1819 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1820 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1821 const struct resource *rsrc, 1822 resource_size_t *start, resource_size_t *end); 1823 #else 1824 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1825 const struct resource *rsrc, resource_size_t *start, 1826 resource_size_t *end) 1827 { 1828 *start = rsrc->start; 1829 *end = rsrc->end; 1830 } 1831 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1832 1833 1834 /* 1835 * The world is not perfect and supplies us with broken PCI devices. 1836 * For at least a part of these bugs we need a work-around, so both 1837 * generic (drivers/pci/quirks.c) and per-architecture code can define 1838 * fixup hooks to be called for particular buggy devices. 1839 */ 1840 1841 struct pci_fixup { 1842 u16 vendor; /* Or PCI_ANY_ID */ 1843 u16 device; /* Or PCI_ANY_ID */ 1844 u32 class; /* Or PCI_ANY_ID */ 1845 unsigned int class_shift; /* should be 0, 8, 16 */ 1846 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1847 int hook_offset; 1848 #else 1849 void (*hook)(struct pci_dev *dev); 1850 #endif 1851 }; 1852 1853 enum pci_fixup_pass { 1854 pci_fixup_early, /* Before probing BARs */ 1855 pci_fixup_header, /* After reading configuration header */ 1856 pci_fixup_final, /* Final phase of device fixups */ 1857 pci_fixup_enable, /* pci_enable_device() time */ 1858 pci_fixup_resume, /* pci_device_resume() */ 1859 pci_fixup_suspend, /* pci_device_suspend() */ 1860 pci_fixup_resume_early, /* pci_device_resume_early() */ 1861 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1862 }; 1863 1864 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1865 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1866 class_shift, hook) \ 1867 __ADDRESSABLE(hook) \ 1868 asm(".section " #sec ", \"a\" \n" \ 1869 ".balign 16 \n" \ 1870 ".short " #vendor ", " #device " \n" \ 1871 ".long " #class ", " #class_shift " \n" \ 1872 ".long " #hook " - . \n" \ 1873 ".previous \n"); 1874 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1875 class_shift, hook) \ 1876 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1877 class_shift, hook) 1878 #else 1879 /* Anonymous variables would be nice... */ 1880 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1881 class_shift, hook) \ 1882 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1883 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1884 = { vendor, device, class, class_shift, hook }; 1885 #endif 1886 1887 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1888 class_shift, hook) \ 1889 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1890 hook, vendor, device, class, class_shift, hook) 1891 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1892 class_shift, hook) \ 1893 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1894 hook, vendor, device, class, class_shift, hook) 1895 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1896 class_shift, hook) \ 1897 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1898 hook, vendor, device, class, class_shift, hook) 1899 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1900 class_shift, hook) \ 1901 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1902 hook, vendor, device, class, class_shift, hook) 1903 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1904 class_shift, hook) \ 1905 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1906 resume##hook, vendor, device, class, class_shift, hook) 1907 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1908 class_shift, hook) \ 1909 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1910 resume_early##hook, vendor, device, class, class_shift, hook) 1911 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1912 class_shift, hook) \ 1913 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1914 suspend##hook, vendor, device, class, class_shift, hook) 1915 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1916 class_shift, hook) \ 1917 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1918 suspend_late##hook, vendor, device, class, class_shift, hook) 1919 1920 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1921 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1922 hook, vendor, device, PCI_ANY_ID, 0, hook) 1923 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1924 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1925 hook, vendor, device, PCI_ANY_ID, 0, hook) 1926 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1927 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1928 hook, vendor, device, PCI_ANY_ID, 0, hook) 1929 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1930 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1931 hook, vendor, device, PCI_ANY_ID, 0, hook) 1932 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1933 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1934 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1935 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1936 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1937 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1938 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1939 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1940 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1941 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1942 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1943 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1944 1945 #ifdef CONFIG_PCI_QUIRKS 1946 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1947 #else 1948 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1949 struct pci_dev *dev) { } 1950 #endif 1951 1952 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1953 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1954 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1955 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1956 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1957 const char *name); 1958 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1959 1960 extern int pci_pci_problems; 1961 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1962 #define PCIPCI_TRITON 2 1963 #define PCIPCI_NATOMA 4 1964 #define PCIPCI_VIAETBF 8 1965 #define PCIPCI_VSFX 16 1966 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1967 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1968 1969 extern unsigned long pci_cardbus_io_size; 1970 extern unsigned long pci_cardbus_mem_size; 1971 extern u8 pci_dfl_cache_line_size; 1972 extern u8 pci_cache_line_size; 1973 1974 extern unsigned long pci_hotplug_io_size; 1975 extern unsigned long pci_hotplug_mem_size; 1976 extern unsigned long pci_hotplug_bus_size; 1977 1978 /* Architecture-specific versions may override these (weak) */ 1979 void pcibios_disable_device(struct pci_dev *dev); 1980 void pcibios_set_master(struct pci_dev *dev); 1981 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1982 enum pcie_reset_state state); 1983 int pcibios_add_device(struct pci_dev *dev); 1984 void pcibios_release_device(struct pci_dev *dev); 1985 #ifdef CONFIG_PCI 1986 void pcibios_penalize_isa_irq(int irq, int active); 1987 #else 1988 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 1989 #endif 1990 int pcibios_alloc_irq(struct pci_dev *dev); 1991 void pcibios_free_irq(struct pci_dev *dev); 1992 resource_size_t pcibios_default_alignment(void); 1993 1994 #ifdef CONFIG_HIBERNATE_CALLBACKS 1995 extern struct dev_pm_ops pcibios_pm_ops; 1996 #endif 1997 1998 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1999 void __init pci_mmcfg_early_init(void); 2000 void __init pci_mmcfg_late_init(void); 2001 #else 2002 static inline void pci_mmcfg_early_init(void) { } 2003 static inline void pci_mmcfg_late_init(void) { } 2004 #endif 2005 2006 int pci_ext_cfg_avail(void); 2007 2008 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2009 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2010 2011 #ifdef CONFIG_PCI_IOV 2012 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2013 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2014 2015 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2016 void pci_disable_sriov(struct pci_dev *dev); 2017 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2018 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2019 int pci_num_vf(struct pci_dev *dev); 2020 int pci_vfs_assigned(struct pci_dev *dev); 2021 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2022 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2023 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2024 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2025 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2026 2027 /* Arch may override these (weak) */ 2028 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2029 int pcibios_sriov_disable(struct pci_dev *pdev); 2030 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2031 #else 2032 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2033 { 2034 return -ENOSYS; 2035 } 2036 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2037 { 2038 return -ENOSYS; 2039 } 2040 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2041 { return -ENODEV; } 2042 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2043 { 2044 return -ENOSYS; 2045 } 2046 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2047 int id) { } 2048 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2049 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2050 static inline int pci_vfs_assigned(struct pci_dev *dev) 2051 { return 0; } 2052 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2053 { return 0; } 2054 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2055 { return 0; } 2056 #define pci_sriov_configure_simple NULL 2057 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2058 { return 0; } 2059 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2060 #endif 2061 2062 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2063 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2064 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2065 #endif 2066 2067 /** 2068 * pci_pcie_cap - get the saved PCIe capability offset 2069 * @dev: PCI device 2070 * 2071 * PCIe capability offset is calculated at PCI device initialization 2072 * time and saved in the data structure. This function returns saved 2073 * PCIe capability offset. Using this instead of pci_find_capability() 2074 * reduces unnecessary search in the PCI configuration space. If you 2075 * need to calculate PCIe capability offset from raw device for some 2076 * reasons, please use pci_find_capability() instead. 2077 */ 2078 static inline int pci_pcie_cap(struct pci_dev *dev) 2079 { 2080 return dev->pcie_cap; 2081 } 2082 2083 /** 2084 * pci_is_pcie - check if the PCI device is PCI Express capable 2085 * @dev: PCI device 2086 * 2087 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2088 */ 2089 static inline bool pci_is_pcie(struct pci_dev *dev) 2090 { 2091 return pci_pcie_cap(dev); 2092 } 2093 2094 /** 2095 * pcie_caps_reg - get the PCIe Capabilities Register 2096 * @dev: PCI device 2097 */ 2098 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2099 { 2100 return dev->pcie_flags_reg; 2101 } 2102 2103 /** 2104 * pci_pcie_type - get the PCIe device/port type 2105 * @dev: PCI device 2106 */ 2107 static inline int pci_pcie_type(const struct pci_dev *dev) 2108 { 2109 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2110 } 2111 2112 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2113 { 2114 while (1) { 2115 if (!pci_is_pcie(dev)) 2116 break; 2117 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2118 return dev; 2119 if (!dev->bus->self) 2120 break; 2121 dev = dev->bus->self; 2122 } 2123 return NULL; 2124 } 2125 2126 void pci_request_acs(void); 2127 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2128 bool pci_acs_path_enabled(struct pci_dev *start, 2129 struct pci_dev *end, u16 acs_flags); 2130 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2131 2132 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2133 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2134 2135 /* Large Resource Data Type Tag Item Names */ 2136 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2137 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2138 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2139 2140 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2141 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2142 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2143 2144 /* Small Resource Data Type Tag Item Names */ 2145 #define PCI_VPD_STIN_END 0x0f /* End */ 2146 2147 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2148 2149 #define PCI_VPD_SRDT_TIN_MASK 0x78 2150 #define PCI_VPD_SRDT_LEN_MASK 0x07 2151 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2152 2153 #define PCI_VPD_LRDT_TAG_SIZE 3 2154 #define PCI_VPD_SRDT_TAG_SIZE 1 2155 2156 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2157 2158 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2159 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2160 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2161 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2162 2163 /** 2164 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2165 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2166 * 2167 * Returns the extracted Large Resource Data Type length. 2168 */ 2169 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2170 { 2171 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2172 } 2173 2174 /** 2175 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2176 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2177 * 2178 * Returns the extracted Large Resource Data Type Tag item. 2179 */ 2180 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2181 { 2182 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2183 } 2184 2185 /** 2186 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2187 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2188 * 2189 * Returns the extracted Small Resource Data Type length. 2190 */ 2191 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2192 { 2193 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2194 } 2195 2196 /** 2197 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2198 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2199 * 2200 * Returns the extracted Small Resource Data Type Tag Item. 2201 */ 2202 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2203 { 2204 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2205 } 2206 2207 /** 2208 * pci_vpd_info_field_size - Extracts the information field length 2209 * @lrdt: Pointer to the beginning of an information field header 2210 * 2211 * Returns the extracted information field length. 2212 */ 2213 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2214 { 2215 return info_field[2]; 2216 } 2217 2218 /** 2219 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2220 * @buf: Pointer to buffered vpd data 2221 * @off: The offset into the buffer at which to begin the search 2222 * @len: The length of the vpd buffer 2223 * @rdt: The Resource Data Type to search for 2224 * 2225 * Returns the index where the Resource Data Type was found or 2226 * -ENOENT otherwise. 2227 */ 2228 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2229 2230 /** 2231 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2232 * @buf: Pointer to buffered vpd data 2233 * @off: The offset into the buffer at which to begin the search 2234 * @len: The length of the buffer area, relative to off, in which to search 2235 * @kw: The keyword to search for 2236 * 2237 * Returns the index where the information field keyword was found or 2238 * -ENOENT otherwise. 2239 */ 2240 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2241 unsigned int len, const char *kw); 2242 2243 /* PCI <-> OF binding helpers */ 2244 #ifdef CONFIG_OF 2245 struct device_node; 2246 struct irq_domain; 2247 void pci_set_of_node(struct pci_dev *dev); 2248 void pci_release_of_node(struct pci_dev *dev); 2249 void pci_set_bus_of_node(struct pci_bus *bus); 2250 void pci_release_bus_of_node(struct pci_bus *bus); 2251 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2252 int pci_parse_request_of_pci_ranges(struct device *dev, 2253 struct list_head *resources, 2254 struct resource **bus_range); 2255 2256 /* Arch may override this (weak) */ 2257 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2258 2259 #else /* CONFIG_OF */ 2260 static inline void pci_set_of_node(struct pci_dev *dev) { } 2261 static inline void pci_release_of_node(struct pci_dev *dev) { } 2262 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2263 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2264 static inline struct irq_domain * 2265 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2266 static inline int pci_parse_request_of_pci_ranges(struct device *dev, 2267 struct list_head *resources, 2268 struct resource **bus_range) 2269 { 2270 return -EINVAL; 2271 } 2272 #endif /* CONFIG_OF */ 2273 2274 static inline struct device_node * 2275 pci_device_to_OF_node(const struct pci_dev *pdev) 2276 { 2277 return pdev ? pdev->dev.of_node : NULL; 2278 } 2279 2280 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2281 { 2282 return bus ? bus->dev.of_node : NULL; 2283 } 2284 2285 #ifdef CONFIG_ACPI 2286 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2287 2288 void 2289 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2290 #else 2291 static inline struct irq_domain * 2292 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2293 #endif 2294 2295 #ifdef CONFIG_EEH 2296 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2297 { 2298 return pdev->dev.archdata.edev; 2299 } 2300 #endif 2301 2302 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2303 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2304 int pci_for_each_dma_alias(struct pci_dev *pdev, 2305 int (*fn)(struct pci_dev *pdev, 2306 u16 alias, void *data), void *data); 2307 2308 /* Helper functions for operation of device flag */ 2309 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2310 { 2311 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2312 } 2313 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2314 { 2315 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2316 } 2317 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2318 { 2319 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2320 } 2321 2322 /** 2323 * pci_ari_enabled - query ARI forwarding status 2324 * @bus: the PCI bus 2325 * 2326 * Returns true if ARI forwarding is enabled. 2327 */ 2328 static inline bool pci_ari_enabled(struct pci_bus *bus) 2329 { 2330 return bus->self && bus->self->ari_enabled; 2331 } 2332 2333 /** 2334 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2335 * @pdev: PCI device to check 2336 * 2337 * Walk upwards from @pdev and check for each encountered bridge if it's part 2338 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2339 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2340 */ 2341 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2342 { 2343 struct pci_dev *parent = pdev; 2344 2345 if (pdev->is_thunderbolt) 2346 return true; 2347 2348 while ((parent = pci_upstream_bridge(parent))) 2349 if (parent->is_thunderbolt) 2350 return true; 2351 2352 return false; 2353 } 2354 2355 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2356 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2357 #endif 2358 2359 /* Provide the legacy pci_dma_* API */ 2360 #include <linux/pci-dma-compat.h> 2361 2362 #define pci_printk(level, pdev, fmt, arg...) \ 2363 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2364 2365 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2366 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2367 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2368 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2369 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2370 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2371 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2372 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2373 2374 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2375 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2376 2377 #endif /* LINUX_PCI_H */ 2378