1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <uapi/linux/pci.h> 33 34 #include <linux/pci_ids.h> 35 36 /* 37 * The PCI interface treats multi-function devices as independent 38 * devices. The slot/function address of each device is encoded 39 * in a single byte as follows: 40 * 41 * 7:3 = slot 42 * 2:0 = function 43 * 44 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 45 * In the interest of not exposing interfaces to user-space unnecessarily, 46 * the following kernel-only defines are being added here. 47 */ 48 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn) 49 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 50 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 51 52 /* pci_slot represents a physical slot */ 53 struct pci_slot { 54 struct pci_bus *bus; /* The bus this slot is on */ 55 struct list_head list; /* node in list of slots on this bus */ 56 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 57 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 58 struct kobject kobj; 59 }; 60 61 static inline const char *pci_slot_name(const struct pci_slot *slot) 62 { 63 return kobject_name(&slot->kobj); 64 } 65 66 /* File state for mmap()s on /proc/bus/pci/X/Y */ 67 enum pci_mmap_state { 68 pci_mmap_io, 69 pci_mmap_mem 70 }; 71 72 /* This defines the direction arg to the DMA mapping routines. */ 73 #define PCI_DMA_BIDIRECTIONAL 0 74 #define PCI_DMA_TODEVICE 1 75 #define PCI_DMA_FROMDEVICE 2 76 #define PCI_DMA_NONE 3 77 78 /* 79 * For PCI devices, the region numbers are assigned this way: 80 */ 81 enum { 82 /* #0-5: standard PCI resources */ 83 PCI_STD_RESOURCES, 84 PCI_STD_RESOURCE_END = 5, 85 86 /* #6: expansion ROM resource */ 87 PCI_ROM_RESOURCE, 88 89 /* device specific resources */ 90 #ifdef CONFIG_PCI_IOV 91 PCI_IOV_RESOURCES, 92 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 93 #endif 94 95 /* resources assigned to buses behind the bridge */ 96 #define PCI_BRIDGE_RESOURCE_NUM 4 97 98 PCI_BRIDGE_RESOURCES, 99 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 100 PCI_BRIDGE_RESOURCE_NUM - 1, 101 102 /* total resources associated with a PCI device */ 103 PCI_NUM_RESOURCES, 104 105 /* preserve this for compatibility */ 106 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 107 }; 108 109 typedef int __bitwise pci_power_t; 110 111 #define PCI_D0 ((pci_power_t __force) 0) 112 #define PCI_D1 ((pci_power_t __force) 1) 113 #define PCI_D2 ((pci_power_t __force) 2) 114 #define PCI_D3hot ((pci_power_t __force) 3) 115 #define PCI_D3cold ((pci_power_t __force) 4) 116 #define PCI_UNKNOWN ((pci_power_t __force) 5) 117 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 118 119 /* Remember to update this when the list above changes! */ 120 extern const char *pci_power_names[]; 121 122 static inline const char *pci_power_name(pci_power_t state) 123 { 124 return pci_power_names[1 + (int) state]; 125 } 126 127 #define PCI_PM_D2_DELAY 200 128 #define PCI_PM_D3_WAIT 10 129 #define PCI_PM_D3COLD_WAIT 100 130 #define PCI_PM_BUS_WAIT 50 131 132 /** The pci_channel state describes connectivity between the CPU and 133 * the pci device. If some PCI bus between here and the pci device 134 * has crashed or locked up, this info is reflected here. 135 */ 136 typedef unsigned int __bitwise pci_channel_state_t; 137 138 enum pci_channel_state { 139 /* I/O channel is in normal state */ 140 pci_channel_io_normal = (__force pci_channel_state_t) 1, 141 142 /* I/O to channel is blocked */ 143 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 144 145 /* PCI card is dead */ 146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 147 }; 148 149 typedef unsigned int __bitwise pcie_reset_state_t; 150 151 enum pcie_reset_state { 152 /* Reset is NOT asserted (Use to deassert reset) */ 153 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 154 155 /* Use #PERST to reset PCIe device */ 156 pcie_warm_reset = (__force pcie_reset_state_t) 2, 157 158 /* Use PCIe Hot Reset to reset device */ 159 pcie_hot_reset = (__force pcie_reset_state_t) 3 160 }; 161 162 typedef unsigned short __bitwise pci_dev_flags_t; 163 enum pci_dev_flags { 164 /* INTX_DISABLE in PCI_COMMAND register disables MSI 165 * generation too. 166 */ 167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, 168 /* Device configuration is irrevocably lost if disabled into D3 */ 169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, 170 /* Provide indication device is assigned by a Virtual Machine Manager */ 171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4, 172 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) 8, 174 }; 175 176 enum pci_irq_reroute_variant { 177 INTEL_IRQ_REROUTE_VARIANT = 1, 178 MAX_IRQ_REROUTE_VARIANTS = 3 179 }; 180 181 typedef unsigned short __bitwise pci_bus_flags_t; 182 enum pci_bus_flags { 183 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 184 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 185 }; 186 187 /* These values come from the PCI Express Spec */ 188 enum pcie_link_width { 189 PCIE_LNK_WIDTH_RESRV = 0x00, 190 PCIE_LNK_X1 = 0x01, 191 PCIE_LNK_X2 = 0x02, 192 PCIE_LNK_X4 = 0x04, 193 PCIE_LNK_X8 = 0x08, 194 PCIE_LNK_X12 = 0x0C, 195 PCIE_LNK_X16 = 0x10, 196 PCIE_LNK_X32 = 0x20, 197 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 198 }; 199 200 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 201 enum pci_bus_speed { 202 PCI_SPEED_33MHz = 0x00, 203 PCI_SPEED_66MHz = 0x01, 204 PCI_SPEED_66MHz_PCIX = 0x02, 205 PCI_SPEED_100MHz_PCIX = 0x03, 206 PCI_SPEED_133MHz_PCIX = 0x04, 207 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 208 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 209 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 210 PCI_SPEED_66MHz_PCIX_266 = 0x09, 211 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 212 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 213 AGP_UNKNOWN = 0x0c, 214 AGP_1X = 0x0d, 215 AGP_2X = 0x0e, 216 AGP_4X = 0x0f, 217 AGP_8X = 0x10, 218 PCI_SPEED_66MHz_PCIX_533 = 0x11, 219 PCI_SPEED_100MHz_PCIX_533 = 0x12, 220 PCI_SPEED_133MHz_PCIX_533 = 0x13, 221 PCIE_SPEED_2_5GT = 0x14, 222 PCIE_SPEED_5_0GT = 0x15, 223 PCIE_SPEED_8_0GT = 0x16, 224 PCI_SPEED_UNKNOWN = 0xff, 225 }; 226 227 struct pci_cap_saved_data { 228 u16 cap_nr; 229 bool cap_extended; 230 unsigned int size; 231 u32 data[0]; 232 }; 233 234 struct pci_cap_saved_state { 235 struct hlist_node next; 236 struct pci_cap_saved_data cap; 237 }; 238 239 struct pcie_link_state; 240 struct pci_vpd; 241 struct pci_sriov; 242 struct pci_ats; 243 244 /* 245 * The pci_dev structure is used to describe PCI devices. 246 */ 247 struct pci_dev { 248 struct list_head bus_list; /* node in per-bus list */ 249 struct pci_bus *bus; /* bus this device is on */ 250 struct pci_bus *subordinate; /* bus this device bridges to */ 251 252 void *sysdata; /* hook for sys-specific extension */ 253 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 254 struct pci_slot *slot; /* Physical slot this device is in */ 255 256 unsigned int devfn; /* encoded device & function index */ 257 unsigned short vendor; 258 unsigned short device; 259 unsigned short subsystem_vendor; 260 unsigned short subsystem_device; 261 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 262 u8 revision; /* PCI revision, low byte of class word */ 263 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 264 u8 pcie_cap; /* PCIe capability offset */ 265 u8 msi_cap; /* MSI capability offset */ 266 u8 msix_cap; /* MSI-X capability offset */ 267 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 268 u8 rom_base_reg; /* which config register controls the ROM */ 269 u8 pin; /* which interrupt pin this device uses */ 270 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 271 272 struct pci_driver *driver; /* which driver has allocated this device */ 273 u64 dma_mask; /* Mask of the bits of bus address this 274 device implements. Normally this is 275 0xffffffff. You only need to change 276 this if your device has broken DMA 277 or supports 64-bit transfers. */ 278 279 struct device_dma_parameters dma_parms; 280 281 pci_power_t current_state; /* Current operating state. In ACPI-speak, 282 this is D0-D3, D0 being fully functional, 283 and D3 being off. */ 284 u8 pm_cap; /* PM capability offset */ 285 unsigned int pme_support:5; /* Bitmask of states from which PME# 286 can be generated */ 287 unsigned int pme_interrupt:1; 288 unsigned int pme_poll:1; /* Poll device's PME status bit */ 289 unsigned int d1_support:1; /* Low power state D1 is supported */ 290 unsigned int d2_support:1; /* Low power state D2 is supported */ 291 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 292 unsigned int no_d3cold:1; /* D3cold is forbidden */ 293 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 294 unsigned int mmio_always_on:1; /* disallow turning off io/mem 295 decoding during bar sizing */ 296 unsigned int wakeup_prepared:1; 297 unsigned int runtime_d3cold:1; /* whether go through runtime 298 D3cold, not set for devices 299 powered on/off by the 300 corresponding bridge */ 301 unsigned int d3_delay; /* D3->D0 transition time in ms */ 302 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 303 304 #ifdef CONFIG_PCIEASPM 305 struct pcie_link_state *link_state; /* ASPM link state */ 306 #endif 307 308 pci_channel_state_t error_state; /* current connectivity state */ 309 struct device dev; /* Generic device interface */ 310 311 int cfg_size; /* Size of configuration space */ 312 313 /* 314 * Instead of touching interrupt line and base address registers 315 * directly, use the values stored here. They might be different! 316 */ 317 unsigned int irq; 318 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 319 320 bool match_driver; /* Skip attaching driver */ 321 /* These fields are used by common fixups */ 322 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 323 unsigned int multifunction:1;/* Part of multi-function device */ 324 /* keep track of device state */ 325 unsigned int is_added:1; 326 unsigned int is_busmaster:1; /* device is busmaster */ 327 unsigned int no_msi:1; /* device may not use msi */ 328 unsigned int block_cfg_access:1; /* config space access is blocked */ 329 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 330 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 331 unsigned int msi_enabled:1; 332 unsigned int msix_enabled:1; 333 unsigned int ari_enabled:1; /* ARI forwarding */ 334 unsigned int is_managed:1; 335 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 336 unsigned int state_saved:1; 337 unsigned int is_physfn:1; 338 unsigned int is_virtfn:1; 339 unsigned int reset_fn:1; 340 unsigned int is_hotplug_bridge:1; 341 unsigned int __aer_firmware_first_valid:1; 342 unsigned int __aer_firmware_first:1; 343 unsigned int broken_intx_masking:1; 344 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 345 pci_dev_flags_t dev_flags; 346 atomic_t enable_cnt; /* pci_enable_device has been called */ 347 348 u32 saved_config_space[16]; /* config space saved at suspend time */ 349 struct hlist_head saved_cap_space; 350 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 351 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 352 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 353 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 354 #ifdef CONFIG_PCI_MSI 355 struct list_head msi_list; 356 const struct attribute_group **msi_irq_groups; 357 #endif 358 struct pci_vpd *vpd; 359 #ifdef CONFIG_PCI_ATS 360 union { 361 struct pci_sriov *sriov; /* SR-IOV capability related */ 362 struct pci_dev *physfn; /* the PF this VF is associated with */ 363 }; 364 struct pci_ats *ats; /* Address Translation Service */ 365 #endif 366 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 367 size_t romlen; /* Length of ROM if it's not from the BAR */ 368 }; 369 370 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 371 { 372 #ifdef CONFIG_PCI_IOV 373 if (dev->is_virtfn) 374 dev = dev->physfn; 375 #endif 376 return dev; 377 } 378 379 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 380 381 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 382 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 383 384 static inline int pci_channel_offline(struct pci_dev *pdev) 385 { 386 return (pdev->error_state != pci_channel_io_normal); 387 } 388 389 struct pci_host_bridge_window { 390 struct list_head list; 391 struct resource *res; /* host bridge aperture (CPU address) */ 392 resource_size_t offset; /* bus address + offset = CPU address */ 393 }; 394 395 struct pci_host_bridge { 396 struct device dev; 397 struct pci_bus *bus; /* root bus */ 398 struct list_head windows; /* pci_host_bridge_windows */ 399 void (*release_fn)(struct pci_host_bridge *); 400 void *release_data; 401 }; 402 403 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 404 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 405 void (*release_fn)(struct pci_host_bridge *), 406 void *release_data); 407 408 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 409 410 /* 411 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 412 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 413 * buses below host bridges or subtractive decode bridges) go in the list. 414 * Use pci_bus_for_each_resource() to iterate through all the resources. 415 */ 416 417 /* 418 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 419 * and there's no way to program the bridge with the details of the window. 420 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 421 * decode bit set, because they are explicit and can be programmed with _SRS. 422 */ 423 #define PCI_SUBTRACTIVE_DECODE 0x1 424 425 struct pci_bus_resource { 426 struct list_head list; 427 struct resource *res; 428 unsigned int flags; 429 }; 430 431 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 432 433 struct pci_bus { 434 struct list_head node; /* node in list of buses */ 435 struct pci_bus *parent; /* parent bus this bridge is on */ 436 struct list_head children; /* list of child buses */ 437 struct list_head devices; /* list of devices on this bus */ 438 struct pci_dev *self; /* bridge device as seen by parent */ 439 struct list_head slots; /* list of slots on this bus */ 440 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 441 struct list_head resources; /* address space routed to this bus */ 442 struct resource busn_res; /* bus numbers routed to this bus */ 443 444 struct pci_ops *ops; /* configuration access functions */ 445 struct msi_chip *msi; /* MSI controller */ 446 void *sysdata; /* hook for sys-specific extension */ 447 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 448 449 unsigned char number; /* bus number */ 450 unsigned char primary; /* number of primary bridge */ 451 unsigned char max_bus_speed; /* enum pci_bus_speed */ 452 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 453 454 char name[48]; 455 456 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 457 pci_bus_flags_t bus_flags; /* inherited by child buses */ 458 struct device *bridge; 459 struct device dev; 460 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 461 struct bin_attribute *legacy_mem; /* legacy mem */ 462 unsigned int is_added:1; 463 }; 464 465 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 466 467 /* 468 * Returns true if the PCI bus is root (behind host-PCI bridge), 469 * false otherwise 470 * 471 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 472 * This is incorrect because "virtual" buses added for SR-IOV (via 473 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 474 */ 475 static inline bool pci_is_root_bus(struct pci_bus *pbus) 476 { 477 return !(pbus->parent); 478 } 479 480 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 481 { 482 dev = pci_physfn(dev); 483 if (pci_is_root_bus(dev->bus)) 484 return NULL; 485 486 return dev->bus->self; 487 } 488 489 #ifdef CONFIG_PCI_MSI 490 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 491 { 492 return pci_dev->msi_enabled || pci_dev->msix_enabled; 493 } 494 #else 495 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 496 #endif 497 498 /* 499 * Error values that may be returned by PCI functions. 500 */ 501 #define PCIBIOS_SUCCESSFUL 0x00 502 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 503 #define PCIBIOS_BAD_VENDOR_ID 0x83 504 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 505 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 506 #define PCIBIOS_SET_FAILED 0x88 507 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 508 509 /* 510 * Translate above to generic errno for passing back through non-PCI code. 511 */ 512 static inline int pcibios_err_to_errno(int err) 513 { 514 if (err <= PCIBIOS_SUCCESSFUL) 515 return err; /* Assume already errno */ 516 517 switch (err) { 518 case PCIBIOS_FUNC_NOT_SUPPORTED: 519 return -ENOENT; 520 case PCIBIOS_BAD_VENDOR_ID: 521 return -EINVAL; 522 case PCIBIOS_DEVICE_NOT_FOUND: 523 return -ENODEV; 524 case PCIBIOS_BAD_REGISTER_NUMBER: 525 return -EFAULT; 526 case PCIBIOS_SET_FAILED: 527 return -EIO; 528 case PCIBIOS_BUFFER_TOO_SMALL: 529 return -ENOSPC; 530 } 531 532 return -ENOTTY; 533 } 534 535 /* Low-level architecture-dependent routines */ 536 537 struct pci_ops { 538 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 539 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 540 }; 541 542 /* 543 * ACPI needs to be able to access PCI config space before we've done a 544 * PCI bus scan and created pci_bus structures. 545 */ 546 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 547 int reg, int len, u32 *val); 548 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 549 int reg, int len, u32 val); 550 551 struct pci_bus_region { 552 dma_addr_t start; 553 dma_addr_t end; 554 }; 555 556 struct pci_dynids { 557 spinlock_t lock; /* protects list, index */ 558 struct list_head list; /* for IDs added at runtime */ 559 }; 560 561 562 /* 563 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 564 * a set of callbacks in struct pci_error_handlers, that device driver 565 * will be notified of PCI bus errors, and will be driven to recovery 566 * when an error occurs. 567 */ 568 569 typedef unsigned int __bitwise pci_ers_result_t; 570 571 enum pci_ers_result { 572 /* no result/none/not supported in device driver */ 573 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 574 575 /* Device driver can recover without slot reset */ 576 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 577 578 /* Device driver wants slot to be reset. */ 579 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 580 581 /* Device has completely failed, is unrecoverable */ 582 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 583 584 /* Device driver is fully recovered and operational */ 585 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 586 587 /* No AER capabilities registered for the driver */ 588 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 589 }; 590 591 /* PCI bus error event callbacks */ 592 struct pci_error_handlers { 593 /* PCI bus error detected on this device */ 594 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 595 enum pci_channel_state error); 596 597 /* MMIO has been re-enabled, but not DMA */ 598 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 599 600 /* PCI Express link has been reset */ 601 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 602 603 /* PCI slot has been reset */ 604 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 605 606 /* Device driver may resume normal operations */ 607 void (*resume)(struct pci_dev *dev); 608 }; 609 610 611 struct module; 612 struct pci_driver { 613 struct list_head node; 614 const char *name; 615 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 616 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 617 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 618 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 619 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 620 int (*resume_early) (struct pci_dev *dev); 621 int (*resume) (struct pci_dev *dev); /* Device woken up */ 622 void (*shutdown) (struct pci_dev *dev); 623 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 624 const struct pci_error_handlers *err_handler; 625 struct device_driver driver; 626 struct pci_dynids dynids; 627 }; 628 629 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 630 631 /** 632 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 633 * @_table: device table name 634 * 635 * This macro is deprecated and should not be used in new code. 636 */ 637 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 638 const struct pci_device_id _table[] 639 640 /** 641 * PCI_DEVICE - macro used to describe a specific pci device 642 * @vend: the 16 bit PCI Vendor ID 643 * @dev: the 16 bit PCI Device ID 644 * 645 * This macro is used to create a struct pci_device_id that matches a 646 * specific device. The subvendor and subdevice fields will be set to 647 * PCI_ANY_ID. 648 */ 649 #define PCI_DEVICE(vend,dev) \ 650 .vendor = (vend), .device = (dev), \ 651 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 652 653 /** 654 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 655 * @vend: the 16 bit PCI Vendor ID 656 * @dev: the 16 bit PCI Device ID 657 * @subvend: the 16 bit PCI Subvendor ID 658 * @subdev: the 16 bit PCI Subdevice ID 659 * 660 * This macro is used to create a struct pci_device_id that matches a 661 * specific device with subsystem information. 662 */ 663 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 664 .vendor = (vend), .device = (dev), \ 665 .subvendor = (subvend), .subdevice = (subdev) 666 667 /** 668 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 669 * @dev_class: the class, subclass, prog-if triple for this device 670 * @dev_class_mask: the class mask for this device 671 * 672 * This macro is used to create a struct pci_device_id that matches a 673 * specific PCI class. The vendor, device, subvendor, and subdevice 674 * fields will be set to PCI_ANY_ID. 675 */ 676 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 677 .class = (dev_class), .class_mask = (dev_class_mask), \ 678 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 679 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 680 681 /** 682 * PCI_VDEVICE - macro used to describe a specific pci device in short form 683 * @vendor: the vendor name 684 * @device: the 16 bit PCI Device ID 685 * 686 * This macro is used to create a struct pci_device_id that matches a 687 * specific PCI device. The subvendor, and subdevice fields will be set 688 * to PCI_ANY_ID. The macro allows the next field to follow as the device 689 * private data. 690 */ 691 692 #define PCI_VDEVICE(vendor, device) \ 693 PCI_VENDOR_ID_##vendor, (device), \ 694 PCI_ANY_ID, PCI_ANY_ID, 0, 0 695 696 /* these external functions are only available when PCI support is enabled */ 697 #ifdef CONFIG_PCI 698 699 void pcie_bus_configure_settings(struct pci_bus *bus); 700 701 enum pcie_bus_config_types { 702 PCIE_BUS_TUNE_OFF, 703 PCIE_BUS_SAFE, 704 PCIE_BUS_PERFORMANCE, 705 PCIE_BUS_PEER2PEER, 706 }; 707 708 extern enum pcie_bus_config_types pcie_bus_config; 709 710 extern struct bus_type pci_bus_type; 711 712 /* Do NOT directly access these two variables, unless you are arch-specific PCI 713 * code, or PCI core code. */ 714 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 715 /* Some device drivers need know if PCI is initiated */ 716 int no_pci_devices(void); 717 718 void pcibios_resource_survey_bus(struct pci_bus *bus); 719 void pcibios_add_bus(struct pci_bus *bus); 720 void pcibios_remove_bus(struct pci_bus *bus); 721 void pcibios_fixup_bus(struct pci_bus *); 722 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 723 /* Architecture-specific versions may override this (weak) */ 724 char *pcibios_setup(char *str); 725 726 /* Used only when drivers/pci/setup.c is used */ 727 resource_size_t pcibios_align_resource(void *, const struct resource *, 728 resource_size_t, 729 resource_size_t); 730 void pcibios_update_irq(struct pci_dev *, int irq); 731 732 /* Weak but can be overriden by arch */ 733 void pci_fixup_cardbus(struct pci_bus *); 734 735 /* Generic PCI functions used internally */ 736 737 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 738 struct resource *res); 739 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 740 struct pci_bus_region *region); 741 void pcibios_scan_specific_bus(int busn); 742 struct pci_bus *pci_find_bus(int domain, int busnr); 743 void pci_bus_add_devices(const struct pci_bus *bus); 744 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, 745 struct pci_ops *ops, void *sysdata); 746 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 747 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 748 struct pci_ops *ops, void *sysdata, 749 struct list_head *resources); 750 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 751 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 752 void pci_bus_release_busn_res(struct pci_bus *b); 753 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 754 struct pci_ops *ops, void *sysdata, 755 struct list_head *resources); 756 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 757 int busnr); 758 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 759 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 760 const char *name, 761 struct hotplug_slot *hotplug); 762 void pci_destroy_slot(struct pci_slot *slot); 763 int pci_scan_slot(struct pci_bus *bus, int devfn); 764 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 765 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 766 unsigned int pci_scan_child_bus(struct pci_bus *bus); 767 int __must_check pci_bus_add_device(struct pci_dev *dev); 768 void pci_read_bridge_bases(struct pci_bus *child); 769 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 770 struct resource *res); 771 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 772 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 773 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 774 struct pci_dev *pci_dev_get(struct pci_dev *dev); 775 void pci_dev_put(struct pci_dev *dev); 776 void pci_remove_bus(struct pci_bus *b); 777 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 778 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 779 void pci_stop_root_bus(struct pci_bus *bus); 780 void pci_remove_root_bus(struct pci_bus *bus); 781 void pci_setup_cardbus(struct pci_bus *bus); 782 void pci_sort_breadthfirst(void); 783 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 784 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 785 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 786 787 /* Generic PCI functions exported to card drivers */ 788 789 enum pci_lost_interrupt_reason { 790 PCI_LOST_IRQ_NO_INFORMATION = 0, 791 PCI_LOST_IRQ_DISABLE_MSI, 792 PCI_LOST_IRQ_DISABLE_MSIX, 793 PCI_LOST_IRQ_DISABLE_ACPI, 794 }; 795 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 796 int pci_find_capability(struct pci_dev *dev, int cap); 797 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 798 int pci_find_ext_capability(struct pci_dev *dev, int cap); 799 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 800 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 801 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 802 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 803 804 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 805 struct pci_dev *from); 806 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 807 unsigned int ss_vendor, unsigned int ss_device, 808 struct pci_dev *from); 809 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 810 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 811 unsigned int devfn); 812 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 813 unsigned int devfn) 814 { 815 return pci_get_domain_bus_and_slot(0, bus, devfn); 816 } 817 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 818 int pci_dev_present(const struct pci_device_id *ids); 819 820 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 821 int where, u8 *val); 822 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 823 int where, u16 *val); 824 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 825 int where, u32 *val); 826 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 827 int where, u8 val); 828 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 829 int where, u16 val); 830 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 831 int where, u32 val); 832 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 833 834 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 835 { 836 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 837 } 838 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 839 { 840 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 841 } 842 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 843 u32 *val) 844 { 845 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 846 } 847 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 848 { 849 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 850 } 851 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 852 { 853 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 854 } 855 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 856 u32 val) 857 { 858 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 859 } 860 861 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 862 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 863 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 864 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 865 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 866 u16 clear, u16 set); 867 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 868 u32 clear, u32 set); 869 870 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 871 u16 set) 872 { 873 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 874 } 875 876 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 877 u32 set) 878 { 879 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 880 } 881 882 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 883 u16 clear) 884 { 885 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 886 } 887 888 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 889 u32 clear) 890 { 891 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 892 } 893 894 /* user-space driven config access */ 895 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 896 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 897 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 898 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 899 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 900 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 901 902 int __must_check pci_enable_device(struct pci_dev *dev); 903 int __must_check pci_enable_device_io(struct pci_dev *dev); 904 int __must_check pci_enable_device_mem(struct pci_dev *dev); 905 int __must_check pci_reenable_device(struct pci_dev *); 906 int __must_check pcim_enable_device(struct pci_dev *pdev); 907 void pcim_pin_device(struct pci_dev *pdev); 908 909 static inline int pci_is_enabled(struct pci_dev *pdev) 910 { 911 return (atomic_read(&pdev->enable_cnt) > 0); 912 } 913 914 static inline int pci_is_managed(struct pci_dev *pdev) 915 { 916 return pdev->is_managed; 917 } 918 919 void pci_disable_device(struct pci_dev *dev); 920 921 extern unsigned int pcibios_max_latency; 922 void pci_set_master(struct pci_dev *dev); 923 void pci_clear_master(struct pci_dev *dev); 924 925 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 926 int pci_set_cacheline_size(struct pci_dev *dev); 927 #define HAVE_PCI_SET_MWI 928 int __must_check pci_set_mwi(struct pci_dev *dev); 929 int pci_try_set_mwi(struct pci_dev *dev); 930 void pci_clear_mwi(struct pci_dev *dev); 931 void pci_intx(struct pci_dev *dev, int enable); 932 bool pci_intx_mask_supported(struct pci_dev *dev); 933 bool pci_check_and_mask_intx(struct pci_dev *dev); 934 bool pci_check_and_unmask_intx(struct pci_dev *dev); 935 void pci_msi_off(struct pci_dev *dev); 936 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 937 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 938 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 939 int pci_wait_for_pending_transaction(struct pci_dev *dev); 940 int pcix_get_max_mmrbc(struct pci_dev *dev); 941 int pcix_get_mmrbc(struct pci_dev *dev); 942 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 943 int pcie_get_readrq(struct pci_dev *dev); 944 int pcie_set_readrq(struct pci_dev *dev, int rq); 945 int pcie_get_mps(struct pci_dev *dev); 946 int pcie_set_mps(struct pci_dev *dev, int mps); 947 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 948 enum pcie_link_width *width); 949 int __pci_reset_function(struct pci_dev *dev); 950 int __pci_reset_function_locked(struct pci_dev *dev); 951 int pci_reset_function(struct pci_dev *dev); 952 int pci_try_reset_function(struct pci_dev *dev); 953 int pci_probe_reset_slot(struct pci_slot *slot); 954 int pci_reset_slot(struct pci_slot *slot); 955 int pci_try_reset_slot(struct pci_slot *slot); 956 int pci_probe_reset_bus(struct pci_bus *bus); 957 int pci_reset_bus(struct pci_bus *bus); 958 int pci_try_reset_bus(struct pci_bus *bus); 959 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 960 void pci_update_resource(struct pci_dev *dev, int resno); 961 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 962 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 963 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 964 bool pci_device_is_present(struct pci_dev *pdev); 965 966 /* ROM control related routines */ 967 int pci_enable_rom(struct pci_dev *pdev); 968 void pci_disable_rom(struct pci_dev *pdev); 969 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 970 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 971 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 972 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 973 974 /* Power management related routines */ 975 int pci_save_state(struct pci_dev *dev); 976 void pci_restore_state(struct pci_dev *dev); 977 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 978 int pci_load_and_free_saved_state(struct pci_dev *dev, 979 struct pci_saved_state **state); 980 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 981 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 982 u16 cap); 983 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 984 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 985 u16 cap, unsigned int size); 986 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 987 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 988 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 989 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 990 void pci_pme_active(struct pci_dev *dev, bool enable); 991 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 992 bool runtime, bool enable); 993 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 994 int pci_prepare_to_sleep(struct pci_dev *dev); 995 int pci_back_from_sleep(struct pci_dev *dev); 996 bool pci_dev_run_wake(struct pci_dev *dev); 997 bool pci_check_pme_status(struct pci_dev *dev); 998 void pci_pme_wakeup_bus(struct pci_bus *bus); 999 1000 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1001 bool enable) 1002 { 1003 return __pci_enable_wake(dev, state, false, enable); 1004 } 1005 1006 /* PCI Virtual Channel */ 1007 int pci_save_vc_state(struct pci_dev *dev); 1008 void pci_restore_vc_state(struct pci_dev *dev); 1009 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1010 1011 /* For use by arch with custom probe code */ 1012 void set_pcie_port_type(struct pci_dev *pdev); 1013 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1014 1015 /* Functions for PCI Hotplug drivers to use */ 1016 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1017 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1018 unsigned int pci_rescan_bus(struct pci_bus *bus); 1019 void pci_lock_rescan_remove(void); 1020 void pci_unlock_rescan_remove(void); 1021 1022 /* Vital product data routines */ 1023 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1024 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1025 1026 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1027 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1028 void pci_bus_assign_resources(const struct pci_bus *bus); 1029 void pci_bus_size_bridges(struct pci_bus *bus); 1030 int pci_claim_resource(struct pci_dev *, int); 1031 void pci_assign_unassigned_resources(void); 1032 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1033 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1034 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1035 void pdev_enable_device(struct pci_dev *); 1036 int pci_enable_resources(struct pci_dev *, int mask); 1037 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1038 int (*)(const struct pci_dev *, u8, u8)); 1039 #define HAVE_PCI_REQ_REGIONS 2 1040 int __must_check pci_request_regions(struct pci_dev *, const char *); 1041 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1042 void pci_release_regions(struct pci_dev *); 1043 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1044 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1045 void pci_release_region(struct pci_dev *, int); 1046 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1047 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1048 void pci_release_selected_regions(struct pci_dev *, int); 1049 1050 /* drivers/pci/bus.c */ 1051 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1052 void pci_bus_put(struct pci_bus *bus); 1053 void pci_add_resource(struct list_head *resources, struct resource *res); 1054 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1055 resource_size_t offset); 1056 void pci_free_resource_list(struct list_head *resources); 1057 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1058 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1059 void pci_bus_remove_resources(struct pci_bus *bus); 1060 1061 #define pci_bus_for_each_resource(bus, res, i) \ 1062 for (i = 0; \ 1063 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1064 i++) 1065 1066 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1067 struct resource *res, resource_size_t size, 1068 resource_size_t align, resource_size_t min, 1069 unsigned long type_mask, 1070 resource_size_t (*alignf)(void *, 1071 const struct resource *, 1072 resource_size_t, 1073 resource_size_t), 1074 void *alignf_data); 1075 1076 static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1077 { 1078 struct pci_bus_region region; 1079 1080 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1081 return region.start; 1082 } 1083 1084 /* Proper probing supporting hot-pluggable devices */ 1085 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1086 const char *mod_name); 1087 1088 /* 1089 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1090 */ 1091 #define pci_register_driver(driver) \ 1092 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1093 1094 void pci_unregister_driver(struct pci_driver *dev); 1095 1096 /** 1097 * module_pci_driver() - Helper macro for registering a PCI driver 1098 * @__pci_driver: pci_driver struct 1099 * 1100 * Helper macro for PCI drivers which do not do anything special in module 1101 * init/exit. This eliminates a lot of boilerplate. Each module may only 1102 * use this macro once, and calling it replaces module_init() and module_exit() 1103 */ 1104 #define module_pci_driver(__pci_driver) \ 1105 module_driver(__pci_driver, pci_register_driver, \ 1106 pci_unregister_driver) 1107 1108 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1109 int pci_add_dynid(struct pci_driver *drv, 1110 unsigned int vendor, unsigned int device, 1111 unsigned int subvendor, unsigned int subdevice, 1112 unsigned int class, unsigned int class_mask, 1113 unsigned long driver_data); 1114 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1115 struct pci_dev *dev); 1116 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1117 int pass); 1118 1119 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1120 void *userdata); 1121 int pci_cfg_space_size(struct pci_dev *dev); 1122 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1123 void pci_setup_bridge(struct pci_bus *bus); 1124 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1125 unsigned long type); 1126 1127 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1128 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1129 1130 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1131 unsigned int command_bits, u32 flags); 1132 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1133 1134 #include <linux/pci-dma.h> 1135 #include <linux/dmapool.h> 1136 1137 #define pci_pool dma_pool 1138 #define pci_pool_create(name, pdev, size, align, allocation) \ 1139 dma_pool_create(name, &pdev->dev, size, align, allocation) 1140 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1141 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1142 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1143 1144 enum pci_dma_burst_strategy { 1145 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, 1146 strategy_parameter is N/A */ 1147 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter 1148 byte boundaries */ 1149 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of 1150 strategy_parameter byte boundaries */ 1151 }; 1152 1153 struct msix_entry { 1154 u32 vector; /* kernel uses to write allocated vector */ 1155 u16 entry; /* driver uses to specify entry, OS writes */ 1156 }; 1157 1158 1159 #ifdef CONFIG_PCI_MSI 1160 int pci_msi_vec_count(struct pci_dev *dev); 1161 int pci_enable_msi_block(struct pci_dev *dev, int nvec); 1162 void pci_msi_shutdown(struct pci_dev *dev); 1163 void pci_disable_msi(struct pci_dev *dev); 1164 int pci_msix_vec_count(struct pci_dev *dev); 1165 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1166 void pci_msix_shutdown(struct pci_dev *dev); 1167 void pci_disable_msix(struct pci_dev *dev); 1168 void msi_remove_pci_irq_vectors(struct pci_dev *dev); 1169 void pci_restore_msi_state(struct pci_dev *dev); 1170 int pci_msi_enabled(void); 1171 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1172 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1173 { 1174 int rc = pci_enable_msi_range(dev, nvec, nvec); 1175 if (rc < 0) 1176 return rc; 1177 return 0; 1178 } 1179 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1180 int minvec, int maxvec); 1181 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1182 struct msix_entry *entries, int nvec) 1183 { 1184 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1185 if (rc < 0) 1186 return rc; 1187 return 0; 1188 } 1189 #else 1190 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1191 static inline int pci_enable_msi_block(struct pci_dev *dev, int nvec) 1192 { return -ENOSYS; } 1193 static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1194 static inline void pci_disable_msi(struct pci_dev *dev) { } 1195 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1196 static inline int pci_enable_msix(struct pci_dev *dev, 1197 struct msix_entry *entries, int nvec) 1198 { return -ENOSYS; } 1199 static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1200 static inline void pci_disable_msix(struct pci_dev *dev) { } 1201 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) { } 1202 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1203 static inline int pci_msi_enabled(void) { return 0; } 1204 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1205 int maxvec) 1206 { return -ENOSYS; } 1207 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1208 { return -ENOSYS; } 1209 static inline int pci_enable_msix_range(struct pci_dev *dev, 1210 struct msix_entry *entries, int minvec, int maxvec) 1211 { return -ENOSYS; } 1212 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1213 struct msix_entry *entries, int nvec) 1214 { return -ENOSYS; } 1215 #endif 1216 1217 #ifdef CONFIG_PCIEPORTBUS 1218 extern bool pcie_ports_disabled; 1219 extern bool pcie_ports_auto; 1220 #else 1221 #define pcie_ports_disabled true 1222 #define pcie_ports_auto false 1223 #endif 1224 1225 #ifdef CONFIG_PCIEASPM 1226 bool pcie_aspm_support_enabled(void); 1227 #else 1228 static inline bool pcie_aspm_support_enabled(void) { return false; } 1229 #endif 1230 1231 #ifdef CONFIG_PCIEAER 1232 void pci_no_aer(void); 1233 bool pci_aer_available(void); 1234 #else 1235 static inline void pci_no_aer(void) { } 1236 static inline bool pci_aer_available(void) { return false; } 1237 #endif 1238 1239 #ifdef CONFIG_PCIE_ECRC 1240 void pcie_set_ecrc_checking(struct pci_dev *dev); 1241 void pcie_ecrc_get_policy(char *str); 1242 #else 1243 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1244 static inline void pcie_ecrc_get_policy(char *str) { } 1245 #endif 1246 1247 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) 1248 1249 #ifdef CONFIG_HT_IRQ 1250 /* The functions a driver should call */ 1251 int ht_create_irq(struct pci_dev *dev, int idx); 1252 void ht_destroy_irq(unsigned int irq); 1253 #endif /* CONFIG_HT_IRQ */ 1254 1255 void pci_cfg_access_lock(struct pci_dev *dev); 1256 bool pci_cfg_access_trylock(struct pci_dev *dev); 1257 void pci_cfg_access_unlock(struct pci_dev *dev); 1258 1259 /* 1260 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1261 * a PCI domain is defined to be a set of PCI buses which share 1262 * configuration space. 1263 */ 1264 #ifdef CONFIG_PCI_DOMAINS 1265 extern int pci_domains_supported; 1266 #else 1267 enum { pci_domains_supported = 0 }; 1268 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1269 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1270 #endif /* CONFIG_PCI_DOMAINS */ 1271 1272 /* some architectures require additional setup to direct VGA traffic */ 1273 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1274 unsigned int command_bits, u32 flags); 1275 void pci_register_set_vga_state(arch_set_vga_state_t func); 1276 1277 #else /* CONFIG_PCI is not enabled */ 1278 1279 /* 1280 * If the system does not have PCI, clearly these return errors. Define 1281 * these as simple inline functions to avoid hair in drivers. 1282 */ 1283 1284 #define _PCI_NOP(o, s, t) \ 1285 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1286 int where, t val) \ 1287 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1288 1289 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1290 _PCI_NOP(o, word, u16 x) \ 1291 _PCI_NOP(o, dword, u32 x) 1292 _PCI_NOP_ALL(read, *) 1293 _PCI_NOP_ALL(write,) 1294 1295 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1296 unsigned int device, 1297 struct pci_dev *from) 1298 { return NULL; } 1299 1300 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1301 unsigned int device, 1302 unsigned int ss_vendor, 1303 unsigned int ss_device, 1304 struct pci_dev *from) 1305 { return NULL; } 1306 1307 static inline struct pci_dev *pci_get_class(unsigned int class, 1308 struct pci_dev *from) 1309 { return NULL; } 1310 1311 #define pci_dev_present(ids) (0) 1312 #define no_pci_devices() (1) 1313 #define pci_dev_put(dev) do { } while (0) 1314 1315 static inline void pci_set_master(struct pci_dev *dev) { } 1316 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1317 static inline void pci_disable_device(struct pci_dev *dev) { } 1318 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1319 { return -EIO; } 1320 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1321 { return -EIO; } 1322 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1323 unsigned int size) 1324 { return -EIO; } 1325 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1326 unsigned long mask) 1327 { return -EIO; } 1328 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1329 { return -EBUSY; } 1330 static inline int __pci_register_driver(struct pci_driver *drv, 1331 struct module *owner) 1332 { return 0; } 1333 static inline int pci_register_driver(struct pci_driver *drv) 1334 { return 0; } 1335 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1336 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1337 { return 0; } 1338 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1339 int cap) 1340 { return 0; } 1341 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1342 { return 0; } 1343 1344 /* Power management related routines */ 1345 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1346 static inline void pci_restore_state(struct pci_dev *dev) { } 1347 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1348 { return 0; } 1349 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1350 { return 0; } 1351 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1352 pm_message_t state) 1353 { return PCI_D0; } 1354 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1355 int enable) 1356 { return 0; } 1357 1358 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1359 { return -EIO; } 1360 static inline void pci_release_regions(struct pci_dev *dev) { } 1361 1362 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 1363 1364 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1365 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1366 { return 0; } 1367 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1368 1369 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1370 { return NULL; } 1371 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1372 unsigned int devfn) 1373 { return NULL; } 1374 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1375 unsigned int devfn) 1376 { return NULL; } 1377 1378 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1379 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1380 1381 #define dev_is_pci(d) (false) 1382 #define dev_is_pf(d) (false) 1383 #define dev_num_vf(d) (0) 1384 #endif /* CONFIG_PCI */ 1385 1386 /* Include architecture-dependent settings and functions */ 1387 1388 #include <asm/pci.h> 1389 1390 /* these helpers provide future and backwards compatibility 1391 * for accessing popular PCI BAR info */ 1392 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1393 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1394 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1395 #define pci_resource_len(dev,bar) \ 1396 ((pci_resource_start((dev), (bar)) == 0 && \ 1397 pci_resource_end((dev), (bar)) == \ 1398 pci_resource_start((dev), (bar))) ? 0 : \ 1399 \ 1400 (pci_resource_end((dev), (bar)) - \ 1401 pci_resource_start((dev), (bar)) + 1)) 1402 1403 /* Similar to the helpers above, these manipulate per-pci_dev 1404 * driver-specific data. They are really just a wrapper around 1405 * the generic device structure functions of these calls. 1406 */ 1407 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1408 { 1409 return dev_get_drvdata(&pdev->dev); 1410 } 1411 1412 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1413 { 1414 dev_set_drvdata(&pdev->dev, data); 1415 } 1416 1417 /* If you want to know what to call your pci_dev, ask this function. 1418 * Again, it's a wrapper around the generic device. 1419 */ 1420 static inline const char *pci_name(const struct pci_dev *pdev) 1421 { 1422 return dev_name(&pdev->dev); 1423 } 1424 1425 1426 /* Some archs don't want to expose struct resource to userland as-is 1427 * in sysfs and /proc 1428 */ 1429 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1430 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1431 const struct resource *rsrc, resource_size_t *start, 1432 resource_size_t *end) 1433 { 1434 *start = rsrc->start; 1435 *end = rsrc->end; 1436 } 1437 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1438 1439 1440 /* 1441 * The world is not perfect and supplies us with broken PCI devices. 1442 * For at least a part of these bugs we need a work-around, so both 1443 * generic (drivers/pci/quirks.c) and per-architecture code can define 1444 * fixup hooks to be called for particular buggy devices. 1445 */ 1446 1447 struct pci_fixup { 1448 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1449 u16 device; /* You can use PCI_ANY_ID here of course */ 1450 u32 class; /* You can use PCI_ANY_ID here too */ 1451 unsigned int class_shift; /* should be 0, 8, 16 */ 1452 void (*hook)(struct pci_dev *dev); 1453 }; 1454 1455 enum pci_fixup_pass { 1456 pci_fixup_early, /* Before probing BARs */ 1457 pci_fixup_header, /* After reading configuration header */ 1458 pci_fixup_final, /* Final phase of device fixups */ 1459 pci_fixup_enable, /* pci_enable_device() time */ 1460 pci_fixup_resume, /* pci_device_resume() */ 1461 pci_fixup_suspend, /* pci_device_suspend */ 1462 pci_fixup_resume_early, /* pci_device_resume_early() */ 1463 }; 1464 1465 /* Anonymous variables would be nice... */ 1466 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1467 class_shift, hook) \ 1468 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1469 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1470 = { vendor, device, class, class_shift, hook }; 1471 1472 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1473 class_shift, hook) \ 1474 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1475 hook, vendor, device, class, class_shift, hook) 1476 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1477 class_shift, hook) \ 1478 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1479 hook, vendor, device, class, class_shift, hook) 1480 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1481 class_shift, hook) \ 1482 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1483 hook, vendor, device, class, class_shift, hook) 1484 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1485 class_shift, hook) \ 1486 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1487 hook, vendor, device, class, class_shift, hook) 1488 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1489 class_shift, hook) \ 1490 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1491 resume##hook, vendor, device, class, \ 1492 class_shift, hook) 1493 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1494 class_shift, hook) \ 1495 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1496 resume_early##hook, vendor, device, \ 1497 class, class_shift, hook) 1498 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1499 class_shift, hook) \ 1500 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1501 suspend##hook, vendor, device, class, \ 1502 class_shift, hook) 1503 1504 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1505 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1506 hook, vendor, device, PCI_ANY_ID, 0, hook) 1507 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1508 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1509 hook, vendor, device, PCI_ANY_ID, 0, hook) 1510 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1511 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1512 hook, vendor, device, PCI_ANY_ID, 0, hook) 1513 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1514 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1515 hook, vendor, device, PCI_ANY_ID, 0, hook) 1516 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1517 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1518 resume##hook, vendor, device, \ 1519 PCI_ANY_ID, 0, hook) 1520 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1521 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1522 resume_early##hook, vendor, device, \ 1523 PCI_ANY_ID, 0, hook) 1524 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1525 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1526 suspend##hook, vendor, device, \ 1527 PCI_ANY_ID, 0, hook) 1528 1529 #ifdef CONFIG_PCI_QUIRKS 1530 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1531 struct pci_dev *pci_get_dma_source(struct pci_dev *dev); 1532 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1533 void pci_dev_specific_enable_acs(struct pci_dev *dev); 1534 #else 1535 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1536 struct pci_dev *dev) { } 1537 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev) 1538 { 1539 return pci_dev_get(dev); 1540 } 1541 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1542 u16 acs_flags) 1543 { 1544 return -ENOTTY; 1545 } 1546 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } 1547 #endif 1548 1549 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1550 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1551 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1552 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1553 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1554 const char *name); 1555 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1556 1557 extern int pci_pci_problems; 1558 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1559 #define PCIPCI_TRITON 2 1560 #define PCIPCI_NATOMA 4 1561 #define PCIPCI_VIAETBF 8 1562 #define PCIPCI_VSFX 16 1563 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1564 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1565 1566 extern unsigned long pci_cardbus_io_size; 1567 extern unsigned long pci_cardbus_mem_size; 1568 extern u8 pci_dfl_cache_line_size; 1569 extern u8 pci_cache_line_size; 1570 1571 extern unsigned long pci_hotplug_io_size; 1572 extern unsigned long pci_hotplug_mem_size; 1573 1574 /* Architecture-specific versions may override these (weak) */ 1575 int pcibios_add_platform_entries(struct pci_dev *dev); 1576 void pcibios_disable_device(struct pci_dev *dev); 1577 void pcibios_set_master(struct pci_dev *dev); 1578 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1579 enum pcie_reset_state state); 1580 int pcibios_add_device(struct pci_dev *dev); 1581 void pcibios_release_device(struct pci_dev *dev); 1582 1583 #ifdef CONFIG_HIBERNATE_CALLBACKS 1584 extern struct dev_pm_ops pcibios_pm_ops; 1585 #endif 1586 1587 #ifdef CONFIG_PCI_MMCONFIG 1588 void __init pci_mmcfg_early_init(void); 1589 void __init pci_mmcfg_late_init(void); 1590 #else 1591 static inline void pci_mmcfg_early_init(void) { } 1592 static inline void pci_mmcfg_late_init(void) { } 1593 #endif 1594 1595 int pci_ext_cfg_avail(void); 1596 1597 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1598 1599 #ifdef CONFIG_PCI_IOV 1600 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1601 void pci_disable_sriov(struct pci_dev *dev); 1602 int pci_num_vf(struct pci_dev *dev); 1603 int pci_vfs_assigned(struct pci_dev *dev); 1604 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1605 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1606 #else 1607 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1608 { return -ENODEV; } 1609 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1610 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1611 static inline int pci_vfs_assigned(struct pci_dev *dev) 1612 { return 0; } 1613 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1614 { return 0; } 1615 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1616 { return 0; } 1617 #endif 1618 1619 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1620 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1621 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1622 #endif 1623 1624 /** 1625 * pci_pcie_cap - get the saved PCIe capability offset 1626 * @dev: PCI device 1627 * 1628 * PCIe capability offset is calculated at PCI device initialization 1629 * time and saved in the data structure. This function returns saved 1630 * PCIe capability offset. Using this instead of pci_find_capability() 1631 * reduces unnecessary search in the PCI configuration space. If you 1632 * need to calculate PCIe capability offset from raw device for some 1633 * reasons, please use pci_find_capability() instead. 1634 */ 1635 static inline int pci_pcie_cap(struct pci_dev *dev) 1636 { 1637 return dev->pcie_cap; 1638 } 1639 1640 /** 1641 * pci_is_pcie - check if the PCI device is PCI Express capable 1642 * @dev: PCI device 1643 * 1644 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1645 */ 1646 static inline bool pci_is_pcie(struct pci_dev *dev) 1647 { 1648 return pci_pcie_cap(dev); 1649 } 1650 1651 /** 1652 * pcie_caps_reg - get the PCIe Capabilities Register 1653 * @dev: PCI device 1654 */ 1655 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1656 { 1657 return dev->pcie_flags_reg; 1658 } 1659 1660 /** 1661 * pci_pcie_type - get the PCIe device/port type 1662 * @dev: PCI device 1663 */ 1664 static inline int pci_pcie_type(const struct pci_dev *dev) 1665 { 1666 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1667 } 1668 1669 void pci_request_acs(void); 1670 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1671 bool pci_acs_path_enabled(struct pci_dev *start, 1672 struct pci_dev *end, u16 acs_flags); 1673 1674 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1675 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) 1676 1677 /* Large Resource Data Type Tag Item Names */ 1678 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1679 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1680 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1681 1682 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1683 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1684 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1685 1686 /* Small Resource Data Type Tag Item Names */ 1687 #define PCI_VPD_STIN_END 0x78 /* End */ 1688 1689 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1690 1691 #define PCI_VPD_SRDT_TIN_MASK 0x78 1692 #define PCI_VPD_SRDT_LEN_MASK 0x07 1693 1694 #define PCI_VPD_LRDT_TAG_SIZE 3 1695 #define PCI_VPD_SRDT_TAG_SIZE 1 1696 1697 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1698 1699 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1700 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1701 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1702 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1703 1704 /** 1705 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1706 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1707 * 1708 * Returns the extracted Large Resource Data Type length. 1709 */ 1710 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1711 { 1712 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1713 } 1714 1715 /** 1716 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1717 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1718 * 1719 * Returns the extracted Small Resource Data Type length. 1720 */ 1721 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1722 { 1723 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1724 } 1725 1726 /** 1727 * pci_vpd_info_field_size - Extracts the information field length 1728 * @lrdt: Pointer to the beginning of an information field header 1729 * 1730 * Returns the extracted information field length. 1731 */ 1732 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1733 { 1734 return info_field[2]; 1735 } 1736 1737 /** 1738 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1739 * @buf: Pointer to buffered vpd data 1740 * @off: The offset into the buffer at which to begin the search 1741 * @len: The length of the vpd buffer 1742 * @rdt: The Resource Data Type to search for 1743 * 1744 * Returns the index where the Resource Data Type was found or 1745 * -ENOENT otherwise. 1746 */ 1747 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1748 1749 /** 1750 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1751 * @buf: Pointer to buffered vpd data 1752 * @off: The offset into the buffer at which to begin the search 1753 * @len: The length of the buffer area, relative to off, in which to search 1754 * @kw: The keyword to search for 1755 * 1756 * Returns the index where the information field keyword was found or 1757 * -ENOENT otherwise. 1758 */ 1759 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1760 unsigned int len, const char *kw); 1761 1762 /* PCI <-> OF binding helpers */ 1763 #ifdef CONFIG_OF 1764 struct device_node; 1765 void pci_set_of_node(struct pci_dev *dev); 1766 void pci_release_of_node(struct pci_dev *dev); 1767 void pci_set_bus_of_node(struct pci_bus *bus); 1768 void pci_release_bus_of_node(struct pci_bus *bus); 1769 1770 /* Arch may override this (weak) */ 1771 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1772 1773 static inline struct device_node * 1774 pci_device_to_OF_node(const struct pci_dev *pdev) 1775 { 1776 return pdev ? pdev->dev.of_node : NULL; 1777 } 1778 1779 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1780 { 1781 return bus ? bus->dev.of_node : NULL; 1782 } 1783 1784 #else /* CONFIG_OF */ 1785 static inline void pci_set_of_node(struct pci_dev *dev) { } 1786 static inline void pci_release_of_node(struct pci_dev *dev) { } 1787 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1788 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1789 #endif /* CONFIG_OF */ 1790 1791 #ifdef CONFIG_EEH 1792 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1793 { 1794 return pdev->dev.archdata.edev; 1795 } 1796 #endif 1797 1798 /** 1799 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device 1800 * @pdev: the PCI device 1801 * 1802 * if the device is PCIE, return NULL 1803 * if the device isn't connected to a PCIe bridge (that is its parent is a 1804 * legacy PCI bridge and the bridge is directly connected to bus 0), return its 1805 * parent 1806 */ 1807 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); 1808 1809 #endif /* LINUX_PCI_H */ 1810