1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/interrupt.h> 32 #include <linux/io.h> 33 #include <linux/resource_ext.h> 34 #include <uapi/linux/pci.h> 35 36 #include <linux/pci_ids.h> 37 38 /* 39 * The PCI interface treats multi-function devices as independent 40 * devices. The slot/function address of each device is encoded 41 * in a single byte as follows: 42 * 43 * 7:3 = slot 44 * 2:0 = function 45 * 46 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 47 * In the interest of not exposing interfaces to user-space unnecessarily, 48 * the following kernel-only defines are being added here. 49 */ 50 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 51 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 52 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 53 54 /* pci_slot represents a physical slot */ 55 struct pci_slot { 56 struct pci_bus *bus; /* The bus this slot is on */ 57 struct list_head list; /* node in list of slots on this bus */ 58 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 59 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 60 struct kobject kobj; 61 }; 62 63 static inline const char *pci_slot_name(const struct pci_slot *slot) 64 { 65 return kobject_name(&slot->kobj); 66 } 67 68 /* File state for mmap()s on /proc/bus/pci/X/Y */ 69 enum pci_mmap_state { 70 pci_mmap_io, 71 pci_mmap_mem 72 }; 73 74 /* 75 * For PCI devices, the region numbers are assigned this way: 76 */ 77 enum { 78 /* #0-5: standard PCI resources */ 79 PCI_STD_RESOURCES, 80 PCI_STD_RESOURCE_END = 5, 81 82 /* #6: expansion ROM resource */ 83 PCI_ROM_RESOURCE, 84 85 /* device specific resources */ 86 #ifdef CONFIG_PCI_IOV 87 PCI_IOV_RESOURCES, 88 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 89 #endif 90 91 /* resources assigned to buses behind the bridge */ 92 #define PCI_BRIDGE_RESOURCE_NUM 4 93 94 PCI_BRIDGE_RESOURCES, 95 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 96 PCI_BRIDGE_RESOURCE_NUM - 1, 97 98 /* total resources associated with a PCI device */ 99 PCI_NUM_RESOURCES, 100 101 /* preserve this for compatibility */ 102 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 103 }; 104 105 /* 106 * pci_power_t values must match the bits in the Capabilities PME_Support 107 * and Control/Status PowerState fields in the Power Management capability. 108 */ 109 typedef int __bitwise pci_power_t; 110 111 #define PCI_D0 ((pci_power_t __force) 0) 112 #define PCI_D1 ((pci_power_t __force) 1) 113 #define PCI_D2 ((pci_power_t __force) 2) 114 #define PCI_D3hot ((pci_power_t __force) 3) 115 #define PCI_D3cold ((pci_power_t __force) 4) 116 #define PCI_UNKNOWN ((pci_power_t __force) 5) 117 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 118 119 /* Remember to update this when the list above changes! */ 120 extern const char *pci_power_names[]; 121 122 static inline const char *pci_power_name(pci_power_t state) 123 { 124 return pci_power_names[1 + (__force int) state]; 125 } 126 127 #define PCI_PM_D2_DELAY 200 128 #define PCI_PM_D3_WAIT 10 129 #define PCI_PM_D3COLD_WAIT 100 130 #define PCI_PM_BUS_WAIT 50 131 132 /** The pci_channel state describes connectivity between the CPU and 133 * the pci device. If some PCI bus between here and the pci device 134 * has crashed or locked up, this info is reflected here. 135 */ 136 typedef unsigned int __bitwise pci_channel_state_t; 137 138 enum pci_channel_state { 139 /* I/O channel is in normal state */ 140 pci_channel_io_normal = (__force pci_channel_state_t) 1, 141 142 /* I/O to channel is blocked */ 143 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 144 145 /* PCI card is dead */ 146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 147 }; 148 149 typedef unsigned int __bitwise pcie_reset_state_t; 150 151 enum pcie_reset_state { 152 /* Reset is NOT asserted (Use to deassert reset) */ 153 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 154 155 /* Use #PERST to reset PCIe device */ 156 pcie_warm_reset = (__force pcie_reset_state_t) 2, 157 158 /* Use PCIe Hot Reset to reset device */ 159 pcie_hot_reset = (__force pcie_reset_state_t) 3 160 }; 161 162 typedef unsigned short __bitwise pci_dev_flags_t; 163 enum pci_dev_flags { 164 /* INTX_DISABLE in PCI_COMMAND register disables MSI 165 * generation too. 166 */ 167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 168 /* Device configuration is irrevocably lost if disabled into D3 */ 169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 170 /* Provide indication device is assigned by a Virtual Machine Manager */ 171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 172 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 174 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 175 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 176 /* Do not use bus resets for device */ 177 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 178 /* Do not use PM reset even if device advertises NoSoftRst- */ 179 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 180 /* Get VPD from function 0 VPD */ 181 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 182 /* a non-root bridge where translation occurs, stop alias search here */ 183 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 184 /* Do not use FLR even if device advertises PCI_AF_CAP */ 185 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 186 }; 187 188 enum pci_irq_reroute_variant { 189 INTEL_IRQ_REROUTE_VARIANT = 1, 190 MAX_IRQ_REROUTE_VARIANTS = 3 191 }; 192 193 typedef unsigned short __bitwise pci_bus_flags_t; 194 enum pci_bus_flags { 195 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 196 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 197 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 198 }; 199 200 /* These values come from the PCI Express Spec */ 201 enum pcie_link_width { 202 PCIE_LNK_WIDTH_RESRV = 0x00, 203 PCIE_LNK_X1 = 0x01, 204 PCIE_LNK_X2 = 0x02, 205 PCIE_LNK_X4 = 0x04, 206 PCIE_LNK_X8 = 0x08, 207 PCIE_LNK_X12 = 0x0C, 208 PCIE_LNK_X16 = 0x10, 209 PCIE_LNK_X32 = 0x20, 210 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 211 }; 212 213 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 214 enum pci_bus_speed { 215 PCI_SPEED_33MHz = 0x00, 216 PCI_SPEED_66MHz = 0x01, 217 PCI_SPEED_66MHz_PCIX = 0x02, 218 PCI_SPEED_100MHz_PCIX = 0x03, 219 PCI_SPEED_133MHz_PCIX = 0x04, 220 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 221 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 222 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 223 PCI_SPEED_66MHz_PCIX_266 = 0x09, 224 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 225 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 226 AGP_UNKNOWN = 0x0c, 227 AGP_1X = 0x0d, 228 AGP_2X = 0x0e, 229 AGP_4X = 0x0f, 230 AGP_8X = 0x10, 231 PCI_SPEED_66MHz_PCIX_533 = 0x11, 232 PCI_SPEED_100MHz_PCIX_533 = 0x12, 233 PCI_SPEED_133MHz_PCIX_533 = 0x13, 234 PCIE_SPEED_2_5GT = 0x14, 235 PCIE_SPEED_5_0GT = 0x15, 236 PCIE_SPEED_8_0GT = 0x16, 237 PCI_SPEED_UNKNOWN = 0xff, 238 }; 239 240 struct pci_cap_saved_data { 241 u16 cap_nr; 242 bool cap_extended; 243 unsigned int size; 244 u32 data[0]; 245 }; 246 247 struct pci_cap_saved_state { 248 struct hlist_node next; 249 struct pci_cap_saved_data cap; 250 }; 251 252 struct irq_affinity; 253 struct pcie_link_state; 254 struct pci_vpd; 255 struct pci_sriov; 256 struct pci_ats; 257 258 /* 259 * The pci_dev structure is used to describe PCI devices. 260 */ 261 struct pci_dev { 262 struct list_head bus_list; /* node in per-bus list */ 263 struct pci_bus *bus; /* bus this device is on */ 264 struct pci_bus *subordinate; /* bus this device bridges to */ 265 266 void *sysdata; /* hook for sys-specific extension */ 267 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 268 struct pci_slot *slot; /* Physical slot this device is in */ 269 270 unsigned int devfn; /* encoded device & function index */ 271 unsigned short vendor; 272 unsigned short device; 273 unsigned short subsystem_vendor; 274 unsigned short subsystem_device; 275 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 276 u8 revision; /* PCI revision, low byte of class word */ 277 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 278 #ifdef CONFIG_PCIEAER 279 u16 aer_cap; /* AER capability offset */ 280 #endif 281 u8 pcie_cap; /* PCIe capability offset */ 282 u8 msi_cap; /* MSI capability offset */ 283 u8 msix_cap; /* MSI-X capability offset */ 284 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 285 u8 rom_base_reg; /* which config register controls the ROM */ 286 u8 pin; /* which interrupt pin this device uses */ 287 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 288 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */ 289 290 struct pci_driver *driver; /* which driver has allocated this device */ 291 u64 dma_mask; /* Mask of the bits of bus address this 292 device implements. Normally this is 293 0xffffffff. You only need to change 294 this if your device has broken DMA 295 or supports 64-bit transfers. */ 296 297 struct device_dma_parameters dma_parms; 298 299 pci_power_t current_state; /* Current operating state. In ACPI-speak, 300 this is D0-D3, D0 being fully functional, 301 and D3 being off. */ 302 u8 pm_cap; /* PM capability offset */ 303 unsigned int pme_support:5; /* Bitmask of states from which PME# 304 can be generated */ 305 unsigned int pme_interrupt:1; 306 unsigned int pme_poll:1; /* Poll device's PME status bit */ 307 unsigned int d1_support:1; /* Low power state D1 is supported */ 308 unsigned int d2_support:1; /* Low power state D2 is supported */ 309 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 310 unsigned int no_d3cold:1; /* D3cold is forbidden */ 311 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 312 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 313 unsigned int mmio_always_on:1; /* disallow turning off io/mem 314 decoding during bar sizing */ 315 unsigned int wakeup_prepared:1; 316 unsigned int runtime_d3cold:1; /* whether go through runtime 317 D3cold, not set for devices 318 powered on/off by the 319 corresponding bridge */ 320 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 321 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 322 controlled exclusively by 323 user sysfs */ 324 unsigned int d3_delay; /* D3->D0 transition time in ms */ 325 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 326 327 #ifdef CONFIG_PCIEASPM 328 struct pcie_link_state *link_state; /* ASPM link state */ 329 #endif 330 331 pci_channel_state_t error_state; /* current connectivity state */ 332 struct device dev; /* Generic device interface */ 333 334 int cfg_size; /* Size of configuration space */ 335 336 /* 337 * Instead of touching interrupt line and base address registers 338 * directly, use the values stored here. They might be different! 339 */ 340 unsigned int irq; 341 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 342 343 bool match_driver; /* Skip attaching driver */ 344 /* These fields are used by common fixups */ 345 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 346 unsigned int multifunction:1;/* Part of multi-function device */ 347 /* keep track of device state */ 348 unsigned int is_added:1; 349 unsigned int is_busmaster:1; /* device is busmaster */ 350 unsigned int no_msi:1; /* device may not use msi */ 351 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 352 unsigned int block_cfg_access:1; /* config space access is blocked */ 353 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 354 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 355 unsigned int msi_enabled:1; 356 unsigned int msix_enabled:1; 357 unsigned int ari_enabled:1; /* ARI forwarding */ 358 unsigned int ats_enabled:1; /* Address Translation Service */ 359 unsigned int is_managed:1; 360 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 361 unsigned int state_saved:1; 362 unsigned int is_physfn:1; 363 unsigned int is_virtfn:1; 364 unsigned int reset_fn:1; 365 unsigned int is_hotplug_bridge:1; 366 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 367 unsigned int __aer_firmware_first_valid:1; 368 unsigned int __aer_firmware_first:1; 369 unsigned int broken_intx_masking:1; 370 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 371 unsigned int irq_managed:1; 372 unsigned int has_secondary_link:1; 373 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 374 pci_dev_flags_t dev_flags; 375 atomic_t enable_cnt; /* pci_enable_device has been called */ 376 377 u32 saved_config_space[16]; /* config space saved at suspend time */ 378 struct hlist_head saved_cap_space; 379 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 380 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 381 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 382 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 383 384 #ifdef CONFIG_PCIE_PTM 385 unsigned int ptm_root:1; 386 unsigned int ptm_enabled:1; 387 u8 ptm_granularity; 388 #endif 389 #ifdef CONFIG_PCI_MSI 390 const struct attribute_group **msi_irq_groups; 391 #endif 392 struct pci_vpd *vpd; 393 #ifdef CONFIG_PCI_ATS 394 union { 395 struct pci_sriov *sriov; /* SR-IOV capability related */ 396 struct pci_dev *physfn; /* the PF this VF is associated with */ 397 }; 398 u16 ats_cap; /* ATS Capability offset */ 399 u8 ats_stu; /* ATS Smallest Translation Unit */ 400 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 401 #endif 402 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 403 size_t romlen; /* Length of ROM if it's not from the BAR */ 404 char *driver_override; /* Driver name to force a match */ 405 406 unsigned long priv_flags; /* Private flags for the pci driver */ 407 }; 408 409 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 410 { 411 #ifdef CONFIG_PCI_IOV 412 if (dev->is_virtfn) 413 dev = dev->physfn; 414 #endif 415 return dev; 416 } 417 418 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 419 420 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 421 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 422 423 static inline int pci_channel_offline(struct pci_dev *pdev) 424 { 425 return (pdev->error_state != pci_channel_io_normal); 426 } 427 428 struct pci_host_bridge { 429 struct device dev; 430 struct pci_bus *bus; /* root bus */ 431 struct pci_ops *ops; 432 void *sysdata; 433 int busnr; 434 struct list_head windows; /* resource_entry */ 435 void (*release_fn)(struct pci_host_bridge *); 436 void *release_data; 437 struct msi_controller *msi; 438 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 439 /* Resource alignment requirements */ 440 resource_size_t (*align_resource)(struct pci_dev *dev, 441 const struct resource *res, 442 resource_size_t start, 443 resource_size_t size, 444 resource_size_t align); 445 unsigned long private[0] ____cacheline_aligned; 446 }; 447 448 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 449 450 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 451 { 452 return (void *)bridge->private; 453 } 454 455 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 456 { 457 return container_of(priv, struct pci_host_bridge, private); 458 } 459 460 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 461 int pci_register_host_bridge(struct pci_host_bridge *bridge); 462 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 463 464 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 465 void (*release_fn)(struct pci_host_bridge *), 466 void *release_data); 467 468 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 469 470 /* 471 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 472 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 473 * buses below host bridges or subtractive decode bridges) go in the list. 474 * Use pci_bus_for_each_resource() to iterate through all the resources. 475 */ 476 477 /* 478 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 479 * and there's no way to program the bridge with the details of the window. 480 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 481 * decode bit set, because they are explicit and can be programmed with _SRS. 482 */ 483 #define PCI_SUBTRACTIVE_DECODE 0x1 484 485 struct pci_bus_resource { 486 struct list_head list; 487 struct resource *res; 488 unsigned int flags; 489 }; 490 491 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 492 493 struct pci_bus { 494 struct list_head node; /* node in list of buses */ 495 struct pci_bus *parent; /* parent bus this bridge is on */ 496 struct list_head children; /* list of child buses */ 497 struct list_head devices; /* list of devices on this bus */ 498 struct pci_dev *self; /* bridge device as seen by parent */ 499 struct list_head slots; /* list of slots on this bus; 500 protected by pci_slot_mutex */ 501 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 502 struct list_head resources; /* address space routed to this bus */ 503 struct resource busn_res; /* bus numbers routed to this bus */ 504 505 struct pci_ops *ops; /* configuration access functions */ 506 struct msi_controller *msi; /* MSI controller */ 507 void *sysdata; /* hook for sys-specific extension */ 508 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 509 510 unsigned char number; /* bus number */ 511 unsigned char primary; /* number of primary bridge */ 512 unsigned char max_bus_speed; /* enum pci_bus_speed */ 513 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 514 #ifdef CONFIG_PCI_DOMAINS_GENERIC 515 int domain_nr; 516 #endif 517 518 char name[48]; 519 520 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 521 pci_bus_flags_t bus_flags; /* inherited by child buses */ 522 struct device *bridge; 523 struct device dev; 524 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 525 struct bin_attribute *legacy_mem; /* legacy mem */ 526 unsigned int is_added:1; 527 }; 528 529 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 530 531 /* 532 * Returns true if the PCI bus is root (behind host-PCI bridge), 533 * false otherwise 534 * 535 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 536 * This is incorrect because "virtual" buses added for SR-IOV (via 537 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 538 */ 539 static inline bool pci_is_root_bus(struct pci_bus *pbus) 540 { 541 return !(pbus->parent); 542 } 543 544 /** 545 * pci_is_bridge - check if the PCI device is a bridge 546 * @dev: PCI device 547 * 548 * Return true if the PCI device is bridge whether it has subordinate 549 * or not. 550 */ 551 static inline bool pci_is_bridge(struct pci_dev *dev) 552 { 553 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 554 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 555 } 556 557 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 558 { 559 dev = pci_physfn(dev); 560 if (pci_is_root_bus(dev->bus)) 561 return NULL; 562 563 return dev->bus->self; 564 } 565 566 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 567 void pci_put_host_bridge_device(struct device *dev); 568 569 #ifdef CONFIG_PCI_MSI 570 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 571 { 572 return pci_dev->msi_enabled || pci_dev->msix_enabled; 573 } 574 #else 575 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 576 #endif 577 578 /* 579 * Error values that may be returned by PCI functions. 580 */ 581 #define PCIBIOS_SUCCESSFUL 0x00 582 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 583 #define PCIBIOS_BAD_VENDOR_ID 0x83 584 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 585 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 586 #define PCIBIOS_SET_FAILED 0x88 587 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 588 589 /* 590 * Translate above to generic errno for passing back through non-PCI code. 591 */ 592 static inline int pcibios_err_to_errno(int err) 593 { 594 if (err <= PCIBIOS_SUCCESSFUL) 595 return err; /* Assume already errno */ 596 597 switch (err) { 598 case PCIBIOS_FUNC_NOT_SUPPORTED: 599 return -ENOENT; 600 case PCIBIOS_BAD_VENDOR_ID: 601 return -ENOTTY; 602 case PCIBIOS_DEVICE_NOT_FOUND: 603 return -ENODEV; 604 case PCIBIOS_BAD_REGISTER_NUMBER: 605 return -EFAULT; 606 case PCIBIOS_SET_FAILED: 607 return -EIO; 608 case PCIBIOS_BUFFER_TOO_SMALL: 609 return -ENOSPC; 610 } 611 612 return -ERANGE; 613 } 614 615 /* Low-level architecture-dependent routines */ 616 617 struct pci_ops { 618 int (*add_bus)(struct pci_bus *bus); 619 void (*remove_bus)(struct pci_bus *bus); 620 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 621 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 622 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 623 }; 624 625 /* 626 * ACPI needs to be able to access PCI config space before we've done a 627 * PCI bus scan and created pci_bus structures. 628 */ 629 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 630 int reg, int len, u32 *val); 631 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 632 int reg, int len, u32 val); 633 634 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 635 typedef u64 pci_bus_addr_t; 636 #else 637 typedef u32 pci_bus_addr_t; 638 #endif 639 640 struct pci_bus_region { 641 pci_bus_addr_t start; 642 pci_bus_addr_t end; 643 }; 644 645 struct pci_dynids { 646 spinlock_t lock; /* protects list, index */ 647 struct list_head list; /* for IDs added at runtime */ 648 }; 649 650 651 /* 652 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 653 * a set of callbacks in struct pci_error_handlers, that device driver 654 * will be notified of PCI bus errors, and will be driven to recovery 655 * when an error occurs. 656 */ 657 658 typedef unsigned int __bitwise pci_ers_result_t; 659 660 enum pci_ers_result { 661 /* no result/none/not supported in device driver */ 662 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 663 664 /* Device driver can recover without slot reset */ 665 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 666 667 /* Device driver wants slot to be reset. */ 668 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 669 670 /* Device has completely failed, is unrecoverable */ 671 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 672 673 /* Device driver is fully recovered and operational */ 674 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 675 676 /* No AER capabilities registered for the driver */ 677 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 678 }; 679 680 /* PCI bus error event callbacks */ 681 struct pci_error_handlers { 682 /* PCI bus error detected on this device */ 683 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 684 enum pci_channel_state error); 685 686 /* MMIO has been re-enabled, but not DMA */ 687 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 688 689 /* PCI slot has been reset */ 690 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 691 692 /* PCI function reset prepare or completed */ 693 void (*reset_notify)(struct pci_dev *dev, bool prepare); 694 695 /* Device driver may resume normal operations */ 696 void (*resume)(struct pci_dev *dev); 697 }; 698 699 700 struct module; 701 struct pci_driver { 702 struct list_head node; 703 const char *name; 704 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 705 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 706 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 707 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 708 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 709 int (*resume_early) (struct pci_dev *dev); 710 int (*resume) (struct pci_dev *dev); /* Device woken up */ 711 void (*shutdown) (struct pci_dev *dev); 712 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 713 const struct pci_error_handlers *err_handler; 714 struct device_driver driver; 715 struct pci_dynids dynids; 716 }; 717 718 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 719 720 /** 721 * PCI_DEVICE - macro used to describe a specific pci device 722 * @vend: the 16 bit PCI Vendor ID 723 * @dev: the 16 bit PCI Device ID 724 * 725 * This macro is used to create a struct pci_device_id that matches a 726 * specific device. The subvendor and subdevice fields will be set to 727 * PCI_ANY_ID. 728 */ 729 #define PCI_DEVICE(vend,dev) \ 730 .vendor = (vend), .device = (dev), \ 731 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 732 733 /** 734 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 735 * @vend: the 16 bit PCI Vendor ID 736 * @dev: the 16 bit PCI Device ID 737 * @subvend: the 16 bit PCI Subvendor ID 738 * @subdev: the 16 bit PCI Subdevice ID 739 * 740 * This macro is used to create a struct pci_device_id that matches a 741 * specific device with subsystem information. 742 */ 743 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 744 .vendor = (vend), .device = (dev), \ 745 .subvendor = (subvend), .subdevice = (subdev) 746 747 /** 748 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 749 * @dev_class: the class, subclass, prog-if triple for this device 750 * @dev_class_mask: the class mask for this device 751 * 752 * This macro is used to create a struct pci_device_id that matches a 753 * specific PCI class. The vendor, device, subvendor, and subdevice 754 * fields will be set to PCI_ANY_ID. 755 */ 756 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 757 .class = (dev_class), .class_mask = (dev_class_mask), \ 758 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 759 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 760 761 /** 762 * PCI_VDEVICE - macro used to describe a specific pci device in short form 763 * @vend: the vendor name 764 * @dev: the 16 bit PCI Device ID 765 * 766 * This macro is used to create a struct pci_device_id that matches a 767 * specific PCI device. The subvendor, and subdevice fields will be set 768 * to PCI_ANY_ID. The macro allows the next field to follow as the device 769 * private data. 770 */ 771 772 #define PCI_VDEVICE(vend, dev) \ 773 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 774 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 775 776 enum { 777 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ 778 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ 779 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ 780 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ 781 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ 782 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 783 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ 784 }; 785 786 /* these external functions are only available when PCI support is enabled */ 787 #ifdef CONFIG_PCI 788 789 extern unsigned int pci_flags; 790 791 static inline void pci_set_flags(int flags) { pci_flags = flags; } 792 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 793 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 794 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 795 796 void pcie_bus_configure_settings(struct pci_bus *bus); 797 798 enum pcie_bus_config_types { 799 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 800 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 801 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 802 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 803 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 804 }; 805 806 extern enum pcie_bus_config_types pcie_bus_config; 807 808 extern struct bus_type pci_bus_type; 809 810 /* Do NOT directly access these two variables, unless you are arch-specific PCI 811 * code, or PCI core code. */ 812 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 813 /* Some device drivers need know if PCI is initiated */ 814 int no_pci_devices(void); 815 816 void pcibios_resource_survey_bus(struct pci_bus *bus); 817 void pcibios_bus_add_device(struct pci_dev *pdev); 818 void pcibios_add_bus(struct pci_bus *bus); 819 void pcibios_remove_bus(struct pci_bus *bus); 820 void pcibios_fixup_bus(struct pci_bus *); 821 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 822 /* Architecture-specific versions may override this (weak) */ 823 char *pcibios_setup(char *str); 824 825 /* Used only when drivers/pci/setup.c is used */ 826 resource_size_t pcibios_align_resource(void *, const struct resource *, 827 resource_size_t, 828 resource_size_t); 829 void pcibios_update_irq(struct pci_dev *, int irq); 830 831 /* Weak but can be overriden by arch */ 832 void pci_fixup_cardbus(struct pci_bus *); 833 834 /* Generic PCI functions used internally */ 835 836 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 837 struct resource *res); 838 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 839 struct pci_bus_region *region); 840 void pcibios_scan_specific_bus(int busn); 841 struct pci_bus *pci_find_bus(int domain, int busnr); 842 void pci_bus_add_devices(const struct pci_bus *bus); 843 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 844 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 845 struct pci_ops *ops, void *sysdata, 846 struct list_head *resources); 847 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 848 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 849 void pci_bus_release_busn_res(struct pci_bus *b); 850 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, 851 struct pci_ops *ops, void *sysdata, 852 struct list_head *resources, 853 struct msi_controller *msi); 854 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 855 struct pci_ops *ops, void *sysdata, 856 struct list_head *resources); 857 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 858 int busnr); 859 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 860 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 861 const char *name, 862 struct hotplug_slot *hotplug); 863 void pci_destroy_slot(struct pci_slot *slot); 864 #ifdef CONFIG_SYSFS 865 void pci_dev_assign_slot(struct pci_dev *dev); 866 #else 867 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 868 #endif 869 int pci_scan_slot(struct pci_bus *bus, int devfn); 870 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 871 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 872 unsigned int pci_scan_child_bus(struct pci_bus *bus); 873 void pci_bus_add_device(struct pci_dev *dev); 874 void pci_read_bridge_bases(struct pci_bus *child); 875 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 876 struct resource *res); 877 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 878 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 879 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 880 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 881 struct pci_dev *pci_dev_get(struct pci_dev *dev); 882 void pci_dev_put(struct pci_dev *dev); 883 void pci_remove_bus(struct pci_bus *b); 884 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 885 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 886 void pci_stop_root_bus(struct pci_bus *bus); 887 void pci_remove_root_bus(struct pci_bus *bus); 888 void pci_setup_cardbus(struct pci_bus *bus); 889 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 890 void pci_sort_breadthfirst(void); 891 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 892 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 893 894 /* Generic PCI functions exported to card drivers */ 895 896 enum pci_lost_interrupt_reason { 897 PCI_LOST_IRQ_NO_INFORMATION = 0, 898 PCI_LOST_IRQ_DISABLE_MSI, 899 PCI_LOST_IRQ_DISABLE_MSIX, 900 PCI_LOST_IRQ_DISABLE_ACPI, 901 }; 902 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 903 int pci_find_capability(struct pci_dev *dev, int cap); 904 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 905 int pci_find_ext_capability(struct pci_dev *dev, int cap); 906 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 907 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 908 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 909 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 910 911 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 912 struct pci_dev *from); 913 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 914 unsigned int ss_vendor, unsigned int ss_device, 915 struct pci_dev *from); 916 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 917 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 918 unsigned int devfn); 919 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 920 unsigned int devfn) 921 { 922 return pci_get_domain_bus_and_slot(0, bus, devfn); 923 } 924 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 925 int pci_dev_present(const struct pci_device_id *ids); 926 927 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 928 int where, u8 *val); 929 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 930 int where, u16 *val); 931 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 932 int where, u32 *val); 933 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 934 int where, u8 val); 935 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 936 int where, u16 val); 937 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 938 int where, u32 val); 939 940 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 941 int where, int size, u32 *val); 942 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 943 int where, int size, u32 val); 944 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 945 int where, int size, u32 *val); 946 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 947 int where, int size, u32 val); 948 949 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 950 951 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 952 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 953 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 954 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 955 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 956 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 957 958 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 959 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 960 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 961 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 962 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 963 u16 clear, u16 set); 964 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 965 u32 clear, u32 set); 966 967 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 968 u16 set) 969 { 970 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 971 } 972 973 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 974 u32 set) 975 { 976 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 977 } 978 979 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 980 u16 clear) 981 { 982 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 983 } 984 985 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 986 u32 clear) 987 { 988 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 989 } 990 991 /* user-space driven config access */ 992 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 993 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 994 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 995 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 996 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 997 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 998 999 int __must_check pci_enable_device(struct pci_dev *dev); 1000 int __must_check pci_enable_device_io(struct pci_dev *dev); 1001 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1002 int __must_check pci_reenable_device(struct pci_dev *); 1003 int __must_check pcim_enable_device(struct pci_dev *pdev); 1004 void pcim_pin_device(struct pci_dev *pdev); 1005 1006 static inline int pci_is_enabled(struct pci_dev *pdev) 1007 { 1008 return (atomic_read(&pdev->enable_cnt) > 0); 1009 } 1010 1011 static inline int pci_is_managed(struct pci_dev *pdev) 1012 { 1013 return pdev->is_managed; 1014 } 1015 1016 void pci_disable_device(struct pci_dev *dev); 1017 1018 extern unsigned int pcibios_max_latency; 1019 void pci_set_master(struct pci_dev *dev); 1020 void pci_clear_master(struct pci_dev *dev); 1021 1022 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1023 int pci_set_cacheline_size(struct pci_dev *dev); 1024 #define HAVE_PCI_SET_MWI 1025 int __must_check pci_set_mwi(struct pci_dev *dev); 1026 int pci_try_set_mwi(struct pci_dev *dev); 1027 void pci_clear_mwi(struct pci_dev *dev); 1028 void pci_intx(struct pci_dev *dev, int enable); 1029 bool pci_intx_mask_supported(struct pci_dev *dev); 1030 bool pci_check_and_mask_intx(struct pci_dev *dev); 1031 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1032 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1033 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1034 int pcix_get_max_mmrbc(struct pci_dev *dev); 1035 int pcix_get_mmrbc(struct pci_dev *dev); 1036 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1037 int pcie_get_readrq(struct pci_dev *dev); 1038 int pcie_set_readrq(struct pci_dev *dev, int rq); 1039 int pcie_get_mps(struct pci_dev *dev); 1040 int pcie_set_mps(struct pci_dev *dev, int mps); 1041 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1042 enum pcie_link_width *width); 1043 void pcie_flr(struct pci_dev *dev); 1044 int __pci_reset_function(struct pci_dev *dev); 1045 int __pci_reset_function_locked(struct pci_dev *dev); 1046 int pci_reset_function(struct pci_dev *dev); 1047 int pci_try_reset_function(struct pci_dev *dev); 1048 int pci_probe_reset_slot(struct pci_slot *slot); 1049 int pci_reset_slot(struct pci_slot *slot); 1050 int pci_try_reset_slot(struct pci_slot *slot); 1051 int pci_probe_reset_bus(struct pci_bus *bus); 1052 int pci_reset_bus(struct pci_bus *bus); 1053 int pci_try_reset_bus(struct pci_bus *bus); 1054 void pci_reset_secondary_bus(struct pci_dev *dev); 1055 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1056 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1057 void pci_update_resource(struct pci_dev *dev, int resno); 1058 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1059 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1060 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1061 bool pci_device_is_present(struct pci_dev *pdev); 1062 void pci_ignore_hotplug(struct pci_dev *dev); 1063 1064 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1065 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1066 const char *fmt, ...); 1067 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1068 1069 /* ROM control related routines */ 1070 int pci_enable_rom(struct pci_dev *pdev); 1071 void pci_disable_rom(struct pci_dev *pdev); 1072 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1073 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1074 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1075 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1076 1077 /* Power management related routines */ 1078 int pci_save_state(struct pci_dev *dev); 1079 void pci_restore_state(struct pci_dev *dev); 1080 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1081 int pci_load_saved_state(struct pci_dev *dev, 1082 struct pci_saved_state *state); 1083 int pci_load_and_free_saved_state(struct pci_dev *dev, 1084 struct pci_saved_state **state); 1085 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1086 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1087 u16 cap); 1088 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1089 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1090 u16 cap, unsigned int size); 1091 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1092 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1093 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1094 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1095 void pci_pme_active(struct pci_dev *dev, bool enable); 1096 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1097 bool runtime, bool enable); 1098 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1099 int pci_prepare_to_sleep(struct pci_dev *dev); 1100 int pci_back_from_sleep(struct pci_dev *dev); 1101 bool pci_dev_run_wake(struct pci_dev *dev); 1102 bool pci_check_pme_status(struct pci_dev *dev); 1103 void pci_pme_wakeup_bus(struct pci_bus *bus); 1104 void pci_d3cold_enable(struct pci_dev *dev); 1105 void pci_d3cold_disable(struct pci_dev *dev); 1106 1107 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1108 bool enable) 1109 { 1110 return __pci_enable_wake(dev, state, false, enable); 1111 } 1112 1113 /* PCI Virtual Channel */ 1114 int pci_save_vc_state(struct pci_dev *dev); 1115 void pci_restore_vc_state(struct pci_dev *dev); 1116 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1117 1118 /* For use by arch with custom probe code */ 1119 void set_pcie_port_type(struct pci_dev *pdev); 1120 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1121 1122 /* Functions for PCI Hotplug drivers to use */ 1123 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1124 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1125 unsigned int pci_rescan_bus(struct pci_bus *bus); 1126 void pci_lock_rescan_remove(void); 1127 void pci_unlock_rescan_remove(void); 1128 1129 /* Vital product data routines */ 1130 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1131 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1132 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1133 1134 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1135 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1136 void pci_bus_assign_resources(const struct pci_bus *bus); 1137 void pci_bus_claim_resources(struct pci_bus *bus); 1138 void pci_bus_size_bridges(struct pci_bus *bus); 1139 int pci_claim_resource(struct pci_dev *, int); 1140 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1141 void pci_assign_unassigned_resources(void); 1142 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1143 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1144 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1145 void pdev_enable_device(struct pci_dev *); 1146 int pci_enable_resources(struct pci_dev *, int mask); 1147 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1148 int (*)(const struct pci_dev *, u8, u8)); 1149 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1150 #define HAVE_PCI_REQ_REGIONS 2 1151 int __must_check pci_request_regions(struct pci_dev *, const char *); 1152 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1153 void pci_release_regions(struct pci_dev *); 1154 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1155 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1156 void pci_release_region(struct pci_dev *, int); 1157 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1158 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1159 void pci_release_selected_regions(struct pci_dev *, int); 1160 1161 /* drivers/pci/bus.c */ 1162 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1163 void pci_bus_put(struct pci_bus *bus); 1164 void pci_add_resource(struct list_head *resources, struct resource *res); 1165 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1166 resource_size_t offset); 1167 void pci_free_resource_list(struct list_head *resources); 1168 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1169 unsigned int flags); 1170 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1171 void pci_bus_remove_resources(struct pci_bus *bus); 1172 int devm_request_pci_bus_resources(struct device *dev, 1173 struct list_head *resources); 1174 1175 #define pci_bus_for_each_resource(bus, res, i) \ 1176 for (i = 0; \ 1177 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1178 i++) 1179 1180 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1181 struct resource *res, resource_size_t size, 1182 resource_size_t align, resource_size_t min, 1183 unsigned long type_mask, 1184 resource_size_t (*alignf)(void *, 1185 const struct resource *, 1186 resource_size_t, 1187 resource_size_t), 1188 void *alignf_data); 1189 1190 1191 int pci_register_io_range(phys_addr_t addr, resource_size_t size); 1192 unsigned long pci_address_to_pio(phys_addr_t addr); 1193 phys_addr_t pci_pio_to_address(unsigned long pio); 1194 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1195 void pci_unmap_iospace(struct resource *res); 1196 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1197 resource_size_t offset, 1198 resource_size_t size); 1199 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1200 struct resource *res); 1201 1202 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1203 { 1204 struct pci_bus_region region; 1205 1206 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1207 return region.start; 1208 } 1209 1210 /* Proper probing supporting hot-pluggable devices */ 1211 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1212 const char *mod_name); 1213 1214 /* 1215 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1216 */ 1217 #define pci_register_driver(driver) \ 1218 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1219 1220 void pci_unregister_driver(struct pci_driver *dev); 1221 1222 /** 1223 * module_pci_driver() - Helper macro for registering a PCI driver 1224 * @__pci_driver: pci_driver struct 1225 * 1226 * Helper macro for PCI drivers which do not do anything special in module 1227 * init/exit. This eliminates a lot of boilerplate. Each module may only 1228 * use this macro once, and calling it replaces module_init() and module_exit() 1229 */ 1230 #define module_pci_driver(__pci_driver) \ 1231 module_driver(__pci_driver, pci_register_driver, \ 1232 pci_unregister_driver) 1233 1234 /** 1235 * builtin_pci_driver() - Helper macro for registering a PCI driver 1236 * @__pci_driver: pci_driver struct 1237 * 1238 * Helper macro for PCI drivers which do not do anything special in their 1239 * init code. This eliminates a lot of boilerplate. Each driver may only 1240 * use this macro once, and calling it replaces device_initcall(...) 1241 */ 1242 #define builtin_pci_driver(__pci_driver) \ 1243 builtin_driver(__pci_driver, pci_register_driver) 1244 1245 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1246 int pci_add_dynid(struct pci_driver *drv, 1247 unsigned int vendor, unsigned int device, 1248 unsigned int subvendor, unsigned int subdevice, 1249 unsigned int class, unsigned int class_mask, 1250 unsigned long driver_data); 1251 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1252 struct pci_dev *dev); 1253 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1254 int pass); 1255 1256 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1257 void *userdata); 1258 int pci_cfg_space_size(struct pci_dev *dev); 1259 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1260 void pci_setup_bridge(struct pci_bus *bus); 1261 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1262 unsigned long type); 1263 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1264 1265 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1266 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1267 1268 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1269 unsigned int command_bits, u32 flags); 1270 1271 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ 1272 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ 1273 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ 1274 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ 1275 #define PCI_IRQ_ALL_TYPES \ 1276 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1277 1278 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1279 1280 #include <linux/pci-dma.h> 1281 #include <linux/dmapool.h> 1282 1283 #define pci_pool dma_pool 1284 #define pci_pool_create(name, pdev, size, align, allocation) \ 1285 dma_pool_create(name, &pdev->dev, size, align, allocation) 1286 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1287 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1288 #define pci_pool_zalloc(pool, flags, handle) \ 1289 dma_pool_zalloc(pool, flags, handle) 1290 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1291 1292 struct msix_entry { 1293 u32 vector; /* kernel uses to write allocated vector */ 1294 u16 entry; /* driver uses to specify entry, OS writes */ 1295 }; 1296 1297 #ifdef CONFIG_PCI_MSI 1298 int pci_msi_vec_count(struct pci_dev *dev); 1299 void pci_disable_msi(struct pci_dev *dev); 1300 int pci_msix_vec_count(struct pci_dev *dev); 1301 void pci_disable_msix(struct pci_dev *dev); 1302 void pci_restore_msi_state(struct pci_dev *dev); 1303 int pci_msi_enabled(void); 1304 int pci_enable_msi(struct pci_dev *dev); 1305 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1306 int minvec, int maxvec); 1307 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1308 struct msix_entry *entries, int nvec) 1309 { 1310 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1311 if (rc < 0) 1312 return rc; 1313 return 0; 1314 } 1315 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1316 unsigned int max_vecs, unsigned int flags, 1317 const struct irq_affinity *affd); 1318 1319 void pci_free_irq_vectors(struct pci_dev *dev); 1320 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1321 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1322 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1323 1324 #else 1325 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1326 static inline void pci_disable_msi(struct pci_dev *dev) { } 1327 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1328 static inline void pci_disable_msix(struct pci_dev *dev) { } 1329 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1330 static inline int pci_msi_enabled(void) { return 0; } 1331 static inline int pci_enable_msi(struct pci_dev *dev) 1332 { return -ENOSYS; } 1333 static inline int pci_enable_msix_range(struct pci_dev *dev, 1334 struct msix_entry *entries, int minvec, int maxvec) 1335 { return -ENOSYS; } 1336 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1337 struct msix_entry *entries, int nvec) 1338 { return -ENOSYS; } 1339 1340 static inline int 1341 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1342 unsigned int max_vecs, unsigned int flags, 1343 const struct irq_affinity *aff_desc) 1344 { 1345 if (min_vecs > 1) 1346 return -EINVAL; 1347 return 1; 1348 } 1349 1350 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1351 { 1352 } 1353 1354 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1355 { 1356 if (WARN_ON_ONCE(nr > 0)) 1357 return -EINVAL; 1358 return dev->irq; 1359 } 1360 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1361 int vec) 1362 { 1363 return cpu_possible_mask; 1364 } 1365 1366 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1367 { 1368 return first_online_node; 1369 } 1370 #endif 1371 1372 static inline int 1373 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1374 unsigned int max_vecs, unsigned int flags) 1375 { 1376 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1377 NULL); 1378 } 1379 1380 #ifdef CONFIG_PCIEPORTBUS 1381 extern bool pcie_ports_disabled; 1382 extern bool pcie_ports_auto; 1383 #else 1384 #define pcie_ports_disabled true 1385 #define pcie_ports_auto false 1386 #endif 1387 1388 #ifdef CONFIG_PCIEASPM 1389 bool pcie_aspm_support_enabled(void); 1390 #else 1391 static inline bool pcie_aspm_support_enabled(void) { return false; } 1392 #endif 1393 1394 #ifdef CONFIG_PCIEAER 1395 void pci_no_aer(void); 1396 bool pci_aer_available(void); 1397 int pci_aer_init(struct pci_dev *dev); 1398 #else 1399 static inline void pci_no_aer(void) { } 1400 static inline bool pci_aer_available(void) { return false; } 1401 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } 1402 #endif 1403 1404 #ifdef CONFIG_PCIE_ECRC 1405 void pcie_set_ecrc_checking(struct pci_dev *dev); 1406 void pcie_ecrc_get_policy(char *str); 1407 #else 1408 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1409 static inline void pcie_ecrc_get_policy(char *str) { } 1410 #endif 1411 1412 #ifdef CONFIG_HT_IRQ 1413 /* The functions a driver should call */ 1414 int ht_create_irq(struct pci_dev *dev, int idx); 1415 void ht_destroy_irq(unsigned int irq); 1416 #endif /* CONFIG_HT_IRQ */ 1417 1418 #ifdef CONFIG_PCI_ATS 1419 /* Address Translation Service */ 1420 void pci_ats_init(struct pci_dev *dev); 1421 int pci_enable_ats(struct pci_dev *dev, int ps); 1422 void pci_disable_ats(struct pci_dev *dev); 1423 int pci_ats_queue_depth(struct pci_dev *dev); 1424 #else 1425 static inline void pci_ats_init(struct pci_dev *d) { } 1426 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1427 static inline void pci_disable_ats(struct pci_dev *d) { } 1428 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1429 #endif 1430 1431 #ifdef CONFIG_PCIE_PTM 1432 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1433 #else 1434 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1435 { return -EINVAL; } 1436 #endif 1437 1438 void pci_cfg_access_lock(struct pci_dev *dev); 1439 bool pci_cfg_access_trylock(struct pci_dev *dev); 1440 void pci_cfg_access_unlock(struct pci_dev *dev); 1441 1442 /* 1443 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1444 * a PCI domain is defined to be a set of PCI buses which share 1445 * configuration space. 1446 */ 1447 #ifdef CONFIG_PCI_DOMAINS 1448 extern int pci_domains_supported; 1449 int pci_get_new_domain_nr(void); 1450 #else 1451 enum { pci_domains_supported = 0 }; 1452 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1453 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1454 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1455 #endif /* CONFIG_PCI_DOMAINS */ 1456 1457 /* 1458 * Generic implementation for PCI domain support. If your 1459 * architecture does not need custom management of PCI 1460 * domains then this implementation will be used 1461 */ 1462 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1463 static inline int pci_domain_nr(struct pci_bus *bus) 1464 { 1465 return bus->domain_nr; 1466 } 1467 #ifdef CONFIG_ACPI 1468 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1469 #else 1470 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1471 { return 0; } 1472 #endif 1473 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1474 #endif 1475 1476 /* some architectures require additional setup to direct VGA traffic */ 1477 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1478 unsigned int command_bits, u32 flags); 1479 void pci_register_set_vga_state(arch_set_vga_state_t func); 1480 1481 static inline int 1482 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1483 { 1484 return pci_request_selected_regions(pdev, 1485 pci_select_bars(pdev, IORESOURCE_IO), name); 1486 } 1487 1488 static inline void 1489 pci_release_io_regions(struct pci_dev *pdev) 1490 { 1491 return pci_release_selected_regions(pdev, 1492 pci_select_bars(pdev, IORESOURCE_IO)); 1493 } 1494 1495 static inline int 1496 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1497 { 1498 return pci_request_selected_regions(pdev, 1499 pci_select_bars(pdev, IORESOURCE_MEM), name); 1500 } 1501 1502 static inline void 1503 pci_release_mem_regions(struct pci_dev *pdev) 1504 { 1505 return pci_release_selected_regions(pdev, 1506 pci_select_bars(pdev, IORESOURCE_MEM)); 1507 } 1508 1509 #else /* CONFIG_PCI is not enabled */ 1510 1511 static inline void pci_set_flags(int flags) { } 1512 static inline void pci_add_flags(int flags) { } 1513 static inline void pci_clear_flags(int flags) { } 1514 static inline int pci_has_flag(int flag) { return 0; } 1515 1516 /* 1517 * If the system does not have PCI, clearly these return errors. Define 1518 * these as simple inline functions to avoid hair in drivers. 1519 */ 1520 1521 #define _PCI_NOP(o, s, t) \ 1522 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1523 int where, t val) \ 1524 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1525 1526 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1527 _PCI_NOP(o, word, u16 x) \ 1528 _PCI_NOP(o, dword, u32 x) 1529 _PCI_NOP_ALL(read, *) 1530 _PCI_NOP_ALL(write,) 1531 1532 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1533 unsigned int device, 1534 struct pci_dev *from) 1535 { return NULL; } 1536 1537 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1538 unsigned int device, 1539 unsigned int ss_vendor, 1540 unsigned int ss_device, 1541 struct pci_dev *from) 1542 { return NULL; } 1543 1544 static inline struct pci_dev *pci_get_class(unsigned int class, 1545 struct pci_dev *from) 1546 { return NULL; } 1547 1548 #define pci_dev_present(ids) (0) 1549 #define no_pci_devices() (1) 1550 #define pci_dev_put(dev) do { } while (0) 1551 1552 static inline void pci_set_master(struct pci_dev *dev) { } 1553 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1554 static inline void pci_disable_device(struct pci_dev *dev) { } 1555 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1556 { return -EBUSY; } 1557 static inline int __pci_register_driver(struct pci_driver *drv, 1558 struct module *owner) 1559 { return 0; } 1560 static inline int pci_register_driver(struct pci_driver *drv) 1561 { return 0; } 1562 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1563 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1564 { return 0; } 1565 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1566 int cap) 1567 { return 0; } 1568 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1569 { return 0; } 1570 1571 /* Power management related routines */ 1572 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1573 static inline void pci_restore_state(struct pci_dev *dev) { } 1574 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1575 { return 0; } 1576 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1577 { return 0; } 1578 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1579 pm_message_t state) 1580 { return PCI_D0; } 1581 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1582 int enable) 1583 { return 0; } 1584 1585 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1586 struct resource *res) 1587 { return NULL; } 1588 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1589 { return -EIO; } 1590 static inline void pci_release_regions(struct pci_dev *dev) { } 1591 1592 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1593 1594 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1595 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1596 { return 0; } 1597 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1598 1599 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1600 { return NULL; } 1601 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1602 unsigned int devfn) 1603 { return NULL; } 1604 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1605 unsigned int devfn) 1606 { return NULL; } 1607 1608 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1609 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1610 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1611 1612 #define dev_is_pci(d) (false) 1613 #define dev_is_pf(d) (false) 1614 #endif /* CONFIG_PCI */ 1615 1616 /* Include architecture-dependent settings and functions */ 1617 1618 #include <asm/pci.h> 1619 1620 /* These two functions provide almost identical functionality. Depennding 1621 * on the architecture, one will be implemented as a wrapper around the 1622 * other (in drivers/pci/mmap.c). 1623 * 1624 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1625 * is expected to be an offset within that region. 1626 * 1627 * pci_mmap_page_range() is the legacy architecture-specific interface, 1628 * which accepts a "user visible" resource address converted by 1629 * pci_resource_to_user(), as used in the legacy mmap() interface in 1630 * /proc/bus/pci/. 1631 */ 1632 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1633 struct vm_area_struct *vma, 1634 enum pci_mmap_state mmap_state, int write_combine); 1635 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1636 struct vm_area_struct *vma, 1637 enum pci_mmap_state mmap_state, int write_combine); 1638 1639 #ifndef arch_can_pci_mmap_wc 1640 #define arch_can_pci_mmap_wc() 0 1641 #endif 1642 1643 #ifndef arch_can_pci_mmap_io 1644 #define arch_can_pci_mmap_io() 0 1645 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1646 #else 1647 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1648 #endif 1649 1650 #ifndef pci_root_bus_fwnode 1651 #define pci_root_bus_fwnode(bus) NULL 1652 #endif 1653 1654 /* these helpers provide future and backwards compatibility 1655 * for accessing popular PCI BAR info */ 1656 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1657 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1658 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1659 #define pci_resource_len(dev,bar) \ 1660 ((pci_resource_start((dev), (bar)) == 0 && \ 1661 pci_resource_end((dev), (bar)) == \ 1662 pci_resource_start((dev), (bar))) ? 0 : \ 1663 \ 1664 (pci_resource_end((dev), (bar)) - \ 1665 pci_resource_start((dev), (bar)) + 1)) 1666 1667 /* Similar to the helpers above, these manipulate per-pci_dev 1668 * driver-specific data. They are really just a wrapper around 1669 * the generic device structure functions of these calls. 1670 */ 1671 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1672 { 1673 return dev_get_drvdata(&pdev->dev); 1674 } 1675 1676 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1677 { 1678 dev_set_drvdata(&pdev->dev, data); 1679 } 1680 1681 /* If you want to know what to call your pci_dev, ask this function. 1682 * Again, it's a wrapper around the generic device. 1683 */ 1684 static inline const char *pci_name(const struct pci_dev *pdev) 1685 { 1686 return dev_name(&pdev->dev); 1687 } 1688 1689 1690 /* Some archs don't want to expose struct resource to userland as-is 1691 * in sysfs and /proc 1692 */ 1693 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1694 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1695 const struct resource *rsrc, 1696 resource_size_t *start, resource_size_t *end); 1697 #else 1698 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1699 const struct resource *rsrc, resource_size_t *start, 1700 resource_size_t *end) 1701 { 1702 *start = rsrc->start; 1703 *end = rsrc->end; 1704 } 1705 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1706 1707 1708 /* 1709 * The world is not perfect and supplies us with broken PCI devices. 1710 * For at least a part of these bugs we need a work-around, so both 1711 * generic (drivers/pci/quirks.c) and per-architecture code can define 1712 * fixup hooks to be called for particular buggy devices. 1713 */ 1714 1715 struct pci_fixup { 1716 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1717 u16 device; /* You can use PCI_ANY_ID here of course */ 1718 u32 class; /* You can use PCI_ANY_ID here too */ 1719 unsigned int class_shift; /* should be 0, 8, 16 */ 1720 void (*hook)(struct pci_dev *dev); 1721 }; 1722 1723 enum pci_fixup_pass { 1724 pci_fixup_early, /* Before probing BARs */ 1725 pci_fixup_header, /* After reading configuration header */ 1726 pci_fixup_final, /* Final phase of device fixups */ 1727 pci_fixup_enable, /* pci_enable_device() time */ 1728 pci_fixup_resume, /* pci_device_resume() */ 1729 pci_fixup_suspend, /* pci_device_suspend() */ 1730 pci_fixup_resume_early, /* pci_device_resume_early() */ 1731 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1732 }; 1733 1734 /* Anonymous variables would be nice... */ 1735 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1736 class_shift, hook) \ 1737 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1738 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1739 = { vendor, device, class, class_shift, hook }; 1740 1741 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1742 class_shift, hook) \ 1743 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1744 hook, vendor, device, class, class_shift, hook) 1745 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1746 class_shift, hook) \ 1747 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1748 hook, vendor, device, class, class_shift, hook) 1749 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1750 class_shift, hook) \ 1751 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1752 hook, vendor, device, class, class_shift, hook) 1753 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1754 class_shift, hook) \ 1755 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1756 hook, vendor, device, class, class_shift, hook) 1757 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1758 class_shift, hook) \ 1759 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1760 resume##hook, vendor, device, class, \ 1761 class_shift, hook) 1762 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1763 class_shift, hook) \ 1764 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1765 resume_early##hook, vendor, device, \ 1766 class, class_shift, hook) 1767 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1768 class_shift, hook) \ 1769 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1770 suspend##hook, vendor, device, class, \ 1771 class_shift, hook) 1772 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1773 class_shift, hook) \ 1774 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1775 suspend_late##hook, vendor, device, \ 1776 class, class_shift, hook) 1777 1778 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1779 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1780 hook, vendor, device, PCI_ANY_ID, 0, hook) 1781 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1782 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1783 hook, vendor, device, PCI_ANY_ID, 0, hook) 1784 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1785 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1786 hook, vendor, device, PCI_ANY_ID, 0, hook) 1787 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1788 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1789 hook, vendor, device, PCI_ANY_ID, 0, hook) 1790 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1791 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1792 resume##hook, vendor, device, \ 1793 PCI_ANY_ID, 0, hook) 1794 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1795 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1796 resume_early##hook, vendor, device, \ 1797 PCI_ANY_ID, 0, hook) 1798 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1799 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1800 suspend##hook, vendor, device, \ 1801 PCI_ANY_ID, 0, hook) 1802 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1803 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1804 suspend_late##hook, vendor, device, \ 1805 PCI_ANY_ID, 0, hook) 1806 1807 #ifdef CONFIG_PCI_QUIRKS 1808 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1809 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1810 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1811 #else 1812 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1813 struct pci_dev *dev) { } 1814 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1815 u16 acs_flags) 1816 { 1817 return -ENOTTY; 1818 } 1819 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1820 { 1821 return -ENOTTY; 1822 } 1823 #endif 1824 1825 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1826 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1827 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1828 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1829 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1830 const char *name); 1831 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1832 1833 extern int pci_pci_problems; 1834 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1835 #define PCIPCI_TRITON 2 1836 #define PCIPCI_NATOMA 4 1837 #define PCIPCI_VIAETBF 8 1838 #define PCIPCI_VSFX 16 1839 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1840 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1841 1842 extern unsigned long pci_cardbus_io_size; 1843 extern unsigned long pci_cardbus_mem_size; 1844 extern u8 pci_dfl_cache_line_size; 1845 extern u8 pci_cache_line_size; 1846 1847 extern unsigned long pci_hotplug_io_size; 1848 extern unsigned long pci_hotplug_mem_size; 1849 extern unsigned long pci_hotplug_bus_size; 1850 1851 /* Architecture-specific versions may override these (weak) */ 1852 void pcibios_disable_device(struct pci_dev *dev); 1853 void pcibios_set_master(struct pci_dev *dev); 1854 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1855 enum pcie_reset_state state); 1856 int pcibios_add_device(struct pci_dev *dev); 1857 void pcibios_release_device(struct pci_dev *dev); 1858 void pcibios_penalize_isa_irq(int irq, int active); 1859 int pcibios_alloc_irq(struct pci_dev *dev); 1860 void pcibios_free_irq(struct pci_dev *dev); 1861 1862 #ifdef CONFIG_HIBERNATE_CALLBACKS 1863 extern struct dev_pm_ops pcibios_pm_ops; 1864 #endif 1865 1866 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1867 void __init pci_mmcfg_early_init(void); 1868 void __init pci_mmcfg_late_init(void); 1869 #else 1870 static inline void pci_mmcfg_early_init(void) { } 1871 static inline void pci_mmcfg_late_init(void) { } 1872 #endif 1873 1874 int pci_ext_cfg_avail(void); 1875 1876 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1877 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1878 1879 #ifdef CONFIG_PCI_IOV 1880 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1881 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1882 1883 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1884 void pci_disable_sriov(struct pci_dev *dev); 1885 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset); 1886 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset); 1887 int pci_num_vf(struct pci_dev *dev); 1888 int pci_vfs_assigned(struct pci_dev *dev); 1889 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1890 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1891 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1892 #else 1893 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1894 { 1895 return -ENOSYS; 1896 } 1897 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1898 { 1899 return -ENOSYS; 1900 } 1901 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1902 { return -ENODEV; } 1903 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset) 1904 { 1905 return -ENOSYS; 1906 } 1907 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 1908 int id, int reset) { } 1909 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1910 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1911 static inline int pci_vfs_assigned(struct pci_dev *dev) 1912 { return 0; } 1913 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1914 { return 0; } 1915 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1916 { return 0; } 1917 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1918 { return 0; } 1919 #endif 1920 1921 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1922 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1923 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1924 #endif 1925 1926 /** 1927 * pci_pcie_cap - get the saved PCIe capability offset 1928 * @dev: PCI device 1929 * 1930 * PCIe capability offset is calculated at PCI device initialization 1931 * time and saved in the data structure. This function returns saved 1932 * PCIe capability offset. Using this instead of pci_find_capability() 1933 * reduces unnecessary search in the PCI configuration space. If you 1934 * need to calculate PCIe capability offset from raw device for some 1935 * reasons, please use pci_find_capability() instead. 1936 */ 1937 static inline int pci_pcie_cap(struct pci_dev *dev) 1938 { 1939 return dev->pcie_cap; 1940 } 1941 1942 /** 1943 * pci_is_pcie - check if the PCI device is PCI Express capable 1944 * @dev: PCI device 1945 * 1946 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1947 */ 1948 static inline bool pci_is_pcie(struct pci_dev *dev) 1949 { 1950 return pci_pcie_cap(dev); 1951 } 1952 1953 /** 1954 * pcie_caps_reg - get the PCIe Capabilities Register 1955 * @dev: PCI device 1956 */ 1957 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1958 { 1959 return dev->pcie_flags_reg; 1960 } 1961 1962 /** 1963 * pci_pcie_type - get the PCIe device/port type 1964 * @dev: PCI device 1965 */ 1966 static inline int pci_pcie_type(const struct pci_dev *dev) 1967 { 1968 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1969 } 1970 1971 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 1972 { 1973 while (1) { 1974 if (!pci_is_pcie(dev)) 1975 break; 1976 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 1977 return dev; 1978 if (!dev->bus->self) 1979 break; 1980 dev = dev->bus->self; 1981 } 1982 return NULL; 1983 } 1984 1985 void pci_request_acs(void); 1986 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1987 bool pci_acs_path_enabled(struct pci_dev *start, 1988 struct pci_dev *end, u16 acs_flags); 1989 1990 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1991 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1992 1993 /* Large Resource Data Type Tag Item Names */ 1994 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1995 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1996 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1997 1998 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1999 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2000 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2001 2002 /* Small Resource Data Type Tag Item Names */ 2003 #define PCI_VPD_STIN_END 0x0f /* End */ 2004 2005 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2006 2007 #define PCI_VPD_SRDT_TIN_MASK 0x78 2008 #define PCI_VPD_SRDT_LEN_MASK 0x07 2009 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2010 2011 #define PCI_VPD_LRDT_TAG_SIZE 3 2012 #define PCI_VPD_SRDT_TAG_SIZE 1 2013 2014 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2015 2016 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2017 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2018 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2019 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2020 2021 /** 2022 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2023 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2024 * 2025 * Returns the extracted Large Resource Data Type length. 2026 */ 2027 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2028 { 2029 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2030 } 2031 2032 /** 2033 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2034 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2035 * 2036 * Returns the extracted Large Resource Data Type Tag item. 2037 */ 2038 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2039 { 2040 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2041 } 2042 2043 /** 2044 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2045 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 2046 * 2047 * Returns the extracted Small Resource Data Type length. 2048 */ 2049 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2050 { 2051 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2052 } 2053 2054 /** 2055 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2056 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 2057 * 2058 * Returns the extracted Small Resource Data Type Tag Item. 2059 */ 2060 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2061 { 2062 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2063 } 2064 2065 /** 2066 * pci_vpd_info_field_size - Extracts the information field length 2067 * @lrdt: Pointer to the beginning of an information field header 2068 * 2069 * Returns the extracted information field length. 2070 */ 2071 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2072 { 2073 return info_field[2]; 2074 } 2075 2076 /** 2077 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2078 * @buf: Pointer to buffered vpd data 2079 * @off: The offset into the buffer at which to begin the search 2080 * @len: The length of the vpd buffer 2081 * @rdt: The Resource Data Type to search for 2082 * 2083 * Returns the index where the Resource Data Type was found or 2084 * -ENOENT otherwise. 2085 */ 2086 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2087 2088 /** 2089 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2090 * @buf: Pointer to buffered vpd data 2091 * @off: The offset into the buffer at which to begin the search 2092 * @len: The length of the buffer area, relative to off, in which to search 2093 * @kw: The keyword to search for 2094 * 2095 * Returns the index where the information field keyword was found or 2096 * -ENOENT otherwise. 2097 */ 2098 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2099 unsigned int len, const char *kw); 2100 2101 /* PCI <-> OF binding helpers */ 2102 #ifdef CONFIG_OF 2103 struct device_node; 2104 struct irq_domain; 2105 void pci_set_of_node(struct pci_dev *dev); 2106 void pci_release_of_node(struct pci_dev *dev); 2107 void pci_set_bus_of_node(struct pci_bus *bus); 2108 void pci_release_bus_of_node(struct pci_bus *bus); 2109 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2110 2111 /* Arch may override this (weak) */ 2112 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2113 2114 static inline struct device_node * 2115 pci_device_to_OF_node(const struct pci_dev *pdev) 2116 { 2117 return pdev ? pdev->dev.of_node : NULL; 2118 } 2119 2120 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2121 { 2122 return bus ? bus->dev.of_node : NULL; 2123 } 2124 2125 #else /* CONFIG_OF */ 2126 static inline void pci_set_of_node(struct pci_dev *dev) { } 2127 static inline void pci_release_of_node(struct pci_dev *dev) { } 2128 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2129 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2130 static inline struct device_node * 2131 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 2132 static inline struct irq_domain * 2133 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2134 #endif /* CONFIG_OF */ 2135 2136 #ifdef CONFIG_ACPI 2137 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2138 2139 void 2140 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2141 #else 2142 static inline struct irq_domain * 2143 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2144 #endif 2145 2146 #ifdef CONFIG_EEH 2147 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2148 { 2149 return pdev->dev.archdata.edev; 2150 } 2151 #endif 2152 2153 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2154 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2155 int pci_for_each_dma_alias(struct pci_dev *pdev, 2156 int (*fn)(struct pci_dev *pdev, 2157 u16 alias, void *data), void *data); 2158 2159 /* helper functions for operation of device flag */ 2160 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2161 { 2162 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2163 } 2164 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2165 { 2166 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2167 } 2168 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2169 { 2170 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2171 } 2172 2173 /** 2174 * pci_ari_enabled - query ARI forwarding status 2175 * @bus: the PCI bus 2176 * 2177 * Returns true if ARI forwarding is enabled. 2178 */ 2179 static inline bool pci_ari_enabled(struct pci_bus *bus) 2180 { 2181 return bus->self && bus->self->ari_enabled; 2182 } 2183 2184 /** 2185 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2186 * @pdev: PCI device to check 2187 * 2188 * Walk upwards from @pdev and check for each encountered bridge if it's part 2189 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2190 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2191 */ 2192 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2193 { 2194 struct pci_dev *parent = pdev; 2195 2196 if (pdev->is_thunderbolt) 2197 return true; 2198 2199 while ((parent = pci_upstream_bridge(parent))) 2200 if (parent->is_thunderbolt) 2201 return true; 2202 2203 return false; 2204 } 2205 2206 /* provide the legacy pci_dma_* API */ 2207 #include <linux/pci-dma-compat.h> 2208 2209 #endif /* LINUX_PCI_H */ 2210