1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * For more information, please consult the following manuals (look at 10 * http://www.pcisig.com/ for how to get them): 11 * 12 * PCI BIOS Specification 13 * PCI Local Bus Specification 14 * PCI to PCI Bridge Specification 15 * PCI System Design Guide 16 */ 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 21 #include <linux/mod_devicetable.h> 22 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/list.h> 27 #include <linux/compiler.h> 28 #include <linux/errno.h> 29 #include <linux/kobject.h> 30 #include <linux/atomic.h> 31 #include <linux/device.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/resource_ext.h> 35 #include <uapi/linux/pci.h> 36 37 #include <linux/pci_ids.h> 38 39 /* 40 * The PCI interface treats multi-function devices as independent 41 * devices. The slot/function address of each device is encoded 42 * in a single byte as follows: 43 * 44 * 7:3 = slot 45 * 2:0 = function 46 * 47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 48 * In the interest of not exposing interfaces to user-space unnecessarily, 49 * the following kernel-only defines are being added here. 50 */ 51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 54 55 /* pci_slot represents a physical slot */ 56 struct pci_slot { 57 struct pci_bus *bus; /* Bus this slot is on */ 58 struct list_head list; /* Node in list of slots */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 61 struct kobject kobj; 62 }; 63 64 static inline const char *pci_slot_name(const struct pci_slot *slot) 65 { 66 return kobject_name(&slot->kobj); 67 } 68 69 /* File state for mmap()s on /proc/bus/pci/X/Y */ 70 enum pci_mmap_state { 71 pci_mmap_io, 72 pci_mmap_mem 73 }; 74 75 /* For PCI devices, the region numbers are assigned this way: */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* Device-specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* Resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* Total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* Preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 /** 105 * enum pci_interrupt_pin - PCI INTx interrupt values 106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 107 * @PCI_INTERRUPT_INTA: PCI INTA pin 108 * @PCI_INTERRUPT_INTB: PCI INTB pin 109 * @PCI_INTERRUPT_INTC: PCI INTC pin 110 * @PCI_INTERRUPT_INTD: PCI INTD pin 111 * 112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 113 * PCI_INTERRUPT_PIN register. 114 */ 115 enum pci_interrupt_pin { 116 PCI_INTERRUPT_UNKNOWN, 117 PCI_INTERRUPT_INTA, 118 PCI_INTERRUPT_INTB, 119 PCI_INTERRUPT_INTC, 120 PCI_INTERRUPT_INTD, 121 }; 122 123 /* The number of legacy PCI INTx interrupts */ 124 #define PCI_NUM_INTX 4 125 126 /* 127 * pci_power_t values must match the bits in the Capabilities PME_Support 128 * and Control/Status PowerState fields in the Power Management capability. 129 */ 130 typedef int __bitwise pci_power_t; 131 132 #define PCI_D0 ((pci_power_t __force) 0) 133 #define PCI_D1 ((pci_power_t __force) 1) 134 #define PCI_D2 ((pci_power_t __force) 2) 135 #define PCI_D3hot ((pci_power_t __force) 3) 136 #define PCI_D3cold ((pci_power_t __force) 4) 137 #define PCI_UNKNOWN ((pci_power_t __force) 5) 138 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 139 140 /* Remember to update this when the list above changes! */ 141 extern const char *pci_power_names[]; 142 143 static inline const char *pci_power_name(pci_power_t state) 144 { 145 return pci_power_names[1 + (__force int) state]; 146 } 147 148 #define PCI_PM_D2_DELAY 200 149 #define PCI_PM_D3_WAIT 10 150 #define PCI_PM_D3COLD_WAIT 100 151 #define PCI_PM_BUS_WAIT 50 152 153 /** 154 * typedef pci_channel_state_t 155 * 156 * The pci_channel state describes connectivity between the CPU and 157 * the PCI device. If some PCI bus between here and the PCI device 158 * has crashed or locked up, this info is reflected here. 159 */ 160 typedef unsigned int __bitwise pci_channel_state_t; 161 162 enum pci_channel_state { 163 /* I/O channel is in normal state */ 164 pci_channel_io_normal = (__force pci_channel_state_t) 1, 165 166 /* I/O to channel is blocked */ 167 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 168 169 /* PCI card is dead */ 170 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 171 }; 172 173 typedef unsigned int __bitwise pcie_reset_state_t; 174 175 enum pcie_reset_state { 176 /* Reset is NOT asserted (Use to deassert reset) */ 177 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 178 179 /* Use #PERST to reset PCIe device */ 180 pcie_warm_reset = (__force pcie_reset_state_t) 2, 181 182 /* Use PCIe Hot Reset to reset device */ 183 pcie_hot_reset = (__force pcie_reset_state_t) 3 184 }; 185 186 typedef unsigned short __bitwise pci_dev_flags_t; 187 enum pci_dev_flags { 188 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 189 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 190 /* Device configuration is irrevocably lost if disabled into D3 */ 191 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 192 /* Provide indication device is assigned by a Virtual Machine Manager */ 193 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 194 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 195 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 196 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 197 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 198 /* Do not use bus resets for device */ 199 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 200 /* Do not use PM reset even if device advertises NoSoftRst- */ 201 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 202 /* Get VPD from function 0 VPD */ 203 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 204 /* A non-root bridge where translation occurs, stop alias search here */ 205 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 206 /* Do not use FLR even if device advertises PCI_AF_CAP */ 207 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 208 /* Don't use Relaxed Ordering for TLPs directed at this device */ 209 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 210 }; 211 212 enum pci_irq_reroute_variant { 213 INTEL_IRQ_REROUTE_VARIANT = 1, 214 MAX_IRQ_REROUTE_VARIANTS = 3 215 }; 216 217 typedef unsigned short __bitwise pci_bus_flags_t; 218 enum pci_bus_flags { 219 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 220 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 221 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 222 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 223 }; 224 225 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 226 enum pcie_link_width { 227 PCIE_LNK_WIDTH_RESRV = 0x00, 228 PCIE_LNK_X1 = 0x01, 229 PCIE_LNK_X2 = 0x02, 230 PCIE_LNK_X4 = 0x04, 231 PCIE_LNK_X8 = 0x08, 232 PCIE_LNK_X12 = 0x0c, 233 PCIE_LNK_X16 = 0x10, 234 PCIE_LNK_X32 = 0x20, 235 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 236 }; 237 238 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 239 enum pci_bus_speed { 240 PCI_SPEED_33MHz = 0x00, 241 PCI_SPEED_66MHz = 0x01, 242 PCI_SPEED_66MHz_PCIX = 0x02, 243 PCI_SPEED_100MHz_PCIX = 0x03, 244 PCI_SPEED_133MHz_PCIX = 0x04, 245 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 246 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 247 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 248 PCI_SPEED_66MHz_PCIX_266 = 0x09, 249 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 250 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 251 AGP_UNKNOWN = 0x0c, 252 AGP_1X = 0x0d, 253 AGP_2X = 0x0e, 254 AGP_4X = 0x0f, 255 AGP_8X = 0x10, 256 PCI_SPEED_66MHz_PCIX_533 = 0x11, 257 PCI_SPEED_100MHz_PCIX_533 = 0x12, 258 PCI_SPEED_133MHz_PCIX_533 = 0x13, 259 PCIE_SPEED_2_5GT = 0x14, 260 PCIE_SPEED_5_0GT = 0x15, 261 PCIE_SPEED_8_0GT = 0x16, 262 PCIE_SPEED_16_0GT = 0x17, 263 PCIE_SPEED_32_0GT = 0x18, 264 PCI_SPEED_UNKNOWN = 0xff, 265 }; 266 267 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 268 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 269 270 struct pci_cap_saved_data { 271 u16 cap_nr; 272 bool cap_extended; 273 unsigned int size; 274 u32 data[0]; 275 }; 276 277 struct pci_cap_saved_state { 278 struct hlist_node next; 279 struct pci_cap_saved_data cap; 280 }; 281 282 struct irq_affinity; 283 struct pcie_link_state; 284 struct pci_vpd; 285 struct pci_sriov; 286 struct pci_ats; 287 struct pci_p2pdma; 288 289 /* The pci_dev structure describes PCI devices */ 290 struct pci_dev { 291 struct list_head bus_list; /* Node in per-bus list */ 292 struct pci_bus *bus; /* Bus this device is on */ 293 struct pci_bus *subordinate; /* Bus this device bridges to */ 294 295 void *sysdata; /* Hook for sys-specific extension */ 296 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 297 struct pci_slot *slot; /* Physical slot this device is in */ 298 299 unsigned int devfn; /* Encoded device & function index */ 300 unsigned short vendor; 301 unsigned short device; 302 unsigned short subsystem_vendor; 303 unsigned short subsystem_device; 304 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 305 u8 revision; /* PCI revision, low byte of class word */ 306 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 307 #ifdef CONFIG_PCIEAER 308 u16 aer_cap; /* AER capability offset */ 309 struct aer_stats *aer_stats; /* AER stats for this device */ 310 #endif 311 u8 pcie_cap; /* PCIe capability offset */ 312 u8 msi_cap; /* MSI capability offset */ 313 u8 msix_cap; /* MSI-X capability offset */ 314 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 315 u8 rom_base_reg; /* Config register controlling ROM */ 316 u8 pin; /* Interrupt pin this device uses */ 317 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 318 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 319 320 struct pci_driver *driver; /* Driver bound to this device */ 321 u64 dma_mask; /* Mask of the bits of bus address this 322 device implements. Normally this is 323 0xffffffff. You only need to change 324 this if your device has broken DMA 325 or supports 64-bit transfers. */ 326 327 struct device_dma_parameters dma_parms; 328 329 pci_power_t current_state; /* Current operating state. In ACPI, 330 this is D0-D3, D0 being fully 331 functional, and D3 being off. */ 332 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 333 u8 pm_cap; /* PM capability offset */ 334 unsigned int pme_support:5; /* Bitmask of states from which PME# 335 can be generated */ 336 unsigned int pme_poll:1; /* Poll device's PME status bit */ 337 unsigned int d1_support:1; /* Low power state D1 is supported */ 338 unsigned int d2_support:1; /* Low power state D2 is supported */ 339 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 340 unsigned int no_d3cold:1; /* D3cold is forbidden */ 341 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 342 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 343 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 344 decoding during BAR sizing */ 345 unsigned int wakeup_prepared:1; 346 unsigned int runtime_d3cold:1; /* Whether go through runtime 347 D3cold, not set for devices 348 powered on/off by the 349 corresponding bridge */ 350 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 351 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 352 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 353 controlled exclusively by 354 user sysfs */ 355 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 356 bit manually */ 357 unsigned int d3_delay; /* D3->D0 transition time in ms */ 358 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 359 360 #ifdef CONFIG_PCIEASPM 361 struct pcie_link_state *link_state; /* ASPM link state */ 362 unsigned int ltr_path:1; /* Latency Tolerance Reporting 363 supported from root to here */ 364 #endif 365 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 366 367 pci_channel_state_t error_state; /* Current connectivity state */ 368 struct device dev; /* Generic device interface */ 369 370 int cfg_size; /* Size of config space */ 371 372 /* 373 * Instead of touching interrupt line and base address registers 374 * directly, use the values stored here. They might be different! 375 */ 376 unsigned int irq; 377 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 378 379 bool match_driver; /* Skip attaching driver */ 380 381 unsigned int transparent:1; /* Subtractive decode bridge */ 382 unsigned int io_window:1; /* Bridge has I/O window */ 383 unsigned int pref_window:1; /* Bridge has pref mem window */ 384 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 385 unsigned int multifunction:1; /* Multi-function device */ 386 387 unsigned int is_busmaster:1; /* Is busmaster */ 388 unsigned int no_msi:1; /* May not use MSI */ 389 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 390 unsigned int block_cfg_access:1; /* Config space access blocked */ 391 unsigned int broken_parity_status:1; /* Generates false positive parity */ 392 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 393 unsigned int msi_enabled:1; 394 unsigned int msix_enabled:1; 395 unsigned int ari_enabled:1; /* ARI forwarding */ 396 unsigned int ats_enabled:1; /* Address Translation Svc */ 397 unsigned int pasid_enabled:1; /* Process Address Space ID */ 398 unsigned int pri_enabled:1; /* Page Request Interface */ 399 unsigned int is_managed:1; 400 unsigned int needs_freset:1; /* Requires fundamental reset */ 401 unsigned int state_saved:1; 402 unsigned int is_physfn:1; 403 unsigned int is_virtfn:1; 404 unsigned int reset_fn:1; 405 unsigned int is_hotplug_bridge:1; 406 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 407 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 408 /* 409 * Devices marked being untrusted are the ones that can potentially 410 * execute DMA attacks and similar. They are typically connected 411 * through external ports such as Thunderbolt but not limited to 412 * that. When an IOMMU is enabled they should be getting full 413 * mappings to make sure they cannot access arbitrary memory. 414 */ 415 unsigned int untrusted:1; 416 unsigned int __aer_firmware_first_valid:1; 417 unsigned int __aer_firmware_first:1; 418 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 419 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 420 unsigned int irq_managed:1; 421 unsigned int has_secondary_link:1; 422 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 423 unsigned int is_probed:1; /* Device probing in progress */ 424 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 425 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 426 pci_dev_flags_t dev_flags; 427 atomic_t enable_cnt; /* pci_enable_device has been called */ 428 429 u32 saved_config_space[16]; /* Config space saved at suspend time */ 430 struct hlist_head saved_cap_space; 431 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 432 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 433 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 434 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 435 436 #ifdef CONFIG_HOTPLUG_PCI_PCIE 437 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 438 #endif 439 #ifdef CONFIG_PCIE_PTM 440 unsigned int ptm_root:1; 441 unsigned int ptm_enabled:1; 442 u8 ptm_granularity; 443 #endif 444 #ifdef CONFIG_PCI_MSI 445 const struct attribute_group **msi_irq_groups; 446 #endif 447 struct pci_vpd *vpd; 448 #ifdef CONFIG_PCI_ATS 449 union { 450 struct pci_sriov *sriov; /* PF: SR-IOV info */ 451 struct pci_dev *physfn; /* VF: related PF */ 452 }; 453 u16 ats_cap; /* ATS Capability offset */ 454 u8 ats_stu; /* ATS Smallest Translation Unit */ 455 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ 456 #endif 457 #ifdef CONFIG_PCI_PRI 458 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 459 #endif 460 #ifdef CONFIG_PCI_PASID 461 u16 pasid_features; 462 #endif 463 #ifdef CONFIG_PCI_P2PDMA 464 struct pci_p2pdma *p2pdma; 465 #endif 466 phys_addr_t rom; /* Physical address if not from BAR */ 467 size_t romlen; /* Length if not from BAR */ 468 char *driver_override; /* Driver name to force a match */ 469 470 unsigned long priv_flags; /* Private flags for the PCI driver */ 471 }; 472 473 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 474 { 475 #ifdef CONFIG_PCI_IOV 476 if (dev->is_virtfn) 477 dev = dev->physfn; 478 #endif 479 return dev; 480 } 481 482 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 483 484 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 485 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 486 487 static inline int pci_channel_offline(struct pci_dev *pdev) 488 { 489 return (pdev->error_state != pci_channel_io_normal); 490 } 491 492 struct pci_host_bridge { 493 struct device dev; 494 struct pci_bus *bus; /* Root bus */ 495 struct pci_ops *ops; 496 void *sysdata; 497 int busnr; 498 struct list_head windows; /* resource_entry */ 499 struct list_head dma_ranges; /* dma ranges resource list */ 500 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 501 int (*map_irq)(const struct pci_dev *, u8, u8); 502 void (*release_fn)(struct pci_host_bridge *); 503 void *release_data; 504 struct msi_controller *msi; 505 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 506 unsigned int no_ext_tags:1; /* No Extended Tags */ 507 unsigned int native_aer:1; /* OS may use PCIe AER */ 508 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 509 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 510 unsigned int native_pme:1; /* OS may use PCIe PME */ 511 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 512 unsigned int preserve_config:1; /* Preserve FW resource setup */ 513 514 /* Resource alignment requirements */ 515 resource_size_t (*align_resource)(struct pci_dev *dev, 516 const struct resource *res, 517 resource_size_t start, 518 resource_size_t size, 519 resource_size_t align); 520 unsigned long private[0] ____cacheline_aligned; 521 }; 522 523 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 524 525 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 526 { 527 return (void *)bridge->private; 528 } 529 530 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 531 { 532 return container_of(priv, struct pci_host_bridge, private); 533 } 534 535 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 536 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 537 size_t priv); 538 void pci_free_host_bridge(struct pci_host_bridge *bridge); 539 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 540 541 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 542 void (*release_fn)(struct pci_host_bridge *), 543 void *release_data); 544 545 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 546 547 /* 548 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 549 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 550 * buses below host bridges or subtractive decode bridges) go in the list. 551 * Use pci_bus_for_each_resource() to iterate through all the resources. 552 */ 553 554 /* 555 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 556 * and there's no way to program the bridge with the details of the window. 557 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 558 * decode bit set, because they are explicit and can be programmed with _SRS. 559 */ 560 #define PCI_SUBTRACTIVE_DECODE 0x1 561 562 struct pci_bus_resource { 563 struct list_head list; 564 struct resource *res; 565 unsigned int flags; 566 }; 567 568 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 569 570 struct pci_bus { 571 struct list_head node; /* Node in list of buses */ 572 struct pci_bus *parent; /* Parent bus this bridge is on */ 573 struct list_head children; /* List of child buses */ 574 struct list_head devices; /* List of devices on this bus */ 575 struct pci_dev *self; /* Bridge device as seen by parent */ 576 struct list_head slots; /* List of slots on this bus; 577 protected by pci_slot_mutex */ 578 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 579 struct list_head resources; /* Address space routed to this bus */ 580 struct resource busn_res; /* Bus numbers routed to this bus */ 581 582 struct pci_ops *ops; /* Configuration access functions */ 583 struct msi_controller *msi; /* MSI controller */ 584 void *sysdata; /* Hook for sys-specific extension */ 585 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 586 587 unsigned char number; /* Bus number */ 588 unsigned char primary; /* Number of primary bridge */ 589 unsigned char max_bus_speed; /* enum pci_bus_speed */ 590 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 591 #ifdef CONFIG_PCI_DOMAINS_GENERIC 592 int domain_nr; 593 #endif 594 595 char name[48]; 596 597 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 598 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 599 struct device *bridge; 600 struct device dev; 601 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 602 struct bin_attribute *legacy_mem; /* Legacy mem */ 603 unsigned int is_added:1; 604 }; 605 606 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 607 608 static inline u16 pci_dev_id(struct pci_dev *dev) 609 { 610 return PCI_DEVID(dev->bus->number, dev->devfn); 611 } 612 613 /* 614 * Returns true if the PCI bus is root (behind host-PCI bridge), 615 * false otherwise 616 * 617 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 618 * This is incorrect because "virtual" buses added for SR-IOV (via 619 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 620 */ 621 static inline bool pci_is_root_bus(struct pci_bus *pbus) 622 { 623 return !(pbus->parent); 624 } 625 626 /** 627 * pci_is_bridge - check if the PCI device is a bridge 628 * @dev: PCI device 629 * 630 * Return true if the PCI device is bridge whether it has subordinate 631 * or not. 632 */ 633 static inline bool pci_is_bridge(struct pci_dev *dev) 634 { 635 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 636 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 637 } 638 639 #define for_each_pci_bridge(dev, bus) \ 640 list_for_each_entry(dev, &bus->devices, bus_list) \ 641 if (!pci_is_bridge(dev)) {} else 642 643 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 644 { 645 dev = pci_physfn(dev); 646 if (pci_is_root_bus(dev->bus)) 647 return NULL; 648 649 return dev->bus->self; 650 } 651 652 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 653 void pci_put_host_bridge_device(struct device *dev); 654 655 #ifdef CONFIG_PCI_MSI 656 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 657 { 658 return pci_dev->msi_enabled || pci_dev->msix_enabled; 659 } 660 #else 661 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 662 #endif 663 664 /* Error values that may be returned by PCI functions */ 665 #define PCIBIOS_SUCCESSFUL 0x00 666 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 667 #define PCIBIOS_BAD_VENDOR_ID 0x83 668 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 669 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 670 #define PCIBIOS_SET_FAILED 0x88 671 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 672 673 /* Translate above to generic errno for passing back through non-PCI code */ 674 static inline int pcibios_err_to_errno(int err) 675 { 676 if (err <= PCIBIOS_SUCCESSFUL) 677 return err; /* Assume already errno */ 678 679 switch (err) { 680 case PCIBIOS_FUNC_NOT_SUPPORTED: 681 return -ENOENT; 682 case PCIBIOS_BAD_VENDOR_ID: 683 return -ENOTTY; 684 case PCIBIOS_DEVICE_NOT_FOUND: 685 return -ENODEV; 686 case PCIBIOS_BAD_REGISTER_NUMBER: 687 return -EFAULT; 688 case PCIBIOS_SET_FAILED: 689 return -EIO; 690 case PCIBIOS_BUFFER_TOO_SMALL: 691 return -ENOSPC; 692 } 693 694 return -ERANGE; 695 } 696 697 /* Low-level architecture-dependent routines */ 698 699 struct pci_ops { 700 int (*add_bus)(struct pci_bus *bus); 701 void (*remove_bus)(struct pci_bus *bus); 702 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 703 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 704 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 705 }; 706 707 /* 708 * ACPI needs to be able to access PCI config space before we've done a 709 * PCI bus scan and created pci_bus structures. 710 */ 711 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 712 int reg, int len, u32 *val); 713 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 714 int reg, int len, u32 val); 715 716 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 717 typedef u64 pci_bus_addr_t; 718 #else 719 typedef u32 pci_bus_addr_t; 720 #endif 721 722 struct pci_bus_region { 723 pci_bus_addr_t start; 724 pci_bus_addr_t end; 725 }; 726 727 struct pci_dynids { 728 spinlock_t lock; /* Protects list, index */ 729 struct list_head list; /* For IDs added at runtime */ 730 }; 731 732 733 /* 734 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 735 * a set of callbacks in struct pci_error_handlers, that device driver 736 * will be notified of PCI bus errors, and will be driven to recovery 737 * when an error occurs. 738 */ 739 740 typedef unsigned int __bitwise pci_ers_result_t; 741 742 enum pci_ers_result { 743 /* No result/none/not supported in device driver */ 744 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 745 746 /* Device driver can recover without slot reset */ 747 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 748 749 /* Device driver wants slot to be reset */ 750 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 751 752 /* Device has completely failed, is unrecoverable */ 753 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 754 755 /* Device driver is fully recovered and operational */ 756 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 757 758 /* No AER capabilities registered for the driver */ 759 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 760 }; 761 762 /* PCI bus error event callbacks */ 763 struct pci_error_handlers { 764 /* PCI bus error detected on this device */ 765 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 766 enum pci_channel_state error); 767 768 /* MMIO has been re-enabled, but not DMA */ 769 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 770 771 /* PCI slot has been reset */ 772 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 773 774 /* PCI function reset prepare or completed */ 775 void (*reset_prepare)(struct pci_dev *dev); 776 void (*reset_done)(struct pci_dev *dev); 777 778 /* Device driver may resume normal operations */ 779 void (*resume)(struct pci_dev *dev); 780 }; 781 782 783 struct module; 784 785 /** 786 * struct pci_driver - PCI driver structure 787 * @node: List of driver structures. 788 * @name: Driver name. 789 * @id_table: Pointer to table of device IDs the driver is 790 * interested in. Most drivers should export this 791 * table using MODULE_DEVICE_TABLE(pci,...). 792 * @probe: This probing function gets called (during execution 793 * of pci_register_driver() for already existing 794 * devices or later if a new device gets inserted) for 795 * all PCI devices which match the ID table and are not 796 * "owned" by the other drivers yet. This function gets 797 * passed a "struct pci_dev \*" for each device whose 798 * entry in the ID table matches the device. The probe 799 * function returns zero when the driver chooses to 800 * take "ownership" of the device or an error code 801 * (negative number) otherwise. 802 * The probe function always gets called from process 803 * context, so it can sleep. 804 * @remove: The remove() function gets called whenever a device 805 * being handled by this driver is removed (either during 806 * deregistration of the driver or when it's manually 807 * pulled out of a hot-pluggable slot). 808 * The remove function always gets called from process 809 * context, so it can sleep. 810 * @suspend: Put device into low power state. 811 * @suspend_late: Put device into low power state. 812 * @resume_early: Wake device from low power state. 813 * @resume: Wake device from low power state. 814 * (Please see Documentation/power/pci.rst for descriptions 815 * of PCI Power Management and the related functions.) 816 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 817 * Intended to stop any idling DMA operations. 818 * Useful for enabling wake-on-lan (NIC) or changing 819 * the power state of a device before reboot. 820 * e.g. drivers/net/e100.c. 821 * @sriov_configure: Optional driver callback to allow configuration of 822 * number of VFs to enable via sysfs "sriov_numvfs" file. 823 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 824 * @groups: Sysfs attribute groups. 825 * @driver: Driver model structure. 826 * @dynids: List of dynamically added device IDs. 827 */ 828 struct pci_driver { 829 struct list_head node; 830 const char *name; 831 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 832 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 833 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 834 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 835 int (*suspend_late)(struct pci_dev *dev, pm_message_t state); 836 int (*resume_early)(struct pci_dev *dev); 837 int (*resume)(struct pci_dev *dev); /* Device woken up */ 838 void (*shutdown)(struct pci_dev *dev); 839 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 840 const struct pci_error_handlers *err_handler; 841 const struct attribute_group **groups; 842 struct device_driver driver; 843 struct pci_dynids dynids; 844 }; 845 846 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 847 848 /** 849 * PCI_DEVICE - macro used to describe a specific PCI device 850 * @vend: the 16 bit PCI Vendor ID 851 * @dev: the 16 bit PCI Device ID 852 * 853 * This macro is used to create a struct pci_device_id that matches a 854 * specific device. The subvendor and subdevice fields will be set to 855 * PCI_ANY_ID. 856 */ 857 #define PCI_DEVICE(vend,dev) \ 858 .vendor = (vend), .device = (dev), \ 859 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 860 861 /** 862 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 863 * @vend: the 16 bit PCI Vendor ID 864 * @dev: the 16 bit PCI Device ID 865 * @subvend: the 16 bit PCI Subvendor ID 866 * @subdev: the 16 bit PCI Subdevice ID 867 * 868 * This macro is used to create a struct pci_device_id that matches a 869 * specific device with subsystem information. 870 */ 871 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 872 .vendor = (vend), .device = (dev), \ 873 .subvendor = (subvend), .subdevice = (subdev) 874 875 /** 876 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 877 * @dev_class: the class, subclass, prog-if triple for this device 878 * @dev_class_mask: the class mask for this device 879 * 880 * This macro is used to create a struct pci_device_id that matches a 881 * specific PCI class. The vendor, device, subvendor, and subdevice 882 * fields will be set to PCI_ANY_ID. 883 */ 884 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 885 .class = (dev_class), .class_mask = (dev_class_mask), \ 886 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 887 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 888 889 /** 890 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 891 * @vend: the vendor name 892 * @dev: the 16 bit PCI Device ID 893 * 894 * This macro is used to create a struct pci_device_id that matches a 895 * specific PCI device. The subvendor, and subdevice fields will be set 896 * to PCI_ANY_ID. The macro allows the next field to follow as the device 897 * private data. 898 */ 899 #define PCI_VDEVICE(vend, dev) \ 900 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 901 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 902 903 /** 904 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 905 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 906 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 907 * @data: the driver data to be filled 908 * 909 * This macro is used to create a struct pci_device_id that matches a 910 * specific PCI device. The subvendor, and subdevice fields will be set 911 * to PCI_ANY_ID. 912 */ 913 #define PCI_DEVICE_DATA(vend, dev, data) \ 914 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 915 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 916 .driver_data = (kernel_ulong_t)(data) 917 918 enum { 919 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 920 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 921 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 922 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 923 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 924 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 925 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 926 }; 927 928 /* These external functions are only available when PCI support is enabled */ 929 #ifdef CONFIG_PCI 930 931 extern unsigned int pci_flags; 932 933 static inline void pci_set_flags(int flags) { pci_flags = flags; } 934 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 935 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 936 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 937 938 void pcie_bus_configure_settings(struct pci_bus *bus); 939 940 enum pcie_bus_config_types { 941 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 942 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 943 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 944 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 945 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 946 }; 947 948 extern enum pcie_bus_config_types pcie_bus_config; 949 950 extern struct bus_type pci_bus_type; 951 952 /* Do NOT directly access these two variables, unless you are arch-specific PCI 953 * code, or PCI core code. */ 954 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 955 /* Some device drivers need know if PCI is initiated */ 956 int no_pci_devices(void); 957 958 void pcibios_resource_survey_bus(struct pci_bus *bus); 959 void pcibios_bus_add_device(struct pci_dev *pdev); 960 void pcibios_add_bus(struct pci_bus *bus); 961 void pcibios_remove_bus(struct pci_bus *bus); 962 void pcibios_fixup_bus(struct pci_bus *); 963 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 964 /* Architecture-specific versions may override this (weak) */ 965 char *pcibios_setup(char *str); 966 967 /* Used only when drivers/pci/setup.c is used */ 968 resource_size_t pcibios_align_resource(void *, const struct resource *, 969 resource_size_t, 970 resource_size_t); 971 972 /* Weak but can be overriden by arch */ 973 void pci_fixup_cardbus(struct pci_bus *); 974 975 /* Generic PCI functions used internally */ 976 977 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 978 struct resource *res); 979 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 980 struct pci_bus_region *region); 981 void pcibios_scan_specific_bus(int busn); 982 struct pci_bus *pci_find_bus(int domain, int busnr); 983 void pci_bus_add_devices(const struct pci_bus *bus); 984 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 985 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 986 struct pci_ops *ops, void *sysdata, 987 struct list_head *resources); 988 int pci_host_probe(struct pci_host_bridge *bridge); 989 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 990 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 991 void pci_bus_release_busn_res(struct pci_bus *b); 992 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 993 struct pci_ops *ops, void *sysdata, 994 struct list_head *resources); 995 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 996 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 997 int busnr); 998 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 999 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1000 const char *name, 1001 struct hotplug_slot *hotplug); 1002 void pci_destroy_slot(struct pci_slot *slot); 1003 #ifdef CONFIG_SYSFS 1004 void pci_dev_assign_slot(struct pci_dev *dev); 1005 #else 1006 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1007 #endif 1008 int pci_scan_slot(struct pci_bus *bus, int devfn); 1009 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1010 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1011 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1012 void pci_bus_add_device(struct pci_dev *dev); 1013 void pci_read_bridge_bases(struct pci_bus *child); 1014 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1015 struct resource *res); 1016 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 1017 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1018 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1019 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1020 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1021 void pci_dev_put(struct pci_dev *dev); 1022 void pci_remove_bus(struct pci_bus *b); 1023 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1024 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1025 void pci_stop_root_bus(struct pci_bus *bus); 1026 void pci_remove_root_bus(struct pci_bus *bus); 1027 void pci_setup_cardbus(struct pci_bus *bus); 1028 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1029 void pci_sort_breadthfirst(void); 1030 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1031 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1032 1033 /* Generic PCI functions exported to card drivers */ 1034 1035 enum pci_lost_interrupt_reason { 1036 PCI_LOST_IRQ_NO_INFORMATION = 0, 1037 PCI_LOST_IRQ_DISABLE_MSI, 1038 PCI_LOST_IRQ_DISABLE_MSIX, 1039 PCI_LOST_IRQ_DISABLE_ACPI, 1040 }; 1041 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 1042 int pci_find_capability(struct pci_dev *dev, int cap); 1043 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1044 int pci_find_ext_capability(struct pci_dev *dev, int cap); 1045 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 1046 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1047 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 1048 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1049 1050 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1051 struct pci_dev *from); 1052 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1053 unsigned int ss_vendor, unsigned int ss_device, 1054 struct pci_dev *from); 1055 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1056 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1057 unsigned int devfn); 1058 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1059 int pci_dev_present(const struct pci_device_id *ids); 1060 1061 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1062 int where, u8 *val); 1063 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1064 int where, u16 *val); 1065 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1066 int where, u32 *val); 1067 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1068 int where, u8 val); 1069 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1070 int where, u16 val); 1071 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1072 int where, u32 val); 1073 1074 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1075 int where, int size, u32 *val); 1076 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1077 int where, int size, u32 val); 1078 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1079 int where, int size, u32 *val); 1080 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1081 int where, int size, u32 val); 1082 1083 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1084 1085 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1086 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1087 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1088 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1089 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1090 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1091 1092 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1093 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1094 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1095 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1096 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1097 u16 clear, u16 set); 1098 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1099 u32 clear, u32 set); 1100 1101 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1102 u16 set) 1103 { 1104 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1105 } 1106 1107 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1108 u32 set) 1109 { 1110 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1111 } 1112 1113 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1114 u16 clear) 1115 { 1116 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1117 } 1118 1119 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1120 u32 clear) 1121 { 1122 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1123 } 1124 1125 /* User-space driven config access */ 1126 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1127 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1128 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1129 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1130 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1131 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1132 1133 int __must_check pci_enable_device(struct pci_dev *dev); 1134 int __must_check pci_enable_device_io(struct pci_dev *dev); 1135 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1136 int __must_check pci_reenable_device(struct pci_dev *); 1137 int __must_check pcim_enable_device(struct pci_dev *pdev); 1138 void pcim_pin_device(struct pci_dev *pdev); 1139 1140 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1141 { 1142 /* 1143 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1144 * writable and no quirk has marked the feature broken. 1145 */ 1146 return !pdev->broken_intx_masking; 1147 } 1148 1149 static inline int pci_is_enabled(struct pci_dev *pdev) 1150 { 1151 return (atomic_read(&pdev->enable_cnt) > 0); 1152 } 1153 1154 static inline int pci_is_managed(struct pci_dev *pdev) 1155 { 1156 return pdev->is_managed; 1157 } 1158 1159 void pci_disable_device(struct pci_dev *dev); 1160 1161 extern unsigned int pcibios_max_latency; 1162 void pci_set_master(struct pci_dev *dev); 1163 void pci_clear_master(struct pci_dev *dev); 1164 1165 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1166 int pci_set_cacheline_size(struct pci_dev *dev); 1167 #define HAVE_PCI_SET_MWI 1168 int __must_check pci_set_mwi(struct pci_dev *dev); 1169 int __must_check pcim_set_mwi(struct pci_dev *dev); 1170 int pci_try_set_mwi(struct pci_dev *dev); 1171 void pci_clear_mwi(struct pci_dev *dev); 1172 void pci_intx(struct pci_dev *dev, int enable); 1173 bool pci_check_and_mask_intx(struct pci_dev *dev); 1174 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1175 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1176 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1177 int pcix_get_max_mmrbc(struct pci_dev *dev); 1178 int pcix_get_mmrbc(struct pci_dev *dev); 1179 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1180 int pcie_get_readrq(struct pci_dev *dev); 1181 int pcie_set_readrq(struct pci_dev *dev, int rq); 1182 int pcie_get_mps(struct pci_dev *dev); 1183 int pcie_set_mps(struct pci_dev *dev, int mps); 1184 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1185 enum pci_bus_speed *speed, 1186 enum pcie_link_width *width); 1187 void pcie_print_link_status(struct pci_dev *dev); 1188 bool pcie_has_flr(struct pci_dev *dev); 1189 int pcie_flr(struct pci_dev *dev); 1190 int __pci_reset_function_locked(struct pci_dev *dev); 1191 int pci_reset_function(struct pci_dev *dev); 1192 int pci_reset_function_locked(struct pci_dev *dev); 1193 int pci_try_reset_function(struct pci_dev *dev); 1194 int pci_probe_reset_slot(struct pci_slot *slot); 1195 int pci_probe_reset_bus(struct pci_bus *bus); 1196 int pci_reset_bus(struct pci_dev *dev); 1197 void pci_reset_secondary_bus(struct pci_dev *dev); 1198 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1199 void pci_update_resource(struct pci_dev *dev, int resno); 1200 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1201 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1202 void pci_release_resource(struct pci_dev *dev, int resno); 1203 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1204 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1205 bool pci_device_is_present(struct pci_dev *pdev); 1206 void pci_ignore_hotplug(struct pci_dev *dev); 1207 1208 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1209 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1210 const char *fmt, ...); 1211 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1212 1213 /* ROM control related routines */ 1214 int pci_enable_rom(struct pci_dev *pdev); 1215 void pci_disable_rom(struct pci_dev *pdev); 1216 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1217 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1218 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1219 1220 /* Power management related routines */ 1221 int pci_save_state(struct pci_dev *dev); 1222 void pci_restore_state(struct pci_dev *dev); 1223 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1224 int pci_load_saved_state(struct pci_dev *dev, 1225 struct pci_saved_state *state); 1226 int pci_load_and_free_saved_state(struct pci_dev *dev, 1227 struct pci_saved_state **state); 1228 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1229 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1230 u16 cap); 1231 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1232 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1233 u16 cap, unsigned int size); 1234 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1235 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1236 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1237 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1238 void pci_pme_active(struct pci_dev *dev, bool enable); 1239 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1240 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1241 int pci_prepare_to_sleep(struct pci_dev *dev); 1242 int pci_back_from_sleep(struct pci_dev *dev); 1243 bool pci_dev_run_wake(struct pci_dev *dev); 1244 bool pci_check_pme_status(struct pci_dev *dev); 1245 void pci_pme_wakeup_bus(struct pci_bus *bus); 1246 void pci_d3cold_enable(struct pci_dev *dev); 1247 void pci_d3cold_disable(struct pci_dev *dev); 1248 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1249 void pci_wakeup_bus(struct pci_bus *bus); 1250 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1251 1252 /* PCI Virtual Channel */ 1253 int pci_save_vc_state(struct pci_dev *dev); 1254 void pci_restore_vc_state(struct pci_dev *dev); 1255 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1256 1257 /* For use by arch with custom probe code */ 1258 void set_pcie_port_type(struct pci_dev *pdev); 1259 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1260 1261 /* Functions for PCI Hotplug drivers to use */ 1262 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1263 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1264 unsigned int pci_rescan_bus(struct pci_bus *bus); 1265 void pci_lock_rescan_remove(void); 1266 void pci_unlock_rescan_remove(void); 1267 1268 /* Vital Product Data routines */ 1269 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1270 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1271 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1272 1273 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1274 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1275 void pci_bus_assign_resources(const struct pci_bus *bus); 1276 void pci_bus_claim_resources(struct pci_bus *bus); 1277 void pci_bus_size_bridges(struct pci_bus *bus); 1278 int pci_claim_resource(struct pci_dev *, int); 1279 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1280 void pci_assign_unassigned_resources(void); 1281 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1282 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1283 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1284 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1285 void pdev_enable_device(struct pci_dev *); 1286 int pci_enable_resources(struct pci_dev *, int mask); 1287 void pci_assign_irq(struct pci_dev *dev); 1288 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1289 #define HAVE_PCI_REQ_REGIONS 2 1290 int __must_check pci_request_regions(struct pci_dev *, const char *); 1291 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1292 void pci_release_regions(struct pci_dev *); 1293 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1294 void pci_release_region(struct pci_dev *, int); 1295 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1296 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1297 void pci_release_selected_regions(struct pci_dev *, int); 1298 1299 /* drivers/pci/bus.c */ 1300 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1301 void pci_bus_put(struct pci_bus *bus); 1302 void pci_add_resource(struct list_head *resources, struct resource *res); 1303 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1304 resource_size_t offset); 1305 void pci_free_resource_list(struct list_head *resources); 1306 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1307 unsigned int flags); 1308 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1309 void pci_bus_remove_resources(struct pci_bus *bus); 1310 int devm_request_pci_bus_resources(struct device *dev, 1311 struct list_head *resources); 1312 1313 /* Temporary until new and working PCI SBR API in place */ 1314 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1315 1316 #define pci_bus_for_each_resource(bus, res, i) \ 1317 for (i = 0; \ 1318 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1319 i++) 1320 1321 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1322 struct resource *res, resource_size_t size, 1323 resource_size_t align, resource_size_t min, 1324 unsigned long type_mask, 1325 resource_size_t (*alignf)(void *, 1326 const struct resource *, 1327 resource_size_t, 1328 resource_size_t), 1329 void *alignf_data); 1330 1331 1332 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1333 resource_size_t size); 1334 unsigned long pci_address_to_pio(phys_addr_t addr); 1335 phys_addr_t pci_pio_to_address(unsigned long pio); 1336 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1337 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1338 phys_addr_t phys_addr); 1339 void pci_unmap_iospace(struct resource *res); 1340 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1341 resource_size_t offset, 1342 resource_size_t size); 1343 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1344 struct resource *res); 1345 1346 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1347 { 1348 struct pci_bus_region region; 1349 1350 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1351 return region.start; 1352 } 1353 1354 /* Proper probing supporting hot-pluggable devices */ 1355 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1356 const char *mod_name); 1357 1358 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1359 #define pci_register_driver(driver) \ 1360 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1361 1362 void pci_unregister_driver(struct pci_driver *dev); 1363 1364 /** 1365 * module_pci_driver() - Helper macro for registering a PCI driver 1366 * @__pci_driver: pci_driver struct 1367 * 1368 * Helper macro for PCI drivers which do not do anything special in module 1369 * init/exit. This eliminates a lot of boilerplate. Each module may only 1370 * use this macro once, and calling it replaces module_init() and module_exit() 1371 */ 1372 #define module_pci_driver(__pci_driver) \ 1373 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1374 1375 /** 1376 * builtin_pci_driver() - Helper macro for registering a PCI driver 1377 * @__pci_driver: pci_driver struct 1378 * 1379 * Helper macro for PCI drivers which do not do anything special in their 1380 * init code. This eliminates a lot of boilerplate. Each driver may only 1381 * use this macro once, and calling it replaces device_initcall(...) 1382 */ 1383 #define builtin_pci_driver(__pci_driver) \ 1384 builtin_driver(__pci_driver, pci_register_driver) 1385 1386 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1387 int pci_add_dynid(struct pci_driver *drv, 1388 unsigned int vendor, unsigned int device, 1389 unsigned int subvendor, unsigned int subdevice, 1390 unsigned int class, unsigned int class_mask, 1391 unsigned long driver_data); 1392 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1393 struct pci_dev *dev); 1394 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1395 int pass); 1396 1397 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1398 void *userdata); 1399 int pci_cfg_space_size(struct pci_dev *dev); 1400 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1401 void pci_setup_bridge(struct pci_bus *bus); 1402 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1403 unsigned long type); 1404 1405 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1406 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1407 1408 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1409 unsigned int command_bits, u32 flags); 1410 1411 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1412 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1413 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1414 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1415 #define PCI_IRQ_ALL_TYPES \ 1416 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1417 1418 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1419 1420 #include <linux/dmapool.h> 1421 1422 #define pci_pool dma_pool 1423 #define pci_pool_create(name, pdev, size, align, allocation) \ 1424 dma_pool_create(name, &pdev->dev, size, align, allocation) 1425 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1426 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1427 #define pci_pool_zalloc(pool, flags, handle) \ 1428 dma_pool_zalloc(pool, flags, handle) 1429 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1430 1431 struct msix_entry { 1432 u32 vector; /* Kernel uses to write allocated vector */ 1433 u16 entry; /* Driver uses to specify entry, OS writes */ 1434 }; 1435 1436 #ifdef CONFIG_PCI_MSI 1437 int pci_msi_vec_count(struct pci_dev *dev); 1438 void pci_disable_msi(struct pci_dev *dev); 1439 int pci_msix_vec_count(struct pci_dev *dev); 1440 void pci_disable_msix(struct pci_dev *dev); 1441 void pci_restore_msi_state(struct pci_dev *dev); 1442 int pci_msi_enabled(void); 1443 int pci_enable_msi(struct pci_dev *dev); 1444 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1445 int minvec, int maxvec); 1446 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1447 struct msix_entry *entries, int nvec) 1448 { 1449 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1450 if (rc < 0) 1451 return rc; 1452 return 0; 1453 } 1454 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1455 unsigned int max_vecs, unsigned int flags, 1456 struct irq_affinity *affd); 1457 1458 void pci_free_irq_vectors(struct pci_dev *dev); 1459 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1460 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1461 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1462 1463 #else 1464 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1465 static inline void pci_disable_msi(struct pci_dev *dev) { } 1466 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1467 static inline void pci_disable_msix(struct pci_dev *dev) { } 1468 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1469 static inline int pci_msi_enabled(void) { return 0; } 1470 static inline int pci_enable_msi(struct pci_dev *dev) 1471 { return -ENOSYS; } 1472 static inline int pci_enable_msix_range(struct pci_dev *dev, 1473 struct msix_entry *entries, int minvec, int maxvec) 1474 { return -ENOSYS; } 1475 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1476 struct msix_entry *entries, int nvec) 1477 { return -ENOSYS; } 1478 1479 static inline int 1480 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1481 unsigned int max_vecs, unsigned int flags, 1482 struct irq_affinity *aff_desc) 1483 { 1484 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1485 return 1; 1486 return -ENOSPC; 1487 } 1488 1489 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1490 { 1491 } 1492 1493 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1494 { 1495 if (WARN_ON_ONCE(nr > 0)) 1496 return -EINVAL; 1497 return dev->irq; 1498 } 1499 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1500 int vec) 1501 { 1502 return cpu_possible_mask; 1503 } 1504 1505 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1506 { 1507 return first_online_node; 1508 } 1509 #endif 1510 1511 static inline int 1512 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1513 unsigned int max_vecs, unsigned int flags) 1514 { 1515 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1516 NULL); 1517 } 1518 1519 /** 1520 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1521 * @d: the INTx IRQ domain 1522 * @node: the DT node for the device whose interrupt we're translating 1523 * @intspec: the interrupt specifier data from the DT 1524 * @intsize: the number of entries in @intspec 1525 * @out_hwirq: pointer at which to write the hwirq number 1526 * @out_type: pointer at which to write the interrupt type 1527 * 1528 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1529 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1530 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1531 * INTx value to obtain the hwirq number. 1532 * 1533 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1534 */ 1535 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1536 struct device_node *node, 1537 const u32 *intspec, 1538 unsigned int intsize, 1539 unsigned long *out_hwirq, 1540 unsigned int *out_type) 1541 { 1542 const u32 intx = intspec[0]; 1543 1544 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1545 return -EINVAL; 1546 1547 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1548 return 0; 1549 } 1550 1551 #ifdef CONFIG_PCIEPORTBUS 1552 extern bool pcie_ports_disabled; 1553 extern bool pcie_ports_native; 1554 #else 1555 #define pcie_ports_disabled true 1556 #define pcie_ports_native false 1557 #endif 1558 1559 #ifdef CONFIG_PCIEASPM 1560 bool pcie_aspm_support_enabled(void); 1561 #else 1562 static inline bool pcie_aspm_support_enabled(void) { return false; } 1563 #endif 1564 1565 #ifdef CONFIG_PCIEAER 1566 bool pci_aer_available(void); 1567 #else 1568 static inline bool pci_aer_available(void) { return false; } 1569 #endif 1570 1571 #ifdef CONFIG_PCIE_ECRC 1572 void pcie_set_ecrc_checking(struct pci_dev *dev); 1573 void pcie_ecrc_get_policy(char *str); 1574 #else 1575 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1576 static inline void pcie_ecrc_get_policy(char *str) { } 1577 #endif 1578 1579 bool pci_ats_disabled(void); 1580 1581 #ifdef CONFIG_PCIE_PTM 1582 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1583 #else 1584 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1585 { return -EINVAL; } 1586 #endif 1587 1588 void pci_cfg_access_lock(struct pci_dev *dev); 1589 bool pci_cfg_access_trylock(struct pci_dev *dev); 1590 void pci_cfg_access_unlock(struct pci_dev *dev); 1591 1592 /* 1593 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1594 * a PCI domain is defined to be a set of PCI buses which share 1595 * configuration space. 1596 */ 1597 #ifdef CONFIG_PCI_DOMAINS 1598 extern int pci_domains_supported; 1599 #else 1600 enum { pci_domains_supported = 0 }; 1601 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1602 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1603 #endif /* CONFIG_PCI_DOMAINS */ 1604 1605 /* 1606 * Generic implementation for PCI domain support. If your 1607 * architecture does not need custom management of PCI 1608 * domains then this implementation will be used 1609 */ 1610 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1611 static inline int pci_domain_nr(struct pci_bus *bus) 1612 { 1613 return bus->domain_nr; 1614 } 1615 #ifdef CONFIG_ACPI 1616 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1617 #else 1618 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1619 { return 0; } 1620 #endif 1621 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1622 #endif 1623 1624 /* Some architectures require additional setup to direct VGA traffic */ 1625 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1626 unsigned int command_bits, u32 flags); 1627 void pci_register_set_vga_state(arch_set_vga_state_t func); 1628 1629 static inline int 1630 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1631 { 1632 return pci_request_selected_regions(pdev, 1633 pci_select_bars(pdev, IORESOURCE_IO), name); 1634 } 1635 1636 static inline void 1637 pci_release_io_regions(struct pci_dev *pdev) 1638 { 1639 return pci_release_selected_regions(pdev, 1640 pci_select_bars(pdev, IORESOURCE_IO)); 1641 } 1642 1643 static inline int 1644 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1645 { 1646 return pci_request_selected_regions(pdev, 1647 pci_select_bars(pdev, IORESOURCE_MEM), name); 1648 } 1649 1650 static inline void 1651 pci_release_mem_regions(struct pci_dev *pdev) 1652 { 1653 return pci_release_selected_regions(pdev, 1654 pci_select_bars(pdev, IORESOURCE_MEM)); 1655 } 1656 1657 #else /* CONFIG_PCI is not enabled */ 1658 1659 static inline void pci_set_flags(int flags) { } 1660 static inline void pci_add_flags(int flags) { } 1661 static inline void pci_clear_flags(int flags) { } 1662 static inline int pci_has_flag(int flag) { return 0; } 1663 1664 /* 1665 * If the system does not have PCI, clearly these return errors. Define 1666 * these as simple inline functions to avoid hair in drivers. 1667 */ 1668 #define _PCI_NOP(o, s, t) \ 1669 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1670 int where, t val) \ 1671 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1672 1673 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1674 _PCI_NOP(o, word, u16 x) \ 1675 _PCI_NOP(o, dword, u32 x) 1676 _PCI_NOP_ALL(read, *) 1677 _PCI_NOP_ALL(write,) 1678 1679 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1680 unsigned int device, 1681 struct pci_dev *from) 1682 { return NULL; } 1683 1684 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1685 unsigned int device, 1686 unsigned int ss_vendor, 1687 unsigned int ss_device, 1688 struct pci_dev *from) 1689 { return NULL; } 1690 1691 static inline struct pci_dev *pci_get_class(unsigned int class, 1692 struct pci_dev *from) 1693 { return NULL; } 1694 1695 #define pci_dev_present(ids) (0) 1696 #define no_pci_devices() (1) 1697 #define pci_dev_put(dev) do { } while (0) 1698 1699 static inline void pci_set_master(struct pci_dev *dev) { } 1700 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1701 static inline void pci_disable_device(struct pci_dev *dev) { } 1702 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1703 { return -EBUSY; } 1704 static inline int __pci_register_driver(struct pci_driver *drv, 1705 struct module *owner) 1706 { return 0; } 1707 static inline int pci_register_driver(struct pci_driver *drv) 1708 { return 0; } 1709 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1710 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1711 { return 0; } 1712 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1713 int cap) 1714 { return 0; } 1715 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1716 { return 0; } 1717 1718 /* Power management related routines */ 1719 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1720 static inline void pci_restore_state(struct pci_dev *dev) { } 1721 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1722 { return 0; } 1723 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1724 { return 0; } 1725 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1726 pm_message_t state) 1727 { return PCI_D0; } 1728 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1729 int enable) 1730 { return 0; } 1731 1732 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1733 struct resource *res) 1734 { return NULL; } 1735 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1736 { return -EIO; } 1737 static inline void pci_release_regions(struct pci_dev *dev) { } 1738 1739 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1740 1741 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1742 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1743 { return 0; } 1744 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1745 1746 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1747 { return NULL; } 1748 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1749 unsigned int devfn) 1750 { return NULL; } 1751 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1752 unsigned int bus, unsigned int devfn) 1753 { return NULL; } 1754 1755 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1756 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1757 1758 #define dev_is_pci(d) (false) 1759 #define dev_is_pf(d) (false) 1760 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1761 { return false; } 1762 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1763 struct device_node *node, 1764 const u32 *intspec, 1765 unsigned int intsize, 1766 unsigned long *out_hwirq, 1767 unsigned int *out_type) 1768 { return -EINVAL; } 1769 1770 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1771 struct pci_dev *dev) 1772 { return NULL; } 1773 static inline bool pci_ats_disabled(void) { return true; } 1774 #endif /* CONFIG_PCI */ 1775 1776 #ifdef CONFIG_PCI_ATS 1777 /* Address Translation Service */ 1778 void pci_ats_init(struct pci_dev *dev); 1779 int pci_enable_ats(struct pci_dev *dev, int ps); 1780 void pci_disable_ats(struct pci_dev *dev); 1781 int pci_ats_queue_depth(struct pci_dev *dev); 1782 int pci_ats_page_aligned(struct pci_dev *dev); 1783 #else 1784 static inline void pci_ats_init(struct pci_dev *d) { } 1785 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1786 static inline void pci_disable_ats(struct pci_dev *d) { } 1787 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1788 static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; } 1789 #endif 1790 1791 /* Include architecture-dependent settings and functions */ 1792 1793 #include <asm/pci.h> 1794 1795 /* These two functions provide almost identical functionality. Depennding 1796 * on the architecture, one will be implemented as a wrapper around the 1797 * other (in drivers/pci/mmap.c). 1798 * 1799 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1800 * is expected to be an offset within that region. 1801 * 1802 * pci_mmap_page_range() is the legacy architecture-specific interface, 1803 * which accepts a "user visible" resource address converted by 1804 * pci_resource_to_user(), as used in the legacy mmap() interface in 1805 * /proc/bus/pci/. 1806 */ 1807 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1808 struct vm_area_struct *vma, 1809 enum pci_mmap_state mmap_state, int write_combine); 1810 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1811 struct vm_area_struct *vma, 1812 enum pci_mmap_state mmap_state, int write_combine); 1813 1814 #ifndef arch_can_pci_mmap_wc 1815 #define arch_can_pci_mmap_wc() 0 1816 #endif 1817 1818 #ifndef arch_can_pci_mmap_io 1819 #define arch_can_pci_mmap_io() 0 1820 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1821 #else 1822 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1823 #endif 1824 1825 #ifndef pci_root_bus_fwnode 1826 #define pci_root_bus_fwnode(bus) NULL 1827 #endif 1828 1829 /* 1830 * These helpers provide future and backwards compatibility 1831 * for accessing popular PCI BAR info 1832 */ 1833 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1834 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1835 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1836 #define pci_resource_len(dev,bar) \ 1837 ((pci_resource_start((dev), (bar)) == 0 && \ 1838 pci_resource_end((dev), (bar)) == \ 1839 pci_resource_start((dev), (bar))) ? 0 : \ 1840 \ 1841 (pci_resource_end((dev), (bar)) - \ 1842 pci_resource_start((dev), (bar)) + 1)) 1843 1844 /* 1845 * Similar to the helpers above, these manipulate per-pci_dev 1846 * driver-specific data. They are really just a wrapper around 1847 * the generic device structure functions of these calls. 1848 */ 1849 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1850 { 1851 return dev_get_drvdata(&pdev->dev); 1852 } 1853 1854 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1855 { 1856 dev_set_drvdata(&pdev->dev, data); 1857 } 1858 1859 static inline const char *pci_name(const struct pci_dev *pdev) 1860 { 1861 return dev_name(&pdev->dev); 1862 } 1863 1864 1865 /* 1866 * Some archs don't want to expose struct resource to userland as-is 1867 * in sysfs and /proc 1868 */ 1869 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1870 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1871 const struct resource *rsrc, 1872 resource_size_t *start, resource_size_t *end); 1873 #else 1874 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1875 const struct resource *rsrc, resource_size_t *start, 1876 resource_size_t *end) 1877 { 1878 *start = rsrc->start; 1879 *end = rsrc->end; 1880 } 1881 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1882 1883 1884 /* 1885 * The world is not perfect and supplies us with broken PCI devices. 1886 * For at least a part of these bugs we need a work-around, so both 1887 * generic (drivers/pci/quirks.c) and per-architecture code can define 1888 * fixup hooks to be called for particular buggy devices. 1889 */ 1890 1891 struct pci_fixup { 1892 u16 vendor; /* Or PCI_ANY_ID */ 1893 u16 device; /* Or PCI_ANY_ID */ 1894 u32 class; /* Or PCI_ANY_ID */ 1895 unsigned int class_shift; /* should be 0, 8, 16 */ 1896 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1897 int hook_offset; 1898 #else 1899 void (*hook)(struct pci_dev *dev); 1900 #endif 1901 }; 1902 1903 enum pci_fixup_pass { 1904 pci_fixup_early, /* Before probing BARs */ 1905 pci_fixup_header, /* After reading configuration header */ 1906 pci_fixup_final, /* Final phase of device fixups */ 1907 pci_fixup_enable, /* pci_enable_device() time */ 1908 pci_fixup_resume, /* pci_device_resume() */ 1909 pci_fixup_suspend, /* pci_device_suspend() */ 1910 pci_fixup_resume_early, /* pci_device_resume_early() */ 1911 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1912 }; 1913 1914 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1915 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1916 class_shift, hook) \ 1917 __ADDRESSABLE(hook) \ 1918 asm(".section " #sec ", \"a\" \n" \ 1919 ".balign 16 \n" \ 1920 ".short " #vendor ", " #device " \n" \ 1921 ".long " #class ", " #class_shift " \n" \ 1922 ".long " #hook " - . \n" \ 1923 ".previous \n"); 1924 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1925 class_shift, hook) \ 1926 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1927 class_shift, hook) 1928 #else 1929 /* Anonymous variables would be nice... */ 1930 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1931 class_shift, hook) \ 1932 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1933 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1934 = { vendor, device, class, class_shift, hook }; 1935 #endif 1936 1937 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1938 class_shift, hook) \ 1939 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1940 hook, vendor, device, class, class_shift, hook) 1941 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1942 class_shift, hook) \ 1943 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1944 hook, vendor, device, class, class_shift, hook) 1945 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1946 class_shift, hook) \ 1947 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1948 hook, vendor, device, class, class_shift, hook) 1949 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1950 class_shift, hook) \ 1951 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1952 hook, vendor, device, class, class_shift, hook) 1953 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1954 class_shift, hook) \ 1955 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1956 resume##hook, vendor, device, class, class_shift, hook) 1957 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1958 class_shift, hook) \ 1959 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1960 resume_early##hook, vendor, device, class, class_shift, hook) 1961 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1962 class_shift, hook) \ 1963 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1964 suspend##hook, vendor, device, class, class_shift, hook) 1965 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1966 class_shift, hook) \ 1967 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1968 suspend_late##hook, vendor, device, class, class_shift, hook) 1969 1970 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1971 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1972 hook, vendor, device, PCI_ANY_ID, 0, hook) 1973 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1974 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1975 hook, vendor, device, PCI_ANY_ID, 0, hook) 1976 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1977 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1978 hook, vendor, device, PCI_ANY_ID, 0, hook) 1979 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1980 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1981 hook, vendor, device, PCI_ANY_ID, 0, hook) 1982 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1983 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1984 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1985 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1986 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1987 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1988 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1989 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1990 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1991 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1992 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1993 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1994 1995 #ifdef CONFIG_PCI_QUIRKS 1996 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1997 #else 1998 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1999 struct pci_dev *dev) { } 2000 #endif 2001 2002 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2003 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2004 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2005 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2006 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2007 const char *name); 2008 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2009 2010 extern int pci_pci_problems; 2011 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2012 #define PCIPCI_TRITON 2 2013 #define PCIPCI_NATOMA 4 2014 #define PCIPCI_VIAETBF 8 2015 #define PCIPCI_VSFX 16 2016 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2017 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2018 2019 extern unsigned long pci_cardbus_io_size; 2020 extern unsigned long pci_cardbus_mem_size; 2021 extern u8 pci_dfl_cache_line_size; 2022 extern u8 pci_cache_line_size; 2023 2024 extern unsigned long pci_hotplug_io_size; 2025 extern unsigned long pci_hotplug_mem_size; 2026 extern unsigned long pci_hotplug_bus_size; 2027 2028 /* Architecture-specific versions may override these (weak) */ 2029 void pcibios_disable_device(struct pci_dev *dev); 2030 void pcibios_set_master(struct pci_dev *dev); 2031 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2032 enum pcie_reset_state state); 2033 int pcibios_add_device(struct pci_dev *dev); 2034 void pcibios_release_device(struct pci_dev *dev); 2035 #ifdef CONFIG_PCI 2036 void pcibios_penalize_isa_irq(int irq, int active); 2037 #else 2038 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2039 #endif 2040 int pcibios_alloc_irq(struct pci_dev *dev); 2041 void pcibios_free_irq(struct pci_dev *dev); 2042 resource_size_t pcibios_default_alignment(void); 2043 2044 #ifdef CONFIG_HIBERNATE_CALLBACKS 2045 extern struct dev_pm_ops pcibios_pm_ops; 2046 #endif 2047 2048 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2049 void __init pci_mmcfg_early_init(void); 2050 void __init pci_mmcfg_late_init(void); 2051 #else 2052 static inline void pci_mmcfg_early_init(void) { } 2053 static inline void pci_mmcfg_late_init(void) { } 2054 #endif 2055 2056 int pci_ext_cfg_avail(void); 2057 2058 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2059 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2060 2061 #ifdef CONFIG_PCI_IOV 2062 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2063 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2064 2065 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2066 void pci_disable_sriov(struct pci_dev *dev); 2067 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2068 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2069 int pci_num_vf(struct pci_dev *dev); 2070 int pci_vfs_assigned(struct pci_dev *dev); 2071 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2072 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2073 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2074 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2075 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2076 2077 /* Arch may override these (weak) */ 2078 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2079 int pcibios_sriov_disable(struct pci_dev *pdev); 2080 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2081 #else 2082 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2083 { 2084 return -ENOSYS; 2085 } 2086 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2087 { 2088 return -ENOSYS; 2089 } 2090 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2091 { return -ENODEV; } 2092 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2093 { 2094 return -ENOSYS; 2095 } 2096 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2097 int id) { } 2098 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2099 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2100 static inline int pci_vfs_assigned(struct pci_dev *dev) 2101 { return 0; } 2102 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2103 { return 0; } 2104 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2105 { return 0; } 2106 #define pci_sriov_configure_simple NULL 2107 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2108 { return 0; } 2109 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2110 #endif 2111 2112 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2113 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2114 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2115 #endif 2116 2117 /** 2118 * pci_pcie_cap - get the saved PCIe capability offset 2119 * @dev: PCI device 2120 * 2121 * PCIe capability offset is calculated at PCI device initialization 2122 * time and saved in the data structure. This function returns saved 2123 * PCIe capability offset. Using this instead of pci_find_capability() 2124 * reduces unnecessary search in the PCI configuration space. If you 2125 * need to calculate PCIe capability offset from raw device for some 2126 * reasons, please use pci_find_capability() instead. 2127 */ 2128 static inline int pci_pcie_cap(struct pci_dev *dev) 2129 { 2130 return dev->pcie_cap; 2131 } 2132 2133 /** 2134 * pci_is_pcie - check if the PCI device is PCI Express capable 2135 * @dev: PCI device 2136 * 2137 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2138 */ 2139 static inline bool pci_is_pcie(struct pci_dev *dev) 2140 { 2141 return pci_pcie_cap(dev); 2142 } 2143 2144 /** 2145 * pcie_caps_reg - get the PCIe Capabilities Register 2146 * @dev: PCI device 2147 */ 2148 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2149 { 2150 return dev->pcie_flags_reg; 2151 } 2152 2153 /** 2154 * pci_pcie_type - get the PCIe device/port type 2155 * @dev: PCI device 2156 */ 2157 static inline int pci_pcie_type(const struct pci_dev *dev) 2158 { 2159 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2160 } 2161 2162 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2163 { 2164 while (1) { 2165 if (!pci_is_pcie(dev)) 2166 break; 2167 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2168 return dev; 2169 if (!dev->bus->self) 2170 break; 2171 dev = dev->bus->self; 2172 } 2173 return NULL; 2174 } 2175 2176 void pci_request_acs(void); 2177 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2178 bool pci_acs_path_enabled(struct pci_dev *start, 2179 struct pci_dev *end, u16 acs_flags); 2180 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2181 2182 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2183 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2184 2185 /* Large Resource Data Type Tag Item Names */ 2186 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2187 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2188 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2189 2190 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2191 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2192 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2193 2194 /* Small Resource Data Type Tag Item Names */ 2195 #define PCI_VPD_STIN_END 0x0f /* End */ 2196 2197 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2198 2199 #define PCI_VPD_SRDT_TIN_MASK 0x78 2200 #define PCI_VPD_SRDT_LEN_MASK 0x07 2201 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2202 2203 #define PCI_VPD_LRDT_TAG_SIZE 3 2204 #define PCI_VPD_SRDT_TAG_SIZE 1 2205 2206 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2207 2208 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2209 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2210 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2211 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2212 2213 /** 2214 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2215 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2216 * 2217 * Returns the extracted Large Resource Data Type length. 2218 */ 2219 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2220 { 2221 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2222 } 2223 2224 /** 2225 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2226 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2227 * 2228 * Returns the extracted Large Resource Data Type Tag item. 2229 */ 2230 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2231 { 2232 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2233 } 2234 2235 /** 2236 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2237 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2238 * 2239 * Returns the extracted Small Resource Data Type length. 2240 */ 2241 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2242 { 2243 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2244 } 2245 2246 /** 2247 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2248 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2249 * 2250 * Returns the extracted Small Resource Data Type Tag Item. 2251 */ 2252 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2253 { 2254 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2255 } 2256 2257 /** 2258 * pci_vpd_info_field_size - Extracts the information field length 2259 * @info_field: Pointer to the beginning of an information field header 2260 * 2261 * Returns the extracted information field length. 2262 */ 2263 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2264 { 2265 return info_field[2]; 2266 } 2267 2268 /** 2269 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2270 * @buf: Pointer to buffered vpd data 2271 * @off: The offset into the buffer at which to begin the search 2272 * @len: The length of the vpd buffer 2273 * @rdt: The Resource Data Type to search for 2274 * 2275 * Returns the index where the Resource Data Type was found or 2276 * -ENOENT otherwise. 2277 */ 2278 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2279 2280 /** 2281 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2282 * @buf: Pointer to buffered vpd data 2283 * @off: The offset into the buffer at which to begin the search 2284 * @len: The length of the buffer area, relative to off, in which to search 2285 * @kw: The keyword to search for 2286 * 2287 * Returns the index where the information field keyword was found or 2288 * -ENOENT otherwise. 2289 */ 2290 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2291 unsigned int len, const char *kw); 2292 2293 /* PCI <-> OF binding helpers */ 2294 #ifdef CONFIG_OF 2295 struct device_node; 2296 struct irq_domain; 2297 void pci_set_of_node(struct pci_dev *dev); 2298 void pci_release_of_node(struct pci_dev *dev); 2299 void pci_set_bus_of_node(struct pci_bus *bus); 2300 void pci_release_bus_of_node(struct pci_bus *bus); 2301 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2302 int pci_parse_request_of_pci_ranges(struct device *dev, 2303 struct list_head *resources, 2304 struct resource **bus_range); 2305 2306 /* Arch may override this (weak) */ 2307 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2308 2309 #else /* CONFIG_OF */ 2310 static inline void pci_set_of_node(struct pci_dev *dev) { } 2311 static inline void pci_release_of_node(struct pci_dev *dev) { } 2312 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2313 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2314 static inline struct irq_domain * 2315 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2316 static inline int pci_parse_request_of_pci_ranges(struct device *dev, 2317 struct list_head *resources, 2318 struct resource **bus_range) 2319 { 2320 return -EINVAL; 2321 } 2322 #endif /* CONFIG_OF */ 2323 2324 static inline struct device_node * 2325 pci_device_to_OF_node(const struct pci_dev *pdev) 2326 { 2327 return pdev ? pdev->dev.of_node : NULL; 2328 } 2329 2330 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2331 { 2332 return bus ? bus->dev.of_node : NULL; 2333 } 2334 2335 #ifdef CONFIG_ACPI 2336 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2337 2338 void 2339 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2340 #else 2341 static inline struct irq_domain * 2342 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2343 #endif 2344 2345 #ifdef CONFIG_EEH 2346 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2347 { 2348 return pdev->dev.archdata.edev; 2349 } 2350 #endif 2351 2352 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2353 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2354 int pci_for_each_dma_alias(struct pci_dev *pdev, 2355 int (*fn)(struct pci_dev *pdev, 2356 u16 alias, void *data), void *data); 2357 2358 /* Helper functions for operation of device flag */ 2359 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2360 { 2361 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2362 } 2363 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2364 { 2365 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2366 } 2367 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2368 { 2369 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2370 } 2371 2372 /** 2373 * pci_ari_enabled - query ARI forwarding status 2374 * @bus: the PCI bus 2375 * 2376 * Returns true if ARI forwarding is enabled. 2377 */ 2378 static inline bool pci_ari_enabled(struct pci_bus *bus) 2379 { 2380 return bus->self && bus->self->ari_enabled; 2381 } 2382 2383 /** 2384 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2385 * @pdev: PCI device to check 2386 * 2387 * Walk upwards from @pdev and check for each encountered bridge if it's part 2388 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2389 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2390 */ 2391 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2392 { 2393 struct pci_dev *parent = pdev; 2394 2395 if (pdev->is_thunderbolt) 2396 return true; 2397 2398 while ((parent = pci_upstream_bridge(parent))) 2399 if (parent->is_thunderbolt) 2400 return true; 2401 2402 return false; 2403 } 2404 2405 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2406 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2407 #endif 2408 2409 /* Provide the legacy pci_dma_* API */ 2410 #include <linux/pci-dma-compat.h> 2411 2412 #define pci_printk(level, pdev, fmt, arg...) \ 2413 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2414 2415 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2416 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2417 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2418 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2419 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2420 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2421 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2422 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2423 2424 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2425 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2426 2427 #endif /* LINUX_PCI_H */ 2428