1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <uapi/linux/pci.h> 33 34 #include <linux/pci_ids.h> 35 36 /* 37 * The PCI interface treats multi-function devices as independent 38 * devices. The slot/function address of each device is encoded 39 * in a single byte as follows: 40 * 41 * 7:3 = slot 42 * 2:0 = function 43 * 44 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 45 * In the interest of not exposing interfaces to user-space unnecessarily, 46 * the following kernel-only defines are being added here. 47 */ 48 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 49 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 50 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 51 52 /* pci_slot represents a physical slot */ 53 struct pci_slot { 54 struct pci_bus *bus; /* The bus this slot is on */ 55 struct list_head list; /* node in list of slots on this bus */ 56 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 57 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 58 struct kobject kobj; 59 }; 60 61 static inline const char *pci_slot_name(const struct pci_slot *slot) 62 { 63 return kobject_name(&slot->kobj); 64 } 65 66 /* File state for mmap()s on /proc/bus/pci/X/Y */ 67 enum pci_mmap_state { 68 pci_mmap_io, 69 pci_mmap_mem 70 }; 71 72 /* This defines the direction arg to the DMA mapping routines. */ 73 #define PCI_DMA_BIDIRECTIONAL 0 74 #define PCI_DMA_TODEVICE 1 75 #define PCI_DMA_FROMDEVICE 2 76 #define PCI_DMA_NONE 3 77 78 /* 79 * For PCI devices, the region numbers are assigned this way: 80 */ 81 enum { 82 /* #0-5: standard PCI resources */ 83 PCI_STD_RESOURCES, 84 PCI_STD_RESOURCE_END = 5, 85 86 /* #6: expansion ROM resource */ 87 PCI_ROM_RESOURCE, 88 89 /* device specific resources */ 90 #ifdef CONFIG_PCI_IOV 91 PCI_IOV_RESOURCES, 92 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 93 #endif 94 95 /* resources assigned to buses behind the bridge */ 96 #define PCI_BRIDGE_RESOURCE_NUM 4 97 98 PCI_BRIDGE_RESOURCES, 99 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 100 PCI_BRIDGE_RESOURCE_NUM - 1, 101 102 /* total resources associated with a PCI device */ 103 PCI_NUM_RESOURCES, 104 105 /* preserve this for compatibility */ 106 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 107 }; 108 109 typedef int __bitwise pci_power_t; 110 111 #define PCI_D0 ((pci_power_t __force) 0) 112 #define PCI_D1 ((pci_power_t __force) 1) 113 #define PCI_D2 ((pci_power_t __force) 2) 114 #define PCI_D3hot ((pci_power_t __force) 3) 115 #define PCI_D3cold ((pci_power_t __force) 4) 116 #define PCI_UNKNOWN ((pci_power_t __force) 5) 117 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 118 119 /* Remember to update this when the list above changes! */ 120 extern const char *pci_power_names[]; 121 122 static inline const char *pci_power_name(pci_power_t state) 123 { 124 return pci_power_names[1 + (int) state]; 125 } 126 127 #define PCI_PM_D2_DELAY 200 128 #define PCI_PM_D3_WAIT 10 129 #define PCI_PM_D3COLD_WAIT 100 130 #define PCI_PM_BUS_WAIT 50 131 132 /** The pci_channel state describes connectivity between the CPU and 133 * the pci device. If some PCI bus between here and the pci device 134 * has crashed or locked up, this info is reflected here. 135 */ 136 typedef unsigned int __bitwise pci_channel_state_t; 137 138 enum pci_channel_state { 139 /* I/O channel is in normal state */ 140 pci_channel_io_normal = (__force pci_channel_state_t) 1, 141 142 /* I/O to channel is blocked */ 143 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 144 145 /* PCI card is dead */ 146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 147 }; 148 149 typedef unsigned int __bitwise pcie_reset_state_t; 150 151 enum pcie_reset_state { 152 /* Reset is NOT asserted (Use to deassert reset) */ 153 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 154 155 /* Use #PERST to reset PCIe device */ 156 pcie_warm_reset = (__force pcie_reset_state_t) 2, 157 158 /* Use PCIe Hot Reset to reset device */ 159 pcie_hot_reset = (__force pcie_reset_state_t) 3 160 }; 161 162 typedef unsigned short __bitwise pci_dev_flags_t; 163 enum pci_dev_flags { 164 /* INTX_DISABLE in PCI_COMMAND register disables MSI 165 * generation too. 166 */ 167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 168 /* Device configuration is irrevocably lost if disabled into D3 */ 169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 170 /* Provide indication device is assigned by a Virtual Machine Manager */ 171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 172 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 174 /* Flag to indicate the device uses dma_alias_devfn */ 175 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), 176 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 177 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 178 }; 179 180 enum pci_irq_reroute_variant { 181 INTEL_IRQ_REROUTE_VARIANT = 1, 182 MAX_IRQ_REROUTE_VARIANTS = 3 183 }; 184 185 typedef unsigned short __bitwise pci_bus_flags_t; 186 enum pci_bus_flags { 187 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 188 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 189 }; 190 191 /* These values come from the PCI Express Spec */ 192 enum pcie_link_width { 193 PCIE_LNK_WIDTH_RESRV = 0x00, 194 PCIE_LNK_X1 = 0x01, 195 PCIE_LNK_X2 = 0x02, 196 PCIE_LNK_X4 = 0x04, 197 PCIE_LNK_X8 = 0x08, 198 PCIE_LNK_X12 = 0x0C, 199 PCIE_LNK_X16 = 0x10, 200 PCIE_LNK_X32 = 0x20, 201 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 202 }; 203 204 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 205 enum pci_bus_speed { 206 PCI_SPEED_33MHz = 0x00, 207 PCI_SPEED_66MHz = 0x01, 208 PCI_SPEED_66MHz_PCIX = 0x02, 209 PCI_SPEED_100MHz_PCIX = 0x03, 210 PCI_SPEED_133MHz_PCIX = 0x04, 211 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 212 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 213 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 214 PCI_SPEED_66MHz_PCIX_266 = 0x09, 215 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 216 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 217 AGP_UNKNOWN = 0x0c, 218 AGP_1X = 0x0d, 219 AGP_2X = 0x0e, 220 AGP_4X = 0x0f, 221 AGP_8X = 0x10, 222 PCI_SPEED_66MHz_PCIX_533 = 0x11, 223 PCI_SPEED_100MHz_PCIX_533 = 0x12, 224 PCI_SPEED_133MHz_PCIX_533 = 0x13, 225 PCIE_SPEED_2_5GT = 0x14, 226 PCIE_SPEED_5_0GT = 0x15, 227 PCIE_SPEED_8_0GT = 0x16, 228 PCI_SPEED_UNKNOWN = 0xff, 229 }; 230 231 struct pci_cap_saved_data { 232 u16 cap_nr; 233 bool cap_extended; 234 unsigned int size; 235 u32 data[0]; 236 }; 237 238 struct pci_cap_saved_state { 239 struct hlist_node next; 240 struct pci_cap_saved_data cap; 241 }; 242 243 struct pcie_link_state; 244 struct pci_vpd; 245 struct pci_sriov; 246 struct pci_ats; 247 248 /* 249 * The pci_dev structure is used to describe PCI devices. 250 */ 251 struct pci_dev { 252 struct list_head bus_list; /* node in per-bus list */ 253 struct pci_bus *bus; /* bus this device is on */ 254 struct pci_bus *subordinate; /* bus this device bridges to */ 255 256 void *sysdata; /* hook for sys-specific extension */ 257 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 258 struct pci_slot *slot; /* Physical slot this device is in */ 259 260 unsigned int devfn; /* encoded device & function index */ 261 unsigned short vendor; 262 unsigned short device; 263 unsigned short subsystem_vendor; 264 unsigned short subsystem_device; 265 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 266 u8 revision; /* PCI revision, low byte of class word */ 267 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 268 u8 pcie_cap; /* PCIe capability offset */ 269 u8 msi_cap; /* MSI capability offset */ 270 u8 msix_cap; /* MSI-X capability offset */ 271 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 272 u8 rom_base_reg; /* which config register controls the ROM */ 273 u8 pin; /* which interrupt pin this device uses */ 274 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 275 u8 dma_alias_devfn;/* devfn of DMA alias, if any */ 276 277 struct pci_driver *driver; /* which driver has allocated this device */ 278 u64 dma_mask; /* Mask of the bits of bus address this 279 device implements. Normally this is 280 0xffffffff. You only need to change 281 this if your device has broken DMA 282 or supports 64-bit transfers. */ 283 284 struct device_dma_parameters dma_parms; 285 286 pci_power_t current_state; /* Current operating state. In ACPI-speak, 287 this is D0-D3, D0 being fully functional, 288 and D3 being off. */ 289 u8 pm_cap; /* PM capability offset */ 290 unsigned int pme_support:5; /* Bitmask of states from which PME# 291 can be generated */ 292 unsigned int pme_interrupt:1; 293 unsigned int pme_poll:1; /* Poll device's PME status bit */ 294 unsigned int d1_support:1; /* Low power state D1 is supported */ 295 unsigned int d2_support:1; /* Low power state D2 is supported */ 296 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 297 unsigned int no_d3cold:1; /* D3cold is forbidden */ 298 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 299 unsigned int mmio_always_on:1; /* disallow turning off io/mem 300 decoding during bar sizing */ 301 unsigned int wakeup_prepared:1; 302 unsigned int runtime_d3cold:1; /* whether go through runtime 303 D3cold, not set for devices 304 powered on/off by the 305 corresponding bridge */ 306 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 307 unsigned int d3_delay; /* D3->D0 transition time in ms */ 308 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 309 310 #ifdef CONFIG_PCIEASPM 311 struct pcie_link_state *link_state; /* ASPM link state */ 312 #endif 313 314 pci_channel_state_t error_state; /* current connectivity state */ 315 struct device dev; /* Generic device interface */ 316 317 int cfg_size; /* Size of configuration space */ 318 319 /* 320 * Instead of touching interrupt line and base address registers 321 * directly, use the values stored here. They might be different! 322 */ 323 unsigned int irq; 324 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 325 326 bool match_driver; /* Skip attaching driver */ 327 /* These fields are used by common fixups */ 328 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 329 unsigned int multifunction:1;/* Part of multi-function device */ 330 /* keep track of device state */ 331 unsigned int is_added:1; 332 unsigned int is_busmaster:1; /* device is busmaster */ 333 unsigned int no_msi:1; /* device may not use msi */ 334 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 335 unsigned int block_cfg_access:1; /* config space access is blocked */ 336 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 337 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 338 unsigned int msi_enabled:1; 339 unsigned int msix_enabled:1; 340 unsigned int ari_enabled:1; /* ARI forwarding */ 341 unsigned int is_managed:1; 342 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 343 unsigned int state_saved:1; 344 unsigned int is_physfn:1; 345 unsigned int is_virtfn:1; 346 unsigned int reset_fn:1; 347 unsigned int is_hotplug_bridge:1; 348 unsigned int __aer_firmware_first_valid:1; 349 unsigned int __aer_firmware_first:1; 350 unsigned int broken_intx_masking:1; 351 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 352 unsigned int irq_managed:1; 353 pci_dev_flags_t dev_flags; 354 atomic_t enable_cnt; /* pci_enable_device has been called */ 355 356 u32 saved_config_space[16]; /* config space saved at suspend time */ 357 struct hlist_head saved_cap_space; 358 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 359 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 360 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 361 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 362 #ifdef CONFIG_PCI_MSI 363 struct list_head msi_list; 364 const struct attribute_group **msi_irq_groups; 365 #endif 366 struct pci_vpd *vpd; 367 #ifdef CONFIG_PCI_ATS 368 union { 369 struct pci_sriov *sriov; /* SR-IOV capability related */ 370 struct pci_dev *physfn; /* the PF this VF is associated with */ 371 }; 372 struct pci_ats *ats; /* Address Translation Service */ 373 #endif 374 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 375 size_t romlen; /* Length of ROM if it's not from the BAR */ 376 char *driver_override; /* Driver name to force a match */ 377 }; 378 379 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 380 { 381 #ifdef CONFIG_PCI_IOV 382 if (dev->is_virtfn) 383 dev = dev->physfn; 384 #endif 385 return dev; 386 } 387 388 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 389 390 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 391 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 392 393 static inline int pci_channel_offline(struct pci_dev *pdev) 394 { 395 return (pdev->error_state != pci_channel_io_normal); 396 } 397 398 struct pci_host_bridge_window { 399 struct list_head list; 400 struct resource *res; /* host bridge aperture (CPU address) */ 401 resource_size_t offset; /* bus address + offset = CPU address */ 402 }; 403 404 struct pci_host_bridge { 405 struct device dev; 406 struct pci_bus *bus; /* root bus */ 407 struct list_head windows; /* pci_host_bridge_windows */ 408 void (*release_fn)(struct pci_host_bridge *); 409 void *release_data; 410 }; 411 412 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 413 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 414 void (*release_fn)(struct pci_host_bridge *), 415 void *release_data); 416 417 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 418 419 /* 420 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 421 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 422 * buses below host bridges or subtractive decode bridges) go in the list. 423 * Use pci_bus_for_each_resource() to iterate through all the resources. 424 */ 425 426 /* 427 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 428 * and there's no way to program the bridge with the details of the window. 429 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 430 * decode bit set, because they are explicit and can be programmed with _SRS. 431 */ 432 #define PCI_SUBTRACTIVE_DECODE 0x1 433 434 struct pci_bus_resource { 435 struct list_head list; 436 struct resource *res; 437 unsigned int flags; 438 }; 439 440 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 441 442 struct pci_bus { 443 struct list_head node; /* node in list of buses */ 444 struct pci_bus *parent; /* parent bus this bridge is on */ 445 struct list_head children; /* list of child buses */ 446 struct list_head devices; /* list of devices on this bus */ 447 struct pci_dev *self; /* bridge device as seen by parent */ 448 struct list_head slots; /* list of slots on this bus */ 449 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 450 struct list_head resources; /* address space routed to this bus */ 451 struct resource busn_res; /* bus numbers routed to this bus */ 452 453 struct pci_ops *ops; /* configuration access functions */ 454 struct msi_controller *msi; /* MSI controller */ 455 void *sysdata; /* hook for sys-specific extension */ 456 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 457 458 unsigned char number; /* bus number */ 459 unsigned char primary; /* number of primary bridge */ 460 unsigned char max_bus_speed; /* enum pci_bus_speed */ 461 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 462 #ifdef CONFIG_PCI_DOMAINS_GENERIC 463 int domain_nr; 464 #endif 465 466 char name[48]; 467 468 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 469 pci_bus_flags_t bus_flags; /* inherited by child buses */ 470 struct device *bridge; 471 struct device dev; 472 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 473 struct bin_attribute *legacy_mem; /* legacy mem */ 474 unsigned int is_added:1; 475 }; 476 477 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 478 479 /* 480 * Returns true if the PCI bus is root (behind host-PCI bridge), 481 * false otherwise 482 * 483 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 484 * This is incorrect because "virtual" buses added for SR-IOV (via 485 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 486 */ 487 static inline bool pci_is_root_bus(struct pci_bus *pbus) 488 { 489 return !(pbus->parent); 490 } 491 492 /** 493 * pci_is_bridge - check if the PCI device is a bridge 494 * @dev: PCI device 495 * 496 * Return true if the PCI device is bridge whether it has subordinate 497 * or not. 498 */ 499 static inline bool pci_is_bridge(struct pci_dev *dev) 500 { 501 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 502 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 503 } 504 505 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 506 { 507 dev = pci_physfn(dev); 508 if (pci_is_root_bus(dev->bus)) 509 return NULL; 510 511 return dev->bus->self; 512 } 513 514 #ifdef CONFIG_PCI_MSI 515 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 516 { 517 return pci_dev->msi_enabled || pci_dev->msix_enabled; 518 } 519 #else 520 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 521 #endif 522 523 /* 524 * Error values that may be returned by PCI functions. 525 */ 526 #define PCIBIOS_SUCCESSFUL 0x00 527 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 528 #define PCIBIOS_BAD_VENDOR_ID 0x83 529 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 530 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 531 #define PCIBIOS_SET_FAILED 0x88 532 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 533 534 /* 535 * Translate above to generic errno for passing back through non-PCI code. 536 */ 537 static inline int pcibios_err_to_errno(int err) 538 { 539 if (err <= PCIBIOS_SUCCESSFUL) 540 return err; /* Assume already errno */ 541 542 switch (err) { 543 case PCIBIOS_FUNC_NOT_SUPPORTED: 544 return -ENOENT; 545 case PCIBIOS_BAD_VENDOR_ID: 546 return -ENOTTY; 547 case PCIBIOS_DEVICE_NOT_FOUND: 548 return -ENODEV; 549 case PCIBIOS_BAD_REGISTER_NUMBER: 550 return -EFAULT; 551 case PCIBIOS_SET_FAILED: 552 return -EIO; 553 case PCIBIOS_BUFFER_TOO_SMALL: 554 return -ENOSPC; 555 } 556 557 return -ERANGE; 558 } 559 560 /* Low-level architecture-dependent routines */ 561 562 struct pci_ops { 563 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 564 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 565 }; 566 567 /* 568 * ACPI needs to be able to access PCI config space before we've done a 569 * PCI bus scan and created pci_bus structures. 570 */ 571 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 572 int reg, int len, u32 *val); 573 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 574 int reg, int len, u32 val); 575 576 struct pci_bus_region { 577 dma_addr_t start; 578 dma_addr_t end; 579 }; 580 581 struct pci_dynids { 582 spinlock_t lock; /* protects list, index */ 583 struct list_head list; /* for IDs added at runtime */ 584 }; 585 586 587 /* 588 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 589 * a set of callbacks in struct pci_error_handlers, that device driver 590 * will be notified of PCI bus errors, and will be driven to recovery 591 * when an error occurs. 592 */ 593 594 typedef unsigned int __bitwise pci_ers_result_t; 595 596 enum pci_ers_result { 597 /* no result/none/not supported in device driver */ 598 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 599 600 /* Device driver can recover without slot reset */ 601 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 602 603 /* Device driver wants slot to be reset. */ 604 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 605 606 /* Device has completely failed, is unrecoverable */ 607 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 608 609 /* Device driver is fully recovered and operational */ 610 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 611 612 /* No AER capabilities registered for the driver */ 613 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 614 }; 615 616 /* PCI bus error event callbacks */ 617 struct pci_error_handlers { 618 /* PCI bus error detected on this device */ 619 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 620 enum pci_channel_state error); 621 622 /* MMIO has been re-enabled, but not DMA */ 623 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 624 625 /* PCI Express link has been reset */ 626 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 627 628 /* PCI slot has been reset */ 629 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 630 631 /* PCI function reset prepare or completed */ 632 void (*reset_notify)(struct pci_dev *dev, bool prepare); 633 634 /* Device driver may resume normal operations */ 635 void (*resume)(struct pci_dev *dev); 636 }; 637 638 639 struct module; 640 struct pci_driver { 641 struct list_head node; 642 const char *name; 643 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 644 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 645 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 646 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 647 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 648 int (*resume_early) (struct pci_dev *dev); 649 int (*resume) (struct pci_dev *dev); /* Device woken up */ 650 void (*shutdown) (struct pci_dev *dev); 651 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 652 const struct pci_error_handlers *err_handler; 653 struct device_driver driver; 654 struct pci_dynids dynids; 655 }; 656 657 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 658 659 /** 660 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 661 * @_table: device table name 662 * 663 * This macro is deprecated and should not be used in new code. 664 */ 665 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 666 const struct pci_device_id _table[] 667 668 /** 669 * PCI_DEVICE - macro used to describe a specific pci device 670 * @vend: the 16 bit PCI Vendor ID 671 * @dev: the 16 bit PCI Device ID 672 * 673 * This macro is used to create a struct pci_device_id that matches a 674 * specific device. The subvendor and subdevice fields will be set to 675 * PCI_ANY_ID. 676 */ 677 #define PCI_DEVICE(vend,dev) \ 678 .vendor = (vend), .device = (dev), \ 679 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 680 681 /** 682 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 683 * @vend: the 16 bit PCI Vendor ID 684 * @dev: the 16 bit PCI Device ID 685 * @subvend: the 16 bit PCI Subvendor ID 686 * @subdev: the 16 bit PCI Subdevice ID 687 * 688 * This macro is used to create a struct pci_device_id that matches a 689 * specific device with subsystem information. 690 */ 691 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 692 .vendor = (vend), .device = (dev), \ 693 .subvendor = (subvend), .subdevice = (subdev) 694 695 /** 696 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 697 * @dev_class: the class, subclass, prog-if triple for this device 698 * @dev_class_mask: the class mask for this device 699 * 700 * This macro is used to create a struct pci_device_id that matches a 701 * specific PCI class. The vendor, device, subvendor, and subdevice 702 * fields will be set to PCI_ANY_ID. 703 */ 704 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 705 .class = (dev_class), .class_mask = (dev_class_mask), \ 706 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 707 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 708 709 /** 710 * PCI_VDEVICE - macro used to describe a specific pci device in short form 711 * @vend: the vendor name 712 * @dev: the 16 bit PCI Device ID 713 * 714 * This macro is used to create a struct pci_device_id that matches a 715 * specific PCI device. The subvendor, and subdevice fields will be set 716 * to PCI_ANY_ID. The macro allows the next field to follow as the device 717 * private data. 718 */ 719 720 #define PCI_VDEVICE(vend, dev) \ 721 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 722 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 723 724 /* these external functions are only available when PCI support is enabled */ 725 #ifdef CONFIG_PCI 726 727 void pcie_bus_configure_settings(struct pci_bus *bus); 728 729 enum pcie_bus_config_types { 730 PCIE_BUS_TUNE_OFF, 731 PCIE_BUS_SAFE, 732 PCIE_BUS_PERFORMANCE, 733 PCIE_BUS_PEER2PEER, 734 }; 735 736 extern enum pcie_bus_config_types pcie_bus_config; 737 738 extern struct bus_type pci_bus_type; 739 740 /* Do NOT directly access these two variables, unless you are arch-specific PCI 741 * code, or PCI core code. */ 742 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 743 /* Some device drivers need know if PCI is initiated */ 744 int no_pci_devices(void); 745 746 void pcibios_resource_survey_bus(struct pci_bus *bus); 747 void pcibios_add_bus(struct pci_bus *bus); 748 void pcibios_remove_bus(struct pci_bus *bus); 749 void pcibios_fixup_bus(struct pci_bus *); 750 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 751 /* Architecture-specific versions may override this (weak) */ 752 char *pcibios_setup(char *str); 753 754 /* Used only when drivers/pci/setup.c is used */ 755 resource_size_t pcibios_align_resource(void *, const struct resource *, 756 resource_size_t, 757 resource_size_t); 758 void pcibios_update_irq(struct pci_dev *, int irq); 759 760 /* Weak but can be overriden by arch */ 761 void pci_fixup_cardbus(struct pci_bus *); 762 763 /* Generic PCI functions used internally */ 764 765 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 766 struct resource *res); 767 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 768 struct pci_bus_region *region); 769 void pcibios_scan_specific_bus(int busn); 770 struct pci_bus *pci_find_bus(int domain, int busnr); 771 void pci_bus_add_devices(const struct pci_bus *bus); 772 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, 773 struct pci_ops *ops, void *sysdata); 774 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 775 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 776 struct pci_ops *ops, void *sysdata, 777 struct list_head *resources); 778 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 779 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 780 void pci_bus_release_busn_res(struct pci_bus *b); 781 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 782 struct pci_ops *ops, void *sysdata, 783 struct list_head *resources); 784 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 785 int busnr); 786 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 787 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 788 const char *name, 789 struct hotplug_slot *hotplug); 790 void pci_destroy_slot(struct pci_slot *slot); 791 int pci_scan_slot(struct pci_bus *bus, int devfn); 792 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 793 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 794 unsigned int pci_scan_child_bus(struct pci_bus *bus); 795 void pci_bus_add_device(struct pci_dev *dev); 796 void pci_read_bridge_bases(struct pci_bus *child); 797 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 798 struct resource *res); 799 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 800 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 801 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 802 struct pci_dev *pci_dev_get(struct pci_dev *dev); 803 void pci_dev_put(struct pci_dev *dev); 804 void pci_remove_bus(struct pci_bus *b); 805 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 806 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 807 void pci_stop_root_bus(struct pci_bus *bus); 808 void pci_remove_root_bus(struct pci_bus *bus); 809 void pci_setup_cardbus(struct pci_bus *bus); 810 void pci_sort_breadthfirst(void); 811 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 812 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 813 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 814 815 /* Generic PCI functions exported to card drivers */ 816 817 enum pci_lost_interrupt_reason { 818 PCI_LOST_IRQ_NO_INFORMATION = 0, 819 PCI_LOST_IRQ_DISABLE_MSI, 820 PCI_LOST_IRQ_DISABLE_MSIX, 821 PCI_LOST_IRQ_DISABLE_ACPI, 822 }; 823 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 824 int pci_find_capability(struct pci_dev *dev, int cap); 825 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 826 int pci_find_ext_capability(struct pci_dev *dev, int cap); 827 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 828 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 829 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 830 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 831 832 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 833 struct pci_dev *from); 834 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 835 unsigned int ss_vendor, unsigned int ss_device, 836 struct pci_dev *from); 837 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 838 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 839 unsigned int devfn); 840 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 841 unsigned int devfn) 842 { 843 return pci_get_domain_bus_and_slot(0, bus, devfn); 844 } 845 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 846 int pci_dev_present(const struct pci_device_id *ids); 847 848 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 849 int where, u8 *val); 850 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 851 int where, u16 *val); 852 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 853 int where, u32 *val); 854 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 855 int where, u8 val); 856 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 857 int where, u16 val); 858 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 859 int where, u32 val); 860 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 861 862 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 863 { 864 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 865 } 866 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 867 { 868 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 869 } 870 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 871 u32 *val) 872 { 873 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 874 } 875 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 876 { 877 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 878 } 879 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 880 { 881 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 882 } 883 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 884 u32 val) 885 { 886 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 887 } 888 889 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 890 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 891 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 892 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 893 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 894 u16 clear, u16 set); 895 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 896 u32 clear, u32 set); 897 898 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 899 u16 set) 900 { 901 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 902 } 903 904 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 905 u32 set) 906 { 907 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 908 } 909 910 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 911 u16 clear) 912 { 913 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 914 } 915 916 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 917 u32 clear) 918 { 919 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 920 } 921 922 /* user-space driven config access */ 923 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 924 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 925 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 926 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 927 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 928 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 929 930 int __must_check pci_enable_device(struct pci_dev *dev); 931 int __must_check pci_enable_device_io(struct pci_dev *dev); 932 int __must_check pci_enable_device_mem(struct pci_dev *dev); 933 int __must_check pci_reenable_device(struct pci_dev *); 934 int __must_check pcim_enable_device(struct pci_dev *pdev); 935 void pcim_pin_device(struct pci_dev *pdev); 936 937 static inline int pci_is_enabled(struct pci_dev *pdev) 938 { 939 return (atomic_read(&pdev->enable_cnt) > 0); 940 } 941 942 static inline int pci_is_managed(struct pci_dev *pdev) 943 { 944 return pdev->is_managed; 945 } 946 947 void pci_disable_device(struct pci_dev *dev); 948 949 extern unsigned int pcibios_max_latency; 950 void pci_set_master(struct pci_dev *dev); 951 void pci_clear_master(struct pci_dev *dev); 952 953 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 954 int pci_set_cacheline_size(struct pci_dev *dev); 955 #define HAVE_PCI_SET_MWI 956 int __must_check pci_set_mwi(struct pci_dev *dev); 957 int pci_try_set_mwi(struct pci_dev *dev); 958 void pci_clear_mwi(struct pci_dev *dev); 959 void pci_intx(struct pci_dev *dev, int enable); 960 bool pci_intx_mask_supported(struct pci_dev *dev); 961 bool pci_check_and_mask_intx(struct pci_dev *dev); 962 bool pci_check_and_unmask_intx(struct pci_dev *dev); 963 void pci_msi_off(struct pci_dev *dev); 964 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 965 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 966 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 967 int pci_wait_for_pending_transaction(struct pci_dev *dev); 968 int pcix_get_max_mmrbc(struct pci_dev *dev); 969 int pcix_get_mmrbc(struct pci_dev *dev); 970 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 971 int pcie_get_readrq(struct pci_dev *dev); 972 int pcie_set_readrq(struct pci_dev *dev, int rq); 973 int pcie_get_mps(struct pci_dev *dev); 974 int pcie_set_mps(struct pci_dev *dev, int mps); 975 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 976 enum pcie_link_width *width); 977 int __pci_reset_function(struct pci_dev *dev); 978 int __pci_reset_function_locked(struct pci_dev *dev); 979 int pci_reset_function(struct pci_dev *dev); 980 int pci_try_reset_function(struct pci_dev *dev); 981 int pci_probe_reset_slot(struct pci_slot *slot); 982 int pci_reset_slot(struct pci_slot *slot); 983 int pci_try_reset_slot(struct pci_slot *slot); 984 int pci_probe_reset_bus(struct pci_bus *bus); 985 int pci_reset_bus(struct pci_bus *bus); 986 int pci_try_reset_bus(struct pci_bus *bus); 987 void pci_reset_secondary_bus(struct pci_dev *dev); 988 void pcibios_reset_secondary_bus(struct pci_dev *dev); 989 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 990 void pci_update_resource(struct pci_dev *dev, int resno); 991 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 992 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 993 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 994 bool pci_device_is_present(struct pci_dev *pdev); 995 996 /* ROM control related routines */ 997 int pci_enable_rom(struct pci_dev *pdev); 998 void pci_disable_rom(struct pci_dev *pdev); 999 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1000 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1001 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1002 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1003 1004 /* Power management related routines */ 1005 int pci_save_state(struct pci_dev *dev); 1006 void pci_restore_state(struct pci_dev *dev); 1007 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1008 int pci_load_saved_state(struct pci_dev *dev, 1009 struct pci_saved_state *state); 1010 int pci_load_and_free_saved_state(struct pci_dev *dev, 1011 struct pci_saved_state **state); 1012 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1013 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1014 u16 cap); 1015 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1016 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1017 u16 cap, unsigned int size); 1018 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1019 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1020 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1021 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1022 void pci_pme_active(struct pci_dev *dev, bool enable); 1023 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1024 bool runtime, bool enable); 1025 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1026 int pci_prepare_to_sleep(struct pci_dev *dev); 1027 int pci_back_from_sleep(struct pci_dev *dev); 1028 bool pci_dev_run_wake(struct pci_dev *dev); 1029 bool pci_check_pme_status(struct pci_dev *dev); 1030 void pci_pme_wakeup_bus(struct pci_bus *bus); 1031 1032 static inline void pci_ignore_hotplug(struct pci_dev *dev) 1033 { 1034 dev->ignore_hotplug = 1; 1035 } 1036 1037 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1038 bool enable) 1039 { 1040 return __pci_enable_wake(dev, state, false, enable); 1041 } 1042 1043 /* PCI Virtual Channel */ 1044 int pci_save_vc_state(struct pci_dev *dev); 1045 void pci_restore_vc_state(struct pci_dev *dev); 1046 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1047 1048 /* For use by arch with custom probe code */ 1049 void set_pcie_port_type(struct pci_dev *pdev); 1050 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1051 1052 /* Functions for PCI Hotplug drivers to use */ 1053 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1054 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1055 unsigned int pci_rescan_bus(struct pci_bus *bus); 1056 void pci_lock_rescan_remove(void); 1057 void pci_unlock_rescan_remove(void); 1058 1059 /* Vital product data routines */ 1060 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1061 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1062 1063 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1064 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1065 void pci_bus_assign_resources(const struct pci_bus *bus); 1066 void pci_bus_size_bridges(struct pci_bus *bus); 1067 int pci_claim_resource(struct pci_dev *, int); 1068 void pci_assign_unassigned_resources(void); 1069 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1070 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1071 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1072 void pdev_enable_device(struct pci_dev *); 1073 int pci_enable_resources(struct pci_dev *, int mask); 1074 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1075 int (*)(const struct pci_dev *, u8, u8)); 1076 #define HAVE_PCI_REQ_REGIONS 2 1077 int __must_check pci_request_regions(struct pci_dev *, const char *); 1078 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1079 void pci_release_regions(struct pci_dev *); 1080 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1081 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1082 void pci_release_region(struct pci_dev *, int); 1083 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1084 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1085 void pci_release_selected_regions(struct pci_dev *, int); 1086 1087 /* drivers/pci/bus.c */ 1088 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1089 void pci_bus_put(struct pci_bus *bus); 1090 void pci_add_resource(struct list_head *resources, struct resource *res); 1091 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1092 resource_size_t offset); 1093 void pci_free_resource_list(struct list_head *resources); 1094 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1095 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1096 void pci_bus_remove_resources(struct pci_bus *bus); 1097 1098 #define pci_bus_for_each_resource(bus, res, i) \ 1099 for (i = 0; \ 1100 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1101 i++) 1102 1103 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1104 struct resource *res, resource_size_t size, 1105 resource_size_t align, resource_size_t min, 1106 unsigned long type_mask, 1107 resource_size_t (*alignf)(void *, 1108 const struct resource *, 1109 resource_size_t, 1110 resource_size_t), 1111 void *alignf_data); 1112 1113 1114 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1115 1116 static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1117 { 1118 struct pci_bus_region region; 1119 1120 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1121 return region.start; 1122 } 1123 1124 /* Proper probing supporting hot-pluggable devices */ 1125 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1126 const char *mod_name); 1127 1128 /* 1129 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1130 */ 1131 #define pci_register_driver(driver) \ 1132 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1133 1134 void pci_unregister_driver(struct pci_driver *dev); 1135 1136 /** 1137 * module_pci_driver() - Helper macro for registering a PCI driver 1138 * @__pci_driver: pci_driver struct 1139 * 1140 * Helper macro for PCI drivers which do not do anything special in module 1141 * init/exit. This eliminates a lot of boilerplate. Each module may only 1142 * use this macro once, and calling it replaces module_init() and module_exit() 1143 */ 1144 #define module_pci_driver(__pci_driver) \ 1145 module_driver(__pci_driver, pci_register_driver, \ 1146 pci_unregister_driver) 1147 1148 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1149 int pci_add_dynid(struct pci_driver *drv, 1150 unsigned int vendor, unsigned int device, 1151 unsigned int subvendor, unsigned int subdevice, 1152 unsigned int class, unsigned int class_mask, 1153 unsigned long driver_data); 1154 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1155 struct pci_dev *dev); 1156 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1157 int pass); 1158 1159 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1160 void *userdata); 1161 int pci_cfg_space_size(struct pci_dev *dev); 1162 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1163 void pci_setup_bridge(struct pci_bus *bus); 1164 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1165 unsigned long type); 1166 1167 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1168 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1169 1170 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1171 unsigned int command_bits, u32 flags); 1172 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1173 1174 #include <linux/pci-dma.h> 1175 #include <linux/dmapool.h> 1176 1177 #define pci_pool dma_pool 1178 #define pci_pool_create(name, pdev, size, align, allocation) \ 1179 dma_pool_create(name, &pdev->dev, size, align, allocation) 1180 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1181 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1182 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1183 1184 enum pci_dma_burst_strategy { 1185 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, 1186 strategy_parameter is N/A */ 1187 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter 1188 byte boundaries */ 1189 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of 1190 strategy_parameter byte boundaries */ 1191 }; 1192 1193 struct msix_entry { 1194 u32 vector; /* kernel uses to write allocated vector */ 1195 u16 entry; /* driver uses to specify entry, OS writes */ 1196 }; 1197 1198 1199 #ifdef CONFIG_PCI_MSI 1200 int pci_msi_vec_count(struct pci_dev *dev); 1201 void pci_msi_shutdown(struct pci_dev *dev); 1202 void pci_disable_msi(struct pci_dev *dev); 1203 int pci_msix_vec_count(struct pci_dev *dev); 1204 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1205 void pci_msix_shutdown(struct pci_dev *dev); 1206 void pci_disable_msix(struct pci_dev *dev); 1207 void pci_restore_msi_state(struct pci_dev *dev); 1208 int pci_msi_enabled(void); 1209 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1210 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1211 { 1212 int rc = pci_enable_msi_range(dev, nvec, nvec); 1213 if (rc < 0) 1214 return rc; 1215 return 0; 1216 } 1217 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1218 int minvec, int maxvec); 1219 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1220 struct msix_entry *entries, int nvec) 1221 { 1222 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1223 if (rc < 0) 1224 return rc; 1225 return 0; 1226 } 1227 #else 1228 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1229 static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1230 static inline void pci_disable_msi(struct pci_dev *dev) { } 1231 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1232 static inline int pci_enable_msix(struct pci_dev *dev, 1233 struct msix_entry *entries, int nvec) 1234 { return -ENOSYS; } 1235 static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1236 static inline void pci_disable_msix(struct pci_dev *dev) { } 1237 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1238 static inline int pci_msi_enabled(void) { return 0; } 1239 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1240 int maxvec) 1241 { return -ENOSYS; } 1242 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1243 { return -ENOSYS; } 1244 static inline int pci_enable_msix_range(struct pci_dev *dev, 1245 struct msix_entry *entries, int minvec, int maxvec) 1246 { return -ENOSYS; } 1247 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1248 struct msix_entry *entries, int nvec) 1249 { return -ENOSYS; } 1250 #endif 1251 1252 #ifdef CONFIG_PCIEPORTBUS 1253 extern bool pcie_ports_disabled; 1254 extern bool pcie_ports_auto; 1255 #else 1256 #define pcie_ports_disabled true 1257 #define pcie_ports_auto false 1258 #endif 1259 1260 #ifdef CONFIG_PCIEASPM 1261 bool pcie_aspm_support_enabled(void); 1262 #else 1263 static inline bool pcie_aspm_support_enabled(void) { return false; } 1264 #endif 1265 1266 #ifdef CONFIG_PCIEAER 1267 void pci_no_aer(void); 1268 bool pci_aer_available(void); 1269 #else 1270 static inline void pci_no_aer(void) { } 1271 static inline bool pci_aer_available(void) { return false; } 1272 #endif 1273 1274 #ifdef CONFIG_PCIE_ECRC 1275 void pcie_set_ecrc_checking(struct pci_dev *dev); 1276 void pcie_ecrc_get_policy(char *str); 1277 #else 1278 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1279 static inline void pcie_ecrc_get_policy(char *str) { } 1280 #endif 1281 1282 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) 1283 1284 #ifdef CONFIG_HT_IRQ 1285 /* The functions a driver should call */ 1286 int ht_create_irq(struct pci_dev *dev, int idx); 1287 void ht_destroy_irq(unsigned int irq); 1288 #endif /* CONFIG_HT_IRQ */ 1289 1290 void pci_cfg_access_lock(struct pci_dev *dev); 1291 bool pci_cfg_access_trylock(struct pci_dev *dev); 1292 void pci_cfg_access_unlock(struct pci_dev *dev); 1293 1294 /* 1295 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1296 * a PCI domain is defined to be a set of PCI buses which share 1297 * configuration space. 1298 */ 1299 #ifdef CONFIG_PCI_DOMAINS 1300 extern int pci_domains_supported; 1301 int pci_get_new_domain_nr(void); 1302 #else 1303 enum { pci_domains_supported = 0 }; 1304 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1305 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1306 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1307 #endif /* CONFIG_PCI_DOMAINS */ 1308 1309 /* 1310 * Generic implementation for PCI domain support. If your 1311 * architecture does not need custom management of PCI 1312 * domains then this implementation will be used 1313 */ 1314 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1315 static inline int pci_domain_nr(struct pci_bus *bus) 1316 { 1317 return bus->domain_nr; 1318 } 1319 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); 1320 #else 1321 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, 1322 struct device *parent) 1323 { 1324 } 1325 #endif 1326 1327 /* some architectures require additional setup to direct VGA traffic */ 1328 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1329 unsigned int command_bits, u32 flags); 1330 void pci_register_set_vga_state(arch_set_vga_state_t func); 1331 1332 #else /* CONFIG_PCI is not enabled */ 1333 1334 /* 1335 * If the system does not have PCI, clearly these return errors. Define 1336 * these as simple inline functions to avoid hair in drivers. 1337 */ 1338 1339 #define _PCI_NOP(o, s, t) \ 1340 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1341 int where, t val) \ 1342 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1343 1344 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1345 _PCI_NOP(o, word, u16 x) \ 1346 _PCI_NOP(o, dword, u32 x) 1347 _PCI_NOP_ALL(read, *) 1348 _PCI_NOP_ALL(write,) 1349 1350 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1351 unsigned int device, 1352 struct pci_dev *from) 1353 { return NULL; } 1354 1355 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1356 unsigned int device, 1357 unsigned int ss_vendor, 1358 unsigned int ss_device, 1359 struct pci_dev *from) 1360 { return NULL; } 1361 1362 static inline struct pci_dev *pci_get_class(unsigned int class, 1363 struct pci_dev *from) 1364 { return NULL; } 1365 1366 #define pci_dev_present(ids) (0) 1367 #define no_pci_devices() (1) 1368 #define pci_dev_put(dev) do { } while (0) 1369 1370 static inline void pci_set_master(struct pci_dev *dev) { } 1371 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1372 static inline void pci_disable_device(struct pci_dev *dev) { } 1373 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1374 { return -EIO; } 1375 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1376 { return -EIO; } 1377 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1378 unsigned int size) 1379 { return -EIO; } 1380 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1381 unsigned long mask) 1382 { return -EIO; } 1383 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1384 { return -EBUSY; } 1385 static inline int __pci_register_driver(struct pci_driver *drv, 1386 struct module *owner) 1387 { return 0; } 1388 static inline int pci_register_driver(struct pci_driver *drv) 1389 { return 0; } 1390 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1391 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1392 { return 0; } 1393 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1394 int cap) 1395 { return 0; } 1396 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1397 { return 0; } 1398 1399 /* Power management related routines */ 1400 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1401 static inline void pci_restore_state(struct pci_dev *dev) { } 1402 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1403 { return 0; } 1404 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1405 { return 0; } 1406 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1407 pm_message_t state) 1408 { return PCI_D0; } 1409 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1410 int enable) 1411 { return 0; } 1412 1413 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1414 { return -EIO; } 1415 static inline void pci_release_regions(struct pci_dev *dev) { } 1416 1417 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 1418 1419 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1420 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1421 { return 0; } 1422 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1423 1424 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1425 { return NULL; } 1426 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1427 unsigned int devfn) 1428 { return NULL; } 1429 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1430 unsigned int devfn) 1431 { return NULL; } 1432 1433 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1434 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1435 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1436 1437 #define dev_is_pci(d) (false) 1438 #define dev_is_pf(d) (false) 1439 #define dev_num_vf(d) (0) 1440 #endif /* CONFIG_PCI */ 1441 1442 /* Include architecture-dependent settings and functions */ 1443 1444 #include <asm/pci.h> 1445 1446 /* these helpers provide future and backwards compatibility 1447 * for accessing popular PCI BAR info */ 1448 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1449 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1450 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1451 #define pci_resource_len(dev,bar) \ 1452 ((pci_resource_start((dev), (bar)) == 0 && \ 1453 pci_resource_end((dev), (bar)) == \ 1454 pci_resource_start((dev), (bar))) ? 0 : \ 1455 \ 1456 (pci_resource_end((dev), (bar)) - \ 1457 pci_resource_start((dev), (bar)) + 1)) 1458 1459 /* Similar to the helpers above, these manipulate per-pci_dev 1460 * driver-specific data. They are really just a wrapper around 1461 * the generic device structure functions of these calls. 1462 */ 1463 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1464 { 1465 return dev_get_drvdata(&pdev->dev); 1466 } 1467 1468 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1469 { 1470 dev_set_drvdata(&pdev->dev, data); 1471 } 1472 1473 /* If you want to know what to call your pci_dev, ask this function. 1474 * Again, it's a wrapper around the generic device. 1475 */ 1476 static inline const char *pci_name(const struct pci_dev *pdev) 1477 { 1478 return dev_name(&pdev->dev); 1479 } 1480 1481 1482 /* Some archs don't want to expose struct resource to userland as-is 1483 * in sysfs and /proc 1484 */ 1485 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1486 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1487 const struct resource *rsrc, resource_size_t *start, 1488 resource_size_t *end) 1489 { 1490 *start = rsrc->start; 1491 *end = rsrc->end; 1492 } 1493 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1494 1495 1496 /* 1497 * The world is not perfect and supplies us with broken PCI devices. 1498 * For at least a part of these bugs we need a work-around, so both 1499 * generic (drivers/pci/quirks.c) and per-architecture code can define 1500 * fixup hooks to be called for particular buggy devices. 1501 */ 1502 1503 struct pci_fixup { 1504 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1505 u16 device; /* You can use PCI_ANY_ID here of course */ 1506 u32 class; /* You can use PCI_ANY_ID here too */ 1507 unsigned int class_shift; /* should be 0, 8, 16 */ 1508 void (*hook)(struct pci_dev *dev); 1509 }; 1510 1511 enum pci_fixup_pass { 1512 pci_fixup_early, /* Before probing BARs */ 1513 pci_fixup_header, /* After reading configuration header */ 1514 pci_fixup_final, /* Final phase of device fixups */ 1515 pci_fixup_enable, /* pci_enable_device() time */ 1516 pci_fixup_resume, /* pci_device_resume() */ 1517 pci_fixup_suspend, /* pci_device_suspend() */ 1518 pci_fixup_resume_early, /* pci_device_resume_early() */ 1519 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1520 }; 1521 1522 /* Anonymous variables would be nice... */ 1523 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1524 class_shift, hook) \ 1525 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1526 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1527 = { vendor, device, class, class_shift, hook }; 1528 1529 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1530 class_shift, hook) \ 1531 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1532 hook, vendor, device, class, class_shift, hook) 1533 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1534 class_shift, hook) \ 1535 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1536 hook, vendor, device, class, class_shift, hook) 1537 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1538 class_shift, hook) \ 1539 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1540 hook, vendor, device, class, class_shift, hook) 1541 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1542 class_shift, hook) \ 1543 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1544 hook, vendor, device, class, class_shift, hook) 1545 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1546 class_shift, hook) \ 1547 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1548 resume##hook, vendor, device, class, \ 1549 class_shift, hook) 1550 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1551 class_shift, hook) \ 1552 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1553 resume_early##hook, vendor, device, \ 1554 class, class_shift, hook) 1555 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1556 class_shift, hook) \ 1557 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1558 suspend##hook, vendor, device, class, \ 1559 class_shift, hook) 1560 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1561 class_shift, hook) \ 1562 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1563 suspend_late##hook, vendor, device, \ 1564 class, class_shift, hook) 1565 1566 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1567 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1568 hook, vendor, device, PCI_ANY_ID, 0, hook) 1569 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1570 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1571 hook, vendor, device, PCI_ANY_ID, 0, hook) 1572 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1573 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1574 hook, vendor, device, PCI_ANY_ID, 0, hook) 1575 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1576 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1577 hook, vendor, device, PCI_ANY_ID, 0, hook) 1578 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1579 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1580 resume##hook, vendor, device, \ 1581 PCI_ANY_ID, 0, hook) 1582 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1583 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1584 resume_early##hook, vendor, device, \ 1585 PCI_ANY_ID, 0, hook) 1586 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1587 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1588 suspend##hook, vendor, device, \ 1589 PCI_ANY_ID, 0, hook) 1590 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1591 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1592 suspend_late##hook, vendor, device, \ 1593 PCI_ANY_ID, 0, hook) 1594 1595 #ifdef CONFIG_PCI_QUIRKS 1596 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1597 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1598 void pci_dev_specific_enable_acs(struct pci_dev *dev); 1599 #else 1600 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1601 struct pci_dev *dev) { } 1602 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1603 u16 acs_flags) 1604 { 1605 return -ENOTTY; 1606 } 1607 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } 1608 #endif 1609 1610 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1611 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1612 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1613 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1614 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1615 const char *name); 1616 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1617 1618 extern int pci_pci_problems; 1619 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1620 #define PCIPCI_TRITON 2 1621 #define PCIPCI_NATOMA 4 1622 #define PCIPCI_VIAETBF 8 1623 #define PCIPCI_VSFX 16 1624 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1625 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1626 1627 extern unsigned long pci_cardbus_io_size; 1628 extern unsigned long pci_cardbus_mem_size; 1629 extern u8 pci_dfl_cache_line_size; 1630 extern u8 pci_cache_line_size; 1631 1632 extern unsigned long pci_hotplug_io_size; 1633 extern unsigned long pci_hotplug_mem_size; 1634 1635 /* Architecture-specific versions may override these (weak) */ 1636 void pcibios_disable_device(struct pci_dev *dev); 1637 void pcibios_set_master(struct pci_dev *dev); 1638 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1639 enum pcie_reset_state state); 1640 int pcibios_add_device(struct pci_dev *dev); 1641 void pcibios_release_device(struct pci_dev *dev); 1642 void pcibios_penalize_isa_irq(int irq, int active); 1643 1644 #ifdef CONFIG_HIBERNATE_CALLBACKS 1645 extern struct dev_pm_ops pcibios_pm_ops; 1646 #endif 1647 1648 #ifdef CONFIG_PCI_MMCONFIG 1649 void __init pci_mmcfg_early_init(void); 1650 void __init pci_mmcfg_late_init(void); 1651 #else 1652 static inline void pci_mmcfg_early_init(void) { } 1653 static inline void pci_mmcfg_late_init(void) { } 1654 #endif 1655 1656 int pci_ext_cfg_avail(void); 1657 1658 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1659 1660 #ifdef CONFIG_PCI_IOV 1661 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1662 void pci_disable_sriov(struct pci_dev *dev); 1663 int pci_num_vf(struct pci_dev *dev); 1664 int pci_vfs_assigned(struct pci_dev *dev); 1665 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1666 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1667 #else 1668 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1669 { return -ENODEV; } 1670 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1671 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1672 static inline int pci_vfs_assigned(struct pci_dev *dev) 1673 { return 0; } 1674 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1675 { return 0; } 1676 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1677 { return 0; } 1678 #endif 1679 1680 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1681 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1682 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1683 #endif 1684 1685 /** 1686 * pci_pcie_cap - get the saved PCIe capability offset 1687 * @dev: PCI device 1688 * 1689 * PCIe capability offset is calculated at PCI device initialization 1690 * time and saved in the data structure. This function returns saved 1691 * PCIe capability offset. Using this instead of pci_find_capability() 1692 * reduces unnecessary search in the PCI configuration space. If you 1693 * need to calculate PCIe capability offset from raw device for some 1694 * reasons, please use pci_find_capability() instead. 1695 */ 1696 static inline int pci_pcie_cap(struct pci_dev *dev) 1697 { 1698 return dev->pcie_cap; 1699 } 1700 1701 /** 1702 * pci_is_pcie - check if the PCI device is PCI Express capable 1703 * @dev: PCI device 1704 * 1705 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1706 */ 1707 static inline bool pci_is_pcie(struct pci_dev *dev) 1708 { 1709 return pci_pcie_cap(dev); 1710 } 1711 1712 /** 1713 * pcie_caps_reg - get the PCIe Capabilities Register 1714 * @dev: PCI device 1715 */ 1716 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1717 { 1718 return dev->pcie_flags_reg; 1719 } 1720 1721 /** 1722 * pci_pcie_type - get the PCIe device/port type 1723 * @dev: PCI device 1724 */ 1725 static inline int pci_pcie_type(const struct pci_dev *dev) 1726 { 1727 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1728 } 1729 1730 void pci_request_acs(void); 1731 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1732 bool pci_acs_path_enabled(struct pci_dev *start, 1733 struct pci_dev *end, u16 acs_flags); 1734 1735 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1736 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1737 1738 /* Large Resource Data Type Tag Item Names */ 1739 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1740 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1741 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1742 1743 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1744 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1745 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1746 1747 /* Small Resource Data Type Tag Item Names */ 1748 #define PCI_VPD_STIN_END 0x78 /* End */ 1749 1750 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1751 1752 #define PCI_VPD_SRDT_TIN_MASK 0x78 1753 #define PCI_VPD_SRDT_LEN_MASK 0x07 1754 1755 #define PCI_VPD_LRDT_TAG_SIZE 3 1756 #define PCI_VPD_SRDT_TAG_SIZE 1 1757 1758 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1759 1760 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1761 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1762 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1763 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1764 1765 /** 1766 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1767 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1768 * 1769 * Returns the extracted Large Resource Data Type length. 1770 */ 1771 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1772 { 1773 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1774 } 1775 1776 /** 1777 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1778 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1779 * 1780 * Returns the extracted Small Resource Data Type length. 1781 */ 1782 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1783 { 1784 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1785 } 1786 1787 /** 1788 * pci_vpd_info_field_size - Extracts the information field length 1789 * @lrdt: Pointer to the beginning of an information field header 1790 * 1791 * Returns the extracted information field length. 1792 */ 1793 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1794 { 1795 return info_field[2]; 1796 } 1797 1798 /** 1799 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1800 * @buf: Pointer to buffered vpd data 1801 * @off: The offset into the buffer at which to begin the search 1802 * @len: The length of the vpd buffer 1803 * @rdt: The Resource Data Type to search for 1804 * 1805 * Returns the index where the Resource Data Type was found or 1806 * -ENOENT otherwise. 1807 */ 1808 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1809 1810 /** 1811 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1812 * @buf: Pointer to buffered vpd data 1813 * @off: The offset into the buffer at which to begin the search 1814 * @len: The length of the buffer area, relative to off, in which to search 1815 * @kw: The keyword to search for 1816 * 1817 * Returns the index where the information field keyword was found or 1818 * -ENOENT otherwise. 1819 */ 1820 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1821 unsigned int len, const char *kw); 1822 1823 /* PCI <-> OF binding helpers */ 1824 #ifdef CONFIG_OF 1825 struct device_node; 1826 void pci_set_of_node(struct pci_dev *dev); 1827 void pci_release_of_node(struct pci_dev *dev); 1828 void pci_set_bus_of_node(struct pci_bus *bus); 1829 void pci_release_bus_of_node(struct pci_bus *bus); 1830 1831 /* Arch may override this (weak) */ 1832 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1833 1834 static inline struct device_node * 1835 pci_device_to_OF_node(const struct pci_dev *pdev) 1836 { 1837 return pdev ? pdev->dev.of_node : NULL; 1838 } 1839 1840 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1841 { 1842 return bus ? bus->dev.of_node : NULL; 1843 } 1844 1845 #else /* CONFIG_OF */ 1846 static inline void pci_set_of_node(struct pci_dev *dev) { } 1847 static inline void pci_release_of_node(struct pci_dev *dev) { } 1848 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1849 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1850 #endif /* CONFIG_OF */ 1851 1852 #ifdef CONFIG_EEH 1853 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1854 { 1855 return pdev->dev.archdata.edev; 1856 } 1857 #endif 1858 1859 int pci_for_each_dma_alias(struct pci_dev *pdev, 1860 int (*fn)(struct pci_dev *pdev, 1861 u16 alias, void *data), void *data); 1862 1863 /* helper functions for operation of device flag */ 1864 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 1865 { 1866 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 1867 } 1868 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 1869 { 1870 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 1871 } 1872 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 1873 { 1874 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 1875 } 1876 #endif /* LINUX_PCI_H */ 1877