1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <linux/resource_ext.h> 33 #include <uapi/linux/pci.h> 34 35 #include <linux/pci_ids.h> 36 37 /* 38 * The PCI interface treats multi-function devices as independent 39 * devices. The slot/function address of each device is encoded 40 * in a single byte as follows: 41 * 42 * 7:3 = slot 43 * 2:0 = function 44 * 45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 46 * In the interest of not exposing interfaces to user-space unnecessarily, 47 * the following kernel-only defines are being added here. 48 */ 49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 52 53 /* pci_slot represents a physical slot */ 54 struct pci_slot { 55 struct pci_bus *bus; /* The bus this slot is on */ 56 struct list_head list; /* node in list of slots on this bus */ 57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 59 struct kobject kobj; 60 }; 61 62 static inline const char *pci_slot_name(const struct pci_slot *slot) 63 { 64 return kobject_name(&slot->kobj); 65 } 66 67 /* File state for mmap()s on /proc/bus/pci/X/Y */ 68 enum pci_mmap_state { 69 pci_mmap_io, 70 pci_mmap_mem 71 }; 72 73 /* 74 * For PCI devices, the region numbers are assigned this way: 75 */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* device specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 /* 105 * pci_power_t values must match the bits in the Capabilities PME_Support 106 * and Control/Status PowerState fields in the Power Management capability. 107 */ 108 typedef int __bitwise pci_power_t; 109 110 #define PCI_D0 ((pci_power_t __force) 0) 111 #define PCI_D1 ((pci_power_t __force) 1) 112 #define PCI_D2 ((pci_power_t __force) 2) 113 #define PCI_D3hot ((pci_power_t __force) 3) 114 #define PCI_D3cold ((pci_power_t __force) 4) 115 #define PCI_UNKNOWN ((pci_power_t __force) 5) 116 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 117 118 /* Remember to update this when the list above changes! */ 119 extern const char *pci_power_names[]; 120 121 static inline const char *pci_power_name(pci_power_t state) 122 { 123 return pci_power_names[1 + (__force int) state]; 124 } 125 126 #define PCI_PM_D2_DELAY 200 127 #define PCI_PM_D3_WAIT 10 128 #define PCI_PM_D3COLD_WAIT 100 129 #define PCI_PM_BUS_WAIT 50 130 131 /** The pci_channel state describes connectivity between the CPU and 132 * the pci device. If some PCI bus between here and the pci device 133 * has crashed or locked up, this info is reflected here. 134 */ 135 typedef unsigned int __bitwise pci_channel_state_t; 136 137 enum pci_channel_state { 138 /* I/O channel is in normal state */ 139 pci_channel_io_normal = (__force pci_channel_state_t) 1, 140 141 /* I/O to channel is blocked */ 142 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 143 144 /* PCI card is dead */ 145 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 146 }; 147 148 typedef unsigned int __bitwise pcie_reset_state_t; 149 150 enum pcie_reset_state { 151 /* Reset is NOT asserted (Use to deassert reset) */ 152 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 153 154 /* Use #PERST to reset PCIe device */ 155 pcie_warm_reset = (__force pcie_reset_state_t) 2, 156 157 /* Use PCIe Hot Reset to reset device */ 158 pcie_hot_reset = (__force pcie_reset_state_t) 3 159 }; 160 161 typedef unsigned short __bitwise pci_dev_flags_t; 162 enum pci_dev_flags { 163 /* INTX_DISABLE in PCI_COMMAND register disables MSI 164 * generation too. 165 */ 166 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 167 /* Device configuration is irrevocably lost if disabled into D3 */ 168 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 169 /* Provide indication device is assigned by a Virtual Machine Manager */ 170 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 171 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 172 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 173 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 174 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 175 /* Do not use bus resets for device */ 176 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 177 /* Do not use PM reset even if device advertises NoSoftRst- */ 178 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 179 /* Get VPD from function 0 VPD */ 180 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 181 }; 182 183 enum pci_irq_reroute_variant { 184 INTEL_IRQ_REROUTE_VARIANT = 1, 185 MAX_IRQ_REROUTE_VARIANTS = 3 186 }; 187 188 typedef unsigned short __bitwise pci_bus_flags_t; 189 enum pci_bus_flags { 190 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 191 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 192 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 193 }; 194 195 /* These values come from the PCI Express Spec */ 196 enum pcie_link_width { 197 PCIE_LNK_WIDTH_RESRV = 0x00, 198 PCIE_LNK_X1 = 0x01, 199 PCIE_LNK_X2 = 0x02, 200 PCIE_LNK_X4 = 0x04, 201 PCIE_LNK_X8 = 0x08, 202 PCIE_LNK_X12 = 0x0C, 203 PCIE_LNK_X16 = 0x10, 204 PCIE_LNK_X32 = 0x20, 205 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 206 }; 207 208 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 209 enum pci_bus_speed { 210 PCI_SPEED_33MHz = 0x00, 211 PCI_SPEED_66MHz = 0x01, 212 PCI_SPEED_66MHz_PCIX = 0x02, 213 PCI_SPEED_100MHz_PCIX = 0x03, 214 PCI_SPEED_133MHz_PCIX = 0x04, 215 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 216 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 217 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 218 PCI_SPEED_66MHz_PCIX_266 = 0x09, 219 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 220 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 221 AGP_UNKNOWN = 0x0c, 222 AGP_1X = 0x0d, 223 AGP_2X = 0x0e, 224 AGP_4X = 0x0f, 225 AGP_8X = 0x10, 226 PCI_SPEED_66MHz_PCIX_533 = 0x11, 227 PCI_SPEED_100MHz_PCIX_533 = 0x12, 228 PCI_SPEED_133MHz_PCIX_533 = 0x13, 229 PCIE_SPEED_2_5GT = 0x14, 230 PCIE_SPEED_5_0GT = 0x15, 231 PCIE_SPEED_8_0GT = 0x16, 232 PCI_SPEED_UNKNOWN = 0xff, 233 }; 234 235 struct pci_cap_saved_data { 236 u16 cap_nr; 237 bool cap_extended; 238 unsigned int size; 239 u32 data[0]; 240 }; 241 242 struct pci_cap_saved_state { 243 struct hlist_node next; 244 struct pci_cap_saved_data cap; 245 }; 246 247 struct irq_affinity; 248 struct pcie_link_state; 249 struct pci_vpd; 250 struct pci_sriov; 251 struct pci_ats; 252 253 /* 254 * The pci_dev structure is used to describe PCI devices. 255 */ 256 struct pci_dev { 257 struct list_head bus_list; /* node in per-bus list */ 258 struct pci_bus *bus; /* bus this device is on */ 259 struct pci_bus *subordinate; /* bus this device bridges to */ 260 261 void *sysdata; /* hook for sys-specific extension */ 262 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 263 struct pci_slot *slot; /* Physical slot this device is in */ 264 265 unsigned int devfn; /* encoded device & function index */ 266 unsigned short vendor; 267 unsigned short device; 268 unsigned short subsystem_vendor; 269 unsigned short subsystem_device; 270 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 271 u8 revision; /* PCI revision, low byte of class word */ 272 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 273 #ifdef CONFIG_PCIEAER 274 u16 aer_cap; /* AER capability offset */ 275 #endif 276 u8 pcie_cap; /* PCIe capability offset */ 277 u8 msi_cap; /* MSI capability offset */ 278 u8 msix_cap; /* MSI-X capability offset */ 279 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 280 u8 rom_base_reg; /* which config register controls the ROM */ 281 u8 pin; /* which interrupt pin this device uses */ 282 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 283 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */ 284 285 struct pci_driver *driver; /* which driver has allocated this device */ 286 u64 dma_mask; /* Mask of the bits of bus address this 287 device implements. Normally this is 288 0xffffffff. You only need to change 289 this if your device has broken DMA 290 or supports 64-bit transfers. */ 291 292 struct device_dma_parameters dma_parms; 293 294 pci_power_t current_state; /* Current operating state. In ACPI-speak, 295 this is D0-D3, D0 being fully functional, 296 and D3 being off. */ 297 u8 pm_cap; /* PM capability offset */ 298 unsigned int pme_support:5; /* Bitmask of states from which PME# 299 can be generated */ 300 unsigned int pme_interrupt:1; 301 unsigned int pme_poll:1; /* Poll device's PME status bit */ 302 unsigned int d1_support:1; /* Low power state D1 is supported */ 303 unsigned int d2_support:1; /* Low power state D2 is supported */ 304 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 305 unsigned int no_d3cold:1; /* D3cold is forbidden */ 306 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 307 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 308 unsigned int mmio_always_on:1; /* disallow turning off io/mem 309 decoding during bar sizing */ 310 unsigned int wakeup_prepared:1; 311 unsigned int runtime_d3cold:1; /* whether go through runtime 312 D3cold, not set for devices 313 powered on/off by the 314 corresponding bridge */ 315 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 316 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 317 controlled exclusively by 318 user sysfs */ 319 unsigned int d3_delay; /* D3->D0 transition time in ms */ 320 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 321 322 #ifdef CONFIG_PCIEASPM 323 struct pcie_link_state *link_state; /* ASPM link state */ 324 #endif 325 326 pci_channel_state_t error_state; /* current connectivity state */ 327 struct device dev; /* Generic device interface */ 328 329 int cfg_size; /* Size of configuration space */ 330 331 /* 332 * Instead of touching interrupt line and base address registers 333 * directly, use the values stored here. They might be different! 334 */ 335 unsigned int irq; 336 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 337 338 bool match_driver; /* Skip attaching driver */ 339 /* These fields are used by common fixups */ 340 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 341 unsigned int multifunction:1;/* Part of multi-function device */ 342 /* keep track of device state */ 343 unsigned int is_added:1; 344 unsigned int is_busmaster:1; /* device is busmaster */ 345 unsigned int no_msi:1; /* device may not use msi */ 346 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 347 unsigned int block_cfg_access:1; /* config space access is blocked */ 348 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 349 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 350 unsigned int msi_enabled:1; 351 unsigned int msix_enabled:1; 352 unsigned int ari_enabled:1; /* ARI forwarding */ 353 unsigned int ats_enabled:1; /* Address Translation Service */ 354 unsigned int is_managed:1; 355 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 356 unsigned int state_saved:1; 357 unsigned int is_physfn:1; 358 unsigned int is_virtfn:1; 359 unsigned int reset_fn:1; 360 unsigned int is_hotplug_bridge:1; 361 unsigned int __aer_firmware_first_valid:1; 362 unsigned int __aer_firmware_first:1; 363 unsigned int broken_intx_masking:1; 364 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 365 unsigned int irq_managed:1; 366 unsigned int has_secondary_link:1; 367 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 368 pci_dev_flags_t dev_flags; 369 atomic_t enable_cnt; /* pci_enable_device has been called */ 370 371 u32 saved_config_space[16]; /* config space saved at suspend time */ 372 struct hlist_head saved_cap_space; 373 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 374 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 375 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 376 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 377 378 #ifdef CONFIG_PCIE_PTM 379 unsigned int ptm_root:1; 380 unsigned int ptm_enabled:1; 381 u8 ptm_granularity; 382 #endif 383 #ifdef CONFIG_PCI_MSI 384 const struct attribute_group **msi_irq_groups; 385 #endif 386 struct pci_vpd *vpd; 387 #ifdef CONFIG_PCI_ATS 388 union { 389 struct pci_sriov *sriov; /* SR-IOV capability related */ 390 struct pci_dev *physfn; /* the PF this VF is associated with */ 391 }; 392 u16 ats_cap; /* ATS Capability offset */ 393 u8 ats_stu; /* ATS Smallest Translation Unit */ 394 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 395 #endif 396 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 397 size_t romlen; /* Length of ROM if it's not from the BAR */ 398 char *driver_override; /* Driver name to force a match */ 399 }; 400 401 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 402 { 403 #ifdef CONFIG_PCI_IOV 404 if (dev->is_virtfn) 405 dev = dev->physfn; 406 #endif 407 return dev; 408 } 409 410 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 411 412 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 413 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 414 415 static inline int pci_channel_offline(struct pci_dev *pdev) 416 { 417 return (pdev->error_state != pci_channel_io_normal); 418 } 419 420 struct pci_host_bridge { 421 struct device dev; 422 struct pci_bus *bus; /* root bus */ 423 struct pci_ops *ops; 424 void *sysdata; 425 int busnr; 426 struct list_head windows; /* resource_entry */ 427 void (*release_fn)(struct pci_host_bridge *); 428 void *release_data; 429 struct msi_controller *msi; 430 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 431 /* Resource alignment requirements */ 432 resource_size_t (*align_resource)(struct pci_dev *dev, 433 const struct resource *res, 434 resource_size_t start, 435 resource_size_t size, 436 resource_size_t align); 437 unsigned long private[0] ____cacheline_aligned; 438 }; 439 440 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 441 442 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 443 { 444 return (void *)bridge->private; 445 } 446 447 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 448 { 449 return container_of(priv, struct pci_host_bridge, private); 450 } 451 452 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 453 int pci_register_host_bridge(struct pci_host_bridge *bridge); 454 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 455 456 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 457 void (*release_fn)(struct pci_host_bridge *), 458 void *release_data); 459 460 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 461 462 /* 463 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 464 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 465 * buses below host bridges or subtractive decode bridges) go in the list. 466 * Use pci_bus_for_each_resource() to iterate through all the resources. 467 */ 468 469 /* 470 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 471 * and there's no way to program the bridge with the details of the window. 472 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 473 * decode bit set, because they are explicit and can be programmed with _SRS. 474 */ 475 #define PCI_SUBTRACTIVE_DECODE 0x1 476 477 struct pci_bus_resource { 478 struct list_head list; 479 struct resource *res; 480 unsigned int flags; 481 }; 482 483 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 484 485 struct pci_bus { 486 struct list_head node; /* node in list of buses */ 487 struct pci_bus *parent; /* parent bus this bridge is on */ 488 struct list_head children; /* list of child buses */ 489 struct list_head devices; /* list of devices on this bus */ 490 struct pci_dev *self; /* bridge device as seen by parent */ 491 struct list_head slots; /* list of slots on this bus; 492 protected by pci_slot_mutex */ 493 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 494 struct list_head resources; /* address space routed to this bus */ 495 struct resource busn_res; /* bus numbers routed to this bus */ 496 497 struct pci_ops *ops; /* configuration access functions */ 498 struct msi_controller *msi; /* MSI controller */ 499 void *sysdata; /* hook for sys-specific extension */ 500 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 501 502 unsigned char number; /* bus number */ 503 unsigned char primary; /* number of primary bridge */ 504 unsigned char max_bus_speed; /* enum pci_bus_speed */ 505 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 506 #ifdef CONFIG_PCI_DOMAINS_GENERIC 507 int domain_nr; 508 #endif 509 510 char name[48]; 511 512 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 513 pci_bus_flags_t bus_flags; /* inherited by child buses */ 514 struct device *bridge; 515 struct device dev; 516 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 517 struct bin_attribute *legacy_mem; /* legacy mem */ 518 unsigned int is_added:1; 519 }; 520 521 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 522 523 /* 524 * Returns true if the PCI bus is root (behind host-PCI bridge), 525 * false otherwise 526 * 527 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 528 * This is incorrect because "virtual" buses added for SR-IOV (via 529 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 530 */ 531 static inline bool pci_is_root_bus(struct pci_bus *pbus) 532 { 533 return !(pbus->parent); 534 } 535 536 /** 537 * pci_is_bridge - check if the PCI device is a bridge 538 * @dev: PCI device 539 * 540 * Return true if the PCI device is bridge whether it has subordinate 541 * or not. 542 */ 543 static inline bool pci_is_bridge(struct pci_dev *dev) 544 { 545 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 546 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 547 } 548 549 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 550 { 551 dev = pci_physfn(dev); 552 if (pci_is_root_bus(dev->bus)) 553 return NULL; 554 555 return dev->bus->self; 556 } 557 558 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 559 void pci_put_host_bridge_device(struct device *dev); 560 561 #ifdef CONFIG_PCI_MSI 562 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 563 { 564 return pci_dev->msi_enabled || pci_dev->msix_enabled; 565 } 566 #else 567 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 568 #endif 569 570 /* 571 * Error values that may be returned by PCI functions. 572 */ 573 #define PCIBIOS_SUCCESSFUL 0x00 574 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 575 #define PCIBIOS_BAD_VENDOR_ID 0x83 576 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 577 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 578 #define PCIBIOS_SET_FAILED 0x88 579 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 580 581 /* 582 * Translate above to generic errno for passing back through non-PCI code. 583 */ 584 static inline int pcibios_err_to_errno(int err) 585 { 586 if (err <= PCIBIOS_SUCCESSFUL) 587 return err; /* Assume already errno */ 588 589 switch (err) { 590 case PCIBIOS_FUNC_NOT_SUPPORTED: 591 return -ENOENT; 592 case PCIBIOS_BAD_VENDOR_ID: 593 return -ENOTTY; 594 case PCIBIOS_DEVICE_NOT_FOUND: 595 return -ENODEV; 596 case PCIBIOS_BAD_REGISTER_NUMBER: 597 return -EFAULT; 598 case PCIBIOS_SET_FAILED: 599 return -EIO; 600 case PCIBIOS_BUFFER_TOO_SMALL: 601 return -ENOSPC; 602 } 603 604 return -ERANGE; 605 } 606 607 /* Low-level architecture-dependent routines */ 608 609 struct pci_ops { 610 int (*add_bus)(struct pci_bus *bus); 611 void (*remove_bus)(struct pci_bus *bus); 612 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 613 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 614 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 615 }; 616 617 /* 618 * ACPI needs to be able to access PCI config space before we've done a 619 * PCI bus scan and created pci_bus structures. 620 */ 621 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 622 int reg, int len, u32 *val); 623 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 624 int reg, int len, u32 val); 625 626 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 627 typedef u64 pci_bus_addr_t; 628 #else 629 typedef u32 pci_bus_addr_t; 630 #endif 631 632 struct pci_bus_region { 633 pci_bus_addr_t start; 634 pci_bus_addr_t end; 635 }; 636 637 struct pci_dynids { 638 spinlock_t lock; /* protects list, index */ 639 struct list_head list; /* for IDs added at runtime */ 640 }; 641 642 643 /* 644 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 645 * a set of callbacks in struct pci_error_handlers, that device driver 646 * will be notified of PCI bus errors, and will be driven to recovery 647 * when an error occurs. 648 */ 649 650 typedef unsigned int __bitwise pci_ers_result_t; 651 652 enum pci_ers_result { 653 /* no result/none/not supported in device driver */ 654 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 655 656 /* Device driver can recover without slot reset */ 657 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 658 659 /* Device driver wants slot to be reset. */ 660 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 661 662 /* Device has completely failed, is unrecoverable */ 663 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 664 665 /* Device driver is fully recovered and operational */ 666 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 667 668 /* No AER capabilities registered for the driver */ 669 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 670 }; 671 672 /* PCI bus error event callbacks */ 673 struct pci_error_handlers { 674 /* PCI bus error detected on this device */ 675 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 676 enum pci_channel_state error); 677 678 /* MMIO has been re-enabled, but not DMA */ 679 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 680 681 /* PCI Express link has been reset */ 682 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 683 684 /* PCI slot has been reset */ 685 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 686 687 /* PCI function reset prepare or completed */ 688 void (*reset_notify)(struct pci_dev *dev, bool prepare); 689 690 /* Device driver may resume normal operations */ 691 void (*resume)(struct pci_dev *dev); 692 }; 693 694 695 struct module; 696 struct pci_driver { 697 struct list_head node; 698 const char *name; 699 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 700 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 701 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 702 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 703 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 704 int (*resume_early) (struct pci_dev *dev); 705 int (*resume) (struct pci_dev *dev); /* Device woken up */ 706 void (*shutdown) (struct pci_dev *dev); 707 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 708 const struct pci_error_handlers *err_handler; 709 struct device_driver driver; 710 struct pci_dynids dynids; 711 }; 712 713 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 714 715 /** 716 * PCI_DEVICE - macro used to describe a specific pci device 717 * @vend: the 16 bit PCI Vendor ID 718 * @dev: the 16 bit PCI Device ID 719 * 720 * This macro is used to create a struct pci_device_id that matches a 721 * specific device. The subvendor and subdevice fields will be set to 722 * PCI_ANY_ID. 723 */ 724 #define PCI_DEVICE(vend,dev) \ 725 .vendor = (vend), .device = (dev), \ 726 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 727 728 /** 729 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 730 * @vend: the 16 bit PCI Vendor ID 731 * @dev: the 16 bit PCI Device ID 732 * @subvend: the 16 bit PCI Subvendor ID 733 * @subdev: the 16 bit PCI Subdevice ID 734 * 735 * This macro is used to create a struct pci_device_id that matches a 736 * specific device with subsystem information. 737 */ 738 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 739 .vendor = (vend), .device = (dev), \ 740 .subvendor = (subvend), .subdevice = (subdev) 741 742 /** 743 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 744 * @dev_class: the class, subclass, prog-if triple for this device 745 * @dev_class_mask: the class mask for this device 746 * 747 * This macro is used to create a struct pci_device_id that matches a 748 * specific PCI class. The vendor, device, subvendor, and subdevice 749 * fields will be set to PCI_ANY_ID. 750 */ 751 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 752 .class = (dev_class), .class_mask = (dev_class_mask), \ 753 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 754 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 755 756 /** 757 * PCI_VDEVICE - macro used to describe a specific pci device in short form 758 * @vend: the vendor name 759 * @dev: the 16 bit PCI Device ID 760 * 761 * This macro is used to create a struct pci_device_id that matches a 762 * specific PCI device. The subvendor, and subdevice fields will be set 763 * to PCI_ANY_ID. The macro allows the next field to follow as the device 764 * private data. 765 */ 766 767 #define PCI_VDEVICE(vend, dev) \ 768 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 769 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 770 771 enum { 772 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ 773 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ 774 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ 775 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ 776 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ 777 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 778 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ 779 }; 780 781 /* these external functions are only available when PCI support is enabled */ 782 #ifdef CONFIG_PCI 783 784 extern unsigned int pci_flags; 785 786 static inline void pci_set_flags(int flags) { pci_flags = flags; } 787 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 788 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 789 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 790 791 void pcie_bus_configure_settings(struct pci_bus *bus); 792 793 enum pcie_bus_config_types { 794 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 795 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 796 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 797 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 798 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 799 }; 800 801 extern enum pcie_bus_config_types pcie_bus_config; 802 803 extern struct bus_type pci_bus_type; 804 805 /* Do NOT directly access these two variables, unless you are arch-specific PCI 806 * code, or PCI core code. */ 807 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 808 /* Some device drivers need know if PCI is initiated */ 809 int no_pci_devices(void); 810 811 void pcibios_resource_survey_bus(struct pci_bus *bus); 812 void pcibios_bus_add_device(struct pci_dev *pdev); 813 void pcibios_add_bus(struct pci_bus *bus); 814 void pcibios_remove_bus(struct pci_bus *bus); 815 void pcibios_fixup_bus(struct pci_bus *); 816 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 817 /* Architecture-specific versions may override this (weak) */ 818 char *pcibios_setup(char *str); 819 820 /* Used only when drivers/pci/setup.c is used */ 821 resource_size_t pcibios_align_resource(void *, const struct resource *, 822 resource_size_t, 823 resource_size_t); 824 void pcibios_update_irq(struct pci_dev *, int irq); 825 826 /* Weak but can be overriden by arch */ 827 void pci_fixup_cardbus(struct pci_bus *); 828 829 /* Generic PCI functions used internally */ 830 831 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 832 struct resource *res); 833 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 834 struct pci_bus_region *region); 835 void pcibios_scan_specific_bus(int busn); 836 struct pci_bus *pci_find_bus(int domain, int busnr); 837 void pci_bus_add_devices(const struct pci_bus *bus); 838 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 839 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 840 struct pci_ops *ops, void *sysdata, 841 struct list_head *resources); 842 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 843 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 844 void pci_bus_release_busn_res(struct pci_bus *b); 845 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, 846 struct pci_ops *ops, void *sysdata, 847 struct list_head *resources, 848 struct msi_controller *msi); 849 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 850 struct pci_ops *ops, void *sysdata, 851 struct list_head *resources); 852 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 853 int busnr); 854 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 855 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 856 const char *name, 857 struct hotplug_slot *hotplug); 858 void pci_destroy_slot(struct pci_slot *slot); 859 #ifdef CONFIG_SYSFS 860 void pci_dev_assign_slot(struct pci_dev *dev); 861 #else 862 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 863 #endif 864 int pci_scan_slot(struct pci_bus *bus, int devfn); 865 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 866 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 867 unsigned int pci_scan_child_bus(struct pci_bus *bus); 868 void pci_bus_add_device(struct pci_dev *dev); 869 void pci_read_bridge_bases(struct pci_bus *child); 870 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 871 struct resource *res); 872 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 873 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 874 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 875 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 876 struct pci_dev *pci_dev_get(struct pci_dev *dev); 877 void pci_dev_put(struct pci_dev *dev); 878 void pci_remove_bus(struct pci_bus *b); 879 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 880 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 881 void pci_stop_root_bus(struct pci_bus *bus); 882 void pci_remove_root_bus(struct pci_bus *bus); 883 void pci_setup_cardbus(struct pci_bus *bus); 884 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 885 void pci_sort_breadthfirst(void); 886 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 887 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 888 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 889 890 /* Generic PCI functions exported to card drivers */ 891 892 enum pci_lost_interrupt_reason { 893 PCI_LOST_IRQ_NO_INFORMATION = 0, 894 PCI_LOST_IRQ_DISABLE_MSI, 895 PCI_LOST_IRQ_DISABLE_MSIX, 896 PCI_LOST_IRQ_DISABLE_ACPI, 897 }; 898 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 899 int pci_find_capability(struct pci_dev *dev, int cap); 900 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 901 int pci_find_ext_capability(struct pci_dev *dev, int cap); 902 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 903 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 904 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 905 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 906 907 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 908 struct pci_dev *from); 909 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 910 unsigned int ss_vendor, unsigned int ss_device, 911 struct pci_dev *from); 912 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 913 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 914 unsigned int devfn); 915 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 916 unsigned int devfn) 917 { 918 return pci_get_domain_bus_and_slot(0, bus, devfn); 919 } 920 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 921 int pci_dev_present(const struct pci_device_id *ids); 922 923 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 924 int where, u8 *val); 925 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 926 int where, u16 *val); 927 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 928 int where, u32 *val); 929 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 930 int where, u8 val); 931 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 932 int where, u16 val); 933 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 934 int where, u32 val); 935 936 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 937 int where, int size, u32 *val); 938 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 939 int where, int size, u32 val); 940 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 941 int where, int size, u32 *val); 942 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 943 int where, int size, u32 val); 944 945 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 946 947 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 948 { 949 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 950 } 951 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 952 { 953 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 954 } 955 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 956 u32 *val) 957 { 958 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 959 } 960 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 961 { 962 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 963 } 964 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 965 { 966 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 967 } 968 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 969 u32 val) 970 { 971 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 972 } 973 974 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 975 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 976 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 977 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 978 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 979 u16 clear, u16 set); 980 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 981 u32 clear, u32 set); 982 983 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 984 u16 set) 985 { 986 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 987 } 988 989 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 990 u32 set) 991 { 992 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 993 } 994 995 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 996 u16 clear) 997 { 998 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 999 } 1000 1001 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1002 u32 clear) 1003 { 1004 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1005 } 1006 1007 /* user-space driven config access */ 1008 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1009 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1010 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1011 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1012 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1013 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1014 1015 int __must_check pci_enable_device(struct pci_dev *dev); 1016 int __must_check pci_enable_device_io(struct pci_dev *dev); 1017 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1018 int __must_check pci_reenable_device(struct pci_dev *); 1019 int __must_check pcim_enable_device(struct pci_dev *pdev); 1020 void pcim_pin_device(struct pci_dev *pdev); 1021 1022 static inline int pci_is_enabled(struct pci_dev *pdev) 1023 { 1024 return (atomic_read(&pdev->enable_cnt) > 0); 1025 } 1026 1027 static inline int pci_is_managed(struct pci_dev *pdev) 1028 { 1029 return pdev->is_managed; 1030 } 1031 1032 void pci_disable_device(struct pci_dev *dev); 1033 1034 extern unsigned int pcibios_max_latency; 1035 void pci_set_master(struct pci_dev *dev); 1036 void pci_clear_master(struct pci_dev *dev); 1037 1038 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1039 int pci_set_cacheline_size(struct pci_dev *dev); 1040 #define HAVE_PCI_SET_MWI 1041 int __must_check pci_set_mwi(struct pci_dev *dev); 1042 int pci_try_set_mwi(struct pci_dev *dev); 1043 void pci_clear_mwi(struct pci_dev *dev); 1044 void pci_intx(struct pci_dev *dev, int enable); 1045 bool pci_intx_mask_supported(struct pci_dev *dev); 1046 bool pci_check_and_mask_intx(struct pci_dev *dev); 1047 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1048 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1049 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1050 int pcix_get_max_mmrbc(struct pci_dev *dev); 1051 int pcix_get_mmrbc(struct pci_dev *dev); 1052 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1053 int pcie_get_readrq(struct pci_dev *dev); 1054 int pcie_set_readrq(struct pci_dev *dev, int rq); 1055 int pcie_get_mps(struct pci_dev *dev); 1056 int pcie_set_mps(struct pci_dev *dev, int mps); 1057 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1058 enum pcie_link_width *width); 1059 int __pci_reset_function(struct pci_dev *dev); 1060 int __pci_reset_function_locked(struct pci_dev *dev); 1061 int pci_reset_function(struct pci_dev *dev); 1062 int pci_try_reset_function(struct pci_dev *dev); 1063 int pci_probe_reset_slot(struct pci_slot *slot); 1064 int pci_reset_slot(struct pci_slot *slot); 1065 int pci_try_reset_slot(struct pci_slot *slot); 1066 int pci_probe_reset_bus(struct pci_bus *bus); 1067 int pci_reset_bus(struct pci_bus *bus); 1068 int pci_try_reset_bus(struct pci_bus *bus); 1069 void pci_reset_secondary_bus(struct pci_dev *dev); 1070 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1071 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1072 void pci_update_resource(struct pci_dev *dev, int resno); 1073 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1074 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1075 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1076 bool pci_device_is_present(struct pci_dev *pdev); 1077 void pci_ignore_hotplug(struct pci_dev *dev); 1078 1079 /* ROM control related routines */ 1080 int pci_enable_rom(struct pci_dev *pdev); 1081 void pci_disable_rom(struct pci_dev *pdev); 1082 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1083 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1084 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1085 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1086 1087 /* Power management related routines */ 1088 int pci_save_state(struct pci_dev *dev); 1089 void pci_restore_state(struct pci_dev *dev); 1090 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1091 int pci_load_saved_state(struct pci_dev *dev, 1092 struct pci_saved_state *state); 1093 int pci_load_and_free_saved_state(struct pci_dev *dev, 1094 struct pci_saved_state **state); 1095 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1096 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1097 u16 cap); 1098 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1099 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1100 u16 cap, unsigned int size); 1101 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1102 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1103 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1104 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1105 void pci_pme_active(struct pci_dev *dev, bool enable); 1106 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1107 bool runtime, bool enable); 1108 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1109 int pci_prepare_to_sleep(struct pci_dev *dev); 1110 int pci_back_from_sleep(struct pci_dev *dev); 1111 bool pci_dev_run_wake(struct pci_dev *dev); 1112 bool pci_check_pme_status(struct pci_dev *dev); 1113 void pci_pme_wakeup_bus(struct pci_bus *bus); 1114 void pci_d3cold_enable(struct pci_dev *dev); 1115 void pci_d3cold_disable(struct pci_dev *dev); 1116 1117 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1118 bool enable) 1119 { 1120 return __pci_enable_wake(dev, state, false, enable); 1121 } 1122 1123 /* PCI Virtual Channel */ 1124 int pci_save_vc_state(struct pci_dev *dev); 1125 void pci_restore_vc_state(struct pci_dev *dev); 1126 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1127 1128 /* For use by arch with custom probe code */ 1129 void set_pcie_port_type(struct pci_dev *pdev); 1130 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1131 1132 /* Functions for PCI Hotplug drivers to use */ 1133 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1134 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1135 unsigned int pci_rescan_bus(struct pci_bus *bus); 1136 void pci_lock_rescan_remove(void); 1137 void pci_unlock_rescan_remove(void); 1138 1139 /* Vital product data routines */ 1140 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1141 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1142 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1143 1144 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1145 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1146 void pci_bus_assign_resources(const struct pci_bus *bus); 1147 void pci_bus_claim_resources(struct pci_bus *bus); 1148 void pci_bus_size_bridges(struct pci_bus *bus); 1149 int pci_claim_resource(struct pci_dev *, int); 1150 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1151 void pci_assign_unassigned_resources(void); 1152 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1153 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1154 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1155 void pdev_enable_device(struct pci_dev *); 1156 int pci_enable_resources(struct pci_dev *, int mask); 1157 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1158 int (*)(const struct pci_dev *, u8, u8)); 1159 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1160 #define HAVE_PCI_REQ_REGIONS 2 1161 int __must_check pci_request_regions(struct pci_dev *, const char *); 1162 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1163 void pci_release_regions(struct pci_dev *); 1164 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1165 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1166 void pci_release_region(struct pci_dev *, int); 1167 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1168 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1169 void pci_release_selected_regions(struct pci_dev *, int); 1170 1171 /* drivers/pci/bus.c */ 1172 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1173 void pci_bus_put(struct pci_bus *bus); 1174 void pci_add_resource(struct list_head *resources, struct resource *res); 1175 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1176 resource_size_t offset); 1177 void pci_free_resource_list(struct list_head *resources); 1178 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1179 unsigned int flags); 1180 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1181 void pci_bus_remove_resources(struct pci_bus *bus); 1182 int devm_request_pci_bus_resources(struct device *dev, 1183 struct list_head *resources); 1184 1185 #define pci_bus_for_each_resource(bus, res, i) \ 1186 for (i = 0; \ 1187 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1188 i++) 1189 1190 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1191 struct resource *res, resource_size_t size, 1192 resource_size_t align, resource_size_t min, 1193 unsigned long type_mask, 1194 resource_size_t (*alignf)(void *, 1195 const struct resource *, 1196 resource_size_t, 1197 resource_size_t), 1198 void *alignf_data); 1199 1200 1201 int pci_register_io_range(phys_addr_t addr, resource_size_t size); 1202 unsigned long pci_address_to_pio(phys_addr_t addr); 1203 phys_addr_t pci_pio_to_address(unsigned long pio); 1204 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1205 void pci_unmap_iospace(struct resource *res); 1206 1207 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1208 { 1209 struct pci_bus_region region; 1210 1211 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1212 return region.start; 1213 } 1214 1215 /* Proper probing supporting hot-pluggable devices */ 1216 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1217 const char *mod_name); 1218 1219 /* 1220 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1221 */ 1222 #define pci_register_driver(driver) \ 1223 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1224 1225 void pci_unregister_driver(struct pci_driver *dev); 1226 1227 /** 1228 * module_pci_driver() - Helper macro for registering a PCI driver 1229 * @__pci_driver: pci_driver struct 1230 * 1231 * Helper macro for PCI drivers which do not do anything special in module 1232 * init/exit. This eliminates a lot of boilerplate. Each module may only 1233 * use this macro once, and calling it replaces module_init() and module_exit() 1234 */ 1235 #define module_pci_driver(__pci_driver) \ 1236 module_driver(__pci_driver, pci_register_driver, \ 1237 pci_unregister_driver) 1238 1239 /** 1240 * builtin_pci_driver() - Helper macro for registering a PCI driver 1241 * @__pci_driver: pci_driver struct 1242 * 1243 * Helper macro for PCI drivers which do not do anything special in their 1244 * init code. This eliminates a lot of boilerplate. Each driver may only 1245 * use this macro once, and calling it replaces device_initcall(...) 1246 */ 1247 #define builtin_pci_driver(__pci_driver) \ 1248 builtin_driver(__pci_driver, pci_register_driver) 1249 1250 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1251 int pci_add_dynid(struct pci_driver *drv, 1252 unsigned int vendor, unsigned int device, 1253 unsigned int subvendor, unsigned int subdevice, 1254 unsigned int class, unsigned int class_mask, 1255 unsigned long driver_data); 1256 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1257 struct pci_dev *dev); 1258 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1259 int pass); 1260 1261 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1262 void *userdata); 1263 int pci_cfg_space_size(struct pci_dev *dev); 1264 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1265 void pci_setup_bridge(struct pci_bus *bus); 1266 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1267 unsigned long type); 1268 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1269 1270 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1271 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1272 1273 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1274 unsigned int command_bits, u32 flags); 1275 1276 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ 1277 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ 1278 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ 1279 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ 1280 #define PCI_IRQ_ALL_TYPES \ 1281 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1282 1283 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1284 1285 #include <linux/pci-dma.h> 1286 #include <linux/dmapool.h> 1287 1288 #define pci_pool dma_pool 1289 #define pci_pool_create(name, pdev, size, align, allocation) \ 1290 dma_pool_create(name, &pdev->dev, size, align, allocation) 1291 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1292 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1293 #define pci_pool_zalloc(pool, flags, handle) \ 1294 dma_pool_zalloc(pool, flags, handle) 1295 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1296 1297 struct msix_entry { 1298 u32 vector; /* kernel uses to write allocated vector */ 1299 u16 entry; /* driver uses to specify entry, OS writes */ 1300 }; 1301 1302 #ifdef CONFIG_PCI_MSI 1303 int pci_msi_vec_count(struct pci_dev *dev); 1304 void pci_msi_shutdown(struct pci_dev *dev); 1305 void pci_disable_msi(struct pci_dev *dev); 1306 int pci_msix_vec_count(struct pci_dev *dev); 1307 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1308 void pci_msix_shutdown(struct pci_dev *dev); 1309 void pci_disable_msix(struct pci_dev *dev); 1310 void pci_restore_msi_state(struct pci_dev *dev); 1311 int pci_msi_enabled(void); 1312 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1313 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1314 { 1315 int rc = pci_enable_msi_range(dev, nvec, nvec); 1316 if (rc < 0) 1317 return rc; 1318 return 0; 1319 } 1320 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1321 int minvec, int maxvec); 1322 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1323 struct msix_entry *entries, int nvec) 1324 { 1325 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1326 if (rc < 0) 1327 return rc; 1328 return 0; 1329 } 1330 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1331 unsigned int max_vecs, unsigned int flags, 1332 const struct irq_affinity *affd); 1333 1334 void pci_free_irq_vectors(struct pci_dev *dev); 1335 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1336 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1337 1338 #else 1339 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1340 static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1341 static inline void pci_disable_msi(struct pci_dev *dev) { } 1342 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1343 static inline int pci_enable_msix(struct pci_dev *dev, 1344 struct msix_entry *entries, int nvec) 1345 { return -ENOSYS; } 1346 static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1347 static inline void pci_disable_msix(struct pci_dev *dev) { } 1348 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1349 static inline int pci_msi_enabled(void) { return 0; } 1350 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1351 int maxvec) 1352 { return -ENOSYS; } 1353 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1354 { return -ENOSYS; } 1355 static inline int pci_enable_msix_range(struct pci_dev *dev, 1356 struct msix_entry *entries, int minvec, int maxvec) 1357 { return -ENOSYS; } 1358 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1359 struct msix_entry *entries, int nvec) 1360 { return -ENOSYS; } 1361 1362 static inline int 1363 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1364 unsigned int max_vecs, unsigned int flags, 1365 const struct irq_affinity *aff_desc) 1366 { 1367 if (min_vecs > 1) 1368 return -EINVAL; 1369 return 1; 1370 } 1371 1372 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1373 { 1374 } 1375 1376 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1377 { 1378 if (WARN_ON_ONCE(nr > 0)) 1379 return -EINVAL; 1380 return dev->irq; 1381 } 1382 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1383 int vec) 1384 { 1385 return cpu_possible_mask; 1386 } 1387 #endif 1388 1389 static inline int 1390 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1391 unsigned int max_vecs, unsigned int flags) 1392 { 1393 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1394 NULL); 1395 } 1396 1397 #ifdef CONFIG_PCIEPORTBUS 1398 extern bool pcie_ports_disabled; 1399 extern bool pcie_ports_auto; 1400 #else 1401 #define pcie_ports_disabled true 1402 #define pcie_ports_auto false 1403 #endif 1404 1405 #ifdef CONFIG_PCIEASPM 1406 bool pcie_aspm_support_enabled(void); 1407 #else 1408 static inline bool pcie_aspm_support_enabled(void) { return false; } 1409 #endif 1410 1411 #ifdef CONFIG_PCIEAER 1412 void pci_no_aer(void); 1413 bool pci_aer_available(void); 1414 int pci_aer_init(struct pci_dev *dev); 1415 #else 1416 static inline void pci_no_aer(void) { } 1417 static inline bool pci_aer_available(void) { return false; } 1418 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } 1419 #endif 1420 1421 #ifdef CONFIG_PCIE_ECRC 1422 void pcie_set_ecrc_checking(struct pci_dev *dev); 1423 void pcie_ecrc_get_policy(char *str); 1424 #else 1425 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1426 static inline void pcie_ecrc_get_policy(char *str) { } 1427 #endif 1428 1429 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) 1430 1431 #ifdef CONFIG_HT_IRQ 1432 /* The functions a driver should call */ 1433 int ht_create_irq(struct pci_dev *dev, int idx); 1434 void ht_destroy_irq(unsigned int irq); 1435 #endif /* CONFIG_HT_IRQ */ 1436 1437 #ifdef CONFIG_PCI_ATS 1438 /* Address Translation Service */ 1439 void pci_ats_init(struct pci_dev *dev); 1440 int pci_enable_ats(struct pci_dev *dev, int ps); 1441 void pci_disable_ats(struct pci_dev *dev); 1442 int pci_ats_queue_depth(struct pci_dev *dev); 1443 #else 1444 static inline void pci_ats_init(struct pci_dev *d) { } 1445 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1446 static inline void pci_disable_ats(struct pci_dev *d) { } 1447 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1448 #endif 1449 1450 #ifdef CONFIG_PCIE_PTM 1451 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1452 #else 1453 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1454 { return -EINVAL; } 1455 #endif 1456 1457 void pci_cfg_access_lock(struct pci_dev *dev); 1458 bool pci_cfg_access_trylock(struct pci_dev *dev); 1459 void pci_cfg_access_unlock(struct pci_dev *dev); 1460 1461 /* 1462 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1463 * a PCI domain is defined to be a set of PCI buses which share 1464 * configuration space. 1465 */ 1466 #ifdef CONFIG_PCI_DOMAINS 1467 extern int pci_domains_supported; 1468 int pci_get_new_domain_nr(void); 1469 #else 1470 enum { pci_domains_supported = 0 }; 1471 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1472 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1473 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1474 #endif /* CONFIG_PCI_DOMAINS */ 1475 1476 /* 1477 * Generic implementation for PCI domain support. If your 1478 * architecture does not need custom management of PCI 1479 * domains then this implementation will be used 1480 */ 1481 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1482 static inline int pci_domain_nr(struct pci_bus *bus) 1483 { 1484 return bus->domain_nr; 1485 } 1486 #ifdef CONFIG_ACPI 1487 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1488 #else 1489 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1490 { return 0; } 1491 #endif 1492 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1493 #endif 1494 1495 /* some architectures require additional setup to direct VGA traffic */ 1496 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1497 unsigned int command_bits, u32 flags); 1498 void pci_register_set_vga_state(arch_set_vga_state_t func); 1499 1500 static inline int 1501 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1502 { 1503 return pci_request_selected_regions(pdev, 1504 pci_select_bars(pdev, IORESOURCE_IO), name); 1505 } 1506 1507 static inline void 1508 pci_release_io_regions(struct pci_dev *pdev) 1509 { 1510 return pci_release_selected_regions(pdev, 1511 pci_select_bars(pdev, IORESOURCE_IO)); 1512 } 1513 1514 static inline int 1515 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1516 { 1517 return pci_request_selected_regions(pdev, 1518 pci_select_bars(pdev, IORESOURCE_MEM), name); 1519 } 1520 1521 static inline void 1522 pci_release_mem_regions(struct pci_dev *pdev) 1523 { 1524 return pci_release_selected_regions(pdev, 1525 pci_select_bars(pdev, IORESOURCE_MEM)); 1526 } 1527 1528 #else /* CONFIG_PCI is not enabled */ 1529 1530 static inline void pci_set_flags(int flags) { } 1531 static inline void pci_add_flags(int flags) { } 1532 static inline void pci_clear_flags(int flags) { } 1533 static inline int pci_has_flag(int flag) { return 0; } 1534 1535 /* 1536 * If the system does not have PCI, clearly these return errors. Define 1537 * these as simple inline functions to avoid hair in drivers. 1538 */ 1539 1540 #define _PCI_NOP(o, s, t) \ 1541 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1542 int where, t val) \ 1543 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1544 1545 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1546 _PCI_NOP(o, word, u16 x) \ 1547 _PCI_NOP(o, dword, u32 x) 1548 _PCI_NOP_ALL(read, *) 1549 _PCI_NOP_ALL(write,) 1550 1551 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1552 unsigned int device, 1553 struct pci_dev *from) 1554 { return NULL; } 1555 1556 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1557 unsigned int device, 1558 unsigned int ss_vendor, 1559 unsigned int ss_device, 1560 struct pci_dev *from) 1561 { return NULL; } 1562 1563 static inline struct pci_dev *pci_get_class(unsigned int class, 1564 struct pci_dev *from) 1565 { return NULL; } 1566 1567 #define pci_dev_present(ids) (0) 1568 #define no_pci_devices() (1) 1569 #define pci_dev_put(dev) do { } while (0) 1570 1571 static inline void pci_set_master(struct pci_dev *dev) { } 1572 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1573 static inline void pci_disable_device(struct pci_dev *dev) { } 1574 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1575 { return -EBUSY; } 1576 static inline int __pci_register_driver(struct pci_driver *drv, 1577 struct module *owner) 1578 { return 0; } 1579 static inline int pci_register_driver(struct pci_driver *drv) 1580 { return 0; } 1581 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1582 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1583 { return 0; } 1584 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1585 int cap) 1586 { return 0; } 1587 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1588 { return 0; } 1589 1590 /* Power management related routines */ 1591 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1592 static inline void pci_restore_state(struct pci_dev *dev) { } 1593 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1594 { return 0; } 1595 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1596 { return 0; } 1597 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1598 pm_message_t state) 1599 { return PCI_D0; } 1600 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1601 int enable) 1602 { return 0; } 1603 1604 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1605 struct resource *res) 1606 { return NULL; } 1607 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1608 { return -EIO; } 1609 static inline void pci_release_regions(struct pci_dev *dev) { } 1610 1611 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1612 1613 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1614 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1615 { return 0; } 1616 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1617 1618 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1619 { return NULL; } 1620 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1621 unsigned int devfn) 1622 { return NULL; } 1623 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1624 unsigned int devfn) 1625 { return NULL; } 1626 1627 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1628 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1629 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1630 1631 #define dev_is_pci(d) (false) 1632 #define dev_is_pf(d) (false) 1633 #define dev_num_vf(d) (0) 1634 #endif /* CONFIG_PCI */ 1635 1636 /* Include architecture-dependent settings and functions */ 1637 1638 #include <asm/pci.h> 1639 1640 #ifndef pci_root_bus_fwnode 1641 #define pci_root_bus_fwnode(bus) NULL 1642 #endif 1643 1644 /* these helpers provide future and backwards compatibility 1645 * for accessing popular PCI BAR info */ 1646 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1647 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1648 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1649 #define pci_resource_len(dev,bar) \ 1650 ((pci_resource_start((dev), (bar)) == 0 && \ 1651 pci_resource_end((dev), (bar)) == \ 1652 pci_resource_start((dev), (bar))) ? 0 : \ 1653 \ 1654 (pci_resource_end((dev), (bar)) - \ 1655 pci_resource_start((dev), (bar)) + 1)) 1656 1657 /* Similar to the helpers above, these manipulate per-pci_dev 1658 * driver-specific data. They are really just a wrapper around 1659 * the generic device structure functions of these calls. 1660 */ 1661 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1662 { 1663 return dev_get_drvdata(&pdev->dev); 1664 } 1665 1666 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1667 { 1668 dev_set_drvdata(&pdev->dev, data); 1669 } 1670 1671 /* If you want to know what to call your pci_dev, ask this function. 1672 * Again, it's a wrapper around the generic device. 1673 */ 1674 static inline const char *pci_name(const struct pci_dev *pdev) 1675 { 1676 return dev_name(&pdev->dev); 1677 } 1678 1679 1680 /* Some archs don't want to expose struct resource to userland as-is 1681 * in sysfs and /proc 1682 */ 1683 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1684 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1685 const struct resource *rsrc, 1686 resource_size_t *start, resource_size_t *end); 1687 #else 1688 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1689 const struct resource *rsrc, resource_size_t *start, 1690 resource_size_t *end) 1691 { 1692 *start = rsrc->start; 1693 *end = rsrc->end; 1694 } 1695 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1696 1697 1698 /* 1699 * The world is not perfect and supplies us with broken PCI devices. 1700 * For at least a part of these bugs we need a work-around, so both 1701 * generic (drivers/pci/quirks.c) and per-architecture code can define 1702 * fixup hooks to be called for particular buggy devices. 1703 */ 1704 1705 struct pci_fixup { 1706 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1707 u16 device; /* You can use PCI_ANY_ID here of course */ 1708 u32 class; /* You can use PCI_ANY_ID here too */ 1709 unsigned int class_shift; /* should be 0, 8, 16 */ 1710 void (*hook)(struct pci_dev *dev); 1711 }; 1712 1713 enum pci_fixup_pass { 1714 pci_fixup_early, /* Before probing BARs */ 1715 pci_fixup_header, /* After reading configuration header */ 1716 pci_fixup_final, /* Final phase of device fixups */ 1717 pci_fixup_enable, /* pci_enable_device() time */ 1718 pci_fixup_resume, /* pci_device_resume() */ 1719 pci_fixup_suspend, /* pci_device_suspend() */ 1720 pci_fixup_resume_early, /* pci_device_resume_early() */ 1721 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1722 }; 1723 1724 /* Anonymous variables would be nice... */ 1725 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1726 class_shift, hook) \ 1727 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1728 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1729 = { vendor, device, class, class_shift, hook }; 1730 1731 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1732 class_shift, hook) \ 1733 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1734 hook, vendor, device, class, class_shift, hook) 1735 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1736 class_shift, hook) \ 1737 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1738 hook, vendor, device, class, class_shift, hook) 1739 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1740 class_shift, hook) \ 1741 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1742 hook, vendor, device, class, class_shift, hook) 1743 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1744 class_shift, hook) \ 1745 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1746 hook, vendor, device, class, class_shift, hook) 1747 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1748 class_shift, hook) \ 1749 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1750 resume##hook, vendor, device, class, \ 1751 class_shift, hook) 1752 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1753 class_shift, hook) \ 1754 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1755 resume_early##hook, vendor, device, \ 1756 class, class_shift, hook) 1757 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1758 class_shift, hook) \ 1759 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1760 suspend##hook, vendor, device, class, \ 1761 class_shift, hook) 1762 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1763 class_shift, hook) \ 1764 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1765 suspend_late##hook, vendor, device, \ 1766 class, class_shift, hook) 1767 1768 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1769 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1770 hook, vendor, device, PCI_ANY_ID, 0, hook) 1771 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1772 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1773 hook, vendor, device, PCI_ANY_ID, 0, hook) 1774 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1775 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1776 hook, vendor, device, PCI_ANY_ID, 0, hook) 1777 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1778 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1779 hook, vendor, device, PCI_ANY_ID, 0, hook) 1780 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1781 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1782 resume##hook, vendor, device, \ 1783 PCI_ANY_ID, 0, hook) 1784 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1785 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1786 resume_early##hook, vendor, device, \ 1787 PCI_ANY_ID, 0, hook) 1788 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1789 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1790 suspend##hook, vendor, device, \ 1791 PCI_ANY_ID, 0, hook) 1792 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1793 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1794 suspend_late##hook, vendor, device, \ 1795 PCI_ANY_ID, 0, hook) 1796 1797 #ifdef CONFIG_PCI_QUIRKS 1798 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1799 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1800 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1801 #else 1802 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1803 struct pci_dev *dev) { } 1804 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1805 u16 acs_flags) 1806 { 1807 return -ENOTTY; 1808 } 1809 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1810 { 1811 return -ENOTTY; 1812 } 1813 #endif 1814 1815 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1816 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1817 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1818 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1819 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1820 const char *name); 1821 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1822 1823 extern int pci_pci_problems; 1824 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1825 #define PCIPCI_TRITON 2 1826 #define PCIPCI_NATOMA 4 1827 #define PCIPCI_VIAETBF 8 1828 #define PCIPCI_VSFX 16 1829 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1830 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1831 1832 extern unsigned long pci_cardbus_io_size; 1833 extern unsigned long pci_cardbus_mem_size; 1834 extern u8 pci_dfl_cache_line_size; 1835 extern u8 pci_cache_line_size; 1836 1837 extern unsigned long pci_hotplug_io_size; 1838 extern unsigned long pci_hotplug_mem_size; 1839 extern unsigned long pci_hotplug_bus_size; 1840 1841 /* Architecture-specific versions may override these (weak) */ 1842 void pcibios_disable_device(struct pci_dev *dev); 1843 void pcibios_set_master(struct pci_dev *dev); 1844 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1845 enum pcie_reset_state state); 1846 int pcibios_add_device(struct pci_dev *dev); 1847 void pcibios_release_device(struct pci_dev *dev); 1848 void pcibios_penalize_isa_irq(int irq, int active); 1849 int pcibios_alloc_irq(struct pci_dev *dev); 1850 void pcibios_free_irq(struct pci_dev *dev); 1851 1852 #ifdef CONFIG_HIBERNATE_CALLBACKS 1853 extern struct dev_pm_ops pcibios_pm_ops; 1854 #endif 1855 1856 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1857 void __init pci_mmcfg_early_init(void); 1858 void __init pci_mmcfg_late_init(void); 1859 #else 1860 static inline void pci_mmcfg_early_init(void) { } 1861 static inline void pci_mmcfg_late_init(void) { } 1862 #endif 1863 1864 int pci_ext_cfg_avail(void); 1865 1866 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1867 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1868 1869 #ifdef CONFIG_PCI_IOV 1870 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1871 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1872 1873 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1874 void pci_disable_sriov(struct pci_dev *dev); 1875 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset); 1876 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset); 1877 int pci_num_vf(struct pci_dev *dev); 1878 int pci_vfs_assigned(struct pci_dev *dev); 1879 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1880 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1881 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1882 #else 1883 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1884 { 1885 return -ENOSYS; 1886 } 1887 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1888 { 1889 return -ENOSYS; 1890 } 1891 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1892 { return -ENODEV; } 1893 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset) 1894 { 1895 return -ENOSYS; 1896 } 1897 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 1898 int id, int reset) { } 1899 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1900 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1901 static inline int pci_vfs_assigned(struct pci_dev *dev) 1902 { return 0; } 1903 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1904 { return 0; } 1905 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1906 { return 0; } 1907 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1908 { return 0; } 1909 #endif 1910 1911 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1912 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1913 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1914 #endif 1915 1916 /** 1917 * pci_pcie_cap - get the saved PCIe capability offset 1918 * @dev: PCI device 1919 * 1920 * PCIe capability offset is calculated at PCI device initialization 1921 * time and saved in the data structure. This function returns saved 1922 * PCIe capability offset. Using this instead of pci_find_capability() 1923 * reduces unnecessary search in the PCI configuration space. If you 1924 * need to calculate PCIe capability offset from raw device for some 1925 * reasons, please use pci_find_capability() instead. 1926 */ 1927 static inline int pci_pcie_cap(struct pci_dev *dev) 1928 { 1929 return dev->pcie_cap; 1930 } 1931 1932 /** 1933 * pci_is_pcie - check if the PCI device is PCI Express capable 1934 * @dev: PCI device 1935 * 1936 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1937 */ 1938 static inline bool pci_is_pcie(struct pci_dev *dev) 1939 { 1940 return pci_pcie_cap(dev); 1941 } 1942 1943 /** 1944 * pcie_caps_reg - get the PCIe Capabilities Register 1945 * @dev: PCI device 1946 */ 1947 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1948 { 1949 return dev->pcie_flags_reg; 1950 } 1951 1952 /** 1953 * pci_pcie_type - get the PCIe device/port type 1954 * @dev: PCI device 1955 */ 1956 static inline int pci_pcie_type(const struct pci_dev *dev) 1957 { 1958 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1959 } 1960 1961 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 1962 { 1963 while (1) { 1964 if (!pci_is_pcie(dev)) 1965 break; 1966 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 1967 return dev; 1968 if (!dev->bus->self) 1969 break; 1970 dev = dev->bus->self; 1971 } 1972 return NULL; 1973 } 1974 1975 void pci_request_acs(void); 1976 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1977 bool pci_acs_path_enabled(struct pci_dev *start, 1978 struct pci_dev *end, u16 acs_flags); 1979 1980 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1981 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1982 1983 /* Large Resource Data Type Tag Item Names */ 1984 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1985 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1986 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1987 1988 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1989 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1990 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1991 1992 /* Small Resource Data Type Tag Item Names */ 1993 #define PCI_VPD_STIN_END 0x0f /* End */ 1994 1995 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 1996 1997 #define PCI_VPD_SRDT_TIN_MASK 0x78 1998 #define PCI_VPD_SRDT_LEN_MASK 0x07 1999 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2000 2001 #define PCI_VPD_LRDT_TAG_SIZE 3 2002 #define PCI_VPD_SRDT_TAG_SIZE 1 2003 2004 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2005 2006 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2007 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2008 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2009 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2010 2011 /** 2012 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2013 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2014 * 2015 * Returns the extracted Large Resource Data Type length. 2016 */ 2017 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2018 { 2019 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2020 } 2021 2022 /** 2023 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2024 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2025 * 2026 * Returns the extracted Large Resource Data Type Tag item. 2027 */ 2028 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2029 { 2030 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2031 } 2032 2033 /** 2034 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2035 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 2036 * 2037 * Returns the extracted Small Resource Data Type length. 2038 */ 2039 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2040 { 2041 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2042 } 2043 2044 /** 2045 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2046 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 2047 * 2048 * Returns the extracted Small Resource Data Type Tag Item. 2049 */ 2050 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2051 { 2052 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2053 } 2054 2055 /** 2056 * pci_vpd_info_field_size - Extracts the information field length 2057 * @lrdt: Pointer to the beginning of an information field header 2058 * 2059 * Returns the extracted information field length. 2060 */ 2061 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2062 { 2063 return info_field[2]; 2064 } 2065 2066 /** 2067 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2068 * @buf: Pointer to buffered vpd data 2069 * @off: The offset into the buffer at which to begin the search 2070 * @len: The length of the vpd buffer 2071 * @rdt: The Resource Data Type to search for 2072 * 2073 * Returns the index where the Resource Data Type was found or 2074 * -ENOENT otherwise. 2075 */ 2076 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2077 2078 /** 2079 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2080 * @buf: Pointer to buffered vpd data 2081 * @off: The offset into the buffer at which to begin the search 2082 * @len: The length of the buffer area, relative to off, in which to search 2083 * @kw: The keyword to search for 2084 * 2085 * Returns the index where the information field keyword was found or 2086 * -ENOENT otherwise. 2087 */ 2088 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2089 unsigned int len, const char *kw); 2090 2091 /* PCI <-> OF binding helpers */ 2092 #ifdef CONFIG_OF 2093 struct device_node; 2094 struct irq_domain; 2095 void pci_set_of_node(struct pci_dev *dev); 2096 void pci_release_of_node(struct pci_dev *dev); 2097 void pci_set_bus_of_node(struct pci_bus *bus); 2098 void pci_release_bus_of_node(struct pci_bus *bus); 2099 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2100 2101 /* Arch may override this (weak) */ 2102 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2103 2104 static inline struct device_node * 2105 pci_device_to_OF_node(const struct pci_dev *pdev) 2106 { 2107 return pdev ? pdev->dev.of_node : NULL; 2108 } 2109 2110 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2111 { 2112 return bus ? bus->dev.of_node : NULL; 2113 } 2114 2115 #else /* CONFIG_OF */ 2116 static inline void pci_set_of_node(struct pci_dev *dev) { } 2117 static inline void pci_release_of_node(struct pci_dev *dev) { } 2118 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2119 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2120 static inline struct device_node * 2121 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 2122 static inline struct irq_domain * 2123 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2124 #endif /* CONFIG_OF */ 2125 2126 #ifdef CONFIG_ACPI 2127 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2128 2129 void 2130 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2131 #else 2132 static inline struct irq_domain * 2133 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2134 #endif 2135 2136 #ifdef CONFIG_EEH 2137 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2138 { 2139 return pdev->dev.archdata.edev; 2140 } 2141 #endif 2142 2143 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2144 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2145 int pci_for_each_dma_alias(struct pci_dev *pdev, 2146 int (*fn)(struct pci_dev *pdev, 2147 u16 alias, void *data), void *data); 2148 2149 /* helper functions for operation of device flag */ 2150 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2151 { 2152 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2153 } 2154 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2155 { 2156 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2157 } 2158 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2159 { 2160 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2161 } 2162 2163 /** 2164 * pci_ari_enabled - query ARI forwarding status 2165 * @bus: the PCI bus 2166 * 2167 * Returns true if ARI forwarding is enabled. 2168 */ 2169 static inline bool pci_ari_enabled(struct pci_bus *bus) 2170 { 2171 return bus->self && bus->self->ari_enabled; 2172 } 2173 2174 /* provide the legacy pci_dma_* API */ 2175 #include <linux/pci-dma-compat.h> 2176 2177 #endif /* LINUX_PCI_H */ 2178