1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <linux/irqreturn.h> 33 #include <uapi/linux/pci.h> 34 35 /* Include the ID list */ 36 #include <linux/pci_ids.h> 37 38 /* pci_slot represents a physical slot */ 39 struct pci_slot { 40 struct pci_bus *bus; /* The bus this slot is on */ 41 struct list_head list; /* node in list of slots on this bus */ 42 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 43 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 44 struct kobject kobj; 45 }; 46 47 static inline const char *pci_slot_name(const struct pci_slot *slot) 48 { 49 return kobject_name(&slot->kobj); 50 } 51 52 /* File state for mmap()s on /proc/bus/pci/X/Y */ 53 enum pci_mmap_state { 54 pci_mmap_io, 55 pci_mmap_mem 56 }; 57 58 /* This defines the direction arg to the DMA mapping routines. */ 59 #define PCI_DMA_BIDIRECTIONAL 0 60 #define PCI_DMA_TODEVICE 1 61 #define PCI_DMA_FROMDEVICE 2 62 #define PCI_DMA_NONE 3 63 64 /* 65 * For PCI devices, the region numbers are assigned this way: 66 */ 67 enum { 68 /* #0-5: standard PCI resources */ 69 PCI_STD_RESOURCES, 70 PCI_STD_RESOURCE_END = 5, 71 72 /* #6: expansion ROM resource */ 73 PCI_ROM_RESOURCE, 74 75 /* device specific resources */ 76 #ifdef CONFIG_PCI_IOV 77 PCI_IOV_RESOURCES, 78 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 79 #endif 80 81 /* resources assigned to buses behind the bridge */ 82 #define PCI_BRIDGE_RESOURCE_NUM 4 83 84 PCI_BRIDGE_RESOURCES, 85 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 86 PCI_BRIDGE_RESOURCE_NUM - 1, 87 88 /* total resources associated with a PCI device */ 89 PCI_NUM_RESOURCES, 90 91 /* preserve this for compatibility */ 92 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 93 }; 94 95 typedef int __bitwise pci_power_t; 96 97 #define PCI_D0 ((pci_power_t __force) 0) 98 #define PCI_D1 ((pci_power_t __force) 1) 99 #define PCI_D2 ((pci_power_t __force) 2) 100 #define PCI_D3hot ((pci_power_t __force) 3) 101 #define PCI_D3cold ((pci_power_t __force) 4) 102 #define PCI_UNKNOWN ((pci_power_t __force) 5) 103 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 104 105 /* Remember to update this when the list above changes! */ 106 extern const char *pci_power_names[]; 107 108 static inline const char *pci_power_name(pci_power_t state) 109 { 110 return pci_power_names[1 + (int) state]; 111 } 112 113 #define PCI_PM_D2_DELAY 200 114 #define PCI_PM_D3_WAIT 10 115 #define PCI_PM_D3COLD_WAIT 100 116 #define PCI_PM_BUS_WAIT 50 117 118 /** The pci_channel state describes connectivity between the CPU and 119 * the pci device. If some PCI bus between here and the pci device 120 * has crashed or locked up, this info is reflected here. 121 */ 122 typedef unsigned int __bitwise pci_channel_state_t; 123 124 enum pci_channel_state { 125 /* I/O channel is in normal state */ 126 pci_channel_io_normal = (__force pci_channel_state_t) 1, 127 128 /* I/O to channel is blocked */ 129 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 130 131 /* PCI card is dead */ 132 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 133 }; 134 135 typedef unsigned int __bitwise pcie_reset_state_t; 136 137 enum pcie_reset_state { 138 /* Reset is NOT asserted (Use to deassert reset) */ 139 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 140 141 /* Use #PERST to reset PCI-E device */ 142 pcie_warm_reset = (__force pcie_reset_state_t) 2, 143 144 /* Use PCI-E Hot Reset to reset device */ 145 pcie_hot_reset = (__force pcie_reset_state_t) 3 146 }; 147 148 typedef unsigned short __bitwise pci_dev_flags_t; 149 enum pci_dev_flags { 150 /* INTX_DISABLE in PCI_COMMAND register disables MSI 151 * generation too. 152 */ 153 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, 154 /* Device configuration is irrevocably lost if disabled into D3 */ 155 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, 156 /* Provide indication device is assigned by a Virtual Machine Manager */ 157 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4, 158 }; 159 160 enum pci_irq_reroute_variant { 161 INTEL_IRQ_REROUTE_VARIANT = 1, 162 MAX_IRQ_REROUTE_VARIANTS = 3 163 }; 164 165 typedef unsigned short __bitwise pci_bus_flags_t; 166 enum pci_bus_flags { 167 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 168 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 169 }; 170 171 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 172 enum pci_bus_speed { 173 PCI_SPEED_33MHz = 0x00, 174 PCI_SPEED_66MHz = 0x01, 175 PCI_SPEED_66MHz_PCIX = 0x02, 176 PCI_SPEED_100MHz_PCIX = 0x03, 177 PCI_SPEED_133MHz_PCIX = 0x04, 178 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 179 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 180 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 181 PCI_SPEED_66MHz_PCIX_266 = 0x09, 182 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 183 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 184 AGP_UNKNOWN = 0x0c, 185 AGP_1X = 0x0d, 186 AGP_2X = 0x0e, 187 AGP_4X = 0x0f, 188 AGP_8X = 0x10, 189 PCI_SPEED_66MHz_PCIX_533 = 0x11, 190 PCI_SPEED_100MHz_PCIX_533 = 0x12, 191 PCI_SPEED_133MHz_PCIX_533 = 0x13, 192 PCIE_SPEED_2_5GT = 0x14, 193 PCIE_SPEED_5_0GT = 0x15, 194 PCIE_SPEED_8_0GT = 0x16, 195 PCI_SPEED_UNKNOWN = 0xff, 196 }; 197 198 struct pci_cap_saved_data { 199 char cap_nr; 200 unsigned int size; 201 u32 data[0]; 202 }; 203 204 struct pci_cap_saved_state { 205 struct hlist_node next; 206 struct pci_cap_saved_data cap; 207 }; 208 209 struct pcie_link_state; 210 struct pci_vpd; 211 struct pci_sriov; 212 struct pci_ats; 213 214 /* 215 * The pci_dev structure is used to describe PCI devices. 216 */ 217 struct pci_dev { 218 struct list_head bus_list; /* node in per-bus list */ 219 struct pci_bus *bus; /* bus this device is on */ 220 struct pci_bus *subordinate; /* bus this device bridges to */ 221 222 void *sysdata; /* hook for sys-specific extension */ 223 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 224 struct pci_slot *slot; /* Physical slot this device is in */ 225 226 unsigned int devfn; /* encoded device & function index */ 227 unsigned short vendor; 228 unsigned short device; 229 unsigned short subsystem_vendor; 230 unsigned short subsystem_device; 231 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 232 u8 revision; /* PCI revision, low byte of class word */ 233 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 234 u8 pcie_cap; /* PCI-E capability offset */ 235 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ 236 u8 rom_base_reg; /* which config register controls the ROM */ 237 u8 pin; /* which interrupt pin this device uses */ 238 u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ 239 240 struct pci_driver *driver; /* which driver has allocated this device */ 241 u64 dma_mask; /* Mask of the bits of bus address this 242 device implements. Normally this is 243 0xffffffff. You only need to change 244 this if your device has broken DMA 245 or supports 64-bit transfers. */ 246 247 struct device_dma_parameters dma_parms; 248 249 pci_power_t current_state; /* Current operating state. In ACPI-speak, 250 this is D0-D3, D0 being fully functional, 251 and D3 being off. */ 252 int pm_cap; /* PM capability offset in the 253 configuration space */ 254 unsigned int pme_support:5; /* Bitmask of states from which PME# 255 can be generated */ 256 unsigned int pme_interrupt:1; 257 unsigned int pme_poll:1; /* Poll device's PME status bit */ 258 unsigned int d1_support:1; /* Low power state D1 is supported */ 259 unsigned int d2_support:1; /* Low power state D2 is supported */ 260 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 261 unsigned int no_d3cold:1; /* D3cold is forbidden */ 262 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 263 unsigned int mmio_always_on:1; /* disallow turning off io/mem 264 decoding during bar sizing */ 265 unsigned int wakeup_prepared:1; 266 unsigned int runtime_d3cold:1; /* whether go through runtime 267 D3cold, not set for devices 268 powered on/off by the 269 corresponding bridge */ 270 unsigned int d3_delay; /* D3->D0 transition time in ms */ 271 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 272 273 #ifdef CONFIG_PCIEASPM 274 struct pcie_link_state *link_state; /* ASPM link state. */ 275 #endif 276 277 pci_channel_state_t error_state; /* current connectivity state */ 278 struct device dev; /* Generic device interface */ 279 280 int cfg_size; /* Size of configuration space */ 281 282 /* 283 * Instead of touching interrupt line and base address registers 284 * directly, use the values stored here. They might be different! 285 */ 286 unsigned int irq; 287 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 288 289 bool match_driver; /* Skip attaching driver */ 290 /* These fields are used by common fixups */ 291 unsigned int transparent:1; /* Transparent PCI bridge */ 292 unsigned int multifunction:1;/* Part of multi-function device */ 293 /* keep track of device state */ 294 unsigned int is_added:1; 295 unsigned int is_busmaster:1; /* device is busmaster */ 296 unsigned int no_msi:1; /* device may not use msi */ 297 unsigned int block_cfg_access:1; /* config space access is blocked */ 298 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 299 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 300 unsigned int msi_enabled:1; 301 unsigned int msix_enabled:1; 302 unsigned int ari_enabled:1; /* ARI forwarding */ 303 unsigned int is_managed:1; 304 unsigned int is_pcie:1; /* Obsolete. Will be removed. 305 Use pci_is_pcie() instead */ 306 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 307 unsigned int state_saved:1; 308 unsigned int is_physfn:1; 309 unsigned int is_virtfn:1; 310 unsigned int reset_fn:1; 311 unsigned int is_hotplug_bridge:1; 312 unsigned int __aer_firmware_first_valid:1; 313 unsigned int __aer_firmware_first:1; 314 unsigned int broken_intx_masking:1; 315 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 316 pci_dev_flags_t dev_flags; 317 atomic_t enable_cnt; /* pci_enable_device has been called */ 318 319 u32 saved_config_space[16]; /* config space saved at suspend time */ 320 struct hlist_head saved_cap_space; 321 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 322 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 323 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 324 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 325 #ifdef CONFIG_PCI_MSI 326 struct list_head msi_list; 327 struct kset *msi_kset; 328 #endif 329 struct pci_vpd *vpd; 330 #ifdef CONFIG_PCI_ATS 331 union { 332 struct pci_sriov *sriov; /* SR-IOV capability related */ 333 struct pci_dev *physfn; /* the PF this VF is associated with */ 334 }; 335 struct pci_ats *ats; /* Address Translation Service */ 336 #endif 337 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 338 size_t romlen; /* Length of ROM if it's not from the BAR */ 339 }; 340 341 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 342 { 343 #ifdef CONFIG_PCI_IOV 344 if (dev->is_virtfn) 345 dev = dev->physfn; 346 #endif 347 348 return dev; 349 } 350 351 extern struct pci_dev *alloc_pci_dev(void); 352 353 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 354 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 355 356 static inline int pci_channel_offline(struct pci_dev *pdev) 357 { 358 return (pdev->error_state != pci_channel_io_normal); 359 } 360 361 extern struct resource busn_resource; 362 363 struct pci_host_bridge_window { 364 struct list_head list; 365 struct resource *res; /* host bridge aperture (CPU address) */ 366 resource_size_t offset; /* bus address + offset = CPU address */ 367 }; 368 369 struct pci_host_bridge { 370 struct device dev; 371 struct pci_bus *bus; /* root bus */ 372 struct list_head windows; /* pci_host_bridge_windows */ 373 void (*release_fn)(struct pci_host_bridge *); 374 void *release_data; 375 }; 376 377 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 378 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 379 void (*release_fn)(struct pci_host_bridge *), 380 void *release_data); 381 382 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 383 384 /* 385 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 386 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 387 * buses below host bridges or subtractive decode bridges) go in the list. 388 * Use pci_bus_for_each_resource() to iterate through all the resources. 389 */ 390 391 /* 392 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 393 * and there's no way to program the bridge with the details of the window. 394 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 395 * decode bit set, because they are explicit and can be programmed with _SRS. 396 */ 397 #define PCI_SUBTRACTIVE_DECODE 0x1 398 399 struct pci_bus_resource { 400 struct list_head list; 401 struct resource *res; 402 unsigned int flags; 403 }; 404 405 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 406 407 struct pci_bus { 408 struct list_head node; /* node in list of buses */ 409 struct pci_bus *parent; /* parent bus this bridge is on */ 410 struct list_head children; /* list of child buses */ 411 struct list_head devices; /* list of devices on this bus */ 412 struct pci_dev *self; /* bridge device as seen by parent */ 413 struct list_head slots; /* list of slots on this bus */ 414 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 415 struct list_head resources; /* address space routed to this bus */ 416 struct resource busn_res; /* bus numbers routed to this bus */ 417 418 struct pci_ops *ops; /* configuration access functions */ 419 void *sysdata; /* hook for sys-specific extension */ 420 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 421 422 unsigned char number; /* bus number */ 423 unsigned char primary; /* number of primary bridge */ 424 unsigned char max_bus_speed; /* enum pci_bus_speed */ 425 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 426 427 char name[48]; 428 429 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 430 pci_bus_flags_t bus_flags; /* Inherited by child busses */ 431 struct device *bridge; 432 struct device dev; 433 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 434 struct bin_attribute *legacy_mem; /* legacy mem */ 435 unsigned int is_added:1; 436 }; 437 438 #define pci_bus_b(n) list_entry(n, struct pci_bus, node) 439 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 440 441 /* 442 * Returns true if the pci bus is root (behind host-pci bridge), 443 * false otherwise 444 */ 445 static inline bool pci_is_root_bus(struct pci_bus *pbus) 446 { 447 return !(pbus->parent); 448 } 449 450 #ifdef CONFIG_PCI_MSI 451 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 452 { 453 return pci_dev->msi_enabled || pci_dev->msix_enabled; 454 } 455 #else 456 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 457 #endif 458 459 /* 460 * Error values that may be returned by PCI functions. 461 */ 462 #define PCIBIOS_SUCCESSFUL 0x00 463 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 464 #define PCIBIOS_BAD_VENDOR_ID 0x83 465 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 466 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 467 #define PCIBIOS_SET_FAILED 0x88 468 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 469 470 /* 471 * Translate above to generic errno for passing back through non-pci. 472 */ 473 static inline int pcibios_err_to_errno(int err) 474 { 475 if (err <= PCIBIOS_SUCCESSFUL) 476 return err; /* Assume already errno */ 477 478 switch (err) { 479 case PCIBIOS_FUNC_NOT_SUPPORTED: 480 return -ENOENT; 481 case PCIBIOS_BAD_VENDOR_ID: 482 return -EINVAL; 483 case PCIBIOS_DEVICE_NOT_FOUND: 484 return -ENODEV; 485 case PCIBIOS_BAD_REGISTER_NUMBER: 486 return -EFAULT; 487 case PCIBIOS_SET_FAILED: 488 return -EIO; 489 case PCIBIOS_BUFFER_TOO_SMALL: 490 return -ENOSPC; 491 } 492 493 return -ENOTTY; 494 } 495 496 /* Low-level architecture-dependent routines */ 497 498 struct pci_ops { 499 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 500 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 501 }; 502 503 /* 504 * ACPI needs to be able to access PCI config space before we've done a 505 * PCI bus scan and created pci_bus structures. 506 */ 507 extern int raw_pci_read(unsigned int domain, unsigned int bus, 508 unsigned int devfn, int reg, int len, u32 *val); 509 extern int raw_pci_write(unsigned int domain, unsigned int bus, 510 unsigned int devfn, int reg, int len, u32 val); 511 512 struct pci_bus_region { 513 resource_size_t start; 514 resource_size_t end; 515 }; 516 517 struct pci_dynids { 518 spinlock_t lock; /* protects list, index */ 519 struct list_head list; /* for IDs added at runtime */ 520 }; 521 522 /* ---------------------------------------------------------------- */ 523 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 524 * a set of callbacks in struct pci_error_handlers, then that device driver 525 * will be notified of PCI bus errors, and will be driven to recovery 526 * when an error occurs. 527 */ 528 529 typedef unsigned int __bitwise pci_ers_result_t; 530 531 enum pci_ers_result { 532 /* no result/none/not supported in device driver */ 533 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 534 535 /* Device driver can recover without slot reset */ 536 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 537 538 /* Device driver wants slot to be reset. */ 539 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 540 541 /* Device has completely failed, is unrecoverable */ 542 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 543 544 /* Device driver is fully recovered and operational */ 545 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 546 547 /* No AER capabilities registered for the driver */ 548 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 549 }; 550 551 /* PCI bus error event callbacks */ 552 struct pci_error_handlers { 553 /* PCI bus error detected on this device */ 554 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 555 enum pci_channel_state error); 556 557 /* MMIO has been re-enabled, but not DMA */ 558 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 559 560 /* PCI Express link has been reset */ 561 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 562 563 /* PCI slot has been reset */ 564 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 565 566 /* Device driver may resume normal operations */ 567 void (*resume)(struct pci_dev *dev); 568 }; 569 570 /* ---------------------------------------------------------------- */ 571 572 struct module; 573 struct pci_driver { 574 struct list_head node; 575 const char *name; 576 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 577 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 578 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 579 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 580 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 581 int (*resume_early) (struct pci_dev *dev); 582 int (*resume) (struct pci_dev *dev); /* Device woken up */ 583 void (*shutdown) (struct pci_dev *dev); 584 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 585 const struct pci_error_handlers *err_handler; 586 struct device_driver driver; 587 struct pci_dynids dynids; 588 }; 589 590 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 591 592 /** 593 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 594 * @_table: device table name 595 * 596 * This macro is used to create a struct pci_device_id array (a device table) 597 * in a generic manner. 598 */ 599 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 600 const struct pci_device_id _table[] 601 602 /** 603 * PCI_DEVICE - macro used to describe a specific pci device 604 * @vend: the 16 bit PCI Vendor ID 605 * @dev: the 16 bit PCI Device ID 606 * 607 * This macro is used to create a struct pci_device_id that matches a 608 * specific device. The subvendor and subdevice fields will be set to 609 * PCI_ANY_ID. 610 */ 611 #define PCI_DEVICE(vend,dev) \ 612 .vendor = (vend), .device = (dev), \ 613 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 614 615 /** 616 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 617 * @vend: the 16 bit PCI Vendor ID 618 * @dev: the 16 bit PCI Device ID 619 * @subvend: the 16 bit PCI Subvendor ID 620 * @subdev: the 16 bit PCI Subdevice ID 621 * 622 * This macro is used to create a struct pci_device_id that matches a 623 * specific device with subsystem information. 624 */ 625 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 626 .vendor = (vend), .device = (dev), \ 627 .subvendor = (subvend), .subdevice = (subdev) 628 629 /** 630 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 631 * @dev_class: the class, subclass, prog-if triple for this device 632 * @dev_class_mask: the class mask for this device 633 * 634 * This macro is used to create a struct pci_device_id that matches a 635 * specific PCI class. The vendor, device, subvendor, and subdevice 636 * fields will be set to PCI_ANY_ID. 637 */ 638 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 639 .class = (dev_class), .class_mask = (dev_class_mask), \ 640 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 641 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 642 643 /** 644 * PCI_VDEVICE - macro used to describe a specific pci device in short form 645 * @vendor: the vendor name 646 * @device: the 16 bit PCI Device ID 647 * 648 * This macro is used to create a struct pci_device_id that matches a 649 * specific PCI device. The subvendor, and subdevice fields will be set 650 * to PCI_ANY_ID. The macro allows the next field to follow as the device 651 * private data. 652 */ 653 654 #define PCI_VDEVICE(vendor, device) \ 655 PCI_VENDOR_ID_##vendor, (device), \ 656 PCI_ANY_ID, PCI_ANY_ID, 0, 0 657 658 /* these external functions are only available when PCI support is enabled */ 659 #ifdef CONFIG_PCI 660 661 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss); 662 663 enum pcie_bus_config_types { 664 PCIE_BUS_TUNE_OFF, 665 PCIE_BUS_SAFE, 666 PCIE_BUS_PERFORMANCE, 667 PCIE_BUS_PEER2PEER, 668 }; 669 670 extern enum pcie_bus_config_types pcie_bus_config; 671 672 extern struct bus_type pci_bus_type; 673 674 /* Do NOT directly access these two variables, unless you are arch specific pci 675 * code, or pci core code. */ 676 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 677 /* Some device drivers need know if pci is initiated */ 678 extern int no_pci_devices(void); 679 680 void pcibios_resource_survey_bus(struct pci_bus *bus); 681 void pcibios_fixup_bus(struct pci_bus *); 682 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 683 /* Architecture specific versions may override this (weak) */ 684 char *pcibios_setup(char *str); 685 686 /* Used only when drivers/pci/setup.c is used */ 687 resource_size_t pcibios_align_resource(void *, const struct resource *, 688 resource_size_t, 689 resource_size_t); 690 void pcibios_update_irq(struct pci_dev *, int irq); 691 692 /* Weak but can be overriden by arch */ 693 void pci_fixup_cardbus(struct pci_bus *); 694 695 /* Generic PCI functions used internally */ 696 697 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 698 struct resource *res); 699 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 700 struct pci_bus_region *region); 701 void pcibios_scan_specific_bus(int busn); 702 extern struct pci_bus *pci_find_bus(int domain, int busnr); 703 void pci_bus_add_devices(const struct pci_bus *bus); 704 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, 705 struct pci_ops *ops, void *sysdata); 706 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 707 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 708 struct pci_ops *ops, void *sysdata, 709 struct list_head *resources); 710 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 711 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 712 void pci_bus_release_busn_res(struct pci_bus *b); 713 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 714 struct pci_ops *ops, void *sysdata, 715 struct list_head *resources); 716 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 717 int busnr); 718 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 719 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 720 const char *name, 721 struct hotplug_slot *hotplug); 722 void pci_destroy_slot(struct pci_slot *slot); 723 void pci_renumber_slot(struct pci_slot *slot, int slot_nr); 724 int pci_scan_slot(struct pci_bus *bus, int devfn); 725 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 726 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 727 unsigned int pci_scan_child_bus(struct pci_bus *bus); 728 int __must_check pci_bus_add_device(struct pci_dev *dev); 729 void pci_read_bridge_bases(struct pci_bus *child); 730 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 731 struct resource *res); 732 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 733 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 734 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 735 extern struct pci_dev *pci_dev_get(struct pci_dev *dev); 736 extern void pci_dev_put(struct pci_dev *dev); 737 extern void pci_remove_bus(struct pci_bus *b); 738 extern void pci_stop_and_remove_bus_device(struct pci_dev *dev); 739 void pci_stop_root_bus(struct pci_bus *bus); 740 void pci_remove_root_bus(struct pci_bus *bus); 741 void pci_setup_cardbus(struct pci_bus *bus); 742 extern void pci_sort_breadthfirst(void); 743 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 744 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 745 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 746 747 /* Generic PCI functions exported to card drivers */ 748 749 enum pci_lost_interrupt_reason { 750 PCI_LOST_IRQ_NO_INFORMATION = 0, 751 PCI_LOST_IRQ_DISABLE_MSI, 752 PCI_LOST_IRQ_DISABLE_MSIX, 753 PCI_LOST_IRQ_DISABLE_ACPI, 754 }; 755 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 756 int pci_find_capability(struct pci_dev *dev, int cap); 757 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 758 int pci_find_ext_capability(struct pci_dev *dev, int cap); 759 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 760 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 761 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 762 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 763 764 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 765 struct pci_dev *from); 766 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 767 unsigned int ss_vendor, unsigned int ss_device, 768 struct pci_dev *from); 769 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 770 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 771 unsigned int devfn); 772 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 773 unsigned int devfn) 774 { 775 return pci_get_domain_bus_and_slot(0, bus, devfn); 776 } 777 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 778 int pci_dev_present(const struct pci_device_id *ids); 779 780 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 781 int where, u8 *val); 782 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 783 int where, u16 *val); 784 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 785 int where, u32 *val); 786 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 787 int where, u8 val); 788 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 789 int where, u16 val); 790 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 791 int where, u32 val); 792 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 793 794 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 795 { 796 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 797 } 798 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 799 { 800 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 801 } 802 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 803 u32 *val) 804 { 805 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 806 } 807 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 808 { 809 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 810 } 811 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 812 { 813 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 814 } 815 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 816 u32 val) 817 { 818 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 819 } 820 821 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 822 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 823 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 824 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 825 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 826 u16 clear, u16 set); 827 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 828 u32 clear, u32 set); 829 830 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 831 u16 set) 832 { 833 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 834 } 835 836 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 837 u32 set) 838 { 839 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 840 } 841 842 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 843 u16 clear) 844 { 845 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 846 } 847 848 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 849 u32 clear) 850 { 851 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 852 } 853 854 /* user-space driven config access */ 855 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 856 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 857 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 858 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 859 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 860 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 861 862 int __must_check pci_enable_device(struct pci_dev *dev); 863 int __must_check pci_enable_device_io(struct pci_dev *dev); 864 int __must_check pci_enable_device_mem(struct pci_dev *dev); 865 int __must_check pci_reenable_device(struct pci_dev *); 866 int __must_check pcim_enable_device(struct pci_dev *pdev); 867 void pcim_pin_device(struct pci_dev *pdev); 868 869 static inline int pci_is_enabled(struct pci_dev *pdev) 870 { 871 return (atomic_read(&pdev->enable_cnt) > 0); 872 } 873 874 static inline int pci_is_managed(struct pci_dev *pdev) 875 { 876 return pdev->is_managed; 877 } 878 879 void pci_disable_device(struct pci_dev *dev); 880 881 extern unsigned int pcibios_max_latency; 882 void pci_set_master(struct pci_dev *dev); 883 void pci_clear_master(struct pci_dev *dev); 884 885 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 886 int pci_set_cacheline_size(struct pci_dev *dev); 887 #define HAVE_PCI_SET_MWI 888 int __must_check pci_set_mwi(struct pci_dev *dev); 889 int pci_try_set_mwi(struct pci_dev *dev); 890 void pci_clear_mwi(struct pci_dev *dev); 891 void pci_intx(struct pci_dev *dev, int enable); 892 bool pci_intx_mask_supported(struct pci_dev *dev); 893 bool pci_check_and_mask_intx(struct pci_dev *dev); 894 bool pci_check_and_unmask_intx(struct pci_dev *dev); 895 void pci_msi_off(struct pci_dev *dev); 896 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 897 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 898 int pcix_get_max_mmrbc(struct pci_dev *dev); 899 int pcix_get_mmrbc(struct pci_dev *dev); 900 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 901 int pcie_get_readrq(struct pci_dev *dev); 902 int pcie_set_readrq(struct pci_dev *dev, int rq); 903 int pcie_get_mps(struct pci_dev *dev); 904 int pcie_set_mps(struct pci_dev *dev, int mps); 905 int __pci_reset_function(struct pci_dev *dev); 906 int __pci_reset_function_locked(struct pci_dev *dev); 907 int pci_reset_function(struct pci_dev *dev); 908 void pci_update_resource(struct pci_dev *dev, int resno); 909 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 910 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 911 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 912 913 /* ROM control related routines */ 914 int pci_enable_rom(struct pci_dev *pdev); 915 void pci_disable_rom(struct pci_dev *pdev); 916 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 917 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 918 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 919 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 920 921 /* Power management related routines */ 922 int pci_save_state(struct pci_dev *dev); 923 void pci_restore_state(struct pci_dev *dev); 924 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 925 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state); 926 int pci_load_and_free_saved_state(struct pci_dev *dev, 927 struct pci_saved_state **state); 928 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 929 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 930 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 931 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 932 void pci_pme_active(struct pci_dev *dev, bool enable); 933 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 934 bool runtime, bool enable); 935 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 936 pci_power_t pci_target_state(struct pci_dev *dev); 937 int pci_prepare_to_sleep(struct pci_dev *dev); 938 int pci_back_from_sleep(struct pci_dev *dev); 939 bool pci_dev_run_wake(struct pci_dev *dev); 940 bool pci_check_pme_status(struct pci_dev *dev); 941 void pci_pme_wakeup_bus(struct pci_bus *bus); 942 943 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 944 bool enable) 945 { 946 return __pci_enable_wake(dev, state, false, enable); 947 } 948 949 #define PCI_EXP_IDO_REQUEST (1<<0) 950 #define PCI_EXP_IDO_COMPLETION (1<<1) 951 void pci_enable_ido(struct pci_dev *dev, unsigned long type); 952 void pci_disable_ido(struct pci_dev *dev, unsigned long type); 953 954 enum pci_obff_signal_type { 955 PCI_EXP_OBFF_SIGNAL_L0 = 0, 956 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1, 957 }; 958 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type); 959 void pci_disable_obff(struct pci_dev *dev); 960 961 int pci_enable_ltr(struct pci_dev *dev); 962 void pci_disable_ltr(struct pci_dev *dev); 963 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns); 964 965 /* For use by arch with custom probe code */ 966 void set_pcie_port_type(struct pci_dev *pdev); 967 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 968 969 /* Functions for PCI Hotplug drivers to use */ 970 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 971 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 972 unsigned int pci_rescan_bus(struct pci_bus *bus); 973 974 /* Vital product data routines */ 975 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 976 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 977 int pci_vpd_truncate(struct pci_dev *dev, size_t size); 978 979 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 980 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 981 void pci_bus_assign_resources(const struct pci_bus *bus); 982 void pci_bus_size_bridges(struct pci_bus *bus); 983 int pci_claim_resource(struct pci_dev *, int); 984 void pci_assign_unassigned_resources(void); 985 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 986 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 987 void pdev_enable_device(struct pci_dev *); 988 int pci_enable_resources(struct pci_dev *, int mask); 989 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 990 int (*)(const struct pci_dev *, u8, u8)); 991 #define HAVE_PCI_REQ_REGIONS 2 992 int __must_check pci_request_regions(struct pci_dev *, const char *); 993 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 994 void pci_release_regions(struct pci_dev *); 995 int __must_check pci_request_region(struct pci_dev *, int, const char *); 996 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 997 void pci_release_region(struct pci_dev *, int); 998 int pci_request_selected_regions(struct pci_dev *, int, const char *); 999 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1000 void pci_release_selected_regions(struct pci_dev *, int); 1001 1002 /* drivers/pci/bus.c */ 1003 void pci_add_resource(struct list_head *resources, struct resource *res); 1004 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1005 resource_size_t offset); 1006 void pci_free_resource_list(struct list_head *resources); 1007 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1008 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1009 void pci_bus_remove_resources(struct pci_bus *bus); 1010 1011 #define pci_bus_for_each_resource(bus, res, i) \ 1012 for (i = 0; \ 1013 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1014 i++) 1015 1016 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1017 struct resource *res, resource_size_t size, 1018 resource_size_t align, resource_size_t min, 1019 unsigned int type_mask, 1020 resource_size_t (*alignf)(void *, 1021 const struct resource *, 1022 resource_size_t, 1023 resource_size_t), 1024 void *alignf_data); 1025 void pci_enable_bridges(struct pci_bus *bus); 1026 1027 /* Proper probing supporting hot-pluggable devices */ 1028 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1029 const char *mod_name); 1030 1031 /* 1032 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1033 */ 1034 #define pci_register_driver(driver) \ 1035 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1036 1037 void pci_unregister_driver(struct pci_driver *dev); 1038 1039 /** 1040 * module_pci_driver() - Helper macro for registering a PCI driver 1041 * @__pci_driver: pci_driver struct 1042 * 1043 * Helper macro for PCI drivers which do not do anything special in module 1044 * init/exit. This eliminates a lot of boilerplate. Each module may only 1045 * use this macro once, and calling it replaces module_init() and module_exit() 1046 */ 1047 #define module_pci_driver(__pci_driver) \ 1048 module_driver(__pci_driver, pci_register_driver, \ 1049 pci_unregister_driver) 1050 1051 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1052 int pci_add_dynid(struct pci_driver *drv, 1053 unsigned int vendor, unsigned int device, 1054 unsigned int subvendor, unsigned int subdevice, 1055 unsigned int class, unsigned int class_mask, 1056 unsigned long driver_data); 1057 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1058 struct pci_dev *dev); 1059 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1060 int pass); 1061 1062 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1063 void *userdata); 1064 int pci_cfg_space_size_ext(struct pci_dev *dev); 1065 int pci_cfg_space_size(struct pci_dev *dev); 1066 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1067 void pci_setup_bridge(struct pci_bus *bus); 1068 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1069 unsigned long type); 1070 1071 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1072 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1073 1074 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1075 unsigned int command_bits, u32 flags); 1076 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1077 1078 #include <linux/pci-dma.h> 1079 #include <linux/dmapool.h> 1080 1081 #define pci_pool dma_pool 1082 #define pci_pool_create(name, pdev, size, align, allocation) \ 1083 dma_pool_create(name, &pdev->dev, size, align, allocation) 1084 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1085 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1086 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1087 1088 enum pci_dma_burst_strategy { 1089 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, 1090 strategy_parameter is N/A */ 1091 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter 1092 byte boundaries */ 1093 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of 1094 strategy_parameter byte boundaries */ 1095 }; 1096 1097 struct msix_entry { 1098 u32 vector; /* kernel uses to write allocated vector */ 1099 u16 entry; /* driver uses to specify entry, OS writes */ 1100 }; 1101 1102 1103 #ifndef CONFIG_PCI_MSI 1104 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) 1105 { 1106 return -1; 1107 } 1108 1109 static inline int 1110 pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) 1111 { 1112 return -1; 1113 } 1114 1115 static inline void pci_msi_shutdown(struct pci_dev *dev) 1116 { } 1117 static inline void pci_disable_msi(struct pci_dev *dev) 1118 { } 1119 1120 static inline int pci_msix_table_size(struct pci_dev *dev) 1121 { 1122 return 0; 1123 } 1124 static inline int pci_enable_msix(struct pci_dev *dev, 1125 struct msix_entry *entries, int nvec) 1126 { 1127 return -1; 1128 } 1129 1130 static inline void pci_msix_shutdown(struct pci_dev *dev) 1131 { } 1132 static inline void pci_disable_msix(struct pci_dev *dev) 1133 { } 1134 1135 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) 1136 { } 1137 1138 static inline void pci_restore_msi_state(struct pci_dev *dev) 1139 { } 1140 static inline int pci_msi_enabled(void) 1141 { 1142 return 0; 1143 } 1144 #else 1145 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); 1146 extern int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec); 1147 extern void pci_msi_shutdown(struct pci_dev *dev); 1148 extern void pci_disable_msi(struct pci_dev *dev); 1149 extern int pci_msix_table_size(struct pci_dev *dev); 1150 extern int pci_enable_msix(struct pci_dev *dev, 1151 struct msix_entry *entries, int nvec); 1152 extern void pci_msix_shutdown(struct pci_dev *dev); 1153 extern void pci_disable_msix(struct pci_dev *dev); 1154 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); 1155 extern void pci_restore_msi_state(struct pci_dev *dev); 1156 extern int pci_msi_enabled(void); 1157 #endif 1158 1159 #ifdef CONFIG_PCIEPORTBUS 1160 extern bool pcie_ports_disabled; 1161 extern bool pcie_ports_auto; 1162 #else 1163 #define pcie_ports_disabled true 1164 #define pcie_ports_auto false 1165 #endif 1166 1167 #ifndef CONFIG_PCIEASPM 1168 static inline int pcie_aspm_enabled(void) { return 0; } 1169 static inline bool pcie_aspm_support_enabled(void) { return false; } 1170 #else 1171 extern int pcie_aspm_enabled(void); 1172 extern bool pcie_aspm_support_enabled(void); 1173 #endif 1174 1175 #ifdef CONFIG_PCIEAER 1176 void pci_no_aer(void); 1177 bool pci_aer_available(void); 1178 #else 1179 static inline void pci_no_aer(void) { } 1180 static inline bool pci_aer_available(void) { return false; } 1181 #endif 1182 1183 #ifndef CONFIG_PCIE_ECRC 1184 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) 1185 { 1186 return; 1187 } 1188 static inline void pcie_ecrc_get_policy(char *str) {}; 1189 #else 1190 extern void pcie_set_ecrc_checking(struct pci_dev *dev); 1191 extern void pcie_ecrc_get_policy(char *str); 1192 #endif 1193 1194 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) 1195 1196 #ifdef CONFIG_HT_IRQ 1197 /* The functions a driver should call */ 1198 int ht_create_irq(struct pci_dev *dev, int idx); 1199 void ht_destroy_irq(unsigned int irq); 1200 #endif /* CONFIG_HT_IRQ */ 1201 1202 extern void pci_cfg_access_lock(struct pci_dev *dev); 1203 extern bool pci_cfg_access_trylock(struct pci_dev *dev); 1204 extern void pci_cfg_access_unlock(struct pci_dev *dev); 1205 1206 /* 1207 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1208 * a PCI domain is defined to be a set of PCI busses which share 1209 * configuration space. 1210 */ 1211 #ifdef CONFIG_PCI_DOMAINS 1212 extern int pci_domains_supported; 1213 #else 1214 enum { pci_domains_supported = 0 }; 1215 static inline int pci_domain_nr(struct pci_bus *bus) 1216 { 1217 return 0; 1218 } 1219 1220 static inline int pci_proc_domain(struct pci_bus *bus) 1221 { 1222 return 0; 1223 } 1224 #endif /* CONFIG_PCI_DOMAINS */ 1225 1226 /* some architectures require additional setup to direct VGA traffic */ 1227 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1228 unsigned int command_bits, u32 flags); 1229 extern void pci_register_set_vga_state(arch_set_vga_state_t func); 1230 1231 #else /* CONFIG_PCI is not enabled */ 1232 1233 /* 1234 * If the system does not have PCI, clearly these return errors. Define 1235 * these as simple inline functions to avoid hair in drivers. 1236 */ 1237 1238 #define _PCI_NOP(o, s, t) \ 1239 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1240 int where, t val) \ 1241 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1242 1243 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1244 _PCI_NOP(o, word, u16 x) \ 1245 _PCI_NOP(o, dword, u32 x) 1246 _PCI_NOP_ALL(read, *) 1247 _PCI_NOP_ALL(write,) 1248 1249 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1250 unsigned int device, 1251 struct pci_dev *from) 1252 { 1253 return NULL; 1254 } 1255 1256 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1257 unsigned int device, 1258 unsigned int ss_vendor, 1259 unsigned int ss_device, 1260 struct pci_dev *from) 1261 { 1262 return NULL; 1263 } 1264 1265 static inline struct pci_dev *pci_get_class(unsigned int class, 1266 struct pci_dev *from) 1267 { 1268 return NULL; 1269 } 1270 1271 #define pci_dev_present(ids) (0) 1272 #define no_pci_devices() (1) 1273 #define pci_dev_put(dev) do { } while (0) 1274 1275 static inline void pci_set_master(struct pci_dev *dev) 1276 { } 1277 1278 static inline int pci_enable_device(struct pci_dev *dev) 1279 { 1280 return -EIO; 1281 } 1282 1283 static inline void pci_disable_device(struct pci_dev *dev) 1284 { } 1285 1286 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1287 { 1288 return -EIO; 1289 } 1290 1291 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1292 { 1293 return -EIO; 1294 } 1295 1296 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1297 unsigned int size) 1298 { 1299 return -EIO; 1300 } 1301 1302 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1303 unsigned long mask) 1304 { 1305 return -EIO; 1306 } 1307 1308 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1309 { 1310 return -EBUSY; 1311 } 1312 1313 static inline int __pci_register_driver(struct pci_driver *drv, 1314 struct module *owner) 1315 { 1316 return 0; 1317 } 1318 1319 static inline int pci_register_driver(struct pci_driver *drv) 1320 { 1321 return 0; 1322 } 1323 1324 static inline void pci_unregister_driver(struct pci_driver *drv) 1325 { } 1326 1327 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1328 { 1329 return 0; 1330 } 1331 1332 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1333 int cap) 1334 { 1335 return 0; 1336 } 1337 1338 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1339 { 1340 return 0; 1341 } 1342 1343 /* Power management related routines */ 1344 static inline int pci_save_state(struct pci_dev *dev) 1345 { 1346 return 0; 1347 } 1348 1349 static inline void pci_restore_state(struct pci_dev *dev) 1350 { } 1351 1352 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1353 { 1354 return 0; 1355 } 1356 1357 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1358 { 1359 return 0; 1360 } 1361 1362 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1363 pm_message_t state) 1364 { 1365 return PCI_D0; 1366 } 1367 1368 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1369 int enable) 1370 { 1371 return 0; 1372 } 1373 1374 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type) 1375 { 1376 } 1377 1378 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type) 1379 { 1380 } 1381 1382 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type) 1383 { 1384 return 0; 1385 } 1386 1387 static inline void pci_disable_obff(struct pci_dev *dev) 1388 { 1389 } 1390 1391 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1392 { 1393 return -EIO; 1394 } 1395 1396 static inline void pci_release_regions(struct pci_dev *dev) 1397 { } 1398 1399 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 1400 1401 static inline void pci_block_cfg_access(struct pci_dev *dev) 1402 { } 1403 1404 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1405 { return 0; } 1406 1407 static inline void pci_unblock_cfg_access(struct pci_dev *dev) 1408 { } 1409 1410 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1411 { return NULL; } 1412 1413 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1414 unsigned int devfn) 1415 { return NULL; } 1416 1417 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1418 unsigned int devfn) 1419 { return NULL; } 1420 1421 static inline int pci_domain_nr(struct pci_bus *bus) 1422 { return 0; } 1423 1424 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) 1425 { return NULL; } 1426 1427 #define dev_is_pci(d) (false) 1428 #define dev_is_pf(d) (false) 1429 #define dev_num_vf(d) (0) 1430 #endif /* CONFIG_PCI */ 1431 1432 /* Include architecture-dependent settings and functions */ 1433 1434 #include <asm/pci.h> 1435 1436 #ifndef PCIBIOS_MAX_MEM_32 1437 #define PCIBIOS_MAX_MEM_32 (-1) 1438 #endif 1439 1440 /* these helpers provide future and backwards compatibility 1441 * for accessing popular PCI BAR info */ 1442 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1443 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1444 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1445 #define pci_resource_len(dev,bar) \ 1446 ((pci_resource_start((dev), (bar)) == 0 && \ 1447 pci_resource_end((dev), (bar)) == \ 1448 pci_resource_start((dev), (bar))) ? 0 : \ 1449 \ 1450 (pci_resource_end((dev), (bar)) - \ 1451 pci_resource_start((dev), (bar)) + 1)) 1452 1453 /* Similar to the helpers above, these manipulate per-pci_dev 1454 * driver-specific data. They are really just a wrapper around 1455 * the generic device structure functions of these calls. 1456 */ 1457 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1458 { 1459 return dev_get_drvdata(&pdev->dev); 1460 } 1461 1462 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1463 { 1464 dev_set_drvdata(&pdev->dev, data); 1465 } 1466 1467 /* If you want to know what to call your pci_dev, ask this function. 1468 * Again, it's a wrapper around the generic device. 1469 */ 1470 static inline const char *pci_name(const struct pci_dev *pdev) 1471 { 1472 return dev_name(&pdev->dev); 1473 } 1474 1475 1476 /* Some archs don't want to expose struct resource to userland as-is 1477 * in sysfs and /proc 1478 */ 1479 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1480 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1481 const struct resource *rsrc, resource_size_t *start, 1482 resource_size_t *end) 1483 { 1484 *start = rsrc->start; 1485 *end = rsrc->end; 1486 } 1487 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1488 1489 1490 /* 1491 * The world is not perfect and supplies us with broken PCI devices. 1492 * For at least a part of these bugs we need a work-around, so both 1493 * generic (drivers/pci/quirks.c) and per-architecture code can define 1494 * fixup hooks to be called for particular buggy devices. 1495 */ 1496 1497 struct pci_fixup { 1498 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1499 u16 device; /* You can use PCI_ANY_ID here of course */ 1500 u32 class; /* You can use PCI_ANY_ID here too */ 1501 unsigned int class_shift; /* should be 0, 8, 16 */ 1502 void (*hook)(struct pci_dev *dev); 1503 }; 1504 1505 enum pci_fixup_pass { 1506 pci_fixup_early, /* Before probing BARs */ 1507 pci_fixup_header, /* After reading configuration header */ 1508 pci_fixup_final, /* Final phase of device fixups */ 1509 pci_fixup_enable, /* pci_enable_device() time */ 1510 pci_fixup_resume, /* pci_device_resume() */ 1511 pci_fixup_suspend, /* pci_device_suspend */ 1512 pci_fixup_resume_early, /* pci_device_resume_early() */ 1513 }; 1514 1515 /* Anonymous variables would be nice... */ 1516 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1517 class_shift, hook) \ 1518 static const struct pci_fixup __pci_fixup_##name __used \ 1519 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1520 = { vendor, device, class, class_shift, hook }; 1521 1522 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1523 class_shift, hook) \ 1524 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1525 vendor##device##hook, vendor, device, class, class_shift, hook) 1526 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1527 class_shift, hook) \ 1528 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1529 vendor##device##hook, vendor, device, class, class_shift, hook) 1530 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1531 class_shift, hook) \ 1532 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1533 vendor##device##hook, vendor, device, class, class_shift, hook) 1534 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1535 class_shift, hook) \ 1536 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1537 vendor##device##hook, vendor, device, class, class_shift, hook) 1538 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1539 class_shift, hook) \ 1540 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1541 resume##vendor##device##hook, vendor, device, class, \ 1542 class_shift, hook) 1543 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1544 class_shift, hook) \ 1545 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1546 resume_early##vendor##device##hook, vendor, device, \ 1547 class, class_shift, hook) 1548 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1549 class_shift, hook) \ 1550 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1551 suspend##vendor##device##hook, vendor, device, class, \ 1552 class_shift, hook) 1553 1554 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1555 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1556 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) 1557 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1558 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1559 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) 1560 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1561 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1562 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) 1563 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1564 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1565 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) 1566 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1567 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1568 resume##vendor##device##hook, vendor, device, \ 1569 PCI_ANY_ID, 0, hook) 1570 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1571 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1572 resume_early##vendor##device##hook, vendor, device, \ 1573 PCI_ANY_ID, 0, hook) 1574 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1575 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1576 suspend##vendor##device##hook, vendor, device, \ 1577 PCI_ANY_ID, 0, hook) 1578 1579 #ifdef CONFIG_PCI_QUIRKS 1580 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1581 struct pci_dev *pci_get_dma_source(struct pci_dev *dev); 1582 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1583 #else 1584 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1585 struct pci_dev *dev) {} 1586 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev) 1587 { 1588 return pci_dev_get(dev); 1589 } 1590 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1591 u16 acs_flags) 1592 { 1593 return -ENOTTY; 1594 } 1595 #endif 1596 1597 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1598 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1599 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1600 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1601 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1602 const char *name); 1603 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1604 1605 extern int pci_pci_problems; 1606 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1607 #define PCIPCI_TRITON 2 1608 #define PCIPCI_NATOMA 4 1609 #define PCIPCI_VIAETBF 8 1610 #define PCIPCI_VSFX 16 1611 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1612 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1613 1614 extern unsigned long pci_cardbus_io_size; 1615 extern unsigned long pci_cardbus_mem_size; 1616 extern u8 pci_dfl_cache_line_size; 1617 extern u8 pci_cache_line_size; 1618 1619 extern unsigned long pci_hotplug_io_size; 1620 extern unsigned long pci_hotplug_mem_size; 1621 1622 /* Architecture specific versions may override these (weak) */ 1623 int pcibios_add_platform_entries(struct pci_dev *dev); 1624 void pcibios_disable_device(struct pci_dev *dev); 1625 void pcibios_set_master(struct pci_dev *dev); 1626 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1627 enum pcie_reset_state state); 1628 int pcibios_add_device(struct pci_dev *dev); 1629 1630 #ifdef CONFIG_PCI_MMCONFIG 1631 extern void __init pci_mmcfg_early_init(void); 1632 extern void __init pci_mmcfg_late_init(void); 1633 #else 1634 static inline void pci_mmcfg_early_init(void) { } 1635 static inline void pci_mmcfg_late_init(void) { } 1636 #endif 1637 1638 int pci_ext_cfg_avail(void); 1639 1640 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1641 1642 #ifdef CONFIG_PCI_IOV 1643 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1644 extern void pci_disable_sriov(struct pci_dev *dev); 1645 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev); 1646 extern int pci_num_vf(struct pci_dev *dev); 1647 extern int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1648 extern int pci_sriov_get_totalvfs(struct pci_dev *dev); 1649 #else 1650 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1651 { 1652 return -ENODEV; 1653 } 1654 static inline void pci_disable_sriov(struct pci_dev *dev) 1655 { 1656 } 1657 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) 1658 { 1659 return IRQ_NONE; 1660 } 1661 static inline int pci_num_vf(struct pci_dev *dev) 1662 { 1663 return 0; 1664 } 1665 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1666 { 1667 return 0; 1668 } 1669 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1670 { 1671 return 0; 1672 } 1673 #endif 1674 1675 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1676 extern void pci_hp_create_module_link(struct pci_slot *pci_slot); 1677 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1678 #endif 1679 1680 /** 1681 * pci_pcie_cap - get the saved PCIe capability offset 1682 * @dev: PCI device 1683 * 1684 * PCIe capability offset is calculated at PCI device initialization 1685 * time and saved in the data structure. This function returns saved 1686 * PCIe capability offset. Using this instead of pci_find_capability() 1687 * reduces unnecessary search in the PCI configuration space. If you 1688 * need to calculate PCIe capability offset from raw device for some 1689 * reasons, please use pci_find_capability() instead. 1690 */ 1691 static inline int pci_pcie_cap(struct pci_dev *dev) 1692 { 1693 return dev->pcie_cap; 1694 } 1695 1696 /** 1697 * pci_is_pcie - check if the PCI device is PCI Express capable 1698 * @dev: PCI device 1699 * 1700 * Retrun true if the PCI device is PCI Express capable, false otherwise. 1701 */ 1702 static inline bool pci_is_pcie(struct pci_dev *dev) 1703 { 1704 return !!pci_pcie_cap(dev); 1705 } 1706 1707 /** 1708 * pcie_caps_reg - get the PCIe Capabilities Register 1709 * @dev: PCI device 1710 */ 1711 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1712 { 1713 return dev->pcie_flags_reg; 1714 } 1715 1716 /** 1717 * pci_pcie_type - get the PCIe device/port type 1718 * @dev: PCI device 1719 */ 1720 static inline int pci_pcie_type(const struct pci_dev *dev) 1721 { 1722 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1723 } 1724 1725 void pci_request_acs(void); 1726 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1727 bool pci_acs_path_enabled(struct pci_dev *start, 1728 struct pci_dev *end, u16 acs_flags); 1729 1730 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1731 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) 1732 1733 /* Large Resource Data Type Tag Item Names */ 1734 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1735 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1736 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1737 1738 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1739 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1740 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1741 1742 /* Small Resource Data Type Tag Item Names */ 1743 #define PCI_VPD_STIN_END 0x78 /* End */ 1744 1745 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1746 1747 #define PCI_VPD_SRDT_TIN_MASK 0x78 1748 #define PCI_VPD_SRDT_LEN_MASK 0x07 1749 1750 #define PCI_VPD_LRDT_TAG_SIZE 3 1751 #define PCI_VPD_SRDT_TAG_SIZE 1 1752 1753 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1754 1755 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1756 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1757 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1758 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1759 1760 /** 1761 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1762 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1763 * 1764 * Returns the extracted Large Resource Data Type length. 1765 */ 1766 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1767 { 1768 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1769 } 1770 1771 /** 1772 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1773 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1774 * 1775 * Returns the extracted Small Resource Data Type length. 1776 */ 1777 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1778 { 1779 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1780 } 1781 1782 /** 1783 * pci_vpd_info_field_size - Extracts the information field length 1784 * @lrdt: Pointer to the beginning of an information field header 1785 * 1786 * Returns the extracted information field length. 1787 */ 1788 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1789 { 1790 return info_field[2]; 1791 } 1792 1793 /** 1794 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1795 * @buf: Pointer to buffered vpd data 1796 * @off: The offset into the buffer at which to begin the search 1797 * @len: The length of the vpd buffer 1798 * @rdt: The Resource Data Type to search for 1799 * 1800 * Returns the index where the Resource Data Type was found or 1801 * -ENOENT otherwise. 1802 */ 1803 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1804 1805 /** 1806 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1807 * @buf: Pointer to buffered vpd data 1808 * @off: The offset into the buffer at which to begin the search 1809 * @len: The length of the buffer area, relative to off, in which to search 1810 * @kw: The keyword to search for 1811 * 1812 * Returns the index where the information field keyword was found or 1813 * -ENOENT otherwise. 1814 */ 1815 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1816 unsigned int len, const char *kw); 1817 1818 /* PCI <-> OF binding helpers */ 1819 #ifdef CONFIG_OF 1820 struct device_node; 1821 extern void pci_set_of_node(struct pci_dev *dev); 1822 extern void pci_release_of_node(struct pci_dev *dev); 1823 extern void pci_set_bus_of_node(struct pci_bus *bus); 1824 extern void pci_release_bus_of_node(struct pci_bus *bus); 1825 1826 /* Arch may override this (weak) */ 1827 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus); 1828 1829 static inline struct device_node * 1830 pci_device_to_OF_node(const struct pci_dev *pdev) 1831 { 1832 return pdev ? pdev->dev.of_node : NULL; 1833 } 1834 1835 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1836 { 1837 return bus ? bus->dev.of_node : NULL; 1838 } 1839 1840 #else /* CONFIG_OF */ 1841 static inline void pci_set_of_node(struct pci_dev *dev) { } 1842 static inline void pci_release_of_node(struct pci_dev *dev) { } 1843 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1844 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1845 #endif /* CONFIG_OF */ 1846 1847 #ifdef CONFIG_EEH 1848 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1849 { 1850 return pdev->dev.archdata.edev; 1851 } 1852 #endif 1853 1854 /** 1855 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device 1856 * @pdev: the PCI device 1857 * 1858 * if the device is PCIE, return NULL 1859 * if the device isn't connected to a PCIe bridge (that is its parent is a 1860 * legacy PCI bridge and the bridge is directly connected to bus 0), return its 1861 * parent 1862 */ 1863 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); 1864 1865 #endif /* LINUX_PCI_H */ 1866