1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * For more information, please consult the following manuals (look at 10 * http://www.pcisig.com/ for how to get them): 11 * 12 * PCI BIOS Specification 13 * PCI Local Bus Specification 14 * PCI to PCI Bridge Specification 15 * PCI System Design Guide 16 */ 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 21 #include <linux/mod_devicetable.h> 22 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/list.h> 27 #include <linux/compiler.h> 28 #include <linux/errno.h> 29 #include <linux/kobject.h> 30 #include <linux/atomic.h> 31 #include <linux/device.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/resource_ext.h> 35 #include <uapi/linux/pci.h> 36 37 #include <linux/pci_ids.h> 38 39 /* 40 * The PCI interface treats multi-function devices as independent 41 * devices. The slot/function address of each device is encoded 42 * in a single byte as follows: 43 * 44 * 7:3 = slot 45 * 2:0 = function 46 * 47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 48 * In the interest of not exposing interfaces to user-space unnecessarily, 49 * the following kernel-only defines are being added here. 50 */ 51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 54 55 /* pci_slot represents a physical slot */ 56 struct pci_slot { 57 struct pci_bus *bus; /* Bus this slot is on */ 58 struct list_head list; /* Node in list of slots */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 61 struct kobject kobj; 62 }; 63 64 static inline const char *pci_slot_name(const struct pci_slot *slot) 65 { 66 return kobject_name(&slot->kobj); 67 } 68 69 /* File state for mmap()s on /proc/bus/pci/X/Y */ 70 enum pci_mmap_state { 71 pci_mmap_io, 72 pci_mmap_mem 73 }; 74 75 /* For PCI devices, the region numbers are assigned this way: */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* Device-specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* Resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* Total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* Preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 /** 105 * enum pci_interrupt_pin - PCI INTx interrupt values 106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 107 * @PCI_INTERRUPT_INTA: PCI INTA pin 108 * @PCI_INTERRUPT_INTB: PCI INTB pin 109 * @PCI_INTERRUPT_INTC: PCI INTC pin 110 * @PCI_INTERRUPT_INTD: PCI INTD pin 111 * 112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 113 * PCI_INTERRUPT_PIN register. 114 */ 115 enum pci_interrupt_pin { 116 PCI_INTERRUPT_UNKNOWN, 117 PCI_INTERRUPT_INTA, 118 PCI_INTERRUPT_INTB, 119 PCI_INTERRUPT_INTC, 120 PCI_INTERRUPT_INTD, 121 }; 122 123 /* The number of legacy PCI INTx interrupts */ 124 #define PCI_NUM_INTX 4 125 126 /* 127 * pci_power_t values must match the bits in the Capabilities PME_Support 128 * and Control/Status PowerState fields in the Power Management capability. 129 */ 130 typedef int __bitwise pci_power_t; 131 132 #define PCI_D0 ((pci_power_t __force) 0) 133 #define PCI_D1 ((pci_power_t __force) 1) 134 #define PCI_D2 ((pci_power_t __force) 2) 135 #define PCI_D3hot ((pci_power_t __force) 3) 136 #define PCI_D3cold ((pci_power_t __force) 4) 137 #define PCI_UNKNOWN ((pci_power_t __force) 5) 138 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 139 140 /* Remember to update this when the list above changes! */ 141 extern const char *pci_power_names[]; 142 143 static inline const char *pci_power_name(pci_power_t state) 144 { 145 return pci_power_names[1 + (__force int) state]; 146 } 147 148 #define PCI_PM_D2_DELAY 200 149 #define PCI_PM_D3_WAIT 10 150 #define PCI_PM_D3COLD_WAIT 100 151 #define PCI_PM_BUS_WAIT 50 152 153 /** 154 * The pci_channel state describes connectivity between the CPU and 155 * the PCI device. If some PCI bus between here and the PCI device 156 * has crashed or locked up, this info is reflected here. 157 */ 158 typedef unsigned int __bitwise pci_channel_state_t; 159 160 enum pci_channel_state { 161 /* I/O channel is in normal state */ 162 pci_channel_io_normal = (__force pci_channel_state_t) 1, 163 164 /* I/O to channel is blocked */ 165 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 166 167 /* PCI card is dead */ 168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 169 }; 170 171 typedef unsigned int __bitwise pcie_reset_state_t; 172 173 enum pcie_reset_state { 174 /* Reset is NOT asserted (Use to deassert reset) */ 175 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 176 177 /* Use #PERST to reset PCIe device */ 178 pcie_warm_reset = (__force pcie_reset_state_t) 2, 179 180 /* Use PCIe Hot Reset to reset device */ 181 pcie_hot_reset = (__force pcie_reset_state_t) 3 182 }; 183 184 typedef unsigned short __bitwise pci_dev_flags_t; 185 enum pci_dev_flags { 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 188 /* Device configuration is irrevocably lost if disabled into D3 */ 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 190 /* Provide indication device is assigned by a Virtual Machine Manager */ 191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 192 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 196 /* Do not use bus resets for device */ 197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 198 /* Do not use PM reset even if device advertises NoSoftRst- */ 199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 200 /* Get VPD from function 0 VPD */ 201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 202 /* A non-root bridge where translation occurs, stop alias search here */ 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 204 /* Do not use FLR even if device advertises PCI_AF_CAP */ 205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 206 /* Don't use Relaxed Ordering for TLPs directed at this device */ 207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 208 }; 209 210 enum pci_irq_reroute_variant { 211 INTEL_IRQ_REROUTE_VARIANT = 1, 212 MAX_IRQ_REROUTE_VARIANTS = 3 213 }; 214 215 typedef unsigned short __bitwise pci_bus_flags_t; 216 enum pci_bus_flags { 217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 221 }; 222 223 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 224 enum pcie_link_width { 225 PCIE_LNK_WIDTH_RESRV = 0x00, 226 PCIE_LNK_X1 = 0x01, 227 PCIE_LNK_X2 = 0x02, 228 PCIE_LNK_X4 = 0x04, 229 PCIE_LNK_X8 = 0x08, 230 PCIE_LNK_X12 = 0x0c, 231 PCIE_LNK_X16 = 0x10, 232 PCIE_LNK_X32 = 0x20, 233 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 234 }; 235 236 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 237 enum pci_bus_speed { 238 PCI_SPEED_33MHz = 0x00, 239 PCI_SPEED_66MHz = 0x01, 240 PCI_SPEED_66MHz_PCIX = 0x02, 241 PCI_SPEED_100MHz_PCIX = 0x03, 242 PCI_SPEED_133MHz_PCIX = 0x04, 243 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 244 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 245 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 246 PCI_SPEED_66MHz_PCIX_266 = 0x09, 247 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 248 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 249 AGP_UNKNOWN = 0x0c, 250 AGP_1X = 0x0d, 251 AGP_2X = 0x0e, 252 AGP_4X = 0x0f, 253 AGP_8X = 0x10, 254 PCI_SPEED_66MHz_PCIX_533 = 0x11, 255 PCI_SPEED_100MHz_PCIX_533 = 0x12, 256 PCI_SPEED_133MHz_PCIX_533 = 0x13, 257 PCIE_SPEED_2_5GT = 0x14, 258 PCIE_SPEED_5_0GT = 0x15, 259 PCIE_SPEED_8_0GT = 0x16, 260 PCIE_SPEED_16_0GT = 0x17, 261 PCI_SPEED_UNKNOWN = 0xff, 262 }; 263 264 struct pci_cap_saved_data { 265 u16 cap_nr; 266 bool cap_extended; 267 unsigned int size; 268 u32 data[0]; 269 }; 270 271 struct pci_cap_saved_state { 272 struct hlist_node next; 273 struct pci_cap_saved_data cap; 274 }; 275 276 struct irq_affinity; 277 struct pcie_link_state; 278 struct pci_vpd; 279 struct pci_sriov; 280 struct pci_ats; 281 282 /* The pci_dev structure describes PCI devices */ 283 struct pci_dev { 284 struct list_head bus_list; /* Node in per-bus list */ 285 struct pci_bus *bus; /* Bus this device is on */ 286 struct pci_bus *subordinate; /* Bus this device bridges to */ 287 288 void *sysdata; /* Hook for sys-specific extension */ 289 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 290 struct pci_slot *slot; /* Physical slot this device is in */ 291 292 unsigned int devfn; /* Encoded device & function index */ 293 unsigned short vendor; 294 unsigned short device; 295 unsigned short subsystem_vendor; 296 unsigned short subsystem_device; 297 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 298 u8 revision; /* PCI revision, low byte of class word */ 299 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 300 #ifdef CONFIG_PCIEAER 301 u16 aer_cap; /* AER capability offset */ 302 #endif 303 u8 pcie_cap; /* PCIe capability offset */ 304 u8 msi_cap; /* MSI capability offset */ 305 u8 msix_cap; /* MSI-X capability offset */ 306 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 307 u8 rom_base_reg; /* Config register controlling ROM */ 308 u8 pin; /* Interrupt pin this device uses */ 309 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 310 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 311 312 struct pci_driver *driver; /* Driver bound to this device */ 313 u64 dma_mask; /* Mask of the bits of bus address this 314 device implements. Normally this is 315 0xffffffff. You only need to change 316 this if your device has broken DMA 317 or supports 64-bit transfers. */ 318 319 struct device_dma_parameters dma_parms; 320 321 pci_power_t current_state; /* Current operating state. In ACPI, 322 this is D0-D3, D0 being fully 323 functional, and D3 being off. */ 324 u8 pm_cap; /* PM capability offset */ 325 unsigned int pme_support:5; /* Bitmask of states from which PME# 326 can be generated */ 327 unsigned int pme_poll:1; /* Poll device's PME status bit */ 328 unsigned int d1_support:1; /* Low power state D1 is supported */ 329 unsigned int d2_support:1; /* Low power state D2 is supported */ 330 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 331 unsigned int no_d3cold:1; /* D3cold is forbidden */ 332 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 333 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 334 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 335 decoding during BAR sizing */ 336 unsigned int wakeup_prepared:1; 337 unsigned int runtime_d3cold:1; /* Whether go through runtime 338 D3cold, not set for devices 339 powered on/off by the 340 corresponding bridge */ 341 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 342 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 343 controlled exclusively by 344 user sysfs */ 345 unsigned int d3_delay; /* D3->D0 transition time in ms */ 346 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 347 348 #ifdef CONFIG_PCIEASPM 349 struct pcie_link_state *link_state; /* ASPM link state */ 350 unsigned int ltr_path:1; /* Latency Tolerance Reporting 351 supported from root to here */ 352 #endif 353 354 pci_channel_state_t error_state; /* Current connectivity state */ 355 struct device dev; /* Generic device interface */ 356 357 int cfg_size; /* Size of config space */ 358 359 /* 360 * Instead of touching interrupt line and base address registers 361 * directly, use the values stored here. They might be different! 362 */ 363 unsigned int irq; 364 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 365 366 bool match_driver; /* Skip attaching driver */ 367 368 unsigned int transparent:1; /* Subtractive decode bridge */ 369 unsigned int multifunction:1; /* Multi-function device */ 370 371 unsigned int is_busmaster:1; /* Is busmaster */ 372 unsigned int no_msi:1; /* May not use MSI */ 373 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 374 unsigned int block_cfg_access:1; /* Config space access blocked */ 375 unsigned int broken_parity_status:1; /* Generates false positive parity */ 376 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 377 unsigned int msi_enabled:1; 378 unsigned int msix_enabled:1; 379 unsigned int ari_enabled:1; /* ARI forwarding */ 380 unsigned int ats_enabled:1; /* Address Translation Svc */ 381 unsigned int pasid_enabled:1; /* Process Address Space ID */ 382 unsigned int pri_enabled:1; /* Page Request Interface */ 383 unsigned int is_managed:1; 384 unsigned int needs_freset:1; /* Requires fundamental reset */ 385 unsigned int state_saved:1; 386 unsigned int is_physfn:1; 387 unsigned int is_virtfn:1; 388 unsigned int reset_fn:1; 389 unsigned int is_hotplug_bridge:1; 390 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 391 unsigned int __aer_firmware_first_valid:1; 392 unsigned int __aer_firmware_first:1; 393 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 394 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 395 unsigned int irq_managed:1; 396 unsigned int has_secondary_link:1; 397 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 398 unsigned int is_probed:1; /* Device probing in progress */ 399 pci_dev_flags_t dev_flags; 400 atomic_t enable_cnt; /* pci_enable_device has been called */ 401 402 u32 saved_config_space[16]; /* Config space saved at suspend time */ 403 struct hlist_head saved_cap_space; 404 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 405 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 406 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 407 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 408 409 #ifdef CONFIG_HOTPLUG_PCI_PCIE 410 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 411 #endif 412 #ifdef CONFIG_PCIE_PTM 413 unsigned int ptm_root:1; 414 unsigned int ptm_enabled:1; 415 u8 ptm_granularity; 416 #endif 417 #ifdef CONFIG_PCI_MSI 418 const struct attribute_group **msi_irq_groups; 419 #endif 420 struct pci_vpd *vpd; 421 #ifdef CONFIG_PCI_ATS 422 union { 423 struct pci_sriov *sriov; /* PF: SR-IOV info */ 424 struct pci_dev *physfn; /* VF: related PF */ 425 }; 426 u16 ats_cap; /* ATS Capability offset */ 427 u8 ats_stu; /* ATS Smallest Translation Unit */ 428 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ 429 #endif 430 #ifdef CONFIG_PCI_PRI 431 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 432 #endif 433 #ifdef CONFIG_PCI_PASID 434 u16 pasid_features; 435 #endif 436 phys_addr_t rom; /* Physical address if not from BAR */ 437 size_t romlen; /* Length if not from BAR */ 438 char *driver_override; /* Driver name to force a match */ 439 440 unsigned long priv_flags; /* Private flags for the PCI driver */ 441 }; 442 443 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 444 { 445 #ifdef CONFIG_PCI_IOV 446 if (dev->is_virtfn) 447 dev = dev->physfn; 448 #endif 449 return dev; 450 } 451 452 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 453 454 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 455 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 456 457 static inline int pci_channel_offline(struct pci_dev *pdev) 458 { 459 return (pdev->error_state != pci_channel_io_normal); 460 } 461 462 struct pci_host_bridge { 463 struct device dev; 464 struct pci_bus *bus; /* Root bus */ 465 struct pci_ops *ops; 466 void *sysdata; 467 int busnr; 468 struct list_head windows; /* resource_entry */ 469 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 470 int (*map_irq)(const struct pci_dev *, u8, u8); 471 void (*release_fn)(struct pci_host_bridge *); 472 void *release_data; 473 struct msi_controller *msi; 474 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 475 unsigned int no_ext_tags:1; /* No Extended Tags */ 476 unsigned int native_aer:1; /* OS may use PCIe AER */ 477 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 478 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 479 unsigned int native_pme:1; /* OS may use PCIe PME */ 480 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 481 /* Resource alignment requirements */ 482 resource_size_t (*align_resource)(struct pci_dev *dev, 483 const struct resource *res, 484 resource_size_t start, 485 resource_size_t size, 486 resource_size_t align); 487 unsigned long private[0] ____cacheline_aligned; 488 }; 489 490 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 491 492 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 493 { 494 return (void *)bridge->private; 495 } 496 497 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 498 { 499 return container_of(priv, struct pci_host_bridge, private); 500 } 501 502 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 503 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 504 size_t priv); 505 void pci_free_host_bridge(struct pci_host_bridge *bridge); 506 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 507 508 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 509 void (*release_fn)(struct pci_host_bridge *), 510 void *release_data); 511 512 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 513 514 /* 515 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 516 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 517 * buses below host bridges or subtractive decode bridges) go in the list. 518 * Use pci_bus_for_each_resource() to iterate through all the resources. 519 */ 520 521 /* 522 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 523 * and there's no way to program the bridge with the details of the window. 524 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 525 * decode bit set, because they are explicit and can be programmed with _SRS. 526 */ 527 #define PCI_SUBTRACTIVE_DECODE 0x1 528 529 struct pci_bus_resource { 530 struct list_head list; 531 struct resource *res; 532 unsigned int flags; 533 }; 534 535 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 536 537 struct pci_bus { 538 struct list_head node; /* Node in list of buses */ 539 struct pci_bus *parent; /* Parent bus this bridge is on */ 540 struct list_head children; /* List of child buses */ 541 struct list_head devices; /* List of devices on this bus */ 542 struct pci_dev *self; /* Bridge device as seen by parent */ 543 struct list_head slots; /* List of slots on this bus; 544 protected by pci_slot_mutex */ 545 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 546 struct list_head resources; /* Address space routed to this bus */ 547 struct resource busn_res; /* Bus numbers routed to this bus */ 548 549 struct pci_ops *ops; /* Configuration access functions */ 550 struct msi_controller *msi; /* MSI controller */ 551 void *sysdata; /* Hook for sys-specific extension */ 552 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 553 554 unsigned char number; /* Bus number */ 555 unsigned char primary; /* Number of primary bridge */ 556 unsigned char max_bus_speed; /* enum pci_bus_speed */ 557 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 558 #ifdef CONFIG_PCI_DOMAINS_GENERIC 559 int domain_nr; 560 #endif 561 562 char name[48]; 563 564 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 565 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 566 struct device *bridge; 567 struct device dev; 568 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 569 struct bin_attribute *legacy_mem; /* Legacy mem */ 570 unsigned int is_added:1; 571 }; 572 573 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 574 575 /* 576 * Returns true if the PCI bus is root (behind host-PCI bridge), 577 * false otherwise 578 * 579 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 580 * This is incorrect because "virtual" buses added for SR-IOV (via 581 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 582 */ 583 static inline bool pci_is_root_bus(struct pci_bus *pbus) 584 { 585 return !(pbus->parent); 586 } 587 588 /** 589 * pci_is_bridge - check if the PCI device is a bridge 590 * @dev: PCI device 591 * 592 * Return true if the PCI device is bridge whether it has subordinate 593 * or not. 594 */ 595 static inline bool pci_is_bridge(struct pci_dev *dev) 596 { 597 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 598 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 599 } 600 601 #define for_each_pci_bridge(dev, bus) \ 602 list_for_each_entry(dev, &bus->devices, bus_list) \ 603 if (!pci_is_bridge(dev)) {} else 604 605 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 606 { 607 dev = pci_physfn(dev); 608 if (pci_is_root_bus(dev->bus)) 609 return NULL; 610 611 return dev->bus->self; 612 } 613 614 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 615 void pci_put_host_bridge_device(struct device *dev); 616 617 #ifdef CONFIG_PCI_MSI 618 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 619 { 620 return pci_dev->msi_enabled || pci_dev->msix_enabled; 621 } 622 #else 623 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 624 #endif 625 626 /* Error values that may be returned by PCI functions */ 627 #define PCIBIOS_SUCCESSFUL 0x00 628 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 629 #define PCIBIOS_BAD_VENDOR_ID 0x83 630 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 631 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 632 #define PCIBIOS_SET_FAILED 0x88 633 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 634 635 /* Translate above to generic errno for passing back through non-PCI code */ 636 static inline int pcibios_err_to_errno(int err) 637 { 638 if (err <= PCIBIOS_SUCCESSFUL) 639 return err; /* Assume already errno */ 640 641 switch (err) { 642 case PCIBIOS_FUNC_NOT_SUPPORTED: 643 return -ENOENT; 644 case PCIBIOS_BAD_VENDOR_ID: 645 return -ENOTTY; 646 case PCIBIOS_DEVICE_NOT_FOUND: 647 return -ENODEV; 648 case PCIBIOS_BAD_REGISTER_NUMBER: 649 return -EFAULT; 650 case PCIBIOS_SET_FAILED: 651 return -EIO; 652 case PCIBIOS_BUFFER_TOO_SMALL: 653 return -ENOSPC; 654 } 655 656 return -ERANGE; 657 } 658 659 /* Low-level architecture-dependent routines */ 660 661 struct pci_ops { 662 int (*add_bus)(struct pci_bus *bus); 663 void (*remove_bus)(struct pci_bus *bus); 664 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 665 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 666 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 667 }; 668 669 /* 670 * ACPI needs to be able to access PCI config space before we've done a 671 * PCI bus scan and created pci_bus structures. 672 */ 673 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 674 int reg, int len, u32 *val); 675 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 676 int reg, int len, u32 val); 677 678 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 679 typedef u64 pci_bus_addr_t; 680 #else 681 typedef u32 pci_bus_addr_t; 682 #endif 683 684 struct pci_bus_region { 685 pci_bus_addr_t start; 686 pci_bus_addr_t end; 687 }; 688 689 struct pci_dynids { 690 spinlock_t lock; /* Protects list, index */ 691 struct list_head list; /* For IDs added at runtime */ 692 }; 693 694 695 /* 696 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 697 * a set of callbacks in struct pci_error_handlers, that device driver 698 * will be notified of PCI bus errors, and will be driven to recovery 699 * when an error occurs. 700 */ 701 702 typedef unsigned int __bitwise pci_ers_result_t; 703 704 enum pci_ers_result { 705 /* No result/none/not supported in device driver */ 706 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 707 708 /* Device driver can recover without slot reset */ 709 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 710 711 /* Device driver wants slot to be reset */ 712 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 713 714 /* Device has completely failed, is unrecoverable */ 715 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 716 717 /* Device driver is fully recovered and operational */ 718 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 719 720 /* No AER capabilities registered for the driver */ 721 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 722 }; 723 724 /* PCI bus error event callbacks */ 725 struct pci_error_handlers { 726 /* PCI bus error detected on this device */ 727 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 728 enum pci_channel_state error); 729 730 /* MMIO has been re-enabled, but not DMA */ 731 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 732 733 /* PCI slot has been reset */ 734 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 735 736 /* PCI function reset prepare or completed */ 737 void (*reset_prepare)(struct pci_dev *dev); 738 void (*reset_done)(struct pci_dev *dev); 739 740 /* Device driver may resume normal operations */ 741 void (*resume)(struct pci_dev *dev); 742 }; 743 744 745 struct module; 746 struct pci_driver { 747 struct list_head node; 748 const char *name; 749 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 750 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 751 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 752 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 753 int (*suspend_late)(struct pci_dev *dev, pm_message_t state); 754 int (*resume_early)(struct pci_dev *dev); 755 int (*resume) (struct pci_dev *dev); /* Device woken up */ 756 void (*shutdown) (struct pci_dev *dev); 757 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */ 758 const struct pci_error_handlers *err_handler; 759 const struct attribute_group **groups; 760 struct device_driver driver; 761 struct pci_dynids dynids; 762 }; 763 764 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 765 766 /** 767 * PCI_DEVICE - macro used to describe a specific PCI device 768 * @vend: the 16 bit PCI Vendor ID 769 * @dev: the 16 bit PCI Device ID 770 * 771 * This macro is used to create a struct pci_device_id that matches a 772 * specific device. The subvendor and subdevice fields will be set to 773 * PCI_ANY_ID. 774 */ 775 #define PCI_DEVICE(vend,dev) \ 776 .vendor = (vend), .device = (dev), \ 777 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 778 779 /** 780 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 781 * @vend: the 16 bit PCI Vendor ID 782 * @dev: the 16 bit PCI Device ID 783 * @subvend: the 16 bit PCI Subvendor ID 784 * @subdev: the 16 bit PCI Subdevice ID 785 * 786 * This macro is used to create a struct pci_device_id that matches a 787 * specific device with subsystem information. 788 */ 789 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 790 .vendor = (vend), .device = (dev), \ 791 .subvendor = (subvend), .subdevice = (subdev) 792 793 /** 794 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 795 * @dev_class: the class, subclass, prog-if triple for this device 796 * @dev_class_mask: the class mask for this device 797 * 798 * This macro is used to create a struct pci_device_id that matches a 799 * specific PCI class. The vendor, device, subvendor, and subdevice 800 * fields will be set to PCI_ANY_ID. 801 */ 802 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 803 .class = (dev_class), .class_mask = (dev_class_mask), \ 804 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 805 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 806 807 /** 808 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 809 * @vend: the vendor name 810 * @dev: the 16 bit PCI Device ID 811 * 812 * This macro is used to create a struct pci_device_id that matches a 813 * specific PCI device. The subvendor, and subdevice fields will be set 814 * to PCI_ANY_ID. The macro allows the next field to follow as the device 815 * private data. 816 */ 817 #define PCI_VDEVICE(vend, dev) \ 818 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 819 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 820 821 enum { 822 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 823 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 824 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 825 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 826 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 827 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 828 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 829 }; 830 831 /* These external functions are only available when PCI support is enabled */ 832 #ifdef CONFIG_PCI 833 834 extern unsigned int pci_flags; 835 836 static inline void pci_set_flags(int flags) { pci_flags = flags; } 837 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 838 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 839 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 840 841 void pcie_bus_configure_settings(struct pci_bus *bus); 842 843 enum pcie_bus_config_types { 844 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 845 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 846 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 847 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 848 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 849 }; 850 851 extern enum pcie_bus_config_types pcie_bus_config; 852 853 extern struct bus_type pci_bus_type; 854 855 /* Do NOT directly access these two variables, unless you are arch-specific PCI 856 * code, or PCI core code. */ 857 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 858 /* Some device drivers need know if PCI is initiated */ 859 int no_pci_devices(void); 860 861 void pcibios_resource_survey_bus(struct pci_bus *bus); 862 void pcibios_bus_add_device(struct pci_dev *pdev); 863 void pcibios_add_bus(struct pci_bus *bus); 864 void pcibios_remove_bus(struct pci_bus *bus); 865 void pcibios_fixup_bus(struct pci_bus *); 866 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 867 /* Architecture-specific versions may override this (weak) */ 868 char *pcibios_setup(char *str); 869 870 /* Used only when drivers/pci/setup.c is used */ 871 resource_size_t pcibios_align_resource(void *, const struct resource *, 872 resource_size_t, 873 resource_size_t); 874 875 /* Weak but can be overriden by arch */ 876 void pci_fixup_cardbus(struct pci_bus *); 877 878 /* Generic PCI functions used internally */ 879 880 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 881 struct resource *res); 882 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 883 struct pci_bus_region *region); 884 void pcibios_scan_specific_bus(int busn); 885 struct pci_bus *pci_find_bus(int domain, int busnr); 886 void pci_bus_add_devices(const struct pci_bus *bus); 887 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 888 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 889 struct pci_ops *ops, void *sysdata, 890 struct list_head *resources); 891 int pci_host_probe(struct pci_host_bridge *bridge); 892 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 893 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 894 void pci_bus_release_busn_res(struct pci_bus *b); 895 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 896 struct pci_ops *ops, void *sysdata, 897 struct list_head *resources); 898 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 899 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 900 int busnr); 901 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 902 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 903 const char *name, 904 struct hotplug_slot *hotplug); 905 void pci_destroy_slot(struct pci_slot *slot); 906 #ifdef CONFIG_SYSFS 907 void pci_dev_assign_slot(struct pci_dev *dev); 908 #else 909 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 910 #endif 911 int pci_scan_slot(struct pci_bus *bus, int devfn); 912 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 913 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 914 unsigned int pci_scan_child_bus(struct pci_bus *bus); 915 void pci_bus_add_device(struct pci_dev *dev); 916 void pci_read_bridge_bases(struct pci_bus *child); 917 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 918 struct resource *res); 919 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 920 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 921 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 922 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 923 struct pci_dev *pci_dev_get(struct pci_dev *dev); 924 void pci_dev_put(struct pci_dev *dev); 925 void pci_remove_bus(struct pci_bus *b); 926 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 927 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 928 void pci_stop_root_bus(struct pci_bus *bus); 929 void pci_remove_root_bus(struct pci_bus *bus); 930 void pci_setup_cardbus(struct pci_bus *bus); 931 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 932 void pci_sort_breadthfirst(void); 933 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 934 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 935 936 /* Generic PCI functions exported to card drivers */ 937 938 enum pci_lost_interrupt_reason { 939 PCI_LOST_IRQ_NO_INFORMATION = 0, 940 PCI_LOST_IRQ_DISABLE_MSI, 941 PCI_LOST_IRQ_DISABLE_MSIX, 942 PCI_LOST_IRQ_DISABLE_ACPI, 943 }; 944 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 945 int pci_find_capability(struct pci_dev *dev, int cap); 946 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 947 int pci_find_ext_capability(struct pci_dev *dev, int cap); 948 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 949 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 950 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 951 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 952 953 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 954 struct pci_dev *from); 955 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 956 unsigned int ss_vendor, unsigned int ss_device, 957 struct pci_dev *from); 958 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 959 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 960 unsigned int devfn); 961 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 962 int pci_dev_present(const struct pci_device_id *ids); 963 964 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 965 int where, u8 *val); 966 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 967 int where, u16 *val); 968 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 969 int where, u32 *val); 970 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 971 int where, u8 val); 972 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 973 int where, u16 val); 974 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 975 int where, u32 val); 976 977 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 978 int where, int size, u32 *val); 979 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 980 int where, int size, u32 val); 981 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 982 int where, int size, u32 *val); 983 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 984 int where, int size, u32 val); 985 986 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 987 988 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 989 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 990 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 991 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 992 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 993 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 994 995 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 996 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 997 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 998 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 999 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1000 u16 clear, u16 set); 1001 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1002 u32 clear, u32 set); 1003 1004 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1005 u16 set) 1006 { 1007 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1008 } 1009 1010 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1011 u32 set) 1012 { 1013 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1014 } 1015 1016 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1017 u16 clear) 1018 { 1019 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1020 } 1021 1022 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1023 u32 clear) 1024 { 1025 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1026 } 1027 1028 /* User-space driven config access */ 1029 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1030 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1031 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1032 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1033 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1034 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1035 1036 int __must_check pci_enable_device(struct pci_dev *dev); 1037 int __must_check pci_enable_device_io(struct pci_dev *dev); 1038 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1039 int __must_check pci_reenable_device(struct pci_dev *); 1040 int __must_check pcim_enable_device(struct pci_dev *pdev); 1041 void pcim_pin_device(struct pci_dev *pdev); 1042 1043 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1044 { 1045 /* 1046 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1047 * writable and no quirk has marked the feature broken. 1048 */ 1049 return !pdev->broken_intx_masking; 1050 } 1051 1052 static inline int pci_is_enabled(struct pci_dev *pdev) 1053 { 1054 return (atomic_read(&pdev->enable_cnt) > 0); 1055 } 1056 1057 static inline int pci_is_managed(struct pci_dev *pdev) 1058 { 1059 return pdev->is_managed; 1060 } 1061 1062 void pci_disable_device(struct pci_dev *dev); 1063 1064 extern unsigned int pcibios_max_latency; 1065 void pci_set_master(struct pci_dev *dev); 1066 void pci_clear_master(struct pci_dev *dev); 1067 1068 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1069 int pci_set_cacheline_size(struct pci_dev *dev); 1070 #define HAVE_PCI_SET_MWI 1071 int __must_check pci_set_mwi(struct pci_dev *dev); 1072 int __must_check pcim_set_mwi(struct pci_dev *dev); 1073 int pci_try_set_mwi(struct pci_dev *dev); 1074 void pci_clear_mwi(struct pci_dev *dev); 1075 void pci_intx(struct pci_dev *dev, int enable); 1076 bool pci_check_and_mask_intx(struct pci_dev *dev); 1077 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1078 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1079 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1080 int pcix_get_max_mmrbc(struct pci_dev *dev); 1081 int pcix_get_mmrbc(struct pci_dev *dev); 1082 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1083 int pcie_get_readrq(struct pci_dev *dev); 1084 int pcie_set_readrq(struct pci_dev *dev, int rq); 1085 int pcie_get_mps(struct pci_dev *dev); 1086 int pcie_set_mps(struct pci_dev *dev, int mps); 1087 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1088 enum pci_bus_speed *speed, 1089 enum pcie_link_width *width); 1090 void pcie_print_link_status(struct pci_dev *dev); 1091 int pcie_flr(struct pci_dev *dev); 1092 int __pci_reset_function_locked(struct pci_dev *dev); 1093 int pci_reset_function(struct pci_dev *dev); 1094 int pci_reset_function_locked(struct pci_dev *dev); 1095 int pci_try_reset_function(struct pci_dev *dev); 1096 int pci_probe_reset_slot(struct pci_slot *slot); 1097 int pci_reset_slot(struct pci_slot *slot); 1098 int pci_try_reset_slot(struct pci_slot *slot); 1099 int pci_probe_reset_bus(struct pci_bus *bus); 1100 int pci_reset_bus(struct pci_bus *bus); 1101 int pci_try_reset_bus(struct pci_bus *bus); 1102 void pci_reset_secondary_bus(struct pci_dev *dev); 1103 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1104 int pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1105 void pci_update_resource(struct pci_dev *dev, int resno); 1106 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1107 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1108 void pci_release_resource(struct pci_dev *dev, int resno); 1109 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1110 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1111 bool pci_device_is_present(struct pci_dev *pdev); 1112 void pci_ignore_hotplug(struct pci_dev *dev); 1113 1114 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1115 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1116 const char *fmt, ...); 1117 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1118 1119 /* ROM control related routines */ 1120 int pci_enable_rom(struct pci_dev *pdev); 1121 void pci_disable_rom(struct pci_dev *pdev); 1122 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1123 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1124 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1125 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1126 1127 /* Power management related routines */ 1128 int pci_save_state(struct pci_dev *dev); 1129 void pci_restore_state(struct pci_dev *dev); 1130 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1131 int pci_load_saved_state(struct pci_dev *dev, 1132 struct pci_saved_state *state); 1133 int pci_load_and_free_saved_state(struct pci_dev *dev, 1134 struct pci_saved_state **state); 1135 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1136 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1137 u16 cap); 1138 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1139 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1140 u16 cap, unsigned int size); 1141 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1142 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1143 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1144 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1145 void pci_pme_active(struct pci_dev *dev, bool enable); 1146 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1147 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1148 int pci_prepare_to_sleep(struct pci_dev *dev); 1149 int pci_back_from_sleep(struct pci_dev *dev); 1150 bool pci_dev_run_wake(struct pci_dev *dev); 1151 bool pci_check_pme_status(struct pci_dev *dev); 1152 void pci_pme_wakeup_bus(struct pci_bus *bus); 1153 void pci_d3cold_enable(struct pci_dev *dev); 1154 void pci_d3cold_disable(struct pci_dev *dev); 1155 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1156 void pci_wakeup_bus(struct pci_bus *bus); 1157 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1158 1159 /* PCI Virtual Channel */ 1160 int pci_save_vc_state(struct pci_dev *dev); 1161 void pci_restore_vc_state(struct pci_dev *dev); 1162 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1163 1164 /* For use by arch with custom probe code */ 1165 void set_pcie_port_type(struct pci_dev *pdev); 1166 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1167 1168 /* Functions for PCI Hotplug drivers to use */ 1169 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1170 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1171 unsigned int pci_rescan_bus(struct pci_bus *bus); 1172 void pci_lock_rescan_remove(void); 1173 void pci_unlock_rescan_remove(void); 1174 1175 /* Vital Product Data routines */ 1176 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1177 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1178 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1179 1180 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1181 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1182 void pci_bus_assign_resources(const struct pci_bus *bus); 1183 void pci_bus_claim_resources(struct pci_bus *bus); 1184 void pci_bus_size_bridges(struct pci_bus *bus); 1185 int pci_claim_resource(struct pci_dev *, int); 1186 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1187 void pci_assign_unassigned_resources(void); 1188 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1189 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1190 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1191 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1192 void pdev_enable_device(struct pci_dev *); 1193 int pci_enable_resources(struct pci_dev *, int mask); 1194 void pci_assign_irq(struct pci_dev *dev); 1195 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1196 #define HAVE_PCI_REQ_REGIONS 2 1197 int __must_check pci_request_regions(struct pci_dev *, const char *); 1198 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1199 void pci_release_regions(struct pci_dev *); 1200 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1201 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1202 void pci_release_region(struct pci_dev *, int); 1203 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1204 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1205 void pci_release_selected_regions(struct pci_dev *, int); 1206 1207 /* drivers/pci/bus.c */ 1208 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1209 void pci_bus_put(struct pci_bus *bus); 1210 void pci_add_resource(struct list_head *resources, struct resource *res); 1211 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1212 resource_size_t offset); 1213 void pci_free_resource_list(struct list_head *resources); 1214 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1215 unsigned int flags); 1216 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1217 void pci_bus_remove_resources(struct pci_bus *bus); 1218 int devm_request_pci_bus_resources(struct device *dev, 1219 struct list_head *resources); 1220 1221 #define pci_bus_for_each_resource(bus, res, i) \ 1222 for (i = 0; \ 1223 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1224 i++) 1225 1226 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1227 struct resource *res, resource_size_t size, 1228 resource_size_t align, resource_size_t min, 1229 unsigned long type_mask, 1230 resource_size_t (*alignf)(void *, 1231 const struct resource *, 1232 resource_size_t, 1233 resource_size_t), 1234 void *alignf_data); 1235 1236 1237 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1238 resource_size_t size); 1239 unsigned long pci_address_to_pio(phys_addr_t addr); 1240 phys_addr_t pci_pio_to_address(unsigned long pio); 1241 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1242 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1243 phys_addr_t phys_addr); 1244 void pci_unmap_iospace(struct resource *res); 1245 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1246 resource_size_t offset, 1247 resource_size_t size); 1248 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1249 struct resource *res); 1250 1251 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1252 { 1253 struct pci_bus_region region; 1254 1255 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1256 return region.start; 1257 } 1258 1259 /* Proper probing supporting hot-pluggable devices */ 1260 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1261 const char *mod_name); 1262 1263 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1264 #define pci_register_driver(driver) \ 1265 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1266 1267 void pci_unregister_driver(struct pci_driver *dev); 1268 1269 /** 1270 * module_pci_driver() - Helper macro for registering a PCI driver 1271 * @__pci_driver: pci_driver struct 1272 * 1273 * Helper macro for PCI drivers which do not do anything special in module 1274 * init/exit. This eliminates a lot of boilerplate. Each module may only 1275 * use this macro once, and calling it replaces module_init() and module_exit() 1276 */ 1277 #define module_pci_driver(__pci_driver) \ 1278 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1279 1280 /** 1281 * builtin_pci_driver() - Helper macro for registering a PCI driver 1282 * @__pci_driver: pci_driver struct 1283 * 1284 * Helper macro for PCI drivers which do not do anything special in their 1285 * init code. This eliminates a lot of boilerplate. Each driver may only 1286 * use this macro once, and calling it replaces device_initcall(...) 1287 */ 1288 #define builtin_pci_driver(__pci_driver) \ 1289 builtin_driver(__pci_driver, pci_register_driver) 1290 1291 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1292 int pci_add_dynid(struct pci_driver *drv, 1293 unsigned int vendor, unsigned int device, 1294 unsigned int subvendor, unsigned int subdevice, 1295 unsigned int class, unsigned int class_mask, 1296 unsigned long driver_data); 1297 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1298 struct pci_dev *dev); 1299 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1300 int pass); 1301 1302 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1303 void *userdata); 1304 int pci_cfg_space_size(struct pci_dev *dev); 1305 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1306 void pci_setup_bridge(struct pci_bus *bus); 1307 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1308 unsigned long type); 1309 1310 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1311 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1312 1313 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1314 unsigned int command_bits, u32 flags); 1315 1316 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1317 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1318 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1319 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1320 #define PCI_IRQ_ALL_TYPES \ 1321 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1322 1323 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1324 1325 #include <linux/pci-dma.h> 1326 #include <linux/dmapool.h> 1327 1328 #define pci_pool dma_pool 1329 #define pci_pool_create(name, pdev, size, align, allocation) \ 1330 dma_pool_create(name, &pdev->dev, size, align, allocation) 1331 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1332 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1333 #define pci_pool_zalloc(pool, flags, handle) \ 1334 dma_pool_zalloc(pool, flags, handle) 1335 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1336 1337 struct msix_entry { 1338 u32 vector; /* Kernel uses to write allocated vector */ 1339 u16 entry; /* Driver uses to specify entry, OS writes */ 1340 }; 1341 1342 #ifdef CONFIG_PCI_MSI 1343 int pci_msi_vec_count(struct pci_dev *dev); 1344 void pci_disable_msi(struct pci_dev *dev); 1345 int pci_msix_vec_count(struct pci_dev *dev); 1346 void pci_disable_msix(struct pci_dev *dev); 1347 void pci_restore_msi_state(struct pci_dev *dev); 1348 int pci_msi_enabled(void); 1349 int pci_enable_msi(struct pci_dev *dev); 1350 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1351 int minvec, int maxvec); 1352 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1353 struct msix_entry *entries, int nvec) 1354 { 1355 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1356 if (rc < 0) 1357 return rc; 1358 return 0; 1359 } 1360 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1361 unsigned int max_vecs, unsigned int flags, 1362 const struct irq_affinity *affd); 1363 1364 void pci_free_irq_vectors(struct pci_dev *dev); 1365 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1366 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1367 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1368 1369 #else 1370 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1371 static inline void pci_disable_msi(struct pci_dev *dev) { } 1372 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1373 static inline void pci_disable_msix(struct pci_dev *dev) { } 1374 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1375 static inline int pci_msi_enabled(void) { return 0; } 1376 static inline int pci_enable_msi(struct pci_dev *dev) 1377 { return -ENOSYS; } 1378 static inline int pci_enable_msix_range(struct pci_dev *dev, 1379 struct msix_entry *entries, int minvec, int maxvec) 1380 { return -ENOSYS; } 1381 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1382 struct msix_entry *entries, int nvec) 1383 { return -ENOSYS; } 1384 1385 static inline int 1386 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1387 unsigned int max_vecs, unsigned int flags, 1388 const struct irq_affinity *aff_desc) 1389 { 1390 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1391 return 1; 1392 return -ENOSPC; 1393 } 1394 1395 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1396 { 1397 } 1398 1399 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1400 { 1401 if (WARN_ON_ONCE(nr > 0)) 1402 return -EINVAL; 1403 return dev->irq; 1404 } 1405 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1406 int vec) 1407 { 1408 return cpu_possible_mask; 1409 } 1410 1411 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1412 { 1413 return first_online_node; 1414 } 1415 #endif 1416 1417 static inline int 1418 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1419 unsigned int max_vecs, unsigned int flags) 1420 { 1421 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1422 NULL); 1423 } 1424 1425 /** 1426 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1427 * @d: the INTx IRQ domain 1428 * @node: the DT node for the device whose interrupt we're translating 1429 * @intspec: the interrupt specifier data from the DT 1430 * @intsize: the number of entries in @intspec 1431 * @out_hwirq: pointer at which to write the hwirq number 1432 * @out_type: pointer at which to write the interrupt type 1433 * 1434 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1435 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1436 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1437 * INTx value to obtain the hwirq number. 1438 * 1439 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1440 */ 1441 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1442 struct device_node *node, 1443 const u32 *intspec, 1444 unsigned int intsize, 1445 unsigned long *out_hwirq, 1446 unsigned int *out_type) 1447 { 1448 const u32 intx = intspec[0]; 1449 1450 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1451 return -EINVAL; 1452 1453 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1454 return 0; 1455 } 1456 1457 #ifdef CONFIG_PCIEPORTBUS 1458 extern bool pcie_ports_disabled; 1459 extern bool pcie_ports_native; 1460 #else 1461 #define pcie_ports_disabled true 1462 #define pcie_ports_native false 1463 #endif 1464 1465 #ifdef CONFIG_PCIEASPM 1466 bool pcie_aspm_support_enabled(void); 1467 #else 1468 static inline bool pcie_aspm_support_enabled(void) { return false; } 1469 #endif 1470 1471 #ifdef CONFIG_PCIEAER 1472 void pci_no_aer(void); 1473 bool pci_aer_available(void); 1474 int pci_aer_init(struct pci_dev *dev); 1475 #else 1476 static inline void pci_no_aer(void) { } 1477 static inline bool pci_aer_available(void) { return false; } 1478 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } 1479 #endif 1480 1481 #ifdef CONFIG_PCIE_ECRC 1482 void pcie_set_ecrc_checking(struct pci_dev *dev); 1483 void pcie_ecrc_get_policy(char *str); 1484 #else 1485 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1486 static inline void pcie_ecrc_get_policy(char *str) { } 1487 #endif 1488 1489 bool pci_ats_disabled(void); 1490 1491 #ifdef CONFIG_PCI_ATS 1492 /* Address Translation Service */ 1493 void pci_ats_init(struct pci_dev *dev); 1494 int pci_enable_ats(struct pci_dev *dev, int ps); 1495 void pci_disable_ats(struct pci_dev *dev); 1496 int pci_ats_queue_depth(struct pci_dev *dev); 1497 #else 1498 static inline void pci_ats_init(struct pci_dev *d) { } 1499 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1500 static inline void pci_disable_ats(struct pci_dev *d) { } 1501 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1502 #endif 1503 1504 #ifdef CONFIG_PCIE_PTM 1505 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1506 #else 1507 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1508 { return -EINVAL; } 1509 #endif 1510 1511 void pci_cfg_access_lock(struct pci_dev *dev); 1512 bool pci_cfg_access_trylock(struct pci_dev *dev); 1513 void pci_cfg_access_unlock(struct pci_dev *dev); 1514 1515 /* 1516 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1517 * a PCI domain is defined to be a set of PCI buses which share 1518 * configuration space. 1519 */ 1520 #ifdef CONFIG_PCI_DOMAINS 1521 extern int pci_domains_supported; 1522 #else 1523 enum { pci_domains_supported = 0 }; 1524 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1525 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1526 #endif /* CONFIG_PCI_DOMAINS */ 1527 1528 /* 1529 * Generic implementation for PCI domain support. If your 1530 * architecture does not need custom management of PCI 1531 * domains then this implementation will be used 1532 */ 1533 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1534 static inline int pci_domain_nr(struct pci_bus *bus) 1535 { 1536 return bus->domain_nr; 1537 } 1538 #ifdef CONFIG_ACPI 1539 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1540 #else 1541 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1542 { return 0; } 1543 #endif 1544 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1545 #endif 1546 1547 /* Some architectures require additional setup to direct VGA traffic */ 1548 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1549 unsigned int command_bits, u32 flags); 1550 void pci_register_set_vga_state(arch_set_vga_state_t func); 1551 1552 static inline int 1553 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1554 { 1555 return pci_request_selected_regions(pdev, 1556 pci_select_bars(pdev, IORESOURCE_IO), name); 1557 } 1558 1559 static inline void 1560 pci_release_io_regions(struct pci_dev *pdev) 1561 { 1562 return pci_release_selected_regions(pdev, 1563 pci_select_bars(pdev, IORESOURCE_IO)); 1564 } 1565 1566 static inline int 1567 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1568 { 1569 return pci_request_selected_regions(pdev, 1570 pci_select_bars(pdev, IORESOURCE_MEM), name); 1571 } 1572 1573 static inline void 1574 pci_release_mem_regions(struct pci_dev *pdev) 1575 { 1576 return pci_release_selected_regions(pdev, 1577 pci_select_bars(pdev, IORESOURCE_MEM)); 1578 } 1579 1580 #else /* CONFIG_PCI is not enabled */ 1581 1582 static inline void pci_set_flags(int flags) { } 1583 static inline void pci_add_flags(int flags) { } 1584 static inline void pci_clear_flags(int flags) { } 1585 static inline int pci_has_flag(int flag) { return 0; } 1586 1587 /* 1588 * If the system does not have PCI, clearly these return errors. Define 1589 * these as simple inline functions to avoid hair in drivers. 1590 */ 1591 #define _PCI_NOP(o, s, t) \ 1592 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1593 int where, t val) \ 1594 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1595 1596 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1597 _PCI_NOP(o, word, u16 x) \ 1598 _PCI_NOP(o, dword, u32 x) 1599 _PCI_NOP_ALL(read, *) 1600 _PCI_NOP_ALL(write,) 1601 1602 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1603 unsigned int device, 1604 struct pci_dev *from) 1605 { return NULL; } 1606 1607 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1608 unsigned int device, 1609 unsigned int ss_vendor, 1610 unsigned int ss_device, 1611 struct pci_dev *from) 1612 { return NULL; } 1613 1614 static inline struct pci_dev *pci_get_class(unsigned int class, 1615 struct pci_dev *from) 1616 { return NULL; } 1617 1618 #define pci_dev_present(ids) (0) 1619 #define no_pci_devices() (1) 1620 #define pci_dev_put(dev) do { } while (0) 1621 1622 static inline void pci_set_master(struct pci_dev *dev) { } 1623 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1624 static inline void pci_disable_device(struct pci_dev *dev) { } 1625 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1626 { return -EBUSY; } 1627 static inline int __pci_register_driver(struct pci_driver *drv, 1628 struct module *owner) 1629 { return 0; } 1630 static inline int pci_register_driver(struct pci_driver *drv) 1631 { return 0; } 1632 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1633 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1634 { return 0; } 1635 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1636 int cap) 1637 { return 0; } 1638 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1639 { return 0; } 1640 1641 /* Power management related routines */ 1642 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1643 static inline void pci_restore_state(struct pci_dev *dev) { } 1644 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1645 { return 0; } 1646 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1647 { return 0; } 1648 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1649 pm_message_t state) 1650 { return PCI_D0; } 1651 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1652 int enable) 1653 { return 0; } 1654 1655 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1656 struct resource *res) 1657 { return NULL; } 1658 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1659 { return -EIO; } 1660 static inline void pci_release_regions(struct pci_dev *dev) { } 1661 1662 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1663 1664 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1665 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1666 { return 0; } 1667 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1668 1669 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1670 { return NULL; } 1671 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1672 unsigned int devfn) 1673 { return NULL; } 1674 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1675 unsigned int bus, unsigned int devfn) 1676 { return NULL; } 1677 1678 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1679 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1680 1681 #define dev_is_pci(d) (false) 1682 #define dev_is_pf(d) (false) 1683 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1684 { return false; } 1685 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1686 struct device_node *node, 1687 const u32 *intspec, 1688 unsigned int intsize, 1689 unsigned long *out_hwirq, 1690 unsigned int *out_type) 1691 { return -EINVAL; } 1692 #endif /* CONFIG_PCI */ 1693 1694 /* Include architecture-dependent settings and functions */ 1695 1696 #include <asm/pci.h> 1697 1698 /* These two functions provide almost identical functionality. Depennding 1699 * on the architecture, one will be implemented as a wrapper around the 1700 * other (in drivers/pci/mmap.c). 1701 * 1702 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1703 * is expected to be an offset within that region. 1704 * 1705 * pci_mmap_page_range() is the legacy architecture-specific interface, 1706 * which accepts a "user visible" resource address converted by 1707 * pci_resource_to_user(), as used in the legacy mmap() interface in 1708 * /proc/bus/pci/. 1709 */ 1710 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1711 struct vm_area_struct *vma, 1712 enum pci_mmap_state mmap_state, int write_combine); 1713 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1714 struct vm_area_struct *vma, 1715 enum pci_mmap_state mmap_state, int write_combine); 1716 1717 #ifndef arch_can_pci_mmap_wc 1718 #define arch_can_pci_mmap_wc() 0 1719 #endif 1720 1721 #ifndef arch_can_pci_mmap_io 1722 #define arch_can_pci_mmap_io() 0 1723 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1724 #else 1725 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1726 #endif 1727 1728 #ifndef pci_root_bus_fwnode 1729 #define pci_root_bus_fwnode(bus) NULL 1730 #endif 1731 1732 /* 1733 * These helpers provide future and backwards compatibility 1734 * for accessing popular PCI BAR info 1735 */ 1736 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1737 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1738 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1739 #define pci_resource_len(dev,bar) \ 1740 ((pci_resource_start((dev), (bar)) == 0 && \ 1741 pci_resource_end((dev), (bar)) == \ 1742 pci_resource_start((dev), (bar))) ? 0 : \ 1743 \ 1744 (pci_resource_end((dev), (bar)) - \ 1745 pci_resource_start((dev), (bar)) + 1)) 1746 1747 /* 1748 * Similar to the helpers above, these manipulate per-pci_dev 1749 * driver-specific data. They are really just a wrapper around 1750 * the generic device structure functions of these calls. 1751 */ 1752 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1753 { 1754 return dev_get_drvdata(&pdev->dev); 1755 } 1756 1757 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1758 { 1759 dev_set_drvdata(&pdev->dev, data); 1760 } 1761 1762 static inline const char *pci_name(const struct pci_dev *pdev) 1763 { 1764 return dev_name(&pdev->dev); 1765 } 1766 1767 1768 /* 1769 * Some archs don't want to expose struct resource to userland as-is 1770 * in sysfs and /proc 1771 */ 1772 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1773 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1774 const struct resource *rsrc, 1775 resource_size_t *start, resource_size_t *end); 1776 #else 1777 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1778 const struct resource *rsrc, resource_size_t *start, 1779 resource_size_t *end) 1780 { 1781 *start = rsrc->start; 1782 *end = rsrc->end; 1783 } 1784 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1785 1786 1787 /* 1788 * The world is not perfect and supplies us with broken PCI devices. 1789 * For at least a part of these bugs we need a work-around, so both 1790 * generic (drivers/pci/quirks.c) and per-architecture code can define 1791 * fixup hooks to be called for particular buggy devices. 1792 */ 1793 1794 struct pci_fixup { 1795 u16 vendor; /* Or PCI_ANY_ID */ 1796 u16 device; /* Or PCI_ANY_ID */ 1797 u32 class; /* Or PCI_ANY_ID */ 1798 unsigned int class_shift; /* should be 0, 8, 16 */ 1799 void (*hook)(struct pci_dev *dev); 1800 }; 1801 1802 enum pci_fixup_pass { 1803 pci_fixup_early, /* Before probing BARs */ 1804 pci_fixup_header, /* After reading configuration header */ 1805 pci_fixup_final, /* Final phase of device fixups */ 1806 pci_fixup_enable, /* pci_enable_device() time */ 1807 pci_fixup_resume, /* pci_device_resume() */ 1808 pci_fixup_suspend, /* pci_device_suspend() */ 1809 pci_fixup_resume_early, /* pci_device_resume_early() */ 1810 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1811 }; 1812 1813 /* Anonymous variables would be nice... */ 1814 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1815 class_shift, hook) \ 1816 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1817 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1818 = { vendor, device, class, class_shift, hook }; 1819 1820 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1821 class_shift, hook) \ 1822 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1823 hook, vendor, device, class, class_shift, hook) 1824 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1825 class_shift, hook) \ 1826 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1827 hook, vendor, device, class, class_shift, hook) 1828 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1829 class_shift, hook) \ 1830 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1831 hook, vendor, device, class, class_shift, hook) 1832 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1833 class_shift, hook) \ 1834 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1835 hook, vendor, device, class, class_shift, hook) 1836 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1837 class_shift, hook) \ 1838 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1839 resume##hook, vendor, device, class, class_shift, hook) 1840 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1841 class_shift, hook) \ 1842 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1843 resume_early##hook, vendor, device, class, class_shift, hook) 1844 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1845 class_shift, hook) \ 1846 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1847 suspend##hook, vendor, device, class, class_shift, hook) 1848 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1849 class_shift, hook) \ 1850 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1851 suspend_late##hook, vendor, device, class, class_shift, hook) 1852 1853 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1854 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1855 hook, vendor, device, PCI_ANY_ID, 0, hook) 1856 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1857 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1858 hook, vendor, device, PCI_ANY_ID, 0, hook) 1859 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1860 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1861 hook, vendor, device, PCI_ANY_ID, 0, hook) 1862 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1864 hook, vendor, device, PCI_ANY_ID, 0, hook) 1865 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1866 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1867 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1868 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1869 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1870 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1871 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1872 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1873 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1874 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1875 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1876 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1877 1878 #ifdef CONFIG_PCI_QUIRKS 1879 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1880 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1881 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1882 #else 1883 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1884 struct pci_dev *dev) { } 1885 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1886 u16 acs_flags) 1887 { 1888 return -ENOTTY; 1889 } 1890 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1891 { 1892 return -ENOTTY; 1893 } 1894 #endif 1895 1896 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1897 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1898 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1899 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1900 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1901 const char *name); 1902 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1903 1904 extern int pci_pci_problems; 1905 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1906 #define PCIPCI_TRITON 2 1907 #define PCIPCI_NATOMA 4 1908 #define PCIPCI_VIAETBF 8 1909 #define PCIPCI_VSFX 16 1910 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1911 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1912 1913 extern unsigned long pci_cardbus_io_size; 1914 extern unsigned long pci_cardbus_mem_size; 1915 extern u8 pci_dfl_cache_line_size; 1916 extern u8 pci_cache_line_size; 1917 1918 extern unsigned long pci_hotplug_io_size; 1919 extern unsigned long pci_hotplug_mem_size; 1920 extern unsigned long pci_hotplug_bus_size; 1921 1922 /* Architecture-specific versions may override these (weak) */ 1923 void pcibios_disable_device(struct pci_dev *dev); 1924 void pcibios_set_master(struct pci_dev *dev); 1925 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1926 enum pcie_reset_state state); 1927 int pcibios_add_device(struct pci_dev *dev); 1928 void pcibios_release_device(struct pci_dev *dev); 1929 void pcibios_penalize_isa_irq(int irq, int active); 1930 int pcibios_alloc_irq(struct pci_dev *dev); 1931 void pcibios_free_irq(struct pci_dev *dev); 1932 resource_size_t pcibios_default_alignment(void); 1933 1934 #ifdef CONFIG_HIBERNATE_CALLBACKS 1935 extern struct dev_pm_ops pcibios_pm_ops; 1936 #endif 1937 1938 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1939 void __init pci_mmcfg_early_init(void); 1940 void __init pci_mmcfg_late_init(void); 1941 #else 1942 static inline void pci_mmcfg_early_init(void) { } 1943 static inline void pci_mmcfg_late_init(void) { } 1944 #endif 1945 1946 int pci_ext_cfg_avail(void); 1947 1948 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1949 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1950 1951 #ifdef CONFIG_PCI_IOV 1952 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1953 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1954 1955 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1956 void pci_disable_sriov(struct pci_dev *dev); 1957 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 1958 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 1959 int pci_num_vf(struct pci_dev *dev); 1960 int pci_vfs_assigned(struct pci_dev *dev); 1961 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1962 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1963 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 1964 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1965 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 1966 1967 /* Arch may override these (weak) */ 1968 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 1969 int pcibios_sriov_disable(struct pci_dev *pdev); 1970 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1971 #else 1972 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1973 { 1974 return -ENOSYS; 1975 } 1976 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1977 { 1978 return -ENOSYS; 1979 } 1980 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1981 { return -ENODEV; } 1982 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 1983 { 1984 return -ENOSYS; 1985 } 1986 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 1987 int id) { } 1988 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1989 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1990 static inline int pci_vfs_assigned(struct pci_dev *dev) 1991 { return 0; } 1992 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1993 { return 0; } 1994 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1995 { return 0; } 1996 #define pci_sriov_configure_simple NULL 1997 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1998 { return 0; } 1999 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2000 #endif 2001 2002 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2003 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2004 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2005 #endif 2006 2007 /** 2008 * pci_pcie_cap - get the saved PCIe capability offset 2009 * @dev: PCI device 2010 * 2011 * PCIe capability offset is calculated at PCI device initialization 2012 * time and saved in the data structure. This function returns saved 2013 * PCIe capability offset. Using this instead of pci_find_capability() 2014 * reduces unnecessary search in the PCI configuration space. If you 2015 * need to calculate PCIe capability offset from raw device for some 2016 * reasons, please use pci_find_capability() instead. 2017 */ 2018 static inline int pci_pcie_cap(struct pci_dev *dev) 2019 { 2020 return dev->pcie_cap; 2021 } 2022 2023 /** 2024 * pci_is_pcie - check if the PCI device is PCI Express capable 2025 * @dev: PCI device 2026 * 2027 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2028 */ 2029 static inline bool pci_is_pcie(struct pci_dev *dev) 2030 { 2031 return pci_pcie_cap(dev); 2032 } 2033 2034 /** 2035 * pcie_caps_reg - get the PCIe Capabilities Register 2036 * @dev: PCI device 2037 */ 2038 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2039 { 2040 return dev->pcie_flags_reg; 2041 } 2042 2043 /** 2044 * pci_pcie_type - get the PCIe device/port type 2045 * @dev: PCI device 2046 */ 2047 static inline int pci_pcie_type(const struct pci_dev *dev) 2048 { 2049 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2050 } 2051 2052 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2053 { 2054 while (1) { 2055 if (!pci_is_pcie(dev)) 2056 break; 2057 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2058 return dev; 2059 if (!dev->bus->self) 2060 break; 2061 dev = dev->bus->self; 2062 } 2063 return NULL; 2064 } 2065 2066 void pci_request_acs(void); 2067 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2068 bool pci_acs_path_enabled(struct pci_dev *start, 2069 struct pci_dev *end, u16 acs_flags); 2070 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2071 2072 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2073 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2074 2075 /* Large Resource Data Type Tag Item Names */ 2076 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2077 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2078 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2079 2080 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2081 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2082 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2083 2084 /* Small Resource Data Type Tag Item Names */ 2085 #define PCI_VPD_STIN_END 0x0f /* End */ 2086 2087 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2088 2089 #define PCI_VPD_SRDT_TIN_MASK 0x78 2090 #define PCI_VPD_SRDT_LEN_MASK 0x07 2091 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2092 2093 #define PCI_VPD_LRDT_TAG_SIZE 3 2094 #define PCI_VPD_SRDT_TAG_SIZE 1 2095 2096 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2097 2098 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2099 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2100 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2101 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2102 2103 /** 2104 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2105 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2106 * 2107 * Returns the extracted Large Resource Data Type length. 2108 */ 2109 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2110 { 2111 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2112 } 2113 2114 /** 2115 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2116 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2117 * 2118 * Returns the extracted Large Resource Data Type Tag item. 2119 */ 2120 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2121 { 2122 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2123 } 2124 2125 /** 2126 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2127 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2128 * 2129 * Returns the extracted Small Resource Data Type length. 2130 */ 2131 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2132 { 2133 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2134 } 2135 2136 /** 2137 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2138 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2139 * 2140 * Returns the extracted Small Resource Data Type Tag Item. 2141 */ 2142 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2143 { 2144 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2145 } 2146 2147 /** 2148 * pci_vpd_info_field_size - Extracts the information field length 2149 * @lrdt: Pointer to the beginning of an information field header 2150 * 2151 * Returns the extracted information field length. 2152 */ 2153 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2154 { 2155 return info_field[2]; 2156 } 2157 2158 /** 2159 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2160 * @buf: Pointer to buffered vpd data 2161 * @off: The offset into the buffer at which to begin the search 2162 * @len: The length of the vpd buffer 2163 * @rdt: The Resource Data Type to search for 2164 * 2165 * Returns the index where the Resource Data Type was found or 2166 * -ENOENT otherwise. 2167 */ 2168 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2169 2170 /** 2171 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2172 * @buf: Pointer to buffered vpd data 2173 * @off: The offset into the buffer at which to begin the search 2174 * @len: The length of the buffer area, relative to off, in which to search 2175 * @kw: The keyword to search for 2176 * 2177 * Returns the index where the information field keyword was found or 2178 * -ENOENT otherwise. 2179 */ 2180 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2181 unsigned int len, const char *kw); 2182 2183 /* PCI <-> OF binding helpers */ 2184 #ifdef CONFIG_OF 2185 struct device_node; 2186 struct irq_domain; 2187 void pci_set_of_node(struct pci_dev *dev); 2188 void pci_release_of_node(struct pci_dev *dev); 2189 void pci_set_bus_of_node(struct pci_bus *bus); 2190 void pci_release_bus_of_node(struct pci_bus *bus); 2191 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2192 int pci_parse_request_of_pci_ranges(struct device *dev, 2193 struct list_head *resources, 2194 struct resource **bus_range); 2195 2196 /* Arch may override this (weak) */ 2197 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2198 2199 #else /* CONFIG_OF */ 2200 static inline void pci_set_of_node(struct pci_dev *dev) { } 2201 static inline void pci_release_of_node(struct pci_dev *dev) { } 2202 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2203 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2204 static inline struct irq_domain * 2205 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2206 static inline int pci_parse_request_of_pci_ranges(struct device *dev, 2207 struct list_head *resources, 2208 struct resource **bus_range) 2209 { 2210 return -EINVAL; 2211 } 2212 #endif /* CONFIG_OF */ 2213 2214 static inline struct device_node * 2215 pci_device_to_OF_node(const struct pci_dev *pdev) 2216 { 2217 return pdev ? pdev->dev.of_node : NULL; 2218 } 2219 2220 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2221 { 2222 return bus ? bus->dev.of_node : NULL; 2223 } 2224 2225 #ifdef CONFIG_ACPI 2226 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2227 2228 void 2229 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2230 #else 2231 static inline struct irq_domain * 2232 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2233 #endif 2234 2235 #ifdef CONFIG_EEH 2236 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2237 { 2238 return pdev->dev.archdata.edev; 2239 } 2240 #endif 2241 2242 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2243 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2244 int pci_for_each_dma_alias(struct pci_dev *pdev, 2245 int (*fn)(struct pci_dev *pdev, 2246 u16 alias, void *data), void *data); 2247 2248 /* Helper functions for operation of device flag */ 2249 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2250 { 2251 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2252 } 2253 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2254 { 2255 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2256 } 2257 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2258 { 2259 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2260 } 2261 2262 /** 2263 * pci_ari_enabled - query ARI forwarding status 2264 * @bus: the PCI bus 2265 * 2266 * Returns true if ARI forwarding is enabled. 2267 */ 2268 static inline bool pci_ari_enabled(struct pci_bus *bus) 2269 { 2270 return bus->self && bus->self->ari_enabled; 2271 } 2272 2273 /** 2274 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2275 * @pdev: PCI device to check 2276 * 2277 * Walk upwards from @pdev and check for each encountered bridge if it's part 2278 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2279 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2280 */ 2281 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2282 { 2283 struct pci_dev *parent = pdev; 2284 2285 if (pdev->is_thunderbolt) 2286 return true; 2287 2288 while ((parent = pci_upstream_bridge(parent))) 2289 if (parent->is_thunderbolt) 2290 return true; 2291 2292 return false; 2293 } 2294 2295 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2296 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2297 #endif 2298 2299 /* Provide the legacy pci_dma_* API */ 2300 #include <linux/pci-dma-compat.h> 2301 2302 #define pci_printk(level, pdev, fmt, arg...) \ 2303 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2304 2305 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2306 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2307 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2308 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2309 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2310 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2311 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2312 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2313 2314 #endif /* LINUX_PCI_H */ 2315