1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 46 PCI_STATUS_SIG_SYSTEM_ERROR | \ 47 PCI_STATUS_REC_MASTER_ABORT | \ 48 PCI_STATUS_REC_TARGET_ABORT | \ 49 PCI_STATUS_SIG_TARGET_ABORT | \ 50 PCI_STATUS_PARITY) 51 52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 53 #define PCI_NUM_RESET_METHODS 7 54 55 #define PCI_RESET_PROBE true 56 #define PCI_RESET_DO_RESET false 57 58 /* 59 * The PCI interface treats multi-function devices as independent 60 * devices. The slot/function address of each device is encoded 61 * in a single byte as follows: 62 * 63 * 7:3 = slot 64 * 2:0 = function 65 * 66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 67 * In the interest of not exposing interfaces to user-space unnecessarily, 68 * the following kernel-only defines are being added here. 69 */ 70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 73 74 /* pci_slot represents a physical slot */ 75 struct pci_slot { 76 struct pci_bus *bus; /* Bus this slot is on */ 77 struct list_head list; /* Node in list of slots */ 78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 80 struct kobject kobj; 81 }; 82 83 static inline const char *pci_slot_name(const struct pci_slot *slot) 84 { 85 return kobject_name(&slot->kobj); 86 } 87 88 /* File state for mmap()s on /proc/bus/pci/X/Y */ 89 enum pci_mmap_state { 90 pci_mmap_io, 91 pci_mmap_mem 92 }; 93 94 /* For PCI devices, the region numbers are assigned this way: */ 95 enum { 96 /* #0-5: standard PCI resources */ 97 PCI_STD_RESOURCES, 98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 99 100 /* #6: expansion ROM resource */ 101 PCI_ROM_RESOURCE, 102 103 /* Device-specific resources */ 104 #ifdef CONFIG_PCI_IOV 105 PCI_IOV_RESOURCES, 106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 107 #endif 108 109 /* PCI-to-PCI (P2P) bridge windows */ 110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 113 114 /* CardBus bridge windows */ 115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 119 120 /* Total number of bridge resources for P2P and CardBus */ 121 #define PCI_BRIDGE_RESOURCE_NUM 4 122 123 /* Resources assigned to buses behind the bridge */ 124 PCI_BRIDGE_RESOURCES, 125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 126 PCI_BRIDGE_RESOURCE_NUM - 1, 127 128 /* Total resources associated with a PCI device */ 129 PCI_NUM_RESOURCES, 130 131 /* Preserve this for compatibility */ 132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 133 }; 134 135 /** 136 * enum pci_interrupt_pin - PCI INTx interrupt values 137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 138 * @PCI_INTERRUPT_INTA: PCI INTA pin 139 * @PCI_INTERRUPT_INTB: PCI INTB pin 140 * @PCI_INTERRUPT_INTC: PCI INTC pin 141 * @PCI_INTERRUPT_INTD: PCI INTD pin 142 * 143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 144 * PCI_INTERRUPT_PIN register. 145 */ 146 enum pci_interrupt_pin { 147 PCI_INTERRUPT_UNKNOWN, 148 PCI_INTERRUPT_INTA, 149 PCI_INTERRUPT_INTB, 150 PCI_INTERRUPT_INTC, 151 PCI_INTERRUPT_INTD, 152 }; 153 154 /* The number of legacy PCI INTx interrupts */ 155 #define PCI_NUM_INTX 4 156 157 /* 158 * Reading from a device that doesn't respond typically returns ~0. A 159 * successful read from a device may also return ~0, so you need additional 160 * information to reliably identify errors. 161 */ 162 #define PCI_ERROR_RESPONSE (~0ULL) 163 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 164 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 165 166 /* 167 * pci_power_t values must match the bits in the Capabilities PME_Support 168 * and Control/Status PowerState fields in the Power Management capability. 169 */ 170 typedef int __bitwise pci_power_t; 171 172 #define PCI_D0 ((pci_power_t __force) 0) 173 #define PCI_D1 ((pci_power_t __force) 1) 174 #define PCI_D2 ((pci_power_t __force) 2) 175 #define PCI_D3hot ((pci_power_t __force) 3) 176 #define PCI_D3cold ((pci_power_t __force) 4) 177 #define PCI_UNKNOWN ((pci_power_t __force) 5) 178 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 179 180 /* Remember to update this when the list above changes! */ 181 extern const char *pci_power_names[]; 182 183 static inline const char *pci_power_name(pci_power_t state) 184 { 185 return pci_power_names[1 + (__force int) state]; 186 } 187 188 /** 189 * typedef pci_channel_state_t 190 * 191 * The pci_channel state describes connectivity between the CPU and 192 * the PCI device. If some PCI bus between here and the PCI device 193 * has crashed or locked up, this info is reflected here. 194 */ 195 typedef unsigned int __bitwise pci_channel_state_t; 196 197 enum { 198 /* I/O channel is in normal state */ 199 pci_channel_io_normal = (__force pci_channel_state_t) 1, 200 201 /* I/O to channel is blocked */ 202 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 203 204 /* PCI card is dead */ 205 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 206 }; 207 208 typedef unsigned int __bitwise pcie_reset_state_t; 209 210 enum pcie_reset_state { 211 /* Reset is NOT asserted (Use to deassert reset) */ 212 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 213 214 /* Use #PERST to reset PCIe device */ 215 pcie_warm_reset = (__force pcie_reset_state_t) 2, 216 217 /* Use PCIe Hot Reset to reset device */ 218 pcie_hot_reset = (__force pcie_reset_state_t) 3 219 }; 220 221 typedef unsigned short __bitwise pci_dev_flags_t; 222 enum pci_dev_flags { 223 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 224 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 225 /* Device configuration is irrevocably lost if disabled into D3 */ 226 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 227 /* Provide indication device is assigned by a Virtual Machine Manager */ 228 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 229 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 230 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 231 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 232 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 233 /* Do not use bus resets for device */ 234 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 235 /* Do not use PM reset even if device advertises NoSoftRst- */ 236 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 237 /* Get VPD from function 0 VPD */ 238 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 239 /* A non-root bridge where translation occurs, stop alias search here */ 240 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 241 /* Do not use FLR even if device advertises PCI_AF_CAP */ 242 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 243 /* Don't use Relaxed Ordering for TLPs directed at this device */ 244 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 245 /* Device does honor MSI masking despite saying otherwise */ 246 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 247 }; 248 249 enum pci_irq_reroute_variant { 250 INTEL_IRQ_REROUTE_VARIANT = 1, 251 MAX_IRQ_REROUTE_VARIANTS = 3 252 }; 253 254 typedef unsigned short __bitwise pci_bus_flags_t; 255 enum pci_bus_flags { 256 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 257 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 258 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 259 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 260 }; 261 262 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 263 enum pcie_link_width { 264 PCIE_LNK_WIDTH_RESRV = 0x00, 265 PCIE_LNK_X1 = 0x01, 266 PCIE_LNK_X2 = 0x02, 267 PCIE_LNK_X4 = 0x04, 268 PCIE_LNK_X8 = 0x08, 269 PCIE_LNK_X12 = 0x0c, 270 PCIE_LNK_X16 = 0x10, 271 PCIE_LNK_X32 = 0x20, 272 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 273 }; 274 275 /* See matching string table in pci_speed_string() */ 276 enum pci_bus_speed { 277 PCI_SPEED_33MHz = 0x00, 278 PCI_SPEED_66MHz = 0x01, 279 PCI_SPEED_66MHz_PCIX = 0x02, 280 PCI_SPEED_100MHz_PCIX = 0x03, 281 PCI_SPEED_133MHz_PCIX = 0x04, 282 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 283 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 284 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 285 PCI_SPEED_66MHz_PCIX_266 = 0x09, 286 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 287 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 288 AGP_UNKNOWN = 0x0c, 289 AGP_1X = 0x0d, 290 AGP_2X = 0x0e, 291 AGP_4X = 0x0f, 292 AGP_8X = 0x10, 293 PCI_SPEED_66MHz_PCIX_533 = 0x11, 294 PCI_SPEED_100MHz_PCIX_533 = 0x12, 295 PCI_SPEED_133MHz_PCIX_533 = 0x13, 296 PCIE_SPEED_2_5GT = 0x14, 297 PCIE_SPEED_5_0GT = 0x15, 298 PCIE_SPEED_8_0GT = 0x16, 299 PCIE_SPEED_16_0GT = 0x17, 300 PCIE_SPEED_32_0GT = 0x18, 301 PCIE_SPEED_64_0GT = 0x19, 302 PCI_SPEED_UNKNOWN = 0xff, 303 }; 304 305 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 306 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 307 308 struct pci_vpd { 309 struct mutex lock; 310 unsigned int len; 311 u8 cap; 312 }; 313 314 struct irq_affinity; 315 struct pcie_link_state; 316 struct pci_sriov; 317 struct pci_p2pdma; 318 struct rcec_ea; 319 320 /* The pci_dev structure describes PCI devices */ 321 struct pci_dev { 322 struct list_head bus_list; /* Node in per-bus list */ 323 struct pci_bus *bus; /* Bus this device is on */ 324 struct pci_bus *subordinate; /* Bus this device bridges to */ 325 326 void *sysdata; /* Hook for sys-specific extension */ 327 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 328 struct pci_slot *slot; /* Physical slot this device is in */ 329 330 unsigned int devfn; /* Encoded device & function index */ 331 unsigned short vendor; 332 unsigned short device; 333 unsigned short subsystem_vendor; 334 unsigned short subsystem_device; 335 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 336 u8 revision; /* PCI revision, low byte of class word */ 337 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 338 #ifdef CONFIG_PCIEAER 339 u16 aer_cap; /* AER capability offset */ 340 struct aer_stats *aer_stats; /* AER stats for this device */ 341 #endif 342 #ifdef CONFIG_PCIEPORTBUS 343 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 344 struct pci_dev *rcec; /* Associated RCEC device */ 345 #endif 346 u32 devcap; /* PCIe Device Capabilities */ 347 u8 pcie_cap; /* PCIe capability offset */ 348 u8 msi_cap; /* MSI capability offset */ 349 u8 msix_cap; /* MSI-X capability offset */ 350 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 351 u8 rom_base_reg; /* Config register controlling ROM */ 352 u8 pin; /* Interrupt pin this device uses */ 353 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 354 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 355 356 struct pci_driver *driver; /* Driver bound to this device */ 357 u64 dma_mask; /* Mask of the bits of bus address this 358 device implements. Normally this is 359 0xffffffff. You only need to change 360 this if your device has broken DMA 361 or supports 64-bit transfers. */ 362 363 struct device_dma_parameters dma_parms; 364 365 pci_power_t current_state; /* Current operating state. In ACPI, 366 this is D0-D3, D0 being fully 367 functional, and D3 being off. */ 368 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 369 u8 pm_cap; /* PM capability offset */ 370 unsigned int pme_support:5; /* Bitmask of states from which PME# 371 can be generated */ 372 unsigned int pme_poll:1; /* Poll device's PME status bit */ 373 unsigned int d1_support:1; /* Low power state D1 is supported */ 374 unsigned int d2_support:1; /* Low power state D2 is supported */ 375 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 376 unsigned int no_d3cold:1; /* D3cold is forbidden */ 377 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 378 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 379 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 380 decoding during BAR sizing */ 381 unsigned int wakeup_prepared:1; 382 unsigned int runtime_d3cold:1; /* Whether go through runtime 383 D3cold, not set for devices 384 powered on/off by the 385 corresponding bridge */ 386 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 387 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 388 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 389 controlled exclusively by 390 user sysfs */ 391 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 392 bit manually */ 393 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 394 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 395 396 #ifdef CONFIG_PCIEASPM 397 struct pcie_link_state *link_state; /* ASPM link state */ 398 unsigned int ltr_path:1; /* Latency Tolerance Reporting 399 supported from root to here */ 400 u16 l1ss; /* L1SS Capability pointer */ 401 #endif 402 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 403 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 404 405 pci_channel_state_t error_state; /* Current connectivity state */ 406 struct device dev; /* Generic device interface */ 407 408 int cfg_size; /* Size of config space */ 409 410 /* 411 * Instead of touching interrupt line and base address registers 412 * directly, use the values stored here. They might be different! 413 */ 414 unsigned int irq; 415 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 416 417 bool match_driver; /* Skip attaching driver */ 418 419 unsigned int transparent:1; /* Subtractive decode bridge */ 420 unsigned int io_window:1; /* Bridge has I/O window */ 421 unsigned int pref_window:1; /* Bridge has pref mem window */ 422 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 423 unsigned int multifunction:1; /* Multi-function device */ 424 425 unsigned int is_busmaster:1; /* Is busmaster */ 426 unsigned int no_msi:1; /* May not use MSI */ 427 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 428 unsigned int block_cfg_access:1; /* Config space access blocked */ 429 unsigned int broken_parity_status:1; /* Generates false positive parity */ 430 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 431 unsigned int msi_enabled:1; 432 unsigned int msix_enabled:1; 433 unsigned int ari_enabled:1; /* ARI forwarding */ 434 unsigned int ats_enabled:1; /* Address Translation Svc */ 435 unsigned int pasid_enabled:1; /* Process Address Space ID */ 436 unsigned int pri_enabled:1; /* Page Request Interface */ 437 unsigned int is_managed:1; /* Managed via devres */ 438 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 439 unsigned int needs_freset:1; /* Requires fundamental reset */ 440 unsigned int state_saved:1; 441 unsigned int is_physfn:1; 442 unsigned int is_virtfn:1; 443 unsigned int is_hotplug_bridge:1; 444 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 445 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 446 /* 447 * Devices marked being untrusted are the ones that can potentially 448 * execute DMA attacks and similar. They are typically connected 449 * through external ports such as Thunderbolt but not limited to 450 * that. When an IOMMU is enabled they should be getting full 451 * mappings to make sure they cannot access arbitrary memory. 452 */ 453 unsigned int untrusted:1; 454 /* 455 * Info from the platform, e.g., ACPI or device tree, may mark a 456 * device as "external-facing". An external-facing device is 457 * itself internal but devices downstream from it are external. 458 */ 459 unsigned int external_facing:1; 460 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 461 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 462 unsigned int irq_managed:1; 463 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 464 unsigned int is_probed:1; /* Device probing in progress */ 465 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 466 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 467 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 468 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 469 pci_dev_flags_t dev_flags; 470 atomic_t enable_cnt; /* pci_enable_device has been called */ 471 472 u32 saved_config_space[16]; /* Config space saved at suspend time */ 473 struct hlist_head saved_cap_space; 474 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 475 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 476 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 477 478 #ifdef CONFIG_HOTPLUG_PCI_PCIE 479 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 480 #endif 481 #ifdef CONFIG_PCIE_PTM 482 unsigned int ptm_root:1; 483 unsigned int ptm_enabled:1; 484 u8 ptm_granularity; 485 #endif 486 #ifdef CONFIG_PCI_MSI 487 void __iomem *msix_base; 488 raw_spinlock_t msi_lock; 489 #endif 490 struct pci_vpd vpd; 491 #ifdef CONFIG_PCIE_DPC 492 u16 dpc_cap; 493 unsigned int dpc_rp_extensions:1; 494 u8 dpc_rp_log_size; 495 #endif 496 #ifdef CONFIG_PCI_ATS 497 union { 498 struct pci_sriov *sriov; /* PF: SR-IOV info */ 499 struct pci_dev *physfn; /* VF: related PF */ 500 }; 501 u16 ats_cap; /* ATS Capability offset */ 502 u8 ats_stu; /* ATS Smallest Translation Unit */ 503 #endif 504 #ifdef CONFIG_PCI_PRI 505 u16 pri_cap; /* PRI Capability offset */ 506 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 507 unsigned int pasid_required:1; /* PRG Response PASID Required */ 508 #endif 509 #ifdef CONFIG_PCI_PASID 510 u16 pasid_cap; /* PASID Capability offset */ 511 u16 pasid_features; 512 #endif 513 #ifdef CONFIG_PCI_P2PDMA 514 struct pci_p2pdma __rcu *p2pdma; 515 #endif 516 u16 acs_cap; /* ACS Capability offset */ 517 phys_addr_t rom; /* Physical address if not from BAR */ 518 size_t romlen; /* Length if not from BAR */ 519 /* 520 * Driver name to force a match. Do not set directly, because core 521 * frees it. Use driver_set_override() to set or clear it. 522 */ 523 const char *driver_override; 524 525 unsigned long priv_flags; /* Private flags for the PCI driver */ 526 527 /* These methods index pci_reset_fn_methods[] */ 528 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 529 }; 530 531 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 532 { 533 #ifdef CONFIG_PCI_IOV 534 if (dev->is_virtfn) 535 dev = dev->physfn; 536 #endif 537 return dev; 538 } 539 540 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 541 542 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 543 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 544 545 static inline int pci_channel_offline(struct pci_dev *pdev) 546 { 547 return (pdev->error_state != pci_channel_io_normal); 548 } 549 550 /* 551 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 552 * Group number is limited to a 16-bit value, therefore (int)-1 is 553 * not a valid PCI domain number, and can be used as a sentinel 554 * value indicating ->domain_nr is not set by the driver (and 555 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 556 * pci_bus_find_domain_nr()). 557 */ 558 #define PCI_DOMAIN_NR_NOT_SET (-1) 559 560 struct pci_host_bridge { 561 struct device dev; 562 struct pci_bus *bus; /* Root bus */ 563 struct pci_ops *ops; 564 struct pci_ops *child_ops; 565 void *sysdata; 566 int busnr; 567 int domain_nr; 568 struct list_head windows; /* resource_entry */ 569 struct list_head dma_ranges; /* dma ranges resource list */ 570 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 571 int (*map_irq)(const struct pci_dev *, u8, u8); 572 void (*release_fn)(struct pci_host_bridge *); 573 void *release_data; 574 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 575 unsigned int no_ext_tags:1; /* No Extended Tags */ 576 unsigned int native_aer:1; /* OS may use PCIe AER */ 577 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 578 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 579 unsigned int native_pme:1; /* OS may use PCIe PME */ 580 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 581 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 582 unsigned int preserve_config:1; /* Preserve FW resource setup */ 583 unsigned int size_windows:1; /* Enable root bus sizing */ 584 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 585 586 /* Resource alignment requirements */ 587 resource_size_t (*align_resource)(struct pci_dev *dev, 588 const struct resource *res, 589 resource_size_t start, 590 resource_size_t size, 591 resource_size_t align); 592 unsigned long private[] ____cacheline_aligned; 593 }; 594 595 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 596 597 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 598 { 599 return (void *)bridge->private; 600 } 601 602 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 603 { 604 return container_of(priv, struct pci_host_bridge, private); 605 } 606 607 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 608 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 609 size_t priv); 610 void pci_free_host_bridge(struct pci_host_bridge *bridge); 611 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 612 613 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 614 void (*release_fn)(struct pci_host_bridge *), 615 void *release_data); 616 617 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 618 619 /* 620 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 621 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 622 * buses below host bridges or subtractive decode bridges) go in the list. 623 * Use pci_bus_for_each_resource() to iterate through all the resources. 624 */ 625 626 /* 627 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 628 * and there's no way to program the bridge with the details of the window. 629 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 630 * decode bit set, because they are explicit and can be programmed with _SRS. 631 */ 632 #define PCI_SUBTRACTIVE_DECODE 0x1 633 634 struct pci_bus_resource { 635 struct list_head list; 636 struct resource *res; 637 unsigned int flags; 638 }; 639 640 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 641 642 struct pci_bus { 643 struct list_head node; /* Node in list of buses */ 644 struct pci_bus *parent; /* Parent bus this bridge is on */ 645 struct list_head children; /* List of child buses */ 646 struct list_head devices; /* List of devices on this bus */ 647 struct pci_dev *self; /* Bridge device as seen by parent */ 648 struct list_head slots; /* List of slots on this bus; 649 protected by pci_slot_mutex */ 650 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 651 struct list_head resources; /* Address space routed to this bus */ 652 struct resource busn_res; /* Bus numbers routed to this bus */ 653 654 struct pci_ops *ops; /* Configuration access functions */ 655 void *sysdata; /* Hook for sys-specific extension */ 656 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 657 658 unsigned char number; /* Bus number */ 659 unsigned char primary; /* Number of primary bridge */ 660 unsigned char max_bus_speed; /* enum pci_bus_speed */ 661 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 662 #ifdef CONFIG_PCI_DOMAINS_GENERIC 663 int domain_nr; 664 #endif 665 666 char name[48]; 667 668 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 669 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 670 struct device *bridge; 671 struct device dev; 672 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 673 struct bin_attribute *legacy_mem; /* Legacy mem */ 674 unsigned int is_added:1; 675 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 676 }; 677 678 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 679 680 static inline u16 pci_dev_id(struct pci_dev *dev) 681 { 682 return PCI_DEVID(dev->bus->number, dev->devfn); 683 } 684 685 /* 686 * Returns true if the PCI bus is root (behind host-PCI bridge), 687 * false otherwise 688 * 689 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 690 * This is incorrect because "virtual" buses added for SR-IOV (via 691 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 692 */ 693 static inline bool pci_is_root_bus(struct pci_bus *pbus) 694 { 695 return !(pbus->parent); 696 } 697 698 /** 699 * pci_is_bridge - check if the PCI device is a bridge 700 * @dev: PCI device 701 * 702 * Return true if the PCI device is bridge whether it has subordinate 703 * or not. 704 */ 705 static inline bool pci_is_bridge(struct pci_dev *dev) 706 { 707 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 708 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 709 } 710 711 #define for_each_pci_bridge(dev, bus) \ 712 list_for_each_entry(dev, &bus->devices, bus_list) \ 713 if (!pci_is_bridge(dev)) {} else 714 715 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 716 { 717 dev = pci_physfn(dev); 718 if (pci_is_root_bus(dev->bus)) 719 return NULL; 720 721 return dev->bus->self; 722 } 723 724 #ifdef CONFIG_PCI_MSI 725 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 726 { 727 return pci_dev->msi_enabled || pci_dev->msix_enabled; 728 } 729 #else 730 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 731 #endif 732 733 /* Error values that may be returned by PCI functions */ 734 #define PCIBIOS_SUCCESSFUL 0x00 735 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 736 #define PCIBIOS_BAD_VENDOR_ID 0x83 737 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 738 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 739 #define PCIBIOS_SET_FAILED 0x88 740 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 741 742 /* Translate above to generic errno for passing back through non-PCI code */ 743 static inline int pcibios_err_to_errno(int err) 744 { 745 if (err <= PCIBIOS_SUCCESSFUL) 746 return err; /* Assume already errno */ 747 748 switch (err) { 749 case PCIBIOS_FUNC_NOT_SUPPORTED: 750 return -ENOENT; 751 case PCIBIOS_BAD_VENDOR_ID: 752 return -ENOTTY; 753 case PCIBIOS_DEVICE_NOT_FOUND: 754 return -ENODEV; 755 case PCIBIOS_BAD_REGISTER_NUMBER: 756 return -EFAULT; 757 case PCIBIOS_SET_FAILED: 758 return -EIO; 759 case PCIBIOS_BUFFER_TOO_SMALL: 760 return -ENOSPC; 761 } 762 763 return -ERANGE; 764 } 765 766 /* Low-level architecture-dependent routines */ 767 768 struct pci_ops { 769 int (*add_bus)(struct pci_bus *bus); 770 void (*remove_bus)(struct pci_bus *bus); 771 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 772 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 773 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 774 }; 775 776 /* 777 * ACPI needs to be able to access PCI config space before we've done a 778 * PCI bus scan and created pci_bus structures. 779 */ 780 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 781 int reg, int len, u32 *val); 782 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 783 int reg, int len, u32 val); 784 785 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 786 typedef u64 pci_bus_addr_t; 787 #else 788 typedef u32 pci_bus_addr_t; 789 #endif 790 791 struct pci_bus_region { 792 pci_bus_addr_t start; 793 pci_bus_addr_t end; 794 }; 795 796 struct pci_dynids { 797 spinlock_t lock; /* Protects list, index */ 798 struct list_head list; /* For IDs added at runtime */ 799 }; 800 801 802 /* 803 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 804 * a set of callbacks in struct pci_error_handlers, that device driver 805 * will be notified of PCI bus errors, and will be driven to recovery 806 * when an error occurs. 807 */ 808 809 typedef unsigned int __bitwise pci_ers_result_t; 810 811 enum pci_ers_result { 812 /* No result/none/not supported in device driver */ 813 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 814 815 /* Device driver can recover without slot reset */ 816 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 817 818 /* Device driver wants slot to be reset */ 819 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 820 821 /* Device has completely failed, is unrecoverable */ 822 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 823 824 /* Device driver is fully recovered and operational */ 825 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 826 827 /* No AER capabilities registered for the driver */ 828 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 829 }; 830 831 /* PCI bus error event callbacks */ 832 struct pci_error_handlers { 833 /* PCI bus error detected on this device */ 834 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 835 pci_channel_state_t error); 836 837 /* MMIO has been re-enabled, but not DMA */ 838 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 839 840 /* PCI slot has been reset */ 841 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 842 843 /* PCI function reset prepare or completed */ 844 void (*reset_prepare)(struct pci_dev *dev); 845 void (*reset_done)(struct pci_dev *dev); 846 847 /* Device driver may resume normal operations */ 848 void (*resume)(struct pci_dev *dev); 849 }; 850 851 852 struct module; 853 854 /** 855 * struct pci_driver - PCI driver structure 856 * @node: List of driver structures. 857 * @name: Driver name. 858 * @id_table: Pointer to table of device IDs the driver is 859 * interested in. Most drivers should export this 860 * table using MODULE_DEVICE_TABLE(pci,...). 861 * @probe: This probing function gets called (during execution 862 * of pci_register_driver() for already existing 863 * devices or later if a new device gets inserted) for 864 * all PCI devices which match the ID table and are not 865 * "owned" by the other drivers yet. This function gets 866 * passed a "struct pci_dev \*" for each device whose 867 * entry in the ID table matches the device. The probe 868 * function returns zero when the driver chooses to 869 * take "ownership" of the device or an error code 870 * (negative number) otherwise. 871 * The probe function always gets called from process 872 * context, so it can sleep. 873 * @remove: The remove() function gets called whenever a device 874 * being handled by this driver is removed (either during 875 * deregistration of the driver or when it's manually 876 * pulled out of a hot-pluggable slot). 877 * The remove function always gets called from process 878 * context, so it can sleep. 879 * @suspend: Put device into low power state. 880 * @resume: Wake device from low power state. 881 * (Please see Documentation/power/pci.rst for descriptions 882 * of PCI Power Management and the related functions.) 883 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 884 * Intended to stop any idling DMA operations. 885 * Useful for enabling wake-on-lan (NIC) or changing 886 * the power state of a device before reboot. 887 * e.g. drivers/net/e100.c. 888 * @sriov_configure: Optional driver callback to allow configuration of 889 * number of VFs to enable via sysfs "sriov_numvfs" file. 890 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 891 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 892 * This will change MSI-X Table Size in the VF Message Control 893 * registers. 894 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 895 * MSI-X vectors available for distribution to the VFs. 896 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 897 * @groups: Sysfs attribute groups. 898 * @dev_groups: Attributes attached to the device that will be 899 * created once it is bound to the driver. 900 * @driver: Driver model structure. 901 * @dynids: List of dynamically added device IDs. 902 */ 903 struct pci_driver { 904 struct list_head node; 905 const char *name; 906 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 907 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 908 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 909 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 910 int (*resume)(struct pci_dev *dev); /* Device woken up */ 911 void (*shutdown)(struct pci_dev *dev); 912 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 913 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 914 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 915 const struct pci_error_handlers *err_handler; 916 const struct attribute_group **groups; 917 const struct attribute_group **dev_groups; 918 struct device_driver driver; 919 struct pci_dynids dynids; 920 }; 921 922 static inline struct pci_driver *to_pci_driver(struct device_driver *drv) 923 { 924 return drv ? container_of(drv, struct pci_driver, driver) : NULL; 925 } 926 927 /** 928 * PCI_DEVICE - macro used to describe a specific PCI device 929 * @vend: the 16 bit PCI Vendor ID 930 * @dev: the 16 bit PCI Device ID 931 * 932 * This macro is used to create a struct pci_device_id that matches a 933 * specific device. The subvendor and subdevice fields will be set to 934 * PCI_ANY_ID. 935 */ 936 #define PCI_DEVICE(vend,dev) \ 937 .vendor = (vend), .device = (dev), \ 938 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 939 940 /** 941 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 942 * override_only flags. 943 * @vend: the 16 bit PCI Vendor ID 944 * @dev: the 16 bit PCI Device ID 945 * @driver_override: the 32 bit PCI Device override_only 946 * 947 * This macro is used to create a struct pci_device_id that matches only a 948 * driver_override device. The subvendor and subdevice fields will be set to 949 * PCI_ANY_ID. 950 */ 951 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 952 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 953 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 954 955 /** 956 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 957 * "driver_override" PCI device. 958 * @vend: the 16 bit PCI Vendor ID 959 * @dev: the 16 bit PCI Device ID 960 * 961 * This macro is used to create a struct pci_device_id that matches a 962 * specific device. The subvendor and subdevice fields will be set to 963 * PCI_ANY_ID and the driver_override will be set to 964 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 965 */ 966 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 967 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 968 969 /** 970 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 971 * @vend: the 16 bit PCI Vendor ID 972 * @dev: the 16 bit PCI Device ID 973 * @subvend: the 16 bit PCI Subvendor ID 974 * @subdev: the 16 bit PCI Subdevice ID 975 * 976 * This macro is used to create a struct pci_device_id that matches a 977 * specific device with subsystem information. 978 */ 979 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 980 .vendor = (vend), .device = (dev), \ 981 .subvendor = (subvend), .subdevice = (subdev) 982 983 /** 984 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 985 * @dev_class: the class, subclass, prog-if triple for this device 986 * @dev_class_mask: the class mask for this device 987 * 988 * This macro is used to create a struct pci_device_id that matches a 989 * specific PCI class. The vendor, device, subvendor, and subdevice 990 * fields will be set to PCI_ANY_ID. 991 */ 992 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 993 .class = (dev_class), .class_mask = (dev_class_mask), \ 994 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 995 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 996 997 /** 998 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 999 * @vend: the vendor name 1000 * @dev: the 16 bit PCI Device ID 1001 * 1002 * This macro is used to create a struct pci_device_id that matches a 1003 * specific PCI device. The subvendor, and subdevice fields will be set 1004 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1005 * private data. 1006 */ 1007 #define PCI_VDEVICE(vend, dev) \ 1008 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1009 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1010 1011 /** 1012 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1013 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1014 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1015 * @data: the driver data to be filled 1016 * 1017 * This macro is used to create a struct pci_device_id that matches a 1018 * specific PCI device. The subvendor, and subdevice fields will be set 1019 * to PCI_ANY_ID. 1020 */ 1021 #define PCI_DEVICE_DATA(vend, dev, data) \ 1022 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1023 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1024 .driver_data = (kernel_ulong_t)(data) 1025 1026 enum { 1027 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1028 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1029 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1030 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1031 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1032 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1033 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1034 }; 1035 1036 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1037 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1038 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1039 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1040 1041 /* These external functions are only available when PCI support is enabled */ 1042 #ifdef CONFIG_PCI 1043 1044 extern unsigned int pci_flags; 1045 1046 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1047 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1048 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1049 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1050 1051 void pcie_bus_configure_settings(struct pci_bus *bus); 1052 1053 enum pcie_bus_config_types { 1054 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1055 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1056 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1057 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1058 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1059 }; 1060 1061 extern enum pcie_bus_config_types pcie_bus_config; 1062 1063 extern struct bus_type pci_bus_type; 1064 1065 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1066 * code, or PCI core code. */ 1067 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1068 /* Some device drivers need know if PCI is initiated */ 1069 int no_pci_devices(void); 1070 1071 void pcibios_resource_survey_bus(struct pci_bus *bus); 1072 void pcibios_bus_add_device(struct pci_dev *pdev); 1073 void pcibios_add_bus(struct pci_bus *bus); 1074 void pcibios_remove_bus(struct pci_bus *bus); 1075 void pcibios_fixup_bus(struct pci_bus *); 1076 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1077 /* Architecture-specific versions may override this (weak) */ 1078 char *pcibios_setup(char *str); 1079 1080 /* Used only when drivers/pci/setup.c is used */ 1081 resource_size_t pcibios_align_resource(void *, const struct resource *, 1082 resource_size_t, 1083 resource_size_t); 1084 1085 /* Weak but can be overridden by arch */ 1086 void pci_fixup_cardbus(struct pci_bus *); 1087 1088 /* Generic PCI functions used internally */ 1089 1090 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1091 struct resource *res); 1092 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1093 struct pci_bus_region *region); 1094 void pcibios_scan_specific_bus(int busn); 1095 struct pci_bus *pci_find_bus(int domain, int busnr); 1096 void pci_bus_add_devices(const struct pci_bus *bus); 1097 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1098 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1099 struct pci_ops *ops, void *sysdata, 1100 struct list_head *resources); 1101 int pci_host_probe(struct pci_host_bridge *bridge); 1102 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1103 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1104 void pci_bus_release_busn_res(struct pci_bus *b); 1105 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1106 struct pci_ops *ops, void *sysdata, 1107 struct list_head *resources); 1108 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1109 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1110 int busnr); 1111 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1112 const char *name, 1113 struct hotplug_slot *hotplug); 1114 void pci_destroy_slot(struct pci_slot *slot); 1115 #ifdef CONFIG_SYSFS 1116 void pci_dev_assign_slot(struct pci_dev *dev); 1117 #else 1118 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1119 #endif 1120 int pci_scan_slot(struct pci_bus *bus, int devfn); 1121 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1122 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1123 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1124 void pci_bus_add_device(struct pci_dev *dev); 1125 void pci_read_bridge_bases(struct pci_bus *child); 1126 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1127 struct resource *res); 1128 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1129 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1130 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1131 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1132 void pci_dev_put(struct pci_dev *dev); 1133 void pci_remove_bus(struct pci_bus *b); 1134 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1135 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1136 void pci_stop_root_bus(struct pci_bus *bus); 1137 void pci_remove_root_bus(struct pci_bus *bus); 1138 void pci_setup_cardbus(struct pci_bus *bus); 1139 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1140 void pci_sort_breadthfirst(void); 1141 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1142 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1143 1144 /* Generic PCI functions exported to card drivers */ 1145 1146 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1147 u8 pci_find_capability(struct pci_dev *dev, int cap); 1148 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1149 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1150 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1151 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1152 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1153 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1154 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1155 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1156 1157 u64 pci_get_dsn(struct pci_dev *dev); 1158 1159 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1160 struct pci_dev *from); 1161 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1162 unsigned int ss_vendor, unsigned int ss_device, 1163 struct pci_dev *from); 1164 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1165 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1166 unsigned int devfn); 1167 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1168 int pci_dev_present(const struct pci_device_id *ids); 1169 1170 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1171 int where, u8 *val); 1172 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1173 int where, u16 *val); 1174 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1175 int where, u32 *val); 1176 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1177 int where, u8 val); 1178 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1179 int where, u16 val); 1180 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1181 int where, u32 val); 1182 1183 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1184 int where, int size, u32 *val); 1185 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1186 int where, int size, u32 val); 1187 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1188 int where, int size, u32 *val); 1189 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1190 int where, int size, u32 val); 1191 1192 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1193 1194 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1195 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1196 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1197 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1198 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1199 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1200 1201 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1202 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1203 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1204 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1205 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1206 u16 clear, u16 set); 1207 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1208 u32 clear, u32 set); 1209 1210 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1211 u16 set) 1212 { 1213 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1214 } 1215 1216 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1217 u32 set) 1218 { 1219 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1220 } 1221 1222 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1223 u16 clear) 1224 { 1225 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1226 } 1227 1228 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1229 u32 clear) 1230 { 1231 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1232 } 1233 1234 /* User-space driven config access */ 1235 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1236 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1237 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1238 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1239 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1240 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1241 1242 int __must_check pci_enable_device(struct pci_dev *dev); 1243 int __must_check pci_enable_device_io(struct pci_dev *dev); 1244 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1245 int __must_check pci_reenable_device(struct pci_dev *); 1246 int __must_check pcim_enable_device(struct pci_dev *pdev); 1247 void pcim_pin_device(struct pci_dev *pdev); 1248 1249 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1250 { 1251 /* 1252 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1253 * writable and no quirk has marked the feature broken. 1254 */ 1255 return !pdev->broken_intx_masking; 1256 } 1257 1258 static inline int pci_is_enabled(struct pci_dev *pdev) 1259 { 1260 return (atomic_read(&pdev->enable_cnt) > 0); 1261 } 1262 1263 static inline int pci_is_managed(struct pci_dev *pdev) 1264 { 1265 return pdev->is_managed; 1266 } 1267 1268 void pci_disable_device(struct pci_dev *dev); 1269 1270 extern unsigned int pcibios_max_latency; 1271 void pci_set_master(struct pci_dev *dev); 1272 void pci_clear_master(struct pci_dev *dev); 1273 1274 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1275 int pci_set_cacheline_size(struct pci_dev *dev); 1276 int __must_check pci_set_mwi(struct pci_dev *dev); 1277 int __must_check pcim_set_mwi(struct pci_dev *dev); 1278 int pci_try_set_mwi(struct pci_dev *dev); 1279 void pci_clear_mwi(struct pci_dev *dev); 1280 void pci_disable_parity(struct pci_dev *dev); 1281 void pci_intx(struct pci_dev *dev, int enable); 1282 bool pci_check_and_mask_intx(struct pci_dev *dev); 1283 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1284 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1285 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1286 int pcix_get_max_mmrbc(struct pci_dev *dev); 1287 int pcix_get_mmrbc(struct pci_dev *dev); 1288 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1289 int pcie_get_readrq(struct pci_dev *dev); 1290 int pcie_set_readrq(struct pci_dev *dev, int rq); 1291 int pcie_get_mps(struct pci_dev *dev); 1292 int pcie_set_mps(struct pci_dev *dev, int mps); 1293 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1294 enum pci_bus_speed *speed, 1295 enum pcie_link_width *width); 1296 void pcie_print_link_status(struct pci_dev *dev); 1297 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1298 int pcie_flr(struct pci_dev *dev); 1299 int __pci_reset_function_locked(struct pci_dev *dev); 1300 int pci_reset_function(struct pci_dev *dev); 1301 int pci_reset_function_locked(struct pci_dev *dev); 1302 int pci_try_reset_function(struct pci_dev *dev); 1303 int pci_probe_reset_slot(struct pci_slot *slot); 1304 int pci_probe_reset_bus(struct pci_bus *bus); 1305 int pci_reset_bus(struct pci_dev *dev); 1306 void pci_reset_secondary_bus(struct pci_dev *dev); 1307 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1308 void pci_update_resource(struct pci_dev *dev, int resno); 1309 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1310 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1311 void pci_release_resource(struct pci_dev *dev, int resno); 1312 static inline int pci_rebar_bytes_to_size(u64 bytes) 1313 { 1314 bytes = roundup_pow_of_two(bytes); 1315 1316 /* Return BAR size as defined in the resizable BAR specification */ 1317 return max(ilog2(bytes), 20) - 20; 1318 } 1319 1320 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1321 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1322 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1323 bool pci_device_is_present(struct pci_dev *pdev); 1324 void pci_ignore_hotplug(struct pci_dev *dev); 1325 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1326 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1327 1328 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1329 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1330 const char *fmt, ...); 1331 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1332 1333 /* ROM control related routines */ 1334 int pci_enable_rom(struct pci_dev *pdev); 1335 void pci_disable_rom(struct pci_dev *pdev); 1336 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1337 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1338 1339 /* Power management related routines */ 1340 int pci_save_state(struct pci_dev *dev); 1341 void pci_restore_state(struct pci_dev *dev); 1342 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1343 int pci_load_saved_state(struct pci_dev *dev, 1344 struct pci_saved_state *state); 1345 int pci_load_and_free_saved_state(struct pci_dev *dev, 1346 struct pci_saved_state **state); 1347 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1348 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1349 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1350 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1351 void pci_pme_active(struct pci_dev *dev, bool enable); 1352 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1353 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1354 int pci_prepare_to_sleep(struct pci_dev *dev); 1355 int pci_back_from_sleep(struct pci_dev *dev); 1356 bool pci_dev_run_wake(struct pci_dev *dev); 1357 void pci_d3cold_enable(struct pci_dev *dev); 1358 void pci_d3cold_disable(struct pci_dev *dev); 1359 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1360 void pci_resume_bus(struct pci_bus *bus); 1361 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1362 1363 /* For use by arch with custom probe code */ 1364 void set_pcie_port_type(struct pci_dev *pdev); 1365 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1366 1367 /* Functions for PCI Hotplug drivers to use */ 1368 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1369 unsigned int pci_rescan_bus(struct pci_bus *bus); 1370 void pci_lock_rescan_remove(void); 1371 void pci_unlock_rescan_remove(void); 1372 1373 /* Vital Product Data routines */ 1374 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1375 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1376 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1377 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1378 1379 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1380 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1381 void pci_bus_assign_resources(const struct pci_bus *bus); 1382 void pci_bus_claim_resources(struct pci_bus *bus); 1383 void pci_bus_size_bridges(struct pci_bus *bus); 1384 int pci_claim_resource(struct pci_dev *, int); 1385 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1386 void pci_assign_unassigned_resources(void); 1387 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1388 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1389 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1390 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1391 void pdev_enable_device(struct pci_dev *); 1392 int pci_enable_resources(struct pci_dev *, int mask); 1393 void pci_assign_irq(struct pci_dev *dev); 1394 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1395 #define HAVE_PCI_REQ_REGIONS 2 1396 int __must_check pci_request_regions(struct pci_dev *, const char *); 1397 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1398 void pci_release_regions(struct pci_dev *); 1399 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1400 void pci_release_region(struct pci_dev *, int); 1401 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1402 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1403 void pci_release_selected_regions(struct pci_dev *, int); 1404 1405 /* drivers/pci/bus.c */ 1406 void pci_add_resource(struct list_head *resources, struct resource *res); 1407 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1408 resource_size_t offset); 1409 void pci_free_resource_list(struct list_head *resources); 1410 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1411 unsigned int flags); 1412 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1413 void pci_bus_remove_resources(struct pci_bus *bus); 1414 int devm_request_pci_bus_resources(struct device *dev, 1415 struct list_head *resources); 1416 1417 /* Temporary until new and working PCI SBR API in place */ 1418 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1419 1420 #define pci_bus_for_each_resource(bus, res, i) \ 1421 for (i = 0; \ 1422 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1423 i++) 1424 1425 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1426 struct resource *res, resource_size_t size, 1427 resource_size_t align, resource_size_t min, 1428 unsigned long type_mask, 1429 resource_size_t (*alignf)(void *, 1430 const struct resource *, 1431 resource_size_t, 1432 resource_size_t), 1433 void *alignf_data); 1434 1435 1436 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1437 resource_size_t size); 1438 unsigned long pci_address_to_pio(phys_addr_t addr); 1439 phys_addr_t pci_pio_to_address(unsigned long pio); 1440 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1441 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1442 phys_addr_t phys_addr); 1443 void pci_unmap_iospace(struct resource *res); 1444 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1445 resource_size_t offset, 1446 resource_size_t size); 1447 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1448 struct resource *res); 1449 1450 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1451 { 1452 struct pci_bus_region region; 1453 1454 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1455 return region.start; 1456 } 1457 1458 /* Proper probing supporting hot-pluggable devices */ 1459 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1460 const char *mod_name); 1461 1462 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1463 #define pci_register_driver(driver) \ 1464 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1465 1466 void pci_unregister_driver(struct pci_driver *dev); 1467 1468 /** 1469 * module_pci_driver() - Helper macro for registering a PCI driver 1470 * @__pci_driver: pci_driver struct 1471 * 1472 * Helper macro for PCI drivers which do not do anything special in module 1473 * init/exit. This eliminates a lot of boilerplate. Each module may only 1474 * use this macro once, and calling it replaces module_init() and module_exit() 1475 */ 1476 #define module_pci_driver(__pci_driver) \ 1477 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1478 1479 /** 1480 * builtin_pci_driver() - Helper macro for registering a PCI driver 1481 * @__pci_driver: pci_driver struct 1482 * 1483 * Helper macro for PCI drivers which do not do anything special in their 1484 * init code. This eliminates a lot of boilerplate. Each driver may only 1485 * use this macro once, and calling it replaces device_initcall(...) 1486 */ 1487 #define builtin_pci_driver(__pci_driver) \ 1488 builtin_driver(__pci_driver, pci_register_driver) 1489 1490 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1491 int pci_add_dynid(struct pci_driver *drv, 1492 unsigned int vendor, unsigned int device, 1493 unsigned int subvendor, unsigned int subdevice, 1494 unsigned int class, unsigned int class_mask, 1495 unsigned long driver_data); 1496 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1497 struct pci_dev *dev); 1498 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1499 int pass); 1500 1501 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1502 void *userdata); 1503 int pci_cfg_space_size(struct pci_dev *dev); 1504 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1505 void pci_setup_bridge(struct pci_bus *bus); 1506 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1507 unsigned long type); 1508 1509 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1510 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1511 1512 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1513 unsigned int command_bits, u32 flags); 1514 1515 /* 1516 * Virtual interrupts allow for more interrupts to be allocated 1517 * than the device has interrupts for. These are not programmed 1518 * into the device's MSI-X table and must be handled by some 1519 * other driver means. 1520 */ 1521 #define PCI_IRQ_VIRTUAL (1 << 4) 1522 1523 #define PCI_IRQ_ALL_TYPES \ 1524 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1525 1526 #include <linux/dmapool.h> 1527 1528 struct msix_entry { 1529 u32 vector; /* Kernel uses to write allocated vector */ 1530 u16 entry; /* Driver uses to specify entry, OS writes */ 1531 }; 1532 1533 #ifdef CONFIG_PCI_MSI 1534 int pci_msi_vec_count(struct pci_dev *dev); 1535 void pci_disable_msi(struct pci_dev *dev); 1536 int pci_msix_vec_count(struct pci_dev *dev); 1537 void pci_disable_msix(struct pci_dev *dev); 1538 void pci_restore_msi_state(struct pci_dev *dev); 1539 int pci_msi_enabled(void); 1540 int pci_enable_msi(struct pci_dev *dev); 1541 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1542 int minvec, int maxvec); 1543 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1544 struct msix_entry *entries, int nvec) 1545 { 1546 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1547 if (rc < 0) 1548 return rc; 1549 return 0; 1550 } 1551 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1552 unsigned int max_vecs, unsigned int flags, 1553 struct irq_affinity *affd); 1554 1555 void pci_free_irq_vectors(struct pci_dev *dev); 1556 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1557 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1558 1559 #else 1560 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1561 static inline void pci_disable_msi(struct pci_dev *dev) { } 1562 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1563 static inline void pci_disable_msix(struct pci_dev *dev) { } 1564 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1565 static inline int pci_msi_enabled(void) { return 0; } 1566 static inline int pci_enable_msi(struct pci_dev *dev) 1567 { return -ENOSYS; } 1568 static inline int pci_enable_msix_range(struct pci_dev *dev, 1569 struct msix_entry *entries, int minvec, int maxvec) 1570 { return -ENOSYS; } 1571 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1572 struct msix_entry *entries, int nvec) 1573 { return -ENOSYS; } 1574 1575 static inline int 1576 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1577 unsigned int max_vecs, unsigned int flags, 1578 struct irq_affinity *aff_desc) 1579 { 1580 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1581 return 1; 1582 return -ENOSPC; 1583 } 1584 1585 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1586 { 1587 } 1588 1589 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1590 { 1591 if (WARN_ON_ONCE(nr > 0)) 1592 return -EINVAL; 1593 return dev->irq; 1594 } 1595 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1596 int vec) 1597 { 1598 return cpu_possible_mask; 1599 } 1600 #endif 1601 1602 /** 1603 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1604 * @d: the INTx IRQ domain 1605 * @node: the DT node for the device whose interrupt we're translating 1606 * @intspec: the interrupt specifier data from the DT 1607 * @intsize: the number of entries in @intspec 1608 * @out_hwirq: pointer at which to write the hwirq number 1609 * @out_type: pointer at which to write the interrupt type 1610 * 1611 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1612 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1613 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1614 * INTx value to obtain the hwirq number. 1615 * 1616 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1617 */ 1618 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1619 struct device_node *node, 1620 const u32 *intspec, 1621 unsigned int intsize, 1622 unsigned long *out_hwirq, 1623 unsigned int *out_type) 1624 { 1625 const u32 intx = intspec[0]; 1626 1627 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1628 return -EINVAL; 1629 1630 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1631 return 0; 1632 } 1633 1634 #ifdef CONFIG_PCIEPORTBUS 1635 extern bool pcie_ports_disabled; 1636 extern bool pcie_ports_native; 1637 #else 1638 #define pcie_ports_disabled true 1639 #define pcie_ports_native false 1640 #endif 1641 1642 #define PCIE_LINK_STATE_L0S BIT(0) 1643 #define PCIE_LINK_STATE_L1 BIT(1) 1644 #define PCIE_LINK_STATE_CLKPM BIT(2) 1645 #define PCIE_LINK_STATE_L1_1 BIT(3) 1646 #define PCIE_LINK_STATE_L1_2 BIT(4) 1647 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1648 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1649 1650 #ifdef CONFIG_PCIEASPM 1651 int pci_disable_link_state(struct pci_dev *pdev, int state); 1652 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1653 void pcie_no_aspm(void); 1654 bool pcie_aspm_support_enabled(void); 1655 bool pcie_aspm_enabled(struct pci_dev *pdev); 1656 #else 1657 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1658 { return 0; } 1659 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1660 { return 0; } 1661 static inline void pcie_no_aspm(void) { } 1662 static inline bool pcie_aspm_support_enabled(void) { return false; } 1663 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1664 #endif 1665 1666 #ifdef CONFIG_PCIEAER 1667 bool pci_aer_available(void); 1668 #else 1669 static inline bool pci_aer_available(void) { return false; } 1670 #endif 1671 1672 bool pci_ats_disabled(void); 1673 1674 #ifdef CONFIG_PCIE_PTM 1675 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1676 bool pcie_ptm_enabled(struct pci_dev *dev); 1677 #else 1678 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1679 { return -EINVAL; } 1680 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1681 { return false; } 1682 #endif 1683 1684 void pci_cfg_access_lock(struct pci_dev *dev); 1685 bool pci_cfg_access_trylock(struct pci_dev *dev); 1686 void pci_cfg_access_unlock(struct pci_dev *dev); 1687 1688 void pci_dev_lock(struct pci_dev *dev); 1689 int pci_dev_trylock(struct pci_dev *dev); 1690 void pci_dev_unlock(struct pci_dev *dev); 1691 1692 /* 1693 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1694 * a PCI domain is defined to be a set of PCI buses which share 1695 * configuration space. 1696 */ 1697 #ifdef CONFIG_PCI_DOMAINS 1698 extern int pci_domains_supported; 1699 #else 1700 enum { pci_domains_supported = 0 }; 1701 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1702 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1703 #endif /* CONFIG_PCI_DOMAINS */ 1704 1705 /* 1706 * Generic implementation for PCI domain support. If your 1707 * architecture does not need custom management of PCI 1708 * domains then this implementation will be used 1709 */ 1710 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1711 static inline int pci_domain_nr(struct pci_bus *bus) 1712 { 1713 return bus->domain_nr; 1714 } 1715 #ifdef CONFIG_ACPI 1716 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1717 #else 1718 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1719 { return 0; } 1720 #endif 1721 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1722 #endif 1723 1724 /* Some architectures require additional setup to direct VGA traffic */ 1725 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1726 unsigned int command_bits, u32 flags); 1727 void pci_register_set_vga_state(arch_set_vga_state_t func); 1728 1729 static inline int 1730 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1731 { 1732 return pci_request_selected_regions(pdev, 1733 pci_select_bars(pdev, IORESOURCE_IO), name); 1734 } 1735 1736 static inline void 1737 pci_release_io_regions(struct pci_dev *pdev) 1738 { 1739 return pci_release_selected_regions(pdev, 1740 pci_select_bars(pdev, IORESOURCE_IO)); 1741 } 1742 1743 static inline int 1744 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1745 { 1746 return pci_request_selected_regions(pdev, 1747 pci_select_bars(pdev, IORESOURCE_MEM), name); 1748 } 1749 1750 static inline void 1751 pci_release_mem_regions(struct pci_dev *pdev) 1752 { 1753 return pci_release_selected_regions(pdev, 1754 pci_select_bars(pdev, IORESOURCE_MEM)); 1755 } 1756 1757 #else /* CONFIG_PCI is not enabled */ 1758 1759 static inline void pci_set_flags(int flags) { } 1760 static inline void pci_add_flags(int flags) { } 1761 static inline void pci_clear_flags(int flags) { } 1762 static inline int pci_has_flag(int flag) { return 0; } 1763 1764 /* 1765 * If the system does not have PCI, clearly these return errors. Define 1766 * these as simple inline functions to avoid hair in drivers. 1767 */ 1768 #define _PCI_NOP(o, s, t) \ 1769 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1770 int where, t val) \ 1771 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1772 1773 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1774 _PCI_NOP(o, word, u16 x) \ 1775 _PCI_NOP(o, dword, u32 x) 1776 _PCI_NOP_ALL(read, *) 1777 _PCI_NOP_ALL(write,) 1778 1779 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1780 unsigned int device, 1781 struct pci_dev *from) 1782 { return NULL; } 1783 1784 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1785 unsigned int device, 1786 unsigned int ss_vendor, 1787 unsigned int ss_device, 1788 struct pci_dev *from) 1789 { return NULL; } 1790 1791 static inline struct pci_dev *pci_get_class(unsigned int class, 1792 struct pci_dev *from) 1793 { return NULL; } 1794 1795 1796 static inline int pci_dev_present(const struct pci_device_id *ids) 1797 { return 0; } 1798 1799 #define no_pci_devices() (1) 1800 #define pci_dev_put(dev) do { } while (0) 1801 1802 static inline void pci_set_master(struct pci_dev *dev) { } 1803 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1804 static inline void pci_disable_device(struct pci_dev *dev) { } 1805 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1806 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1807 { return -EBUSY; } 1808 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 1809 struct module *owner, 1810 const char *mod_name) 1811 { return 0; } 1812 static inline int pci_register_driver(struct pci_driver *drv) 1813 { return 0; } 1814 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1815 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1816 { return 0; } 1817 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1818 int cap) 1819 { return 0; } 1820 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1821 { return 0; } 1822 1823 static inline u64 pci_get_dsn(struct pci_dev *dev) 1824 { return 0; } 1825 1826 /* Power management related routines */ 1827 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1828 static inline void pci_restore_state(struct pci_dev *dev) { } 1829 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1830 { return 0; } 1831 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1832 { return 0; } 1833 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1834 pm_message_t state) 1835 { return PCI_D0; } 1836 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1837 int enable) 1838 { return 0; } 1839 1840 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1841 struct resource *res) 1842 { return NULL; } 1843 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1844 { return -EIO; } 1845 static inline void pci_release_regions(struct pci_dev *dev) { } 1846 1847 static inline int pci_register_io_range(struct fwnode_handle *fwnode, 1848 phys_addr_t addr, resource_size_t size) 1849 { return -EINVAL; } 1850 1851 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1852 1853 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1854 { return NULL; } 1855 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1856 unsigned int devfn) 1857 { return NULL; } 1858 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1859 unsigned int bus, unsigned int devfn) 1860 { return NULL; } 1861 1862 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1863 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1864 1865 #define dev_is_pci(d) (false) 1866 #define dev_is_pf(d) (false) 1867 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1868 { return false; } 1869 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1870 struct device_node *node, 1871 const u32 *intspec, 1872 unsigned int intsize, 1873 unsigned long *out_hwirq, 1874 unsigned int *out_type) 1875 { return -EINVAL; } 1876 1877 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1878 struct pci_dev *dev) 1879 { return NULL; } 1880 static inline bool pci_ats_disabled(void) { return true; } 1881 1882 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1883 { 1884 return -EINVAL; 1885 } 1886 1887 static inline int 1888 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1889 unsigned int max_vecs, unsigned int flags, 1890 struct irq_affinity *aff_desc) 1891 { 1892 return -ENOSPC; 1893 } 1894 #endif /* CONFIG_PCI */ 1895 1896 static inline int 1897 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1898 unsigned int max_vecs, unsigned int flags) 1899 { 1900 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1901 NULL); 1902 } 1903 1904 /* Include architecture-dependent settings and functions */ 1905 1906 #include <asm/pci.h> 1907 1908 /* These two functions provide almost identical functionality. Depending 1909 * on the architecture, one will be implemented as a wrapper around the 1910 * other (in drivers/pci/mmap.c). 1911 * 1912 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1913 * is expected to be an offset within that region. 1914 * 1915 * pci_mmap_page_range() is the legacy architecture-specific interface, 1916 * which accepts a "user visible" resource address converted by 1917 * pci_resource_to_user(), as used in the legacy mmap() interface in 1918 * /proc/bus/pci/. 1919 */ 1920 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1921 struct vm_area_struct *vma, 1922 enum pci_mmap_state mmap_state, int write_combine); 1923 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1924 struct vm_area_struct *vma, 1925 enum pci_mmap_state mmap_state, int write_combine); 1926 1927 #ifndef arch_can_pci_mmap_wc 1928 #define arch_can_pci_mmap_wc() 0 1929 #endif 1930 1931 #ifndef arch_can_pci_mmap_io 1932 #define arch_can_pci_mmap_io() 0 1933 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1934 #else 1935 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1936 #endif 1937 1938 #ifndef pci_root_bus_fwnode 1939 #define pci_root_bus_fwnode(bus) NULL 1940 #endif 1941 1942 /* 1943 * These helpers provide future and backwards compatibility 1944 * for accessing popular PCI BAR info 1945 */ 1946 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1947 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1948 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1949 #define pci_resource_len(dev,bar) \ 1950 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \ 1951 \ 1952 (pci_resource_end((dev), (bar)) - \ 1953 pci_resource_start((dev), (bar)) + 1)) 1954 1955 /* 1956 * Similar to the helpers above, these manipulate per-pci_dev 1957 * driver-specific data. They are really just a wrapper around 1958 * the generic device structure functions of these calls. 1959 */ 1960 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1961 { 1962 return dev_get_drvdata(&pdev->dev); 1963 } 1964 1965 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1966 { 1967 dev_set_drvdata(&pdev->dev, data); 1968 } 1969 1970 static inline const char *pci_name(const struct pci_dev *pdev) 1971 { 1972 return dev_name(&pdev->dev); 1973 } 1974 1975 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1976 const struct resource *rsrc, 1977 resource_size_t *start, resource_size_t *end); 1978 1979 /* 1980 * The world is not perfect and supplies us with broken PCI devices. 1981 * For at least a part of these bugs we need a work-around, so both 1982 * generic (drivers/pci/quirks.c) and per-architecture code can define 1983 * fixup hooks to be called for particular buggy devices. 1984 */ 1985 1986 struct pci_fixup { 1987 u16 vendor; /* Or PCI_ANY_ID */ 1988 u16 device; /* Or PCI_ANY_ID */ 1989 u32 class; /* Or PCI_ANY_ID */ 1990 unsigned int class_shift; /* should be 0, 8, 16 */ 1991 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1992 int hook_offset; 1993 #else 1994 void (*hook)(struct pci_dev *dev); 1995 #endif 1996 }; 1997 1998 enum pci_fixup_pass { 1999 pci_fixup_early, /* Before probing BARs */ 2000 pci_fixup_header, /* After reading configuration header */ 2001 pci_fixup_final, /* Final phase of device fixups */ 2002 pci_fixup_enable, /* pci_enable_device() time */ 2003 pci_fixup_resume, /* pci_device_resume() */ 2004 pci_fixup_suspend, /* pci_device_suspend() */ 2005 pci_fixup_resume_early, /* pci_device_resume_early() */ 2006 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2007 }; 2008 2009 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2010 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2011 class_shift, hook) \ 2012 __ADDRESSABLE(hook) \ 2013 asm(".section " #sec ", \"a\" \n" \ 2014 ".balign 16 \n" \ 2015 ".short " #vendor ", " #device " \n" \ 2016 ".long " #class ", " #class_shift " \n" \ 2017 ".long " #hook " - . \n" \ 2018 ".previous \n"); 2019 2020 /* 2021 * Clang's LTO may rename static functions in C, but has no way to 2022 * handle such renamings when referenced from inline asm. To work 2023 * around this, create global C stubs for these cases. 2024 */ 2025 #ifdef CONFIG_LTO_CLANG 2026 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2027 class_shift, hook, stub) \ 2028 void __cficanonical stub(struct pci_dev *dev); \ 2029 void __cficanonical stub(struct pci_dev *dev) \ 2030 { \ 2031 hook(dev); \ 2032 } \ 2033 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2034 class_shift, stub) 2035 #else 2036 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2037 class_shift, hook, stub) \ 2038 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2039 class_shift, hook) 2040 #endif 2041 2042 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2043 class_shift, hook) \ 2044 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2045 class_shift, hook, __UNIQUE_ID(hook)) 2046 #else 2047 /* Anonymous variables would be nice... */ 2048 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2049 class_shift, hook) \ 2050 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2051 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2052 = { vendor, device, class, class_shift, hook }; 2053 #endif 2054 2055 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2056 class_shift, hook) \ 2057 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2058 hook, vendor, device, class, class_shift, hook) 2059 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2060 class_shift, hook) \ 2061 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2062 hook, vendor, device, class, class_shift, hook) 2063 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2064 class_shift, hook) \ 2065 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2066 hook, vendor, device, class, class_shift, hook) 2067 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2068 class_shift, hook) \ 2069 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2070 hook, vendor, device, class, class_shift, hook) 2071 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2072 class_shift, hook) \ 2073 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2074 resume##hook, vendor, device, class, class_shift, hook) 2075 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2076 class_shift, hook) \ 2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2078 resume_early##hook, vendor, device, class, class_shift, hook) 2079 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2080 class_shift, hook) \ 2081 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2082 suspend##hook, vendor, device, class, class_shift, hook) 2083 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2084 class_shift, hook) \ 2085 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2086 suspend_late##hook, vendor, device, class, class_shift, hook) 2087 2088 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2089 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2090 hook, vendor, device, PCI_ANY_ID, 0, hook) 2091 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2092 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2093 hook, vendor, device, PCI_ANY_ID, 0, hook) 2094 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2095 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2096 hook, vendor, device, PCI_ANY_ID, 0, hook) 2097 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2098 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2099 hook, vendor, device, PCI_ANY_ID, 0, hook) 2100 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2101 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2102 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2103 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2104 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2105 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2106 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2107 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2108 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2109 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2110 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2111 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2112 2113 #ifdef CONFIG_PCI_QUIRKS 2114 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2115 #else 2116 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2117 struct pci_dev *dev) { } 2118 #endif 2119 2120 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2121 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2122 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2123 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2124 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2125 const char *name); 2126 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2127 2128 extern int pci_pci_problems; 2129 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2130 #define PCIPCI_TRITON 2 2131 #define PCIPCI_NATOMA 4 2132 #define PCIPCI_VIAETBF 8 2133 #define PCIPCI_VSFX 16 2134 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2135 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2136 2137 extern unsigned long pci_cardbus_io_size; 2138 extern unsigned long pci_cardbus_mem_size; 2139 extern u8 pci_dfl_cache_line_size; 2140 extern u8 pci_cache_line_size; 2141 2142 /* Architecture-specific versions may override these (weak) */ 2143 void pcibios_disable_device(struct pci_dev *dev); 2144 void pcibios_set_master(struct pci_dev *dev); 2145 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2146 enum pcie_reset_state state); 2147 int pcibios_device_add(struct pci_dev *dev); 2148 void pcibios_release_device(struct pci_dev *dev); 2149 #ifdef CONFIG_PCI 2150 void pcibios_penalize_isa_irq(int irq, int active); 2151 #else 2152 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2153 #endif 2154 int pcibios_alloc_irq(struct pci_dev *dev); 2155 void pcibios_free_irq(struct pci_dev *dev); 2156 resource_size_t pcibios_default_alignment(void); 2157 2158 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2159 void __init pci_mmcfg_early_init(void); 2160 void __init pci_mmcfg_late_init(void); 2161 #else 2162 static inline void pci_mmcfg_early_init(void) { } 2163 static inline void pci_mmcfg_late_init(void) { } 2164 #endif 2165 2166 int pci_ext_cfg_avail(void); 2167 2168 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2169 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2170 2171 #ifdef CONFIG_PCI_IOV 2172 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2173 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2174 int pci_iov_vf_id(struct pci_dev *dev); 2175 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2176 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2177 void pci_disable_sriov(struct pci_dev *dev); 2178 2179 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2180 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2181 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2182 int pci_num_vf(struct pci_dev *dev); 2183 int pci_vfs_assigned(struct pci_dev *dev); 2184 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2185 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2186 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2187 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2188 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2189 2190 /* Arch may override these (weak) */ 2191 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2192 int pcibios_sriov_disable(struct pci_dev *pdev); 2193 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2194 #else 2195 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2196 { 2197 return -ENOSYS; 2198 } 2199 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2200 { 2201 return -ENOSYS; 2202 } 2203 2204 static inline int pci_iov_vf_id(struct pci_dev *dev) 2205 { 2206 return -ENOSYS; 2207 } 2208 2209 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2210 struct pci_driver *pf_driver) 2211 { 2212 return ERR_PTR(-EINVAL); 2213 } 2214 2215 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2216 { return -ENODEV; } 2217 2218 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2219 struct pci_dev *virtfn, int id) 2220 { 2221 return -ENODEV; 2222 } 2223 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2224 { 2225 return -ENOSYS; 2226 } 2227 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2228 int id) { } 2229 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2230 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2231 static inline int pci_vfs_assigned(struct pci_dev *dev) 2232 { return 0; } 2233 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2234 { return 0; } 2235 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2236 { return 0; } 2237 #define pci_sriov_configure_simple NULL 2238 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2239 { return 0; } 2240 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2241 #endif 2242 2243 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2244 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2245 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2246 #endif 2247 2248 /** 2249 * pci_pcie_cap - get the saved PCIe capability offset 2250 * @dev: PCI device 2251 * 2252 * PCIe capability offset is calculated at PCI device initialization 2253 * time and saved in the data structure. This function returns saved 2254 * PCIe capability offset. Using this instead of pci_find_capability() 2255 * reduces unnecessary search in the PCI configuration space. If you 2256 * need to calculate PCIe capability offset from raw device for some 2257 * reasons, please use pci_find_capability() instead. 2258 */ 2259 static inline int pci_pcie_cap(struct pci_dev *dev) 2260 { 2261 return dev->pcie_cap; 2262 } 2263 2264 /** 2265 * pci_is_pcie - check if the PCI device is PCI Express capable 2266 * @dev: PCI device 2267 * 2268 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2269 */ 2270 static inline bool pci_is_pcie(struct pci_dev *dev) 2271 { 2272 return pci_pcie_cap(dev); 2273 } 2274 2275 /** 2276 * pcie_caps_reg - get the PCIe Capabilities Register 2277 * @dev: PCI device 2278 */ 2279 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2280 { 2281 return dev->pcie_flags_reg; 2282 } 2283 2284 /** 2285 * pci_pcie_type - get the PCIe device/port type 2286 * @dev: PCI device 2287 */ 2288 static inline int pci_pcie_type(const struct pci_dev *dev) 2289 { 2290 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2291 } 2292 2293 /** 2294 * pcie_find_root_port - Get the PCIe root port device 2295 * @dev: PCI device 2296 * 2297 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2298 * for a given PCI/PCIe Device. 2299 */ 2300 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2301 { 2302 while (dev) { 2303 if (pci_is_pcie(dev) && 2304 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2305 return dev; 2306 dev = pci_upstream_bridge(dev); 2307 } 2308 2309 return NULL; 2310 } 2311 2312 void pci_request_acs(void); 2313 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2314 bool pci_acs_path_enabled(struct pci_dev *start, 2315 struct pci_dev *end, u16 acs_flags); 2316 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2317 2318 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2319 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2320 2321 /* Large Resource Data Type Tag Item Names */ 2322 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2323 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2324 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2325 2326 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2327 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2328 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2329 2330 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2331 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2332 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2333 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2334 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2335 2336 /** 2337 * pci_vpd_alloc - Allocate buffer and read VPD into it 2338 * @dev: PCI device 2339 * @size: pointer to field where VPD length is returned 2340 * 2341 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2342 */ 2343 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2344 2345 /** 2346 * pci_vpd_find_id_string - Locate id string in VPD 2347 * @buf: Pointer to buffered VPD data 2348 * @len: The length of the buffer area in which to search 2349 * @size: Pointer to field where length of id string is returned 2350 * 2351 * Returns the index of the id string or -ENOENT if not found. 2352 */ 2353 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2354 2355 /** 2356 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2357 * @buf: Pointer to buffered VPD data 2358 * @len: The length of the buffer area in which to search 2359 * @kw: The keyword to search for 2360 * @size: Pointer to field where length of found keyword data is returned 2361 * 2362 * Returns the index of the information field keyword data or -ENOENT if 2363 * not found. 2364 */ 2365 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2366 const char *kw, unsigned int *size); 2367 2368 /** 2369 * pci_vpd_check_csum - Check VPD checksum 2370 * @buf: Pointer to buffered VPD data 2371 * @len: VPD size 2372 * 2373 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2374 */ 2375 int pci_vpd_check_csum(const void *buf, unsigned int len); 2376 2377 /* PCI <-> OF binding helpers */ 2378 #ifdef CONFIG_OF 2379 struct device_node; 2380 struct irq_domain; 2381 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2382 bool pci_host_of_has_msi_map(struct device *dev); 2383 2384 /* Arch may override this (weak) */ 2385 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2386 2387 #else /* CONFIG_OF */ 2388 static inline struct irq_domain * 2389 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2390 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2391 #endif /* CONFIG_OF */ 2392 2393 static inline struct device_node * 2394 pci_device_to_OF_node(const struct pci_dev *pdev) 2395 { 2396 return pdev ? pdev->dev.of_node : NULL; 2397 } 2398 2399 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2400 { 2401 return bus ? bus->dev.of_node : NULL; 2402 } 2403 2404 #ifdef CONFIG_ACPI 2405 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2406 2407 void 2408 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2409 bool pci_pr3_present(struct pci_dev *pdev); 2410 #else 2411 static inline struct irq_domain * 2412 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2413 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2414 #endif 2415 2416 #ifdef CONFIG_EEH 2417 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2418 { 2419 return pdev->dev.archdata.edev; 2420 } 2421 #endif 2422 2423 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2424 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2425 int pci_for_each_dma_alias(struct pci_dev *pdev, 2426 int (*fn)(struct pci_dev *pdev, 2427 u16 alias, void *data), void *data); 2428 2429 /* Helper functions for operation of device flag */ 2430 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2431 { 2432 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2433 } 2434 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2435 { 2436 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2437 } 2438 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2439 { 2440 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2441 } 2442 2443 /** 2444 * pci_ari_enabled - query ARI forwarding status 2445 * @bus: the PCI bus 2446 * 2447 * Returns true if ARI forwarding is enabled. 2448 */ 2449 static inline bool pci_ari_enabled(struct pci_bus *bus) 2450 { 2451 return bus->self && bus->self->ari_enabled; 2452 } 2453 2454 /** 2455 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2456 * @pdev: PCI device to check 2457 * 2458 * Walk upwards from @pdev and check for each encountered bridge if it's part 2459 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2460 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2461 */ 2462 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2463 { 2464 struct pci_dev *parent = pdev; 2465 2466 if (pdev->is_thunderbolt) 2467 return true; 2468 2469 while ((parent = pci_upstream_bridge(parent))) 2470 if (parent->is_thunderbolt) 2471 return true; 2472 2473 return false; 2474 } 2475 2476 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2477 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2478 #endif 2479 2480 #include <linux/dma-mapping.h> 2481 2482 #define pci_printk(level, pdev, fmt, arg...) \ 2483 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2484 2485 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2486 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2487 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2488 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2489 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2490 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2491 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2492 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2493 2494 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2495 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2496 2497 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2498 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2499 2500 #define pci_WARN(pdev, condition, fmt, arg...) \ 2501 WARN(condition, "%s %s: " fmt, \ 2502 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2503 2504 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2505 WARN_ONCE(condition, "%s %s: " fmt, \ 2506 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2507 2508 #endif /* LINUX_PCI_H */ 2509