1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * For more information, please consult the following manuals (look at 10 * http://www.pcisig.com/ for how to get them): 11 * 12 * PCI BIOS Specification 13 * PCI Local Bus Specification 14 * PCI to PCI Bridge Specification 15 * PCI System Design Guide 16 */ 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 21 #include <linux/mod_devicetable.h> 22 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/list.h> 27 #include <linux/compiler.h> 28 #include <linux/errno.h> 29 #include <linux/kobject.h> 30 #include <linux/atomic.h> 31 #include <linux/device.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/resource_ext.h> 35 #include <uapi/linux/pci.h> 36 37 #include <linux/pci_ids.h> 38 39 /* 40 * The PCI interface treats multi-function devices as independent 41 * devices. The slot/function address of each device is encoded 42 * in a single byte as follows: 43 * 44 * 7:3 = slot 45 * 2:0 = function 46 * 47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 48 * In the interest of not exposing interfaces to user-space unnecessarily, 49 * the following kernel-only defines are being added here. 50 */ 51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 54 55 /* pci_slot represents a physical slot */ 56 struct pci_slot { 57 struct pci_bus *bus; /* Bus this slot is on */ 58 struct list_head list; /* Node in list of slots */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 61 struct kobject kobj; 62 }; 63 64 static inline const char *pci_slot_name(const struct pci_slot *slot) 65 { 66 return kobject_name(&slot->kobj); 67 } 68 69 /* File state for mmap()s on /proc/bus/pci/X/Y */ 70 enum pci_mmap_state { 71 pci_mmap_io, 72 pci_mmap_mem 73 }; 74 75 /* For PCI devices, the region numbers are assigned this way: */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* Device-specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* Resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* Total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* Preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 /** 105 * enum pci_interrupt_pin - PCI INTx interrupt values 106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 107 * @PCI_INTERRUPT_INTA: PCI INTA pin 108 * @PCI_INTERRUPT_INTB: PCI INTB pin 109 * @PCI_INTERRUPT_INTC: PCI INTC pin 110 * @PCI_INTERRUPT_INTD: PCI INTD pin 111 * 112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 113 * PCI_INTERRUPT_PIN register. 114 */ 115 enum pci_interrupt_pin { 116 PCI_INTERRUPT_UNKNOWN, 117 PCI_INTERRUPT_INTA, 118 PCI_INTERRUPT_INTB, 119 PCI_INTERRUPT_INTC, 120 PCI_INTERRUPT_INTD, 121 }; 122 123 /* The number of legacy PCI INTx interrupts */ 124 #define PCI_NUM_INTX 4 125 126 /* 127 * pci_power_t values must match the bits in the Capabilities PME_Support 128 * and Control/Status PowerState fields in the Power Management capability. 129 */ 130 typedef int __bitwise pci_power_t; 131 132 #define PCI_D0 ((pci_power_t __force) 0) 133 #define PCI_D1 ((pci_power_t __force) 1) 134 #define PCI_D2 ((pci_power_t __force) 2) 135 #define PCI_D3hot ((pci_power_t __force) 3) 136 #define PCI_D3cold ((pci_power_t __force) 4) 137 #define PCI_UNKNOWN ((pci_power_t __force) 5) 138 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 139 140 /* Remember to update this when the list above changes! */ 141 extern const char *pci_power_names[]; 142 143 static inline const char *pci_power_name(pci_power_t state) 144 { 145 return pci_power_names[1 + (__force int) state]; 146 } 147 148 #define PCI_PM_D2_DELAY 200 149 #define PCI_PM_D3_WAIT 10 150 #define PCI_PM_D3COLD_WAIT 100 151 #define PCI_PM_BUS_WAIT 50 152 153 /** 154 * The pci_channel state describes connectivity between the CPU and 155 * the PCI device. If some PCI bus between here and the PCI device 156 * has crashed or locked up, this info is reflected here. 157 */ 158 typedef unsigned int __bitwise pci_channel_state_t; 159 160 enum pci_channel_state { 161 /* I/O channel is in normal state */ 162 pci_channel_io_normal = (__force pci_channel_state_t) 1, 163 164 /* I/O to channel is blocked */ 165 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 166 167 /* PCI card is dead */ 168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 169 }; 170 171 typedef unsigned int __bitwise pcie_reset_state_t; 172 173 enum pcie_reset_state { 174 /* Reset is NOT asserted (Use to deassert reset) */ 175 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 176 177 /* Use #PERST to reset PCIe device */ 178 pcie_warm_reset = (__force pcie_reset_state_t) 2, 179 180 /* Use PCIe Hot Reset to reset device */ 181 pcie_hot_reset = (__force pcie_reset_state_t) 3 182 }; 183 184 typedef unsigned short __bitwise pci_dev_flags_t; 185 enum pci_dev_flags { 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 188 /* Device configuration is irrevocably lost if disabled into D3 */ 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 190 /* Provide indication device is assigned by a Virtual Machine Manager */ 191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 192 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 196 /* Do not use bus resets for device */ 197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 198 /* Do not use PM reset even if device advertises NoSoftRst- */ 199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 200 /* Get VPD from function 0 VPD */ 201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 202 /* A non-root bridge where translation occurs, stop alias search here */ 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 204 /* Do not use FLR even if device advertises PCI_AF_CAP */ 205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 206 /* Don't use Relaxed Ordering for TLPs directed at this device */ 207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 208 }; 209 210 enum pci_irq_reroute_variant { 211 INTEL_IRQ_REROUTE_VARIANT = 1, 212 MAX_IRQ_REROUTE_VARIANTS = 3 213 }; 214 215 typedef unsigned short __bitwise pci_bus_flags_t; 216 enum pci_bus_flags { 217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 221 }; 222 223 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 224 enum pcie_link_width { 225 PCIE_LNK_WIDTH_RESRV = 0x00, 226 PCIE_LNK_X1 = 0x01, 227 PCIE_LNK_X2 = 0x02, 228 PCIE_LNK_X4 = 0x04, 229 PCIE_LNK_X8 = 0x08, 230 PCIE_LNK_X12 = 0x0c, 231 PCIE_LNK_X16 = 0x10, 232 PCIE_LNK_X32 = 0x20, 233 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 234 }; 235 236 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 237 enum pci_bus_speed { 238 PCI_SPEED_33MHz = 0x00, 239 PCI_SPEED_66MHz = 0x01, 240 PCI_SPEED_66MHz_PCIX = 0x02, 241 PCI_SPEED_100MHz_PCIX = 0x03, 242 PCI_SPEED_133MHz_PCIX = 0x04, 243 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 244 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 245 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 246 PCI_SPEED_66MHz_PCIX_266 = 0x09, 247 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 248 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 249 AGP_UNKNOWN = 0x0c, 250 AGP_1X = 0x0d, 251 AGP_2X = 0x0e, 252 AGP_4X = 0x0f, 253 AGP_8X = 0x10, 254 PCI_SPEED_66MHz_PCIX_533 = 0x11, 255 PCI_SPEED_100MHz_PCIX_533 = 0x12, 256 PCI_SPEED_133MHz_PCIX_533 = 0x13, 257 PCIE_SPEED_2_5GT = 0x14, 258 PCIE_SPEED_5_0GT = 0x15, 259 PCIE_SPEED_8_0GT = 0x16, 260 PCIE_SPEED_16_0GT = 0x17, 261 PCI_SPEED_UNKNOWN = 0xff, 262 }; 263 264 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 265 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 266 267 struct pci_cap_saved_data { 268 u16 cap_nr; 269 bool cap_extended; 270 unsigned int size; 271 u32 data[0]; 272 }; 273 274 struct pci_cap_saved_state { 275 struct hlist_node next; 276 struct pci_cap_saved_data cap; 277 }; 278 279 struct irq_affinity; 280 struct pcie_link_state; 281 struct pci_vpd; 282 struct pci_sriov; 283 struct pci_ats; 284 struct pci_p2pdma; 285 286 /* The pci_dev structure describes PCI devices */ 287 struct pci_dev { 288 struct list_head bus_list; /* Node in per-bus list */ 289 struct pci_bus *bus; /* Bus this device is on */ 290 struct pci_bus *subordinate; /* Bus this device bridges to */ 291 292 void *sysdata; /* Hook for sys-specific extension */ 293 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 294 struct pci_slot *slot; /* Physical slot this device is in */ 295 296 unsigned int devfn; /* Encoded device & function index */ 297 unsigned short vendor; 298 unsigned short device; 299 unsigned short subsystem_vendor; 300 unsigned short subsystem_device; 301 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 302 u8 revision; /* PCI revision, low byte of class word */ 303 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 304 #ifdef CONFIG_PCIEAER 305 u16 aer_cap; /* AER capability offset */ 306 struct aer_stats *aer_stats; /* AER stats for this device */ 307 #endif 308 u8 pcie_cap; /* PCIe capability offset */ 309 u8 msi_cap; /* MSI capability offset */ 310 u8 msix_cap; /* MSI-X capability offset */ 311 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 312 u8 rom_base_reg; /* Config register controlling ROM */ 313 u8 pin; /* Interrupt pin this device uses */ 314 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 315 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 316 317 struct pci_driver *driver; /* Driver bound to this device */ 318 u64 dma_mask; /* Mask of the bits of bus address this 319 device implements. Normally this is 320 0xffffffff. You only need to change 321 this if your device has broken DMA 322 or supports 64-bit transfers. */ 323 324 struct device_dma_parameters dma_parms; 325 326 pci_power_t current_state; /* Current operating state. In ACPI, 327 this is D0-D3, D0 being fully 328 functional, and D3 being off. */ 329 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 330 u8 pm_cap; /* PM capability offset */ 331 unsigned int pme_support:5; /* Bitmask of states from which PME# 332 can be generated */ 333 unsigned int pme_poll:1; /* Poll device's PME status bit */ 334 unsigned int d1_support:1; /* Low power state D1 is supported */ 335 unsigned int d2_support:1; /* Low power state D2 is supported */ 336 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 337 unsigned int no_d3cold:1; /* D3cold is forbidden */ 338 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 339 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 340 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 341 decoding during BAR sizing */ 342 unsigned int wakeup_prepared:1; 343 unsigned int runtime_d3cold:1; /* Whether go through runtime 344 D3cold, not set for devices 345 powered on/off by the 346 corresponding bridge */ 347 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 348 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 349 controlled exclusively by 350 user sysfs */ 351 unsigned int d3_delay; /* D3->D0 transition time in ms */ 352 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 353 354 #ifdef CONFIG_PCIEASPM 355 struct pcie_link_state *link_state; /* ASPM link state */ 356 unsigned int ltr_path:1; /* Latency Tolerance Reporting 357 supported from root to here */ 358 #endif 359 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 360 361 pci_channel_state_t error_state; /* Current connectivity state */ 362 struct device dev; /* Generic device interface */ 363 364 int cfg_size; /* Size of config space */ 365 366 /* 367 * Instead of touching interrupt line and base address registers 368 * directly, use the values stored here. They might be different! 369 */ 370 unsigned int irq; 371 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 372 373 bool match_driver; /* Skip attaching driver */ 374 375 unsigned int transparent:1; /* Subtractive decode bridge */ 376 unsigned int multifunction:1; /* Multi-function device */ 377 378 unsigned int is_busmaster:1; /* Is busmaster */ 379 unsigned int no_msi:1; /* May not use MSI */ 380 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 381 unsigned int block_cfg_access:1; /* Config space access blocked */ 382 unsigned int broken_parity_status:1; /* Generates false positive parity */ 383 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 384 unsigned int msi_enabled:1; 385 unsigned int msix_enabled:1; 386 unsigned int ari_enabled:1; /* ARI forwarding */ 387 unsigned int ats_enabled:1; /* Address Translation Svc */ 388 unsigned int pasid_enabled:1; /* Process Address Space ID */ 389 unsigned int pri_enabled:1; /* Page Request Interface */ 390 unsigned int is_managed:1; 391 unsigned int needs_freset:1; /* Requires fundamental reset */ 392 unsigned int state_saved:1; 393 unsigned int is_physfn:1; 394 unsigned int is_virtfn:1; 395 unsigned int reset_fn:1; 396 unsigned int is_hotplug_bridge:1; 397 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 398 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 399 /* 400 * Devices marked being untrusted are the ones that can potentially 401 * execute DMA attacks and similar. They are typically connected 402 * through external ports such as Thunderbolt but not limited to 403 * that. When an IOMMU is enabled they should be getting full 404 * mappings to make sure they cannot access arbitrary memory. 405 */ 406 unsigned int untrusted:1; 407 unsigned int __aer_firmware_first_valid:1; 408 unsigned int __aer_firmware_first:1; 409 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 410 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 411 unsigned int irq_managed:1; 412 unsigned int has_secondary_link:1; 413 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 414 unsigned int is_probed:1; /* Device probing in progress */ 415 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 416 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 417 pci_dev_flags_t dev_flags; 418 atomic_t enable_cnt; /* pci_enable_device has been called */ 419 420 u32 saved_config_space[16]; /* Config space saved at suspend time */ 421 struct hlist_head saved_cap_space; 422 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 423 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 424 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 425 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 426 427 #ifdef CONFIG_HOTPLUG_PCI_PCIE 428 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 429 #endif 430 #ifdef CONFIG_PCIE_PTM 431 unsigned int ptm_root:1; 432 unsigned int ptm_enabled:1; 433 u8 ptm_granularity; 434 #endif 435 #ifdef CONFIG_PCI_MSI 436 const struct attribute_group **msi_irq_groups; 437 #endif 438 struct pci_vpd *vpd; 439 #ifdef CONFIG_PCI_ATS 440 union { 441 struct pci_sriov *sriov; /* PF: SR-IOV info */ 442 struct pci_dev *physfn; /* VF: related PF */ 443 }; 444 u16 ats_cap; /* ATS Capability offset */ 445 u8 ats_stu; /* ATS Smallest Translation Unit */ 446 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ 447 #endif 448 #ifdef CONFIG_PCI_PRI 449 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 450 #endif 451 #ifdef CONFIG_PCI_PASID 452 u16 pasid_features; 453 #endif 454 #ifdef CONFIG_PCI_P2PDMA 455 struct pci_p2pdma *p2pdma; 456 #endif 457 phys_addr_t rom; /* Physical address if not from BAR */ 458 size_t romlen; /* Length if not from BAR */ 459 char *driver_override; /* Driver name to force a match */ 460 461 unsigned long priv_flags; /* Private flags for the PCI driver */ 462 }; 463 464 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 465 { 466 #ifdef CONFIG_PCI_IOV 467 if (dev->is_virtfn) 468 dev = dev->physfn; 469 #endif 470 return dev; 471 } 472 473 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 474 475 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 476 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 477 478 static inline int pci_channel_offline(struct pci_dev *pdev) 479 { 480 return (pdev->error_state != pci_channel_io_normal); 481 } 482 483 struct pci_host_bridge { 484 struct device dev; 485 struct pci_bus *bus; /* Root bus */ 486 struct pci_ops *ops; 487 void *sysdata; 488 int busnr; 489 struct list_head windows; /* resource_entry */ 490 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 491 int (*map_irq)(const struct pci_dev *, u8, u8); 492 void (*release_fn)(struct pci_host_bridge *); 493 void *release_data; 494 struct msi_controller *msi; 495 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 496 unsigned int no_ext_tags:1; /* No Extended Tags */ 497 unsigned int native_aer:1; /* OS may use PCIe AER */ 498 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 499 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 500 unsigned int native_pme:1; /* OS may use PCIe PME */ 501 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 502 /* Resource alignment requirements */ 503 resource_size_t (*align_resource)(struct pci_dev *dev, 504 const struct resource *res, 505 resource_size_t start, 506 resource_size_t size, 507 resource_size_t align); 508 unsigned long private[0] ____cacheline_aligned; 509 }; 510 511 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 512 513 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 514 { 515 return (void *)bridge->private; 516 } 517 518 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 519 { 520 return container_of(priv, struct pci_host_bridge, private); 521 } 522 523 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 524 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 525 size_t priv); 526 void pci_free_host_bridge(struct pci_host_bridge *bridge); 527 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 528 529 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 530 void (*release_fn)(struct pci_host_bridge *), 531 void *release_data); 532 533 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 534 535 /* 536 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 537 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 538 * buses below host bridges or subtractive decode bridges) go in the list. 539 * Use pci_bus_for_each_resource() to iterate through all the resources. 540 */ 541 542 /* 543 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 544 * and there's no way to program the bridge with the details of the window. 545 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 546 * decode bit set, because they are explicit and can be programmed with _SRS. 547 */ 548 #define PCI_SUBTRACTIVE_DECODE 0x1 549 550 struct pci_bus_resource { 551 struct list_head list; 552 struct resource *res; 553 unsigned int flags; 554 }; 555 556 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 557 558 struct pci_bus { 559 struct list_head node; /* Node in list of buses */ 560 struct pci_bus *parent; /* Parent bus this bridge is on */ 561 struct list_head children; /* List of child buses */ 562 struct list_head devices; /* List of devices on this bus */ 563 struct pci_dev *self; /* Bridge device as seen by parent */ 564 struct list_head slots; /* List of slots on this bus; 565 protected by pci_slot_mutex */ 566 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 567 struct list_head resources; /* Address space routed to this bus */ 568 struct resource busn_res; /* Bus numbers routed to this bus */ 569 570 struct pci_ops *ops; /* Configuration access functions */ 571 struct msi_controller *msi; /* MSI controller */ 572 void *sysdata; /* Hook for sys-specific extension */ 573 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 574 575 unsigned char number; /* Bus number */ 576 unsigned char primary; /* Number of primary bridge */ 577 unsigned char max_bus_speed; /* enum pci_bus_speed */ 578 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 579 #ifdef CONFIG_PCI_DOMAINS_GENERIC 580 int domain_nr; 581 #endif 582 583 char name[48]; 584 585 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 586 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 587 struct device *bridge; 588 struct device dev; 589 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 590 struct bin_attribute *legacy_mem; /* Legacy mem */ 591 unsigned int is_added:1; 592 }; 593 594 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 595 596 /* 597 * Returns true if the PCI bus is root (behind host-PCI bridge), 598 * false otherwise 599 * 600 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 601 * This is incorrect because "virtual" buses added for SR-IOV (via 602 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 603 */ 604 static inline bool pci_is_root_bus(struct pci_bus *pbus) 605 { 606 return !(pbus->parent); 607 } 608 609 /** 610 * pci_is_bridge - check if the PCI device is a bridge 611 * @dev: PCI device 612 * 613 * Return true if the PCI device is bridge whether it has subordinate 614 * or not. 615 */ 616 static inline bool pci_is_bridge(struct pci_dev *dev) 617 { 618 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 619 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 620 } 621 622 #define for_each_pci_bridge(dev, bus) \ 623 list_for_each_entry(dev, &bus->devices, bus_list) \ 624 if (!pci_is_bridge(dev)) {} else 625 626 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 627 { 628 dev = pci_physfn(dev); 629 if (pci_is_root_bus(dev->bus)) 630 return NULL; 631 632 return dev->bus->self; 633 } 634 635 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 636 void pci_put_host_bridge_device(struct device *dev); 637 638 #ifdef CONFIG_PCI_MSI 639 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 640 { 641 return pci_dev->msi_enabled || pci_dev->msix_enabled; 642 } 643 #else 644 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 645 #endif 646 647 /* Error values that may be returned by PCI functions */ 648 #define PCIBIOS_SUCCESSFUL 0x00 649 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 650 #define PCIBIOS_BAD_VENDOR_ID 0x83 651 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 652 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 653 #define PCIBIOS_SET_FAILED 0x88 654 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 655 656 /* Translate above to generic errno for passing back through non-PCI code */ 657 static inline int pcibios_err_to_errno(int err) 658 { 659 if (err <= PCIBIOS_SUCCESSFUL) 660 return err; /* Assume already errno */ 661 662 switch (err) { 663 case PCIBIOS_FUNC_NOT_SUPPORTED: 664 return -ENOENT; 665 case PCIBIOS_BAD_VENDOR_ID: 666 return -ENOTTY; 667 case PCIBIOS_DEVICE_NOT_FOUND: 668 return -ENODEV; 669 case PCIBIOS_BAD_REGISTER_NUMBER: 670 return -EFAULT; 671 case PCIBIOS_SET_FAILED: 672 return -EIO; 673 case PCIBIOS_BUFFER_TOO_SMALL: 674 return -ENOSPC; 675 } 676 677 return -ERANGE; 678 } 679 680 /* Low-level architecture-dependent routines */ 681 682 struct pci_ops { 683 int (*add_bus)(struct pci_bus *bus); 684 void (*remove_bus)(struct pci_bus *bus); 685 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 686 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 687 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 688 }; 689 690 /* 691 * ACPI needs to be able to access PCI config space before we've done a 692 * PCI bus scan and created pci_bus structures. 693 */ 694 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 695 int reg, int len, u32 *val); 696 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 697 int reg, int len, u32 val); 698 699 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 700 typedef u64 pci_bus_addr_t; 701 #else 702 typedef u32 pci_bus_addr_t; 703 #endif 704 705 struct pci_bus_region { 706 pci_bus_addr_t start; 707 pci_bus_addr_t end; 708 }; 709 710 struct pci_dynids { 711 spinlock_t lock; /* Protects list, index */ 712 struct list_head list; /* For IDs added at runtime */ 713 }; 714 715 716 /* 717 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 718 * a set of callbacks in struct pci_error_handlers, that device driver 719 * will be notified of PCI bus errors, and will be driven to recovery 720 * when an error occurs. 721 */ 722 723 typedef unsigned int __bitwise pci_ers_result_t; 724 725 enum pci_ers_result { 726 /* No result/none/not supported in device driver */ 727 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 728 729 /* Device driver can recover without slot reset */ 730 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 731 732 /* Device driver wants slot to be reset */ 733 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 734 735 /* Device has completely failed, is unrecoverable */ 736 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 737 738 /* Device driver is fully recovered and operational */ 739 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 740 741 /* No AER capabilities registered for the driver */ 742 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 743 }; 744 745 /* PCI bus error event callbacks */ 746 struct pci_error_handlers { 747 /* PCI bus error detected on this device */ 748 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 749 enum pci_channel_state error); 750 751 /* MMIO has been re-enabled, but not DMA */ 752 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 753 754 /* PCI slot has been reset */ 755 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 756 757 /* PCI function reset prepare or completed */ 758 void (*reset_prepare)(struct pci_dev *dev); 759 void (*reset_done)(struct pci_dev *dev); 760 761 /* Device driver may resume normal operations */ 762 void (*resume)(struct pci_dev *dev); 763 }; 764 765 766 struct module; 767 struct pci_driver { 768 struct list_head node; 769 const char *name; 770 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 771 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 772 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 773 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 774 int (*suspend_late)(struct pci_dev *dev, pm_message_t state); 775 int (*resume_early)(struct pci_dev *dev); 776 int (*resume)(struct pci_dev *dev); /* Device woken up */ 777 void (*shutdown)(struct pci_dev *dev); 778 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 779 const struct pci_error_handlers *err_handler; 780 const struct attribute_group **groups; 781 struct device_driver driver; 782 struct pci_dynids dynids; 783 }; 784 785 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 786 787 /** 788 * PCI_DEVICE - macro used to describe a specific PCI device 789 * @vend: the 16 bit PCI Vendor ID 790 * @dev: the 16 bit PCI Device ID 791 * 792 * This macro is used to create a struct pci_device_id that matches a 793 * specific device. The subvendor and subdevice fields will be set to 794 * PCI_ANY_ID. 795 */ 796 #define PCI_DEVICE(vend,dev) \ 797 .vendor = (vend), .device = (dev), \ 798 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 799 800 /** 801 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 802 * @vend: the 16 bit PCI Vendor ID 803 * @dev: the 16 bit PCI Device ID 804 * @subvend: the 16 bit PCI Subvendor ID 805 * @subdev: the 16 bit PCI Subdevice ID 806 * 807 * This macro is used to create a struct pci_device_id that matches a 808 * specific device with subsystem information. 809 */ 810 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 811 .vendor = (vend), .device = (dev), \ 812 .subvendor = (subvend), .subdevice = (subdev) 813 814 /** 815 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 816 * @dev_class: the class, subclass, prog-if triple for this device 817 * @dev_class_mask: the class mask for this device 818 * 819 * This macro is used to create a struct pci_device_id that matches a 820 * specific PCI class. The vendor, device, subvendor, and subdevice 821 * fields will be set to PCI_ANY_ID. 822 */ 823 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 824 .class = (dev_class), .class_mask = (dev_class_mask), \ 825 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 826 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 827 828 /** 829 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 830 * @vend: the vendor name 831 * @dev: the 16 bit PCI Device ID 832 * 833 * This macro is used to create a struct pci_device_id that matches a 834 * specific PCI device. The subvendor, and subdevice fields will be set 835 * to PCI_ANY_ID. The macro allows the next field to follow as the device 836 * private data. 837 */ 838 #define PCI_VDEVICE(vend, dev) \ 839 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 840 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 841 842 /** 843 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 844 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 845 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 846 * @data: the driver data to be filled 847 * 848 * This macro is used to create a struct pci_device_id that matches a 849 * specific PCI device. The subvendor, and subdevice fields will be set 850 * to PCI_ANY_ID. 851 */ 852 #define PCI_DEVICE_DATA(vend, dev, data) \ 853 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 854 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 855 .driver_data = (kernel_ulong_t)(data) 856 857 enum { 858 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 859 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 860 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 861 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 862 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 863 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 864 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 865 }; 866 867 /* These external functions are only available when PCI support is enabled */ 868 #ifdef CONFIG_PCI 869 870 extern unsigned int pci_flags; 871 872 static inline void pci_set_flags(int flags) { pci_flags = flags; } 873 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 874 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 875 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 876 877 void pcie_bus_configure_settings(struct pci_bus *bus); 878 879 enum pcie_bus_config_types { 880 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 881 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 882 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 883 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 884 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 885 }; 886 887 extern enum pcie_bus_config_types pcie_bus_config; 888 889 extern struct bus_type pci_bus_type; 890 891 /* Do NOT directly access these two variables, unless you are arch-specific PCI 892 * code, or PCI core code. */ 893 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 894 /* Some device drivers need know if PCI is initiated */ 895 int no_pci_devices(void); 896 897 void pcibios_resource_survey_bus(struct pci_bus *bus); 898 void pcibios_bus_add_device(struct pci_dev *pdev); 899 void pcibios_add_bus(struct pci_bus *bus); 900 void pcibios_remove_bus(struct pci_bus *bus); 901 void pcibios_fixup_bus(struct pci_bus *); 902 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 903 /* Architecture-specific versions may override this (weak) */ 904 char *pcibios_setup(char *str); 905 906 /* Used only when drivers/pci/setup.c is used */ 907 resource_size_t pcibios_align_resource(void *, const struct resource *, 908 resource_size_t, 909 resource_size_t); 910 911 /* Weak but can be overriden by arch */ 912 void pci_fixup_cardbus(struct pci_bus *); 913 914 /* Generic PCI functions used internally */ 915 916 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 917 struct resource *res); 918 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 919 struct pci_bus_region *region); 920 void pcibios_scan_specific_bus(int busn); 921 struct pci_bus *pci_find_bus(int domain, int busnr); 922 void pci_bus_add_devices(const struct pci_bus *bus); 923 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 924 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 925 struct pci_ops *ops, void *sysdata, 926 struct list_head *resources); 927 int pci_host_probe(struct pci_host_bridge *bridge); 928 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 929 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 930 void pci_bus_release_busn_res(struct pci_bus *b); 931 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 932 struct pci_ops *ops, void *sysdata, 933 struct list_head *resources); 934 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 935 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 936 int busnr); 937 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 938 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 939 const char *name, 940 struct hotplug_slot *hotplug); 941 void pci_destroy_slot(struct pci_slot *slot); 942 #ifdef CONFIG_SYSFS 943 void pci_dev_assign_slot(struct pci_dev *dev); 944 #else 945 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 946 #endif 947 int pci_scan_slot(struct pci_bus *bus, int devfn); 948 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 949 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 950 unsigned int pci_scan_child_bus(struct pci_bus *bus); 951 void pci_bus_add_device(struct pci_dev *dev); 952 void pci_read_bridge_bases(struct pci_bus *child); 953 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 954 struct resource *res); 955 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 956 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 957 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 958 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 959 struct pci_dev *pci_dev_get(struct pci_dev *dev); 960 void pci_dev_put(struct pci_dev *dev); 961 void pci_remove_bus(struct pci_bus *b); 962 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 963 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 964 void pci_stop_root_bus(struct pci_bus *bus); 965 void pci_remove_root_bus(struct pci_bus *bus); 966 void pci_setup_cardbus(struct pci_bus *bus); 967 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 968 void pci_sort_breadthfirst(void); 969 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 970 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 971 972 /* Generic PCI functions exported to card drivers */ 973 974 enum pci_lost_interrupt_reason { 975 PCI_LOST_IRQ_NO_INFORMATION = 0, 976 PCI_LOST_IRQ_DISABLE_MSI, 977 PCI_LOST_IRQ_DISABLE_MSIX, 978 PCI_LOST_IRQ_DISABLE_ACPI, 979 }; 980 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 981 int pci_find_capability(struct pci_dev *dev, int cap); 982 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 983 int pci_find_ext_capability(struct pci_dev *dev, int cap); 984 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 985 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 986 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 987 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 988 989 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 990 struct pci_dev *from); 991 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 992 unsigned int ss_vendor, unsigned int ss_device, 993 struct pci_dev *from); 994 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 995 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 996 unsigned int devfn); 997 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 998 int pci_dev_present(const struct pci_device_id *ids); 999 1000 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1001 int where, u8 *val); 1002 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1003 int where, u16 *val); 1004 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1005 int where, u32 *val); 1006 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1007 int where, u8 val); 1008 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1009 int where, u16 val); 1010 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1011 int where, u32 val); 1012 1013 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1014 int where, int size, u32 *val); 1015 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1016 int where, int size, u32 val); 1017 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1018 int where, int size, u32 *val); 1019 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1020 int where, int size, u32 val); 1021 1022 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1023 1024 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1025 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1026 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1027 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1028 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1029 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1030 1031 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1032 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1033 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1034 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1035 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1036 u16 clear, u16 set); 1037 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1038 u32 clear, u32 set); 1039 1040 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1041 u16 set) 1042 { 1043 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1044 } 1045 1046 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1047 u32 set) 1048 { 1049 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1050 } 1051 1052 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1053 u16 clear) 1054 { 1055 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1056 } 1057 1058 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1059 u32 clear) 1060 { 1061 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1062 } 1063 1064 /* User-space driven config access */ 1065 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1066 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1067 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1068 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1069 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1070 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1071 1072 int __must_check pci_enable_device(struct pci_dev *dev); 1073 int __must_check pci_enable_device_io(struct pci_dev *dev); 1074 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1075 int __must_check pci_reenable_device(struct pci_dev *); 1076 int __must_check pcim_enable_device(struct pci_dev *pdev); 1077 void pcim_pin_device(struct pci_dev *pdev); 1078 1079 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1080 { 1081 /* 1082 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1083 * writable and no quirk has marked the feature broken. 1084 */ 1085 return !pdev->broken_intx_masking; 1086 } 1087 1088 static inline int pci_is_enabled(struct pci_dev *pdev) 1089 { 1090 return (atomic_read(&pdev->enable_cnt) > 0); 1091 } 1092 1093 static inline int pci_is_managed(struct pci_dev *pdev) 1094 { 1095 return pdev->is_managed; 1096 } 1097 1098 void pci_disable_device(struct pci_dev *dev); 1099 1100 extern unsigned int pcibios_max_latency; 1101 void pci_set_master(struct pci_dev *dev); 1102 void pci_clear_master(struct pci_dev *dev); 1103 1104 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1105 int pci_set_cacheline_size(struct pci_dev *dev); 1106 #define HAVE_PCI_SET_MWI 1107 int __must_check pci_set_mwi(struct pci_dev *dev); 1108 int __must_check pcim_set_mwi(struct pci_dev *dev); 1109 int pci_try_set_mwi(struct pci_dev *dev); 1110 void pci_clear_mwi(struct pci_dev *dev); 1111 void pci_intx(struct pci_dev *dev, int enable); 1112 bool pci_check_and_mask_intx(struct pci_dev *dev); 1113 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1114 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1115 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1116 int pcix_get_max_mmrbc(struct pci_dev *dev); 1117 int pcix_get_mmrbc(struct pci_dev *dev); 1118 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1119 int pcie_get_readrq(struct pci_dev *dev); 1120 int pcie_set_readrq(struct pci_dev *dev, int rq); 1121 int pcie_get_mps(struct pci_dev *dev); 1122 int pcie_set_mps(struct pci_dev *dev, int mps); 1123 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1124 enum pci_bus_speed *speed, 1125 enum pcie_link_width *width); 1126 void pcie_print_link_status(struct pci_dev *dev); 1127 bool pcie_has_flr(struct pci_dev *dev); 1128 int pcie_flr(struct pci_dev *dev); 1129 int __pci_reset_function_locked(struct pci_dev *dev); 1130 int pci_reset_function(struct pci_dev *dev); 1131 int pci_reset_function_locked(struct pci_dev *dev); 1132 int pci_try_reset_function(struct pci_dev *dev); 1133 int pci_probe_reset_slot(struct pci_slot *slot); 1134 int pci_probe_reset_bus(struct pci_bus *bus); 1135 int pci_reset_bus(struct pci_dev *dev); 1136 void pci_reset_secondary_bus(struct pci_dev *dev); 1137 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1138 void pci_update_resource(struct pci_dev *dev, int resno); 1139 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1140 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1141 void pci_release_resource(struct pci_dev *dev, int resno); 1142 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1143 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1144 bool pci_device_is_present(struct pci_dev *pdev); 1145 void pci_ignore_hotplug(struct pci_dev *dev); 1146 1147 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1148 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1149 const char *fmt, ...); 1150 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1151 1152 /* ROM control related routines */ 1153 int pci_enable_rom(struct pci_dev *pdev); 1154 void pci_disable_rom(struct pci_dev *pdev); 1155 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1156 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1157 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1158 1159 /* Power management related routines */ 1160 int pci_save_state(struct pci_dev *dev); 1161 void pci_restore_state(struct pci_dev *dev); 1162 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1163 int pci_load_saved_state(struct pci_dev *dev, 1164 struct pci_saved_state *state); 1165 int pci_load_and_free_saved_state(struct pci_dev *dev, 1166 struct pci_saved_state **state); 1167 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1168 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1169 u16 cap); 1170 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1171 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1172 u16 cap, unsigned int size); 1173 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1174 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1175 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1176 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1177 void pci_pme_active(struct pci_dev *dev, bool enable); 1178 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1179 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1180 int pci_prepare_to_sleep(struct pci_dev *dev); 1181 int pci_back_from_sleep(struct pci_dev *dev); 1182 bool pci_dev_run_wake(struct pci_dev *dev); 1183 bool pci_check_pme_status(struct pci_dev *dev); 1184 void pci_pme_wakeup_bus(struct pci_bus *bus); 1185 void pci_d3cold_enable(struct pci_dev *dev); 1186 void pci_d3cold_disable(struct pci_dev *dev); 1187 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1188 void pci_wakeup_bus(struct pci_bus *bus); 1189 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1190 1191 /* PCI Virtual Channel */ 1192 int pci_save_vc_state(struct pci_dev *dev); 1193 void pci_restore_vc_state(struct pci_dev *dev); 1194 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1195 1196 /* For use by arch with custom probe code */ 1197 void set_pcie_port_type(struct pci_dev *pdev); 1198 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1199 1200 /* Functions for PCI Hotplug drivers to use */ 1201 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1202 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1203 unsigned int pci_rescan_bus(struct pci_bus *bus); 1204 void pci_lock_rescan_remove(void); 1205 void pci_unlock_rescan_remove(void); 1206 1207 /* Vital Product Data routines */ 1208 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1209 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1210 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1211 1212 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1213 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1214 void pci_bus_assign_resources(const struct pci_bus *bus); 1215 void pci_bus_claim_resources(struct pci_bus *bus); 1216 void pci_bus_size_bridges(struct pci_bus *bus); 1217 int pci_claim_resource(struct pci_dev *, int); 1218 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1219 void pci_assign_unassigned_resources(void); 1220 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1221 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1222 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1223 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1224 void pdev_enable_device(struct pci_dev *); 1225 int pci_enable_resources(struct pci_dev *, int mask); 1226 void pci_assign_irq(struct pci_dev *dev); 1227 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1228 #define HAVE_PCI_REQ_REGIONS 2 1229 int __must_check pci_request_regions(struct pci_dev *, const char *); 1230 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1231 void pci_release_regions(struct pci_dev *); 1232 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1233 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1234 void pci_release_region(struct pci_dev *, int); 1235 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1236 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1237 void pci_release_selected_regions(struct pci_dev *, int); 1238 1239 /* drivers/pci/bus.c */ 1240 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1241 void pci_bus_put(struct pci_bus *bus); 1242 void pci_add_resource(struct list_head *resources, struct resource *res); 1243 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1244 resource_size_t offset); 1245 void pci_free_resource_list(struct list_head *resources); 1246 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1247 unsigned int flags); 1248 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1249 void pci_bus_remove_resources(struct pci_bus *bus); 1250 int devm_request_pci_bus_resources(struct device *dev, 1251 struct list_head *resources); 1252 1253 /* Temporary until new and working PCI SBR API in place */ 1254 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1255 1256 #define pci_bus_for_each_resource(bus, res, i) \ 1257 for (i = 0; \ 1258 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1259 i++) 1260 1261 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1262 struct resource *res, resource_size_t size, 1263 resource_size_t align, resource_size_t min, 1264 unsigned long type_mask, 1265 resource_size_t (*alignf)(void *, 1266 const struct resource *, 1267 resource_size_t, 1268 resource_size_t), 1269 void *alignf_data); 1270 1271 1272 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1273 resource_size_t size); 1274 unsigned long pci_address_to_pio(phys_addr_t addr); 1275 phys_addr_t pci_pio_to_address(unsigned long pio); 1276 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1277 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1278 phys_addr_t phys_addr); 1279 void pci_unmap_iospace(struct resource *res); 1280 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1281 resource_size_t offset, 1282 resource_size_t size); 1283 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1284 struct resource *res); 1285 1286 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1287 { 1288 struct pci_bus_region region; 1289 1290 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1291 return region.start; 1292 } 1293 1294 /* Proper probing supporting hot-pluggable devices */ 1295 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1296 const char *mod_name); 1297 1298 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1299 #define pci_register_driver(driver) \ 1300 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1301 1302 void pci_unregister_driver(struct pci_driver *dev); 1303 1304 /** 1305 * module_pci_driver() - Helper macro for registering a PCI driver 1306 * @__pci_driver: pci_driver struct 1307 * 1308 * Helper macro for PCI drivers which do not do anything special in module 1309 * init/exit. This eliminates a lot of boilerplate. Each module may only 1310 * use this macro once, and calling it replaces module_init() and module_exit() 1311 */ 1312 #define module_pci_driver(__pci_driver) \ 1313 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1314 1315 /** 1316 * builtin_pci_driver() - Helper macro for registering a PCI driver 1317 * @__pci_driver: pci_driver struct 1318 * 1319 * Helper macro for PCI drivers which do not do anything special in their 1320 * init code. This eliminates a lot of boilerplate. Each driver may only 1321 * use this macro once, and calling it replaces device_initcall(...) 1322 */ 1323 #define builtin_pci_driver(__pci_driver) \ 1324 builtin_driver(__pci_driver, pci_register_driver) 1325 1326 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1327 int pci_add_dynid(struct pci_driver *drv, 1328 unsigned int vendor, unsigned int device, 1329 unsigned int subvendor, unsigned int subdevice, 1330 unsigned int class, unsigned int class_mask, 1331 unsigned long driver_data); 1332 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1333 struct pci_dev *dev); 1334 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1335 int pass); 1336 1337 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1338 void *userdata); 1339 int pci_cfg_space_size(struct pci_dev *dev); 1340 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1341 void pci_setup_bridge(struct pci_bus *bus); 1342 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1343 unsigned long type); 1344 1345 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1346 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1347 1348 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1349 unsigned int command_bits, u32 flags); 1350 1351 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1352 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1353 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1354 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1355 #define PCI_IRQ_ALL_TYPES \ 1356 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1357 1358 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1359 1360 #include <linux/dmapool.h> 1361 1362 #define pci_pool dma_pool 1363 #define pci_pool_create(name, pdev, size, align, allocation) \ 1364 dma_pool_create(name, &pdev->dev, size, align, allocation) 1365 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1366 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1367 #define pci_pool_zalloc(pool, flags, handle) \ 1368 dma_pool_zalloc(pool, flags, handle) 1369 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1370 1371 struct msix_entry { 1372 u32 vector; /* Kernel uses to write allocated vector */ 1373 u16 entry; /* Driver uses to specify entry, OS writes */ 1374 }; 1375 1376 #ifdef CONFIG_PCI_MSI 1377 int pci_msi_vec_count(struct pci_dev *dev); 1378 void pci_disable_msi(struct pci_dev *dev); 1379 int pci_msix_vec_count(struct pci_dev *dev); 1380 void pci_disable_msix(struct pci_dev *dev); 1381 void pci_restore_msi_state(struct pci_dev *dev); 1382 int pci_msi_enabled(void); 1383 int pci_enable_msi(struct pci_dev *dev); 1384 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1385 int minvec, int maxvec); 1386 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1387 struct msix_entry *entries, int nvec) 1388 { 1389 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1390 if (rc < 0) 1391 return rc; 1392 return 0; 1393 } 1394 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1395 unsigned int max_vecs, unsigned int flags, 1396 const struct irq_affinity *affd); 1397 1398 void pci_free_irq_vectors(struct pci_dev *dev); 1399 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1400 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1401 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1402 1403 #else 1404 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1405 static inline void pci_disable_msi(struct pci_dev *dev) { } 1406 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1407 static inline void pci_disable_msix(struct pci_dev *dev) { } 1408 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1409 static inline int pci_msi_enabled(void) { return 0; } 1410 static inline int pci_enable_msi(struct pci_dev *dev) 1411 { return -ENOSYS; } 1412 static inline int pci_enable_msix_range(struct pci_dev *dev, 1413 struct msix_entry *entries, int minvec, int maxvec) 1414 { return -ENOSYS; } 1415 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1416 struct msix_entry *entries, int nvec) 1417 { return -ENOSYS; } 1418 1419 static inline int 1420 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1421 unsigned int max_vecs, unsigned int flags, 1422 const struct irq_affinity *aff_desc) 1423 { 1424 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1425 return 1; 1426 return -ENOSPC; 1427 } 1428 1429 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1430 { 1431 } 1432 1433 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1434 { 1435 if (WARN_ON_ONCE(nr > 0)) 1436 return -EINVAL; 1437 return dev->irq; 1438 } 1439 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1440 int vec) 1441 { 1442 return cpu_possible_mask; 1443 } 1444 1445 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1446 { 1447 return first_online_node; 1448 } 1449 #endif 1450 1451 static inline int 1452 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1453 unsigned int max_vecs, unsigned int flags) 1454 { 1455 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1456 NULL); 1457 } 1458 1459 /** 1460 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1461 * @d: the INTx IRQ domain 1462 * @node: the DT node for the device whose interrupt we're translating 1463 * @intspec: the interrupt specifier data from the DT 1464 * @intsize: the number of entries in @intspec 1465 * @out_hwirq: pointer at which to write the hwirq number 1466 * @out_type: pointer at which to write the interrupt type 1467 * 1468 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1469 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1470 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1471 * INTx value to obtain the hwirq number. 1472 * 1473 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1474 */ 1475 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1476 struct device_node *node, 1477 const u32 *intspec, 1478 unsigned int intsize, 1479 unsigned long *out_hwirq, 1480 unsigned int *out_type) 1481 { 1482 const u32 intx = intspec[0]; 1483 1484 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1485 return -EINVAL; 1486 1487 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1488 return 0; 1489 } 1490 1491 #ifdef CONFIG_PCIEPORTBUS 1492 extern bool pcie_ports_disabled; 1493 extern bool pcie_ports_native; 1494 #else 1495 #define pcie_ports_disabled true 1496 #define pcie_ports_native false 1497 #endif 1498 1499 #ifdef CONFIG_PCIEASPM 1500 bool pcie_aspm_support_enabled(void); 1501 #else 1502 static inline bool pcie_aspm_support_enabled(void) { return false; } 1503 #endif 1504 1505 #ifdef CONFIG_PCIEAER 1506 bool pci_aer_available(void); 1507 #else 1508 static inline bool pci_aer_available(void) { return false; } 1509 #endif 1510 1511 #ifdef CONFIG_PCIE_ECRC 1512 void pcie_set_ecrc_checking(struct pci_dev *dev); 1513 void pcie_ecrc_get_policy(char *str); 1514 #else 1515 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1516 static inline void pcie_ecrc_get_policy(char *str) { } 1517 #endif 1518 1519 bool pci_ats_disabled(void); 1520 1521 #ifdef CONFIG_PCI_ATS 1522 /* Address Translation Service */ 1523 void pci_ats_init(struct pci_dev *dev); 1524 int pci_enable_ats(struct pci_dev *dev, int ps); 1525 void pci_disable_ats(struct pci_dev *dev); 1526 int pci_ats_queue_depth(struct pci_dev *dev); 1527 #else 1528 static inline void pci_ats_init(struct pci_dev *d) { } 1529 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1530 static inline void pci_disable_ats(struct pci_dev *d) { } 1531 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1532 #endif 1533 1534 #ifdef CONFIG_PCIE_PTM 1535 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1536 #else 1537 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1538 { return -EINVAL; } 1539 #endif 1540 1541 void pci_cfg_access_lock(struct pci_dev *dev); 1542 bool pci_cfg_access_trylock(struct pci_dev *dev); 1543 void pci_cfg_access_unlock(struct pci_dev *dev); 1544 1545 /* 1546 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1547 * a PCI domain is defined to be a set of PCI buses which share 1548 * configuration space. 1549 */ 1550 #ifdef CONFIG_PCI_DOMAINS 1551 extern int pci_domains_supported; 1552 #else 1553 enum { pci_domains_supported = 0 }; 1554 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1555 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1556 #endif /* CONFIG_PCI_DOMAINS */ 1557 1558 /* 1559 * Generic implementation for PCI domain support. If your 1560 * architecture does not need custom management of PCI 1561 * domains then this implementation will be used 1562 */ 1563 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1564 static inline int pci_domain_nr(struct pci_bus *bus) 1565 { 1566 return bus->domain_nr; 1567 } 1568 #ifdef CONFIG_ACPI 1569 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1570 #else 1571 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1572 { return 0; } 1573 #endif 1574 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1575 #endif 1576 1577 /* Some architectures require additional setup to direct VGA traffic */ 1578 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1579 unsigned int command_bits, u32 flags); 1580 void pci_register_set_vga_state(arch_set_vga_state_t func); 1581 1582 static inline int 1583 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1584 { 1585 return pci_request_selected_regions(pdev, 1586 pci_select_bars(pdev, IORESOURCE_IO), name); 1587 } 1588 1589 static inline void 1590 pci_release_io_regions(struct pci_dev *pdev) 1591 { 1592 return pci_release_selected_regions(pdev, 1593 pci_select_bars(pdev, IORESOURCE_IO)); 1594 } 1595 1596 static inline int 1597 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1598 { 1599 return pci_request_selected_regions(pdev, 1600 pci_select_bars(pdev, IORESOURCE_MEM), name); 1601 } 1602 1603 static inline void 1604 pci_release_mem_regions(struct pci_dev *pdev) 1605 { 1606 return pci_release_selected_regions(pdev, 1607 pci_select_bars(pdev, IORESOURCE_MEM)); 1608 } 1609 1610 #else /* CONFIG_PCI is not enabled */ 1611 1612 static inline void pci_set_flags(int flags) { } 1613 static inline void pci_add_flags(int flags) { } 1614 static inline void pci_clear_flags(int flags) { } 1615 static inline int pci_has_flag(int flag) { return 0; } 1616 1617 /* 1618 * If the system does not have PCI, clearly these return errors. Define 1619 * these as simple inline functions to avoid hair in drivers. 1620 */ 1621 #define _PCI_NOP(o, s, t) \ 1622 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1623 int where, t val) \ 1624 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1625 1626 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1627 _PCI_NOP(o, word, u16 x) \ 1628 _PCI_NOP(o, dword, u32 x) 1629 _PCI_NOP_ALL(read, *) 1630 _PCI_NOP_ALL(write,) 1631 1632 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1633 unsigned int device, 1634 struct pci_dev *from) 1635 { return NULL; } 1636 1637 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1638 unsigned int device, 1639 unsigned int ss_vendor, 1640 unsigned int ss_device, 1641 struct pci_dev *from) 1642 { return NULL; } 1643 1644 static inline struct pci_dev *pci_get_class(unsigned int class, 1645 struct pci_dev *from) 1646 { return NULL; } 1647 1648 #define pci_dev_present(ids) (0) 1649 #define no_pci_devices() (1) 1650 #define pci_dev_put(dev) do { } while (0) 1651 1652 static inline void pci_set_master(struct pci_dev *dev) { } 1653 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1654 static inline void pci_disable_device(struct pci_dev *dev) { } 1655 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1656 { return -EBUSY; } 1657 static inline int __pci_register_driver(struct pci_driver *drv, 1658 struct module *owner) 1659 { return 0; } 1660 static inline int pci_register_driver(struct pci_driver *drv) 1661 { return 0; } 1662 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1663 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1664 { return 0; } 1665 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1666 int cap) 1667 { return 0; } 1668 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1669 { return 0; } 1670 1671 /* Power management related routines */ 1672 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1673 static inline void pci_restore_state(struct pci_dev *dev) { } 1674 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1675 { return 0; } 1676 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1677 { return 0; } 1678 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1679 pm_message_t state) 1680 { return PCI_D0; } 1681 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1682 int enable) 1683 { return 0; } 1684 1685 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1686 struct resource *res) 1687 { return NULL; } 1688 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1689 { return -EIO; } 1690 static inline void pci_release_regions(struct pci_dev *dev) { } 1691 1692 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1693 1694 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1695 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1696 { return 0; } 1697 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1698 1699 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1700 { return NULL; } 1701 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1702 unsigned int devfn) 1703 { return NULL; } 1704 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1705 unsigned int bus, unsigned int devfn) 1706 { return NULL; } 1707 1708 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1709 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1710 1711 #define dev_is_pci(d) (false) 1712 #define dev_is_pf(d) (false) 1713 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1714 { return false; } 1715 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1716 struct device_node *node, 1717 const u32 *intspec, 1718 unsigned int intsize, 1719 unsigned long *out_hwirq, 1720 unsigned int *out_type) 1721 { return -EINVAL; } 1722 1723 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1724 struct pci_dev *dev) 1725 { return NULL; } 1726 #endif /* CONFIG_PCI */ 1727 1728 /* Include architecture-dependent settings and functions */ 1729 1730 #include <asm/pci.h> 1731 1732 /* These two functions provide almost identical functionality. Depennding 1733 * on the architecture, one will be implemented as a wrapper around the 1734 * other (in drivers/pci/mmap.c). 1735 * 1736 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1737 * is expected to be an offset within that region. 1738 * 1739 * pci_mmap_page_range() is the legacy architecture-specific interface, 1740 * which accepts a "user visible" resource address converted by 1741 * pci_resource_to_user(), as used in the legacy mmap() interface in 1742 * /proc/bus/pci/. 1743 */ 1744 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1745 struct vm_area_struct *vma, 1746 enum pci_mmap_state mmap_state, int write_combine); 1747 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1748 struct vm_area_struct *vma, 1749 enum pci_mmap_state mmap_state, int write_combine); 1750 1751 #ifndef arch_can_pci_mmap_wc 1752 #define arch_can_pci_mmap_wc() 0 1753 #endif 1754 1755 #ifndef arch_can_pci_mmap_io 1756 #define arch_can_pci_mmap_io() 0 1757 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1758 #else 1759 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1760 #endif 1761 1762 #ifndef pci_root_bus_fwnode 1763 #define pci_root_bus_fwnode(bus) NULL 1764 #endif 1765 1766 /* 1767 * These helpers provide future and backwards compatibility 1768 * for accessing popular PCI BAR info 1769 */ 1770 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1771 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1772 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1773 #define pci_resource_len(dev,bar) \ 1774 ((pci_resource_start((dev), (bar)) == 0 && \ 1775 pci_resource_end((dev), (bar)) == \ 1776 pci_resource_start((dev), (bar))) ? 0 : \ 1777 \ 1778 (pci_resource_end((dev), (bar)) - \ 1779 pci_resource_start((dev), (bar)) + 1)) 1780 1781 /* 1782 * Similar to the helpers above, these manipulate per-pci_dev 1783 * driver-specific data. They are really just a wrapper around 1784 * the generic device structure functions of these calls. 1785 */ 1786 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1787 { 1788 return dev_get_drvdata(&pdev->dev); 1789 } 1790 1791 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1792 { 1793 dev_set_drvdata(&pdev->dev, data); 1794 } 1795 1796 static inline const char *pci_name(const struct pci_dev *pdev) 1797 { 1798 return dev_name(&pdev->dev); 1799 } 1800 1801 1802 /* 1803 * Some archs don't want to expose struct resource to userland as-is 1804 * in sysfs and /proc 1805 */ 1806 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1807 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1808 const struct resource *rsrc, 1809 resource_size_t *start, resource_size_t *end); 1810 #else 1811 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1812 const struct resource *rsrc, resource_size_t *start, 1813 resource_size_t *end) 1814 { 1815 *start = rsrc->start; 1816 *end = rsrc->end; 1817 } 1818 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1819 1820 1821 /* 1822 * The world is not perfect and supplies us with broken PCI devices. 1823 * For at least a part of these bugs we need a work-around, so both 1824 * generic (drivers/pci/quirks.c) and per-architecture code can define 1825 * fixup hooks to be called for particular buggy devices. 1826 */ 1827 1828 struct pci_fixup { 1829 u16 vendor; /* Or PCI_ANY_ID */ 1830 u16 device; /* Or PCI_ANY_ID */ 1831 u32 class; /* Or PCI_ANY_ID */ 1832 unsigned int class_shift; /* should be 0, 8, 16 */ 1833 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1834 int hook_offset; 1835 #else 1836 void (*hook)(struct pci_dev *dev); 1837 #endif 1838 }; 1839 1840 enum pci_fixup_pass { 1841 pci_fixup_early, /* Before probing BARs */ 1842 pci_fixup_header, /* After reading configuration header */ 1843 pci_fixup_final, /* Final phase of device fixups */ 1844 pci_fixup_enable, /* pci_enable_device() time */ 1845 pci_fixup_resume, /* pci_device_resume() */ 1846 pci_fixup_suspend, /* pci_device_suspend() */ 1847 pci_fixup_resume_early, /* pci_device_resume_early() */ 1848 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1849 }; 1850 1851 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1852 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1853 class_shift, hook) \ 1854 __ADDRESSABLE(hook) \ 1855 asm(".section " #sec ", \"a\" \n" \ 1856 ".balign 16 \n" \ 1857 ".short " #vendor ", " #device " \n" \ 1858 ".long " #class ", " #class_shift " \n" \ 1859 ".long " #hook " - . \n" \ 1860 ".previous \n"); 1861 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1862 class_shift, hook) \ 1863 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1864 class_shift, hook) 1865 #else 1866 /* Anonymous variables would be nice... */ 1867 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1868 class_shift, hook) \ 1869 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1870 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1871 = { vendor, device, class, class_shift, hook }; 1872 #endif 1873 1874 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1875 class_shift, hook) \ 1876 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1877 hook, vendor, device, class, class_shift, hook) 1878 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1879 class_shift, hook) \ 1880 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1881 hook, vendor, device, class, class_shift, hook) 1882 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1883 class_shift, hook) \ 1884 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1885 hook, vendor, device, class, class_shift, hook) 1886 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1887 class_shift, hook) \ 1888 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1889 hook, vendor, device, class, class_shift, hook) 1890 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1891 class_shift, hook) \ 1892 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1893 resume##hook, vendor, device, class, class_shift, hook) 1894 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1895 class_shift, hook) \ 1896 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1897 resume_early##hook, vendor, device, class, class_shift, hook) 1898 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1899 class_shift, hook) \ 1900 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1901 suspend##hook, vendor, device, class, class_shift, hook) 1902 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1903 class_shift, hook) \ 1904 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1905 suspend_late##hook, vendor, device, class, class_shift, hook) 1906 1907 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1908 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1909 hook, vendor, device, PCI_ANY_ID, 0, hook) 1910 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1911 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1912 hook, vendor, device, PCI_ANY_ID, 0, hook) 1913 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1914 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1915 hook, vendor, device, PCI_ANY_ID, 0, hook) 1916 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1917 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1918 hook, vendor, device, PCI_ANY_ID, 0, hook) 1919 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1920 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1921 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1922 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1923 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1924 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1925 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1926 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1927 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1928 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1929 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1930 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1931 1932 #ifdef CONFIG_PCI_QUIRKS 1933 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1934 #else 1935 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1936 struct pci_dev *dev) { } 1937 #endif 1938 1939 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1940 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1941 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1942 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1943 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1944 const char *name); 1945 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1946 1947 extern int pci_pci_problems; 1948 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1949 #define PCIPCI_TRITON 2 1950 #define PCIPCI_NATOMA 4 1951 #define PCIPCI_VIAETBF 8 1952 #define PCIPCI_VSFX 16 1953 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1954 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1955 1956 extern unsigned long pci_cardbus_io_size; 1957 extern unsigned long pci_cardbus_mem_size; 1958 extern u8 pci_dfl_cache_line_size; 1959 extern u8 pci_cache_line_size; 1960 1961 extern unsigned long pci_hotplug_io_size; 1962 extern unsigned long pci_hotplug_mem_size; 1963 extern unsigned long pci_hotplug_bus_size; 1964 1965 /* Architecture-specific versions may override these (weak) */ 1966 void pcibios_disable_device(struct pci_dev *dev); 1967 void pcibios_set_master(struct pci_dev *dev); 1968 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1969 enum pcie_reset_state state); 1970 int pcibios_add_device(struct pci_dev *dev); 1971 void pcibios_release_device(struct pci_dev *dev); 1972 #ifdef CONFIG_PCI 1973 void pcibios_penalize_isa_irq(int irq, int active); 1974 #else 1975 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 1976 #endif 1977 int pcibios_alloc_irq(struct pci_dev *dev); 1978 void pcibios_free_irq(struct pci_dev *dev); 1979 resource_size_t pcibios_default_alignment(void); 1980 1981 #ifdef CONFIG_HIBERNATE_CALLBACKS 1982 extern struct dev_pm_ops pcibios_pm_ops; 1983 #endif 1984 1985 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1986 void __init pci_mmcfg_early_init(void); 1987 void __init pci_mmcfg_late_init(void); 1988 #else 1989 static inline void pci_mmcfg_early_init(void) { } 1990 static inline void pci_mmcfg_late_init(void) { } 1991 #endif 1992 1993 int pci_ext_cfg_avail(void); 1994 1995 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1996 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1997 1998 #ifdef CONFIG_PCI_IOV 1999 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2000 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2001 2002 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2003 void pci_disable_sriov(struct pci_dev *dev); 2004 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2005 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2006 int pci_num_vf(struct pci_dev *dev); 2007 int pci_vfs_assigned(struct pci_dev *dev); 2008 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2009 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2010 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2011 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2012 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2013 2014 /* Arch may override these (weak) */ 2015 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2016 int pcibios_sriov_disable(struct pci_dev *pdev); 2017 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2018 #else 2019 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2020 { 2021 return -ENOSYS; 2022 } 2023 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2024 { 2025 return -ENOSYS; 2026 } 2027 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2028 { return -ENODEV; } 2029 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2030 { 2031 return -ENOSYS; 2032 } 2033 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2034 int id) { } 2035 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2036 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2037 static inline int pci_vfs_assigned(struct pci_dev *dev) 2038 { return 0; } 2039 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2040 { return 0; } 2041 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2042 { return 0; } 2043 #define pci_sriov_configure_simple NULL 2044 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2045 { return 0; } 2046 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2047 #endif 2048 2049 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2050 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2051 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2052 #endif 2053 2054 /** 2055 * pci_pcie_cap - get the saved PCIe capability offset 2056 * @dev: PCI device 2057 * 2058 * PCIe capability offset is calculated at PCI device initialization 2059 * time and saved in the data structure. This function returns saved 2060 * PCIe capability offset. Using this instead of pci_find_capability() 2061 * reduces unnecessary search in the PCI configuration space. If you 2062 * need to calculate PCIe capability offset from raw device for some 2063 * reasons, please use pci_find_capability() instead. 2064 */ 2065 static inline int pci_pcie_cap(struct pci_dev *dev) 2066 { 2067 return dev->pcie_cap; 2068 } 2069 2070 /** 2071 * pci_is_pcie - check if the PCI device is PCI Express capable 2072 * @dev: PCI device 2073 * 2074 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2075 */ 2076 static inline bool pci_is_pcie(struct pci_dev *dev) 2077 { 2078 return pci_pcie_cap(dev); 2079 } 2080 2081 /** 2082 * pcie_caps_reg - get the PCIe Capabilities Register 2083 * @dev: PCI device 2084 */ 2085 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2086 { 2087 return dev->pcie_flags_reg; 2088 } 2089 2090 /** 2091 * pci_pcie_type - get the PCIe device/port type 2092 * @dev: PCI device 2093 */ 2094 static inline int pci_pcie_type(const struct pci_dev *dev) 2095 { 2096 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2097 } 2098 2099 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2100 { 2101 while (1) { 2102 if (!pci_is_pcie(dev)) 2103 break; 2104 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2105 return dev; 2106 if (!dev->bus->self) 2107 break; 2108 dev = dev->bus->self; 2109 } 2110 return NULL; 2111 } 2112 2113 void pci_request_acs(void); 2114 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2115 bool pci_acs_path_enabled(struct pci_dev *start, 2116 struct pci_dev *end, u16 acs_flags); 2117 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2118 2119 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2120 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2121 2122 /* Large Resource Data Type Tag Item Names */ 2123 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2124 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2125 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2126 2127 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2128 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2129 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2130 2131 /* Small Resource Data Type Tag Item Names */ 2132 #define PCI_VPD_STIN_END 0x0f /* End */ 2133 2134 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2135 2136 #define PCI_VPD_SRDT_TIN_MASK 0x78 2137 #define PCI_VPD_SRDT_LEN_MASK 0x07 2138 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2139 2140 #define PCI_VPD_LRDT_TAG_SIZE 3 2141 #define PCI_VPD_SRDT_TAG_SIZE 1 2142 2143 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2144 2145 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2146 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2147 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2148 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2149 2150 /** 2151 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2152 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2153 * 2154 * Returns the extracted Large Resource Data Type length. 2155 */ 2156 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2157 { 2158 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2159 } 2160 2161 /** 2162 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2163 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2164 * 2165 * Returns the extracted Large Resource Data Type Tag item. 2166 */ 2167 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2168 { 2169 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2170 } 2171 2172 /** 2173 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2174 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2175 * 2176 * Returns the extracted Small Resource Data Type length. 2177 */ 2178 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2179 { 2180 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2181 } 2182 2183 /** 2184 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2185 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2186 * 2187 * Returns the extracted Small Resource Data Type Tag Item. 2188 */ 2189 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2190 { 2191 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2192 } 2193 2194 /** 2195 * pci_vpd_info_field_size - Extracts the information field length 2196 * @lrdt: Pointer to the beginning of an information field header 2197 * 2198 * Returns the extracted information field length. 2199 */ 2200 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2201 { 2202 return info_field[2]; 2203 } 2204 2205 /** 2206 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2207 * @buf: Pointer to buffered vpd data 2208 * @off: The offset into the buffer at which to begin the search 2209 * @len: The length of the vpd buffer 2210 * @rdt: The Resource Data Type to search for 2211 * 2212 * Returns the index where the Resource Data Type was found or 2213 * -ENOENT otherwise. 2214 */ 2215 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2216 2217 /** 2218 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2219 * @buf: Pointer to buffered vpd data 2220 * @off: The offset into the buffer at which to begin the search 2221 * @len: The length of the buffer area, relative to off, in which to search 2222 * @kw: The keyword to search for 2223 * 2224 * Returns the index where the information field keyword was found or 2225 * -ENOENT otherwise. 2226 */ 2227 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2228 unsigned int len, const char *kw); 2229 2230 /* PCI <-> OF binding helpers */ 2231 #ifdef CONFIG_OF 2232 struct device_node; 2233 struct irq_domain; 2234 void pci_set_of_node(struct pci_dev *dev); 2235 void pci_release_of_node(struct pci_dev *dev); 2236 void pci_set_bus_of_node(struct pci_bus *bus); 2237 void pci_release_bus_of_node(struct pci_bus *bus); 2238 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2239 int pci_parse_request_of_pci_ranges(struct device *dev, 2240 struct list_head *resources, 2241 struct resource **bus_range); 2242 2243 /* Arch may override this (weak) */ 2244 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2245 2246 #else /* CONFIG_OF */ 2247 static inline void pci_set_of_node(struct pci_dev *dev) { } 2248 static inline void pci_release_of_node(struct pci_dev *dev) { } 2249 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2250 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2251 static inline struct irq_domain * 2252 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2253 static inline int pci_parse_request_of_pci_ranges(struct device *dev, 2254 struct list_head *resources, 2255 struct resource **bus_range) 2256 { 2257 return -EINVAL; 2258 } 2259 #endif /* CONFIG_OF */ 2260 2261 static inline struct device_node * 2262 pci_device_to_OF_node(const struct pci_dev *pdev) 2263 { 2264 return pdev ? pdev->dev.of_node : NULL; 2265 } 2266 2267 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2268 { 2269 return bus ? bus->dev.of_node : NULL; 2270 } 2271 2272 #ifdef CONFIG_ACPI 2273 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2274 2275 void 2276 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2277 #else 2278 static inline struct irq_domain * 2279 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2280 #endif 2281 2282 #ifdef CONFIG_EEH 2283 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2284 { 2285 return pdev->dev.archdata.edev; 2286 } 2287 #endif 2288 2289 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2290 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2291 int pci_for_each_dma_alias(struct pci_dev *pdev, 2292 int (*fn)(struct pci_dev *pdev, 2293 u16 alias, void *data), void *data); 2294 2295 /* Helper functions for operation of device flag */ 2296 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2297 { 2298 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2299 } 2300 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2301 { 2302 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2303 } 2304 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2305 { 2306 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2307 } 2308 2309 /** 2310 * pci_ari_enabled - query ARI forwarding status 2311 * @bus: the PCI bus 2312 * 2313 * Returns true if ARI forwarding is enabled. 2314 */ 2315 static inline bool pci_ari_enabled(struct pci_bus *bus) 2316 { 2317 return bus->self && bus->self->ari_enabled; 2318 } 2319 2320 /** 2321 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2322 * @pdev: PCI device to check 2323 * 2324 * Walk upwards from @pdev and check for each encountered bridge if it's part 2325 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2326 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2327 */ 2328 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2329 { 2330 struct pci_dev *parent = pdev; 2331 2332 if (pdev->is_thunderbolt) 2333 return true; 2334 2335 while ((parent = pci_upstream_bridge(parent))) 2336 if (parent->is_thunderbolt) 2337 return true; 2338 2339 return false; 2340 } 2341 2342 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2343 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2344 #endif 2345 2346 /* Provide the legacy pci_dma_* API */ 2347 #include <linux/pci-dma-compat.h> 2348 2349 #define pci_printk(level, pdev, fmt, arg...) \ 2350 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2351 2352 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2353 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2354 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2355 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2356 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2357 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2358 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2359 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2360 2361 #endif /* LINUX_PCI_H */ 2362