1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 #include <linux/pci_regs.h> /* The pci register defines */ 21 22 /* 23 * The PCI interface treats multi-function devices as independent 24 * devices. The slot/function address of each device is encoded 25 * in a single byte as follows: 26 * 27 * 7:3 = slot 28 * 2:0 = function 29 */ 30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 32 #define PCI_FUNC(devfn) ((devfn) & 0x07) 33 34 /* Ioctls for /proc/bus/pci/X/Y nodes. */ 35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) 36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ 37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ 38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ 39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ 40 41 #ifdef __KERNEL__ 42 43 #include <linux/mod_devicetable.h> 44 45 #include <linux/types.h> 46 #include <linux/init.h> 47 #include <linux/ioport.h> 48 #include <linux/list.h> 49 #include <linux/compiler.h> 50 #include <linux/errno.h> 51 #include <linux/kobject.h> 52 #include <asm/atomic.h> 53 #include <linux/device.h> 54 55 /* Include the ID list */ 56 #include <linux/pci_ids.h> 57 58 /* pci_slot represents a physical slot */ 59 struct pci_slot { 60 struct pci_bus *bus; /* The bus this slot is on */ 61 struct list_head list; /* node in list of slots on this bus */ 62 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 63 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 64 struct kobject kobj; 65 }; 66 67 /* File state for mmap()s on /proc/bus/pci/X/Y */ 68 enum pci_mmap_state { 69 pci_mmap_io, 70 pci_mmap_mem 71 }; 72 73 /* This defines the direction arg to the DMA mapping routines. */ 74 #define PCI_DMA_BIDIRECTIONAL 0 75 #define PCI_DMA_TODEVICE 1 76 #define PCI_DMA_FROMDEVICE 2 77 #define PCI_DMA_NONE 3 78 79 #define DEVICE_COUNT_RESOURCE 12 80 81 typedef int __bitwise pci_power_t; 82 83 #define PCI_D0 ((pci_power_t __force) 0) 84 #define PCI_D1 ((pci_power_t __force) 1) 85 #define PCI_D2 ((pci_power_t __force) 2) 86 #define PCI_D3hot ((pci_power_t __force) 3) 87 #define PCI_D3cold ((pci_power_t __force) 4) 88 #define PCI_UNKNOWN ((pci_power_t __force) 5) 89 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 90 91 /** The pci_channel state describes connectivity between the CPU and 92 * the pci device. If some PCI bus between here and the pci device 93 * has crashed or locked up, this info is reflected here. 94 */ 95 typedef unsigned int __bitwise pci_channel_state_t; 96 97 enum pci_channel_state { 98 /* I/O channel is in normal state */ 99 pci_channel_io_normal = (__force pci_channel_state_t) 1, 100 101 /* I/O to channel is blocked */ 102 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 103 104 /* PCI card is dead */ 105 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 106 }; 107 108 typedef unsigned int __bitwise pcie_reset_state_t; 109 110 enum pcie_reset_state { 111 /* Reset is NOT asserted (Use to deassert reset) */ 112 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 113 114 /* Use #PERST to reset PCI-E device */ 115 pcie_warm_reset = (__force pcie_reset_state_t) 2, 116 117 /* Use PCI-E Hot Reset to reset device */ 118 pcie_hot_reset = (__force pcie_reset_state_t) 3 119 }; 120 121 typedef unsigned short __bitwise pci_dev_flags_t; 122 enum pci_dev_flags { 123 /* INTX_DISABLE in PCI_COMMAND register disables MSI 124 * generation too. 125 */ 126 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, 127 /* Device configuration is irrevocably lost if disabled into D3 */ 128 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, 129 }; 130 131 typedef unsigned short __bitwise pci_bus_flags_t; 132 enum pci_bus_flags { 133 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 134 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 135 }; 136 137 struct pci_cap_saved_state { 138 struct hlist_node next; 139 char cap_nr; 140 u32 data[0]; 141 }; 142 143 struct pcie_link_state; 144 struct pci_vpd; 145 146 /* 147 * The pci_dev structure is used to describe PCI devices. 148 */ 149 struct pci_dev { 150 struct list_head bus_list; /* node in per-bus list */ 151 struct pci_bus *bus; /* bus this device is on */ 152 struct pci_bus *subordinate; /* bus this device bridges to */ 153 154 void *sysdata; /* hook for sys-specific extension */ 155 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 156 struct pci_slot *slot; /* Physical slot this device is in */ 157 158 unsigned int devfn; /* encoded device & function index */ 159 unsigned short vendor; 160 unsigned short device; 161 unsigned short subsystem_vendor; 162 unsigned short subsystem_device; 163 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 164 u8 revision; /* PCI revision, low byte of class word */ 165 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 166 u8 pcie_type; /* PCI-E device/port type */ 167 u8 rom_base_reg; /* which config register controls the ROM */ 168 u8 pin; /* which interrupt pin this device uses */ 169 170 struct pci_driver *driver; /* which driver has allocated this device */ 171 u64 dma_mask; /* Mask of the bits of bus address this 172 device implements. Normally this is 173 0xffffffff. You only need to change 174 this if your device has broken DMA 175 or supports 64-bit transfers. */ 176 177 struct device_dma_parameters dma_parms; 178 179 pci_power_t current_state; /* Current operating state. In ACPI-speak, 180 this is D0-D3, D0 being fully functional, 181 and D3 being off. */ 182 int pm_cap; /* PM capability offset in the 183 configuration space */ 184 unsigned int pme_support:5; /* Bitmask of states from which PME# 185 can be generated */ 186 unsigned int d1_support:1; /* Low power state D1 is supported */ 187 unsigned int d2_support:1; /* Low power state D2 is supported */ 188 unsigned int no_d1d2:1; /* Only allow D0 and D3 */ 189 190 #ifdef CONFIG_PCIEASPM 191 struct pcie_link_state *link_state; /* ASPM link state. */ 192 #endif 193 194 pci_channel_state_t error_state; /* current connectivity state */ 195 struct device dev; /* Generic device interface */ 196 197 int cfg_size; /* Size of configuration space */ 198 199 /* 200 * Instead of touching interrupt line and base address registers 201 * directly, use the values stored here. They might be different! 202 */ 203 unsigned int irq; 204 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 205 206 /* These fields are used by common fixups */ 207 unsigned int transparent:1; /* Transparent PCI bridge */ 208 unsigned int multifunction:1;/* Part of multi-function device */ 209 /* keep track of device state */ 210 unsigned int is_added:1; 211 unsigned int is_busmaster:1; /* device is busmaster */ 212 unsigned int no_msi:1; /* device may not use msi */ 213 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ 214 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 215 unsigned int msi_enabled:1; 216 unsigned int msix_enabled:1; 217 unsigned int is_managed:1; 218 unsigned int is_pcie:1; 219 pci_dev_flags_t dev_flags; 220 atomic_t enable_cnt; /* pci_enable_device has been called */ 221 222 u32 saved_config_space[16]; /* config space saved at suspend time */ 223 struct hlist_head saved_cap_space; 224 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 225 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 226 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 227 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 228 #ifdef CONFIG_PCI_MSI 229 struct list_head msi_list; 230 #endif 231 struct pci_vpd *vpd; 232 }; 233 234 extern struct pci_dev *alloc_pci_dev(void); 235 236 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) 237 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 238 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 239 240 static inline int pci_channel_offline(struct pci_dev *pdev) 241 { 242 return (pdev->error_state != pci_channel_io_normal); 243 } 244 245 static inline struct pci_cap_saved_state *pci_find_saved_cap( 246 struct pci_dev *pci_dev, char cap) 247 { 248 struct pci_cap_saved_state *tmp; 249 struct hlist_node *pos; 250 251 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { 252 if (tmp->cap_nr == cap) 253 return tmp; 254 } 255 return NULL; 256 } 257 258 static inline void pci_add_saved_cap(struct pci_dev *pci_dev, 259 struct pci_cap_saved_state *new_cap) 260 { 261 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); 262 } 263 264 /* 265 * For PCI devices, the region numbers are assigned this way: 266 * 267 * 0-5 standard PCI regions 268 * 6 expansion ROM 269 * 7-10 bridges: address space assigned to buses behind the bridge 270 */ 271 272 #define PCI_ROM_RESOURCE 6 273 #define PCI_BRIDGE_RESOURCES 7 274 #define PCI_NUM_RESOURCES 11 275 276 #ifndef PCI_BUS_NUM_RESOURCES 277 #define PCI_BUS_NUM_RESOURCES 16 278 #endif 279 280 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 281 282 struct pci_bus { 283 struct list_head node; /* node in list of buses */ 284 struct pci_bus *parent; /* parent bus this bridge is on */ 285 struct list_head children; /* list of child buses */ 286 struct list_head devices; /* list of devices on this bus */ 287 struct pci_dev *self; /* bridge device as seen by parent */ 288 struct list_head slots; /* list of slots on this bus */ 289 struct resource *resource[PCI_BUS_NUM_RESOURCES]; 290 /* address space routed to this bus */ 291 292 struct pci_ops *ops; /* configuration access functions */ 293 void *sysdata; /* hook for sys-specific extension */ 294 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 295 296 unsigned char number; /* bus number */ 297 unsigned char primary; /* number of primary bridge */ 298 unsigned char secondary; /* number of secondary bridge */ 299 unsigned char subordinate; /* max number of subordinate buses */ 300 301 char name[48]; 302 303 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 304 pci_bus_flags_t bus_flags; /* Inherited by child busses */ 305 struct device *bridge; 306 struct device dev; 307 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 308 struct bin_attribute *legacy_mem; /* legacy mem */ 309 unsigned int is_added:1; 310 }; 311 312 #define pci_bus_b(n) list_entry(n, struct pci_bus, node) 313 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 314 315 /* 316 * Error values that may be returned by PCI functions. 317 */ 318 #define PCIBIOS_SUCCESSFUL 0x00 319 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 320 #define PCIBIOS_BAD_VENDOR_ID 0x83 321 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 322 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 323 #define PCIBIOS_SET_FAILED 0x88 324 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 325 326 /* Low-level architecture-dependent routines */ 327 328 struct pci_ops { 329 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 330 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 331 }; 332 333 /* 334 * ACPI needs to be able to access PCI config space before we've done a 335 * PCI bus scan and created pci_bus structures. 336 */ 337 extern int raw_pci_read(unsigned int domain, unsigned int bus, 338 unsigned int devfn, int reg, int len, u32 *val); 339 extern int raw_pci_write(unsigned int domain, unsigned int bus, 340 unsigned int devfn, int reg, int len, u32 val); 341 342 struct pci_bus_region { 343 resource_size_t start; 344 resource_size_t end; 345 }; 346 347 struct pci_dynids { 348 spinlock_t lock; /* protects list, index */ 349 struct list_head list; /* for IDs added at runtime */ 350 unsigned int use_driver_data:1; /* pci_device_id->driver_data is used */ 351 }; 352 353 /* ---------------------------------------------------------------- */ 354 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 355 * a set of callbacks in struct pci_error_handlers, then that device driver 356 * will be notified of PCI bus errors, and will be driven to recovery 357 * when an error occurs. 358 */ 359 360 typedef unsigned int __bitwise pci_ers_result_t; 361 362 enum pci_ers_result { 363 /* no result/none/not supported in device driver */ 364 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 365 366 /* Device driver can recover without slot reset */ 367 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 368 369 /* Device driver wants slot to be reset. */ 370 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 371 372 /* Device has completely failed, is unrecoverable */ 373 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 374 375 /* Device driver is fully recovered and operational */ 376 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 377 }; 378 379 /* PCI bus error event callbacks */ 380 struct pci_error_handlers { 381 /* PCI bus error detected on this device */ 382 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 383 enum pci_channel_state error); 384 385 /* MMIO has been re-enabled, but not DMA */ 386 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 387 388 /* PCI Express link has been reset */ 389 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 390 391 /* PCI slot has been reset */ 392 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 393 394 /* Device driver may resume normal operations */ 395 void (*resume)(struct pci_dev *dev); 396 }; 397 398 /* ---------------------------------------------------------------- */ 399 400 struct module; 401 struct pci_driver { 402 struct list_head node; 403 char *name; 404 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 405 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 406 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 407 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 408 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 409 int (*resume_early) (struct pci_dev *dev); 410 int (*resume) (struct pci_dev *dev); /* Device woken up */ 411 void (*shutdown) (struct pci_dev *dev); 412 struct pm_ext_ops *pm; 413 struct pci_error_handlers *err_handler; 414 struct device_driver driver; 415 struct pci_dynids dynids; 416 }; 417 418 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 419 420 /** 421 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 422 * @_table: device table name 423 * 424 * This macro is used to create a struct pci_device_id array (a device table) 425 * in a generic manner. 426 */ 427 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 428 const struct pci_device_id _table[] __devinitconst 429 430 /** 431 * PCI_DEVICE - macro used to describe a specific pci device 432 * @vend: the 16 bit PCI Vendor ID 433 * @dev: the 16 bit PCI Device ID 434 * 435 * This macro is used to create a struct pci_device_id that matches a 436 * specific device. The subvendor and subdevice fields will be set to 437 * PCI_ANY_ID. 438 */ 439 #define PCI_DEVICE(vend,dev) \ 440 .vendor = (vend), .device = (dev), \ 441 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 442 443 /** 444 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 445 * @dev_class: the class, subclass, prog-if triple for this device 446 * @dev_class_mask: the class mask for this device 447 * 448 * This macro is used to create a struct pci_device_id that matches a 449 * specific PCI class. The vendor, device, subvendor, and subdevice 450 * fields will be set to PCI_ANY_ID. 451 */ 452 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 453 .class = (dev_class), .class_mask = (dev_class_mask), \ 454 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 455 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 456 457 /** 458 * PCI_VDEVICE - macro used to describe a specific pci device in short form 459 * @vend: the vendor name 460 * @dev: the 16 bit PCI Device ID 461 * 462 * This macro is used to create a struct pci_device_id that matches a 463 * specific PCI device. The subvendor, and subdevice fields will be set 464 * to PCI_ANY_ID. The macro allows the next field to follow as the device 465 * private data. 466 */ 467 468 #define PCI_VDEVICE(vendor, device) \ 469 PCI_VENDOR_ID_##vendor, (device), \ 470 PCI_ANY_ID, PCI_ANY_ID, 0, 0 471 472 /* these external functions are only available when PCI support is enabled */ 473 #ifdef CONFIG_PCI 474 475 extern struct bus_type pci_bus_type; 476 477 /* Do NOT directly access these two variables, unless you are arch specific pci 478 * code, or pci core code. */ 479 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 480 /* Some device drivers need know if pci is initiated */ 481 extern int no_pci_devices(void); 482 483 void pcibios_fixup_bus(struct pci_bus *); 484 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 485 char *pcibios_setup(char *str); 486 487 /* Used only when drivers/pci/setup.c is used */ 488 void pcibios_align_resource(void *, struct resource *, resource_size_t, 489 resource_size_t); 490 void pcibios_update_irq(struct pci_dev *, int irq); 491 492 /* Generic PCI functions used internally */ 493 494 extern struct pci_bus *pci_find_bus(int domain, int busnr); 495 void pci_bus_add_devices(struct pci_bus *bus); 496 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, 497 struct pci_ops *ops, void *sysdata); 498 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, 499 void *sysdata) 500 { 501 struct pci_bus *root_bus; 502 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); 503 if (root_bus) 504 pci_bus_add_devices(root_bus); 505 return root_bus; 506 } 507 struct pci_bus *pci_create_bus(struct device *parent, int bus, 508 struct pci_ops *ops, void *sysdata); 509 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 510 int busnr); 511 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 512 const char *name); 513 void pci_destroy_slot(struct pci_slot *slot); 514 void pci_update_slot_number(struct pci_slot *slot, int slot_nr); 515 int pci_scan_slot(struct pci_bus *bus, int devfn); 516 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 517 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 518 unsigned int pci_scan_child_bus(struct pci_bus *bus); 519 int __must_check pci_bus_add_device(struct pci_dev *dev); 520 void pci_read_bridge_bases(struct pci_bus *child); 521 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 522 struct resource *res); 523 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 524 extern struct pci_dev *pci_dev_get(struct pci_dev *dev); 525 extern void pci_dev_put(struct pci_dev *dev); 526 extern void pci_remove_bus(struct pci_bus *b); 527 extern void pci_remove_bus_device(struct pci_dev *dev); 528 extern void pci_stop_bus_device(struct pci_dev *dev); 529 void pci_setup_cardbus(struct pci_bus *bus); 530 extern void pci_sort_breadthfirst(void); 531 532 /* Generic PCI functions exported to card drivers */ 533 534 #ifdef CONFIG_PCI_LEGACY 535 struct pci_dev __deprecated *pci_find_device(unsigned int vendor, 536 unsigned int device, 537 const struct pci_dev *from); 538 struct pci_dev __deprecated *pci_find_slot(unsigned int bus, 539 unsigned int devfn); 540 #endif /* CONFIG_PCI_LEGACY */ 541 542 int pci_find_capability(struct pci_dev *dev, int cap); 543 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 544 int pci_find_ext_capability(struct pci_dev *dev, int cap); 545 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 546 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 547 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 548 549 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 550 struct pci_dev *from); 551 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 552 unsigned int ss_vendor, unsigned int ss_device, 553 const struct pci_dev *from); 554 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 555 struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); 556 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 557 int pci_dev_present(const struct pci_device_id *ids); 558 559 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 560 int where, u8 *val); 561 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 562 int where, u16 *val); 563 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 564 int where, u32 *val); 565 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 566 int where, u8 val); 567 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 568 int where, u16 val); 569 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 570 int where, u32 val); 571 572 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) 573 { 574 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 575 } 576 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) 577 { 578 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 579 } 580 static inline int pci_read_config_dword(struct pci_dev *dev, int where, 581 u32 *val) 582 { 583 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 584 } 585 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) 586 { 587 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 588 } 589 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) 590 { 591 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 592 } 593 static inline int pci_write_config_dword(struct pci_dev *dev, int where, 594 u32 val) 595 { 596 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 597 } 598 599 int __must_check pci_enable_device(struct pci_dev *dev); 600 int __must_check pci_enable_device_io(struct pci_dev *dev); 601 int __must_check pci_enable_device_mem(struct pci_dev *dev); 602 int __must_check pci_reenable_device(struct pci_dev *); 603 int __must_check pcim_enable_device(struct pci_dev *pdev); 604 void pcim_pin_device(struct pci_dev *pdev); 605 606 static inline int pci_is_managed(struct pci_dev *pdev) 607 { 608 return pdev->is_managed; 609 } 610 611 void pci_disable_device(struct pci_dev *dev); 612 void pci_set_master(struct pci_dev *dev); 613 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 614 #define HAVE_PCI_SET_MWI 615 int __must_check pci_set_mwi(struct pci_dev *dev); 616 int pci_try_set_mwi(struct pci_dev *dev); 617 void pci_clear_mwi(struct pci_dev *dev); 618 void pci_intx(struct pci_dev *dev, int enable); 619 void pci_msi_off(struct pci_dev *dev); 620 int pci_set_dma_mask(struct pci_dev *dev, u64 mask); 621 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); 622 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 623 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 624 int pcix_get_max_mmrbc(struct pci_dev *dev); 625 int pcix_get_mmrbc(struct pci_dev *dev); 626 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 627 int pcie_get_readrq(struct pci_dev *dev); 628 int pcie_set_readrq(struct pci_dev *dev, int rq); 629 void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); 630 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 631 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 632 633 /* ROM control related routines */ 634 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 635 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 636 size_t pci_get_rom_size(void __iomem *rom, size_t size); 637 638 /* Power management related routines */ 639 int pci_save_state(struct pci_dev *dev); 640 int pci_restore_state(struct pci_dev *dev); 641 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 642 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 643 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 644 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); 645 pci_power_t pci_target_state(struct pci_dev *dev); 646 int pci_prepare_to_sleep(struct pci_dev *dev); 647 int pci_back_from_sleep(struct pci_dev *dev); 648 649 /* Functions for PCI Hotplug drivers to use */ 650 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 651 652 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 653 void pci_bus_assign_resources(struct pci_bus *bus); 654 void pci_bus_size_bridges(struct pci_bus *bus); 655 int pci_claim_resource(struct pci_dev *, int); 656 void pci_assign_unassigned_resources(void); 657 void pdev_enable_device(struct pci_dev *); 658 void pdev_sort_resources(struct pci_dev *, struct resource_list *); 659 int pci_enable_resources(struct pci_dev *, int mask); 660 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 661 int (*)(struct pci_dev *, u8, u8)); 662 #define HAVE_PCI_REQ_REGIONS 2 663 int __must_check pci_request_regions(struct pci_dev *, const char *); 664 void pci_release_regions(struct pci_dev *); 665 int __must_check pci_request_region(struct pci_dev *, int, const char *); 666 void pci_release_region(struct pci_dev *, int); 667 int pci_request_selected_regions(struct pci_dev *, int, const char *); 668 void pci_release_selected_regions(struct pci_dev *, int); 669 670 /* drivers/pci/bus.c */ 671 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 672 struct resource *res, resource_size_t size, 673 resource_size_t align, resource_size_t min, 674 unsigned int type_mask, 675 void (*alignf)(void *, struct resource *, 676 resource_size_t, resource_size_t), 677 void *alignf_data); 678 void pci_enable_bridges(struct pci_bus *bus); 679 680 /* Proper probing supporting hot-pluggable devices */ 681 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 682 const char *mod_name); 683 static inline int __must_check pci_register_driver(struct pci_driver *driver) 684 { 685 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME); 686 } 687 688 void pci_unregister_driver(struct pci_driver *dev); 689 void pci_remove_behind_bridge(struct pci_dev *dev); 690 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 691 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 692 struct pci_dev *dev); 693 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 694 int pass); 695 696 void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *), 697 void *userdata); 698 int pci_cfg_space_size_ext(struct pci_dev *dev); 699 int pci_cfg_space_size(struct pci_dev *dev); 700 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 701 702 /* kmem_cache style wrapper around pci_alloc_consistent() */ 703 704 #include <linux/dmapool.h> 705 706 #define pci_pool dma_pool 707 #define pci_pool_create(name, pdev, size, align, allocation) \ 708 dma_pool_create(name, &pdev->dev, size, align, allocation) 709 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 710 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 711 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 712 713 enum pci_dma_burst_strategy { 714 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, 715 strategy_parameter is N/A */ 716 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter 717 byte boundaries */ 718 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of 719 strategy_parameter byte boundaries */ 720 }; 721 722 struct msix_entry { 723 u16 vector; /* kernel uses to write allocated vector */ 724 u16 entry; /* driver uses to specify entry, OS writes */ 725 }; 726 727 728 #ifndef CONFIG_PCI_MSI 729 static inline int pci_enable_msi(struct pci_dev *dev) 730 { 731 return -1; 732 } 733 734 static inline void pci_msi_shutdown(struct pci_dev *dev) 735 { } 736 static inline void pci_disable_msi(struct pci_dev *dev) 737 { } 738 739 static inline int pci_enable_msix(struct pci_dev *dev, 740 struct msix_entry *entries, int nvec) 741 { 742 return -1; 743 } 744 745 static inline void pci_msix_shutdown(struct pci_dev *dev) 746 { } 747 static inline void pci_disable_msix(struct pci_dev *dev) 748 { } 749 750 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) 751 { } 752 753 static inline void pci_restore_msi_state(struct pci_dev *dev) 754 { } 755 #else 756 extern int pci_enable_msi(struct pci_dev *dev); 757 extern void pci_msi_shutdown(struct pci_dev *dev); 758 extern void pci_disable_msi(struct pci_dev *dev); 759 extern int pci_enable_msix(struct pci_dev *dev, 760 struct msix_entry *entries, int nvec); 761 extern void pci_msix_shutdown(struct pci_dev *dev); 762 extern void pci_disable_msix(struct pci_dev *dev); 763 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); 764 extern void pci_restore_msi_state(struct pci_dev *dev); 765 #endif 766 767 #ifdef CONFIG_HT_IRQ 768 /* The functions a driver should call */ 769 int ht_create_irq(struct pci_dev *dev, int idx); 770 void ht_destroy_irq(unsigned int irq); 771 #endif /* CONFIG_HT_IRQ */ 772 773 extern void pci_block_user_cfg_access(struct pci_dev *dev); 774 extern void pci_unblock_user_cfg_access(struct pci_dev *dev); 775 776 /* 777 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 778 * a PCI domain is defined to be a set of PCI busses which share 779 * configuration space. 780 */ 781 #ifdef CONFIG_PCI_DOMAINS 782 extern int pci_domains_supported; 783 #else 784 enum { pci_domains_supported = 0 }; 785 static inline int pci_domain_nr(struct pci_bus *bus) 786 { 787 return 0; 788 } 789 790 static inline int pci_proc_domain(struct pci_bus *bus) 791 { 792 return 0; 793 } 794 #endif /* CONFIG_PCI_DOMAINS */ 795 796 #else /* CONFIG_PCI is not enabled */ 797 798 /* 799 * If the system does not have PCI, clearly these return errors. Define 800 * these as simple inline functions to avoid hair in drivers. 801 */ 802 803 #define _PCI_NOP(o, s, t) \ 804 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 805 int where, t val) \ 806 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 807 808 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 809 _PCI_NOP(o, word, u16 x) \ 810 _PCI_NOP(o, dword, u32 x) 811 _PCI_NOP_ALL(read, *) 812 _PCI_NOP_ALL(write,) 813 814 static inline struct pci_dev *pci_find_device(unsigned int vendor, 815 unsigned int device, 816 const struct pci_dev *from) 817 { 818 return NULL; 819 } 820 821 static inline struct pci_dev *pci_find_slot(unsigned int bus, 822 unsigned int devfn) 823 { 824 return NULL; 825 } 826 827 static inline struct pci_dev *pci_get_device(unsigned int vendor, 828 unsigned int device, 829 struct pci_dev *from) 830 { 831 return NULL; 832 } 833 834 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 835 unsigned int device, 836 unsigned int ss_vendor, 837 unsigned int ss_device, 838 const struct pci_dev *from) 839 { 840 return NULL; 841 } 842 843 static inline struct pci_dev *pci_get_class(unsigned int class, 844 struct pci_dev *from) 845 { 846 return NULL; 847 } 848 849 #define pci_dev_present(ids) (0) 850 #define no_pci_devices() (1) 851 #define pci_dev_put(dev) do { } while (0) 852 853 static inline void pci_set_master(struct pci_dev *dev) 854 { } 855 856 static inline int pci_enable_device(struct pci_dev *dev) 857 { 858 return -EIO; 859 } 860 861 static inline void pci_disable_device(struct pci_dev *dev) 862 { } 863 864 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 865 { 866 return -EIO; 867 } 868 869 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 870 { 871 return -EIO; 872 } 873 874 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 875 unsigned int size) 876 { 877 return -EIO; 878 } 879 880 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 881 unsigned long mask) 882 { 883 return -EIO; 884 } 885 886 static inline int pci_assign_resource(struct pci_dev *dev, int i) 887 { 888 return -EBUSY; 889 } 890 891 static inline int __pci_register_driver(struct pci_driver *drv, 892 struct module *owner) 893 { 894 return 0; 895 } 896 897 static inline int pci_register_driver(struct pci_driver *drv) 898 { 899 return 0; 900 } 901 902 static inline void pci_unregister_driver(struct pci_driver *drv) 903 { } 904 905 static inline int pci_find_capability(struct pci_dev *dev, int cap) 906 { 907 return 0; 908 } 909 910 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 911 int cap) 912 { 913 return 0; 914 } 915 916 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 917 { 918 return 0; 919 } 920 921 /* Power management related routines */ 922 static inline int pci_save_state(struct pci_dev *dev) 923 { 924 return 0; 925 } 926 927 static inline int pci_restore_state(struct pci_dev *dev) 928 { 929 return 0; 930 } 931 932 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 933 { 934 return 0; 935 } 936 937 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 938 pm_message_t state) 939 { 940 return PCI_D0; 941 } 942 943 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 944 int enable) 945 { 946 return 0; 947 } 948 949 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 950 { 951 return -EIO; 952 } 953 954 static inline void pci_release_regions(struct pci_dev *dev) 955 { } 956 957 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 958 959 static inline void pci_block_user_cfg_access(struct pci_dev *dev) 960 { } 961 962 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) 963 { } 964 965 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 966 { return NULL; } 967 968 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 969 unsigned int devfn) 970 { return NULL; } 971 972 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 973 unsigned int devfn) 974 { return NULL; } 975 976 #endif /* CONFIG_PCI */ 977 978 /* Include architecture-dependent settings and functions */ 979 980 #include <asm/pci.h> 981 982 /* these helpers provide future and backwards compatibility 983 * for accessing popular PCI BAR info */ 984 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 985 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 986 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 987 #define pci_resource_len(dev,bar) \ 988 ((pci_resource_start((dev), (bar)) == 0 && \ 989 pci_resource_end((dev), (bar)) == \ 990 pci_resource_start((dev), (bar))) ? 0 : \ 991 \ 992 (pci_resource_end((dev), (bar)) - \ 993 pci_resource_start((dev), (bar)) + 1)) 994 995 /* Similar to the helpers above, these manipulate per-pci_dev 996 * driver-specific data. They are really just a wrapper around 997 * the generic device structure functions of these calls. 998 */ 999 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1000 { 1001 return dev_get_drvdata(&pdev->dev); 1002 } 1003 1004 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1005 { 1006 dev_set_drvdata(&pdev->dev, data); 1007 } 1008 1009 /* If you want to know what to call your pci_dev, ask this function. 1010 * Again, it's a wrapper around the generic device. 1011 */ 1012 static inline const char *pci_name(struct pci_dev *pdev) 1013 { 1014 return dev_name(&pdev->dev); 1015 } 1016 1017 1018 /* Some archs don't want to expose struct resource to userland as-is 1019 * in sysfs and /proc 1020 */ 1021 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1022 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1023 const struct resource *rsrc, resource_size_t *start, 1024 resource_size_t *end) 1025 { 1026 *start = rsrc->start; 1027 *end = rsrc->end; 1028 } 1029 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1030 1031 1032 /* 1033 * The world is not perfect and supplies us with broken PCI devices. 1034 * For at least a part of these bugs we need a work-around, so both 1035 * generic (drivers/pci/quirks.c) and per-architecture code can define 1036 * fixup hooks to be called for particular buggy devices. 1037 */ 1038 1039 struct pci_fixup { 1040 u16 vendor, device; /* You can use PCI_ANY_ID here of course */ 1041 void (*hook)(struct pci_dev *dev); 1042 }; 1043 1044 enum pci_fixup_pass { 1045 pci_fixup_early, /* Before probing BARs */ 1046 pci_fixup_header, /* After reading configuration header */ 1047 pci_fixup_final, /* Final phase of device fixups */ 1048 pci_fixup_enable, /* pci_enable_device() time */ 1049 pci_fixup_resume, /* pci_device_resume() */ 1050 pci_fixup_suspend, /* pci_device_suspend */ 1051 pci_fixup_resume_early, /* pci_device_resume_early() */ 1052 }; 1053 1054 /* Anonymous variables would be nice... */ 1055 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ 1056 static const struct pci_fixup __pci_fixup_##name __used \ 1057 __attribute__((__section__(#section))) = { vendor, device, hook }; 1058 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1059 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1060 vendor##device##hook, vendor, device, hook) 1061 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1062 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1063 vendor##device##hook, vendor, device, hook) 1064 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1065 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1066 vendor##device##hook, vendor, device, hook) 1067 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1068 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1069 vendor##device##hook, vendor, device, hook) 1070 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1071 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1072 resume##vendor##device##hook, vendor, device, hook) 1073 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1074 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1075 resume_early##vendor##device##hook, vendor, device, hook) 1076 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1078 suspend##vendor##device##hook, vendor, device, hook) 1079 1080 1081 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1082 1083 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1084 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1085 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1086 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); 1087 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, 1088 const char *name); 1089 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); 1090 1091 extern int pci_pci_problems; 1092 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1093 #define PCIPCI_TRITON 2 1094 #define PCIPCI_NATOMA 4 1095 #define PCIPCI_VIAETBF 8 1096 #define PCIPCI_VSFX 16 1097 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1098 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1099 1100 extern unsigned long pci_cardbus_io_size; 1101 extern unsigned long pci_cardbus_mem_size; 1102 1103 int pcibios_add_platform_entries(struct pci_dev *dev); 1104 void pcibios_disable_device(struct pci_dev *dev); 1105 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1106 enum pcie_reset_state state); 1107 1108 #ifdef CONFIG_PCI_MMCONFIG 1109 extern void __init pci_mmcfg_early_init(void); 1110 extern void __init pci_mmcfg_late_init(void); 1111 #else 1112 static inline void pci_mmcfg_early_init(void) { } 1113 static inline void pci_mmcfg_late_init(void) { } 1114 #endif 1115 1116 #endif /* __KERNEL__ */ 1117 #endif /* LINUX_PCI_H */ 1118