1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 46 PCI_STATUS_SIG_SYSTEM_ERROR | \ 47 PCI_STATUS_REC_MASTER_ABORT | \ 48 PCI_STATUS_REC_TARGET_ABORT | \ 49 PCI_STATUS_SIG_TARGET_ABORT | \ 50 PCI_STATUS_PARITY) 51 52 /* 53 * The PCI interface treats multi-function devices as independent 54 * devices. The slot/function address of each device is encoded 55 * in a single byte as follows: 56 * 57 * 7:3 = slot 58 * 2:0 = function 59 * 60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 61 * In the interest of not exposing interfaces to user-space unnecessarily, 62 * the following kernel-only defines are being added here. 63 */ 64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 67 68 /* pci_slot represents a physical slot */ 69 struct pci_slot { 70 struct pci_bus *bus; /* Bus this slot is on */ 71 struct list_head list; /* Node in list of slots */ 72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 74 struct kobject kobj; 75 }; 76 77 static inline const char *pci_slot_name(const struct pci_slot *slot) 78 { 79 return kobject_name(&slot->kobj); 80 } 81 82 /* File state for mmap()s on /proc/bus/pci/X/Y */ 83 enum pci_mmap_state { 84 pci_mmap_io, 85 pci_mmap_mem 86 }; 87 88 /* For PCI devices, the region numbers are assigned this way: */ 89 enum { 90 /* #0-5: standard PCI resources */ 91 PCI_STD_RESOURCES, 92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 93 94 /* #6: expansion ROM resource */ 95 PCI_ROM_RESOURCE, 96 97 /* Device-specific resources */ 98 #ifdef CONFIG_PCI_IOV 99 PCI_IOV_RESOURCES, 100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 101 #endif 102 103 /* Resources assigned to buses behind the bridge */ 104 #define PCI_BRIDGE_RESOURCE_NUM 4 105 106 PCI_BRIDGE_RESOURCES, 107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 108 PCI_BRIDGE_RESOURCE_NUM - 1, 109 110 /* Total resources associated with a PCI device */ 111 PCI_NUM_RESOURCES, 112 113 /* Preserve this for compatibility */ 114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 115 }; 116 117 /** 118 * enum pci_interrupt_pin - PCI INTx interrupt values 119 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 120 * @PCI_INTERRUPT_INTA: PCI INTA pin 121 * @PCI_INTERRUPT_INTB: PCI INTB pin 122 * @PCI_INTERRUPT_INTC: PCI INTC pin 123 * @PCI_INTERRUPT_INTD: PCI INTD pin 124 * 125 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 126 * PCI_INTERRUPT_PIN register. 127 */ 128 enum pci_interrupt_pin { 129 PCI_INTERRUPT_UNKNOWN, 130 PCI_INTERRUPT_INTA, 131 PCI_INTERRUPT_INTB, 132 PCI_INTERRUPT_INTC, 133 PCI_INTERRUPT_INTD, 134 }; 135 136 /* The number of legacy PCI INTx interrupts */ 137 #define PCI_NUM_INTX 4 138 139 /* 140 * pci_power_t values must match the bits in the Capabilities PME_Support 141 * and Control/Status PowerState fields in the Power Management capability. 142 */ 143 typedef int __bitwise pci_power_t; 144 145 #define PCI_D0 ((pci_power_t __force) 0) 146 #define PCI_D1 ((pci_power_t __force) 1) 147 #define PCI_D2 ((pci_power_t __force) 2) 148 #define PCI_D3hot ((pci_power_t __force) 3) 149 #define PCI_D3cold ((pci_power_t __force) 4) 150 #define PCI_UNKNOWN ((pci_power_t __force) 5) 151 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 152 153 /* Remember to update this when the list above changes! */ 154 extern const char *pci_power_names[]; 155 156 static inline const char *pci_power_name(pci_power_t state) 157 { 158 return pci_power_names[1 + (__force int) state]; 159 } 160 161 /** 162 * typedef pci_channel_state_t 163 * 164 * The pci_channel state describes connectivity between the CPU and 165 * the PCI device. If some PCI bus between here and the PCI device 166 * has crashed or locked up, this info is reflected here. 167 */ 168 typedef unsigned int __bitwise pci_channel_state_t; 169 170 enum pci_channel_state { 171 /* I/O channel is in normal state */ 172 pci_channel_io_normal = (__force pci_channel_state_t) 1, 173 174 /* I/O to channel is blocked */ 175 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 176 177 /* PCI card is dead */ 178 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 179 }; 180 181 typedef unsigned int __bitwise pcie_reset_state_t; 182 183 enum pcie_reset_state { 184 /* Reset is NOT asserted (Use to deassert reset) */ 185 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 186 187 /* Use #PERST to reset PCIe device */ 188 pcie_warm_reset = (__force pcie_reset_state_t) 2, 189 190 /* Use PCIe Hot Reset to reset device */ 191 pcie_hot_reset = (__force pcie_reset_state_t) 3 192 }; 193 194 typedef unsigned short __bitwise pci_dev_flags_t; 195 enum pci_dev_flags { 196 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 197 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 198 /* Device configuration is irrevocably lost if disabled into D3 */ 199 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 200 /* Provide indication device is assigned by a Virtual Machine Manager */ 201 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 202 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 203 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 204 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 205 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 206 /* Do not use bus resets for device */ 207 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 208 /* Do not use PM reset even if device advertises NoSoftRst- */ 209 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 210 /* Get VPD from function 0 VPD */ 211 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 212 /* A non-root bridge where translation occurs, stop alias search here */ 213 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 214 /* Do not use FLR even if device advertises PCI_AF_CAP */ 215 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 216 /* Don't use Relaxed Ordering for TLPs directed at this device */ 217 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 218 }; 219 220 enum pci_irq_reroute_variant { 221 INTEL_IRQ_REROUTE_VARIANT = 1, 222 MAX_IRQ_REROUTE_VARIANTS = 3 223 }; 224 225 typedef unsigned short __bitwise pci_bus_flags_t; 226 enum pci_bus_flags { 227 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 228 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 229 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 230 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 231 }; 232 233 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 234 enum pcie_link_width { 235 PCIE_LNK_WIDTH_RESRV = 0x00, 236 PCIE_LNK_X1 = 0x01, 237 PCIE_LNK_X2 = 0x02, 238 PCIE_LNK_X4 = 0x04, 239 PCIE_LNK_X8 = 0x08, 240 PCIE_LNK_X12 = 0x0c, 241 PCIE_LNK_X16 = 0x10, 242 PCIE_LNK_X32 = 0x20, 243 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 244 }; 245 246 /* See matching string table in pci_speed_string() */ 247 enum pci_bus_speed { 248 PCI_SPEED_33MHz = 0x00, 249 PCI_SPEED_66MHz = 0x01, 250 PCI_SPEED_66MHz_PCIX = 0x02, 251 PCI_SPEED_100MHz_PCIX = 0x03, 252 PCI_SPEED_133MHz_PCIX = 0x04, 253 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 254 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 255 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 256 PCI_SPEED_66MHz_PCIX_266 = 0x09, 257 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 258 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 259 AGP_UNKNOWN = 0x0c, 260 AGP_1X = 0x0d, 261 AGP_2X = 0x0e, 262 AGP_4X = 0x0f, 263 AGP_8X = 0x10, 264 PCI_SPEED_66MHz_PCIX_533 = 0x11, 265 PCI_SPEED_100MHz_PCIX_533 = 0x12, 266 PCI_SPEED_133MHz_PCIX_533 = 0x13, 267 PCIE_SPEED_2_5GT = 0x14, 268 PCIE_SPEED_5_0GT = 0x15, 269 PCIE_SPEED_8_0GT = 0x16, 270 PCIE_SPEED_16_0GT = 0x17, 271 PCIE_SPEED_32_0GT = 0x18, 272 PCI_SPEED_UNKNOWN = 0xff, 273 }; 274 275 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 276 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 277 278 struct pci_cap_saved_data { 279 u16 cap_nr; 280 bool cap_extended; 281 unsigned int size; 282 u32 data[0]; 283 }; 284 285 struct pci_cap_saved_state { 286 struct hlist_node next; 287 struct pci_cap_saved_data cap; 288 }; 289 290 struct irq_affinity; 291 struct pcie_link_state; 292 struct pci_vpd; 293 struct pci_sriov; 294 struct pci_p2pdma; 295 296 /* The pci_dev structure describes PCI devices */ 297 struct pci_dev { 298 struct list_head bus_list; /* Node in per-bus list */ 299 struct pci_bus *bus; /* Bus this device is on */ 300 struct pci_bus *subordinate; /* Bus this device bridges to */ 301 302 void *sysdata; /* Hook for sys-specific extension */ 303 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 304 struct pci_slot *slot; /* Physical slot this device is in */ 305 306 unsigned int devfn; /* Encoded device & function index */ 307 unsigned short vendor; 308 unsigned short device; 309 unsigned short subsystem_vendor; 310 unsigned short subsystem_device; 311 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 312 u8 revision; /* PCI revision, low byte of class word */ 313 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 314 #ifdef CONFIG_PCIEAER 315 u16 aer_cap; /* AER capability offset */ 316 struct aer_stats *aer_stats; /* AER stats for this device */ 317 #endif 318 u8 pcie_cap; /* PCIe capability offset */ 319 u8 msi_cap; /* MSI capability offset */ 320 u8 msix_cap; /* MSI-X capability offset */ 321 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 322 u8 rom_base_reg; /* Config register controlling ROM */ 323 u8 pin; /* Interrupt pin this device uses */ 324 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 325 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 326 327 struct pci_driver *driver; /* Driver bound to this device */ 328 u64 dma_mask; /* Mask of the bits of bus address this 329 device implements. Normally this is 330 0xffffffff. You only need to change 331 this if your device has broken DMA 332 or supports 64-bit transfers. */ 333 334 struct device_dma_parameters dma_parms; 335 336 pci_power_t current_state; /* Current operating state. In ACPI, 337 this is D0-D3, D0 being fully 338 functional, and D3 being off. */ 339 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 340 u8 pm_cap; /* PM capability offset */ 341 unsigned int pme_support:5; /* Bitmask of states from which PME# 342 can be generated */ 343 unsigned int pme_poll:1; /* Poll device's PME status bit */ 344 unsigned int d1_support:1; /* Low power state D1 is supported */ 345 unsigned int d2_support:1; /* Low power state D2 is supported */ 346 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 347 unsigned int no_d3cold:1; /* D3cold is forbidden */ 348 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 349 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 350 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 351 decoding during BAR sizing */ 352 unsigned int wakeup_prepared:1; 353 unsigned int runtime_d3cold:1; /* Whether go through runtime 354 D3cold, not set for devices 355 powered on/off by the 356 corresponding bridge */ 357 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 358 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 359 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 360 controlled exclusively by 361 user sysfs */ 362 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 363 bit manually */ 364 unsigned int d3_delay; /* D3->D0 transition time in ms */ 365 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 366 367 #ifdef CONFIG_PCIEASPM 368 struct pcie_link_state *link_state; /* ASPM link state */ 369 unsigned int ltr_path:1; /* Latency Tolerance Reporting 370 supported from root to here */ 371 #endif 372 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 373 374 pci_channel_state_t error_state; /* Current connectivity state */ 375 struct device dev; /* Generic device interface */ 376 377 int cfg_size; /* Size of config space */ 378 379 /* 380 * Instead of touching interrupt line and base address registers 381 * directly, use the values stored here. They might be different! 382 */ 383 unsigned int irq; 384 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 385 386 bool match_driver; /* Skip attaching driver */ 387 388 unsigned int transparent:1; /* Subtractive decode bridge */ 389 unsigned int io_window:1; /* Bridge has I/O window */ 390 unsigned int pref_window:1; /* Bridge has pref mem window */ 391 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 392 unsigned int multifunction:1; /* Multi-function device */ 393 394 unsigned int is_busmaster:1; /* Is busmaster */ 395 unsigned int no_msi:1; /* May not use MSI */ 396 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 397 unsigned int block_cfg_access:1; /* Config space access blocked */ 398 unsigned int broken_parity_status:1; /* Generates false positive parity */ 399 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 400 unsigned int msi_enabled:1; 401 unsigned int msix_enabled:1; 402 unsigned int ari_enabled:1; /* ARI forwarding */ 403 unsigned int ats_enabled:1; /* Address Translation Svc */ 404 unsigned int pasid_enabled:1; /* Process Address Space ID */ 405 unsigned int pri_enabled:1; /* Page Request Interface */ 406 unsigned int is_managed:1; 407 unsigned int needs_freset:1; /* Requires fundamental reset */ 408 unsigned int state_saved:1; 409 unsigned int is_physfn:1; 410 unsigned int is_virtfn:1; 411 unsigned int reset_fn:1; 412 unsigned int is_hotplug_bridge:1; 413 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 414 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 415 /* 416 * Devices marked being untrusted are the ones that can potentially 417 * execute DMA attacks and similar. They are typically connected 418 * through external ports such as Thunderbolt but not limited to 419 * that. When an IOMMU is enabled they should be getting full 420 * mappings to make sure they cannot access arbitrary memory. 421 */ 422 unsigned int untrusted:1; 423 unsigned int __aer_firmware_first_valid:1; 424 unsigned int __aer_firmware_first:1; 425 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 426 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 427 unsigned int irq_managed:1; 428 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 429 unsigned int is_probed:1; /* Device probing in progress */ 430 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 431 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 432 pci_dev_flags_t dev_flags; 433 atomic_t enable_cnt; /* pci_enable_device has been called */ 434 435 u32 saved_config_space[16]; /* Config space saved at suspend time */ 436 struct hlist_head saved_cap_space; 437 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 438 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 439 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 440 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 441 442 #ifdef CONFIG_HOTPLUG_PCI_PCIE 443 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 444 #endif 445 #ifdef CONFIG_PCIE_PTM 446 unsigned int ptm_root:1; 447 unsigned int ptm_enabled:1; 448 u8 ptm_granularity; 449 #endif 450 #ifdef CONFIG_PCI_MSI 451 const struct attribute_group **msi_irq_groups; 452 #endif 453 struct pci_vpd *vpd; 454 #ifdef CONFIG_PCIE_DPC 455 u16 dpc_cap; 456 unsigned int dpc_rp_extensions:1; 457 u8 dpc_rp_log_size; 458 #endif 459 #ifdef CONFIG_PCI_ATS 460 union { 461 struct pci_sriov *sriov; /* PF: SR-IOV info */ 462 struct pci_dev *physfn; /* VF: related PF */ 463 }; 464 u16 ats_cap; /* ATS Capability offset */ 465 u8 ats_stu; /* ATS Smallest Translation Unit */ 466 #endif 467 #ifdef CONFIG_PCI_PRI 468 u16 pri_cap; /* PRI Capability offset */ 469 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 470 unsigned int pasid_required:1; /* PRG Response PASID Required */ 471 #endif 472 #ifdef CONFIG_PCI_PASID 473 u16 pasid_cap; /* PASID Capability offset */ 474 u16 pasid_features; 475 #endif 476 #ifdef CONFIG_PCI_P2PDMA 477 struct pci_p2pdma *p2pdma; 478 #endif 479 phys_addr_t rom; /* Physical address if not from BAR */ 480 size_t romlen; /* Length if not from BAR */ 481 char *driver_override; /* Driver name to force a match */ 482 483 unsigned long priv_flags; /* Private flags for the PCI driver */ 484 }; 485 486 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 487 { 488 #ifdef CONFIG_PCI_IOV 489 if (dev->is_virtfn) 490 dev = dev->physfn; 491 #endif 492 return dev; 493 } 494 495 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 496 497 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 498 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 499 500 static inline int pci_channel_offline(struct pci_dev *pdev) 501 { 502 return (pdev->error_state != pci_channel_io_normal); 503 } 504 505 struct pci_host_bridge { 506 struct device dev; 507 struct pci_bus *bus; /* Root bus */ 508 struct pci_ops *ops; 509 void *sysdata; 510 int busnr; 511 struct list_head windows; /* resource_entry */ 512 struct list_head dma_ranges; /* dma ranges resource list */ 513 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 514 int (*map_irq)(const struct pci_dev *, u8, u8); 515 void (*release_fn)(struct pci_host_bridge *); 516 void *release_data; 517 struct msi_controller *msi; 518 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 519 unsigned int no_ext_tags:1; /* No Extended Tags */ 520 unsigned int native_aer:1; /* OS may use PCIe AER */ 521 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 522 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 523 unsigned int native_pme:1; /* OS may use PCIe PME */ 524 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 525 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 526 unsigned int preserve_config:1; /* Preserve FW resource setup */ 527 unsigned int size_windows:1; /* Enable root bus sizing */ 528 529 /* Resource alignment requirements */ 530 resource_size_t (*align_resource)(struct pci_dev *dev, 531 const struct resource *res, 532 resource_size_t start, 533 resource_size_t size, 534 resource_size_t align); 535 unsigned long private[0] ____cacheline_aligned; 536 }; 537 538 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 539 540 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 541 { 542 return (void *)bridge->private; 543 } 544 545 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 546 { 547 return container_of(priv, struct pci_host_bridge, private); 548 } 549 550 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 551 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 552 size_t priv); 553 void pci_free_host_bridge(struct pci_host_bridge *bridge); 554 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 555 556 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 557 void (*release_fn)(struct pci_host_bridge *), 558 void *release_data); 559 560 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 561 562 /* 563 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 564 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 565 * buses below host bridges or subtractive decode bridges) go in the list. 566 * Use pci_bus_for_each_resource() to iterate through all the resources. 567 */ 568 569 /* 570 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 571 * and there's no way to program the bridge with the details of the window. 572 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 573 * decode bit set, because they are explicit and can be programmed with _SRS. 574 */ 575 #define PCI_SUBTRACTIVE_DECODE 0x1 576 577 struct pci_bus_resource { 578 struct list_head list; 579 struct resource *res; 580 unsigned int flags; 581 }; 582 583 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 584 585 struct pci_bus { 586 struct list_head node; /* Node in list of buses */ 587 struct pci_bus *parent; /* Parent bus this bridge is on */ 588 struct list_head children; /* List of child buses */ 589 struct list_head devices; /* List of devices on this bus */ 590 struct pci_dev *self; /* Bridge device as seen by parent */ 591 struct list_head slots; /* List of slots on this bus; 592 protected by pci_slot_mutex */ 593 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 594 struct list_head resources; /* Address space routed to this bus */ 595 struct resource busn_res; /* Bus numbers routed to this bus */ 596 597 struct pci_ops *ops; /* Configuration access functions */ 598 struct msi_controller *msi; /* MSI controller */ 599 void *sysdata; /* Hook for sys-specific extension */ 600 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 601 602 unsigned char number; /* Bus number */ 603 unsigned char primary; /* Number of primary bridge */ 604 unsigned char max_bus_speed; /* enum pci_bus_speed */ 605 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 606 #ifdef CONFIG_PCI_DOMAINS_GENERIC 607 int domain_nr; 608 #endif 609 610 char name[48]; 611 612 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 613 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 614 struct device *bridge; 615 struct device dev; 616 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 617 struct bin_attribute *legacy_mem; /* Legacy mem */ 618 unsigned int is_added:1; 619 }; 620 621 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 622 623 static inline u16 pci_dev_id(struct pci_dev *dev) 624 { 625 return PCI_DEVID(dev->bus->number, dev->devfn); 626 } 627 628 /* 629 * Returns true if the PCI bus is root (behind host-PCI bridge), 630 * false otherwise 631 * 632 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 633 * This is incorrect because "virtual" buses added for SR-IOV (via 634 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 635 */ 636 static inline bool pci_is_root_bus(struct pci_bus *pbus) 637 { 638 return !(pbus->parent); 639 } 640 641 /** 642 * pci_is_bridge - check if the PCI device is a bridge 643 * @dev: PCI device 644 * 645 * Return true if the PCI device is bridge whether it has subordinate 646 * or not. 647 */ 648 static inline bool pci_is_bridge(struct pci_dev *dev) 649 { 650 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 651 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 652 } 653 654 #define for_each_pci_bridge(dev, bus) \ 655 list_for_each_entry(dev, &bus->devices, bus_list) \ 656 if (!pci_is_bridge(dev)) {} else 657 658 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 659 { 660 dev = pci_physfn(dev); 661 if (pci_is_root_bus(dev->bus)) 662 return NULL; 663 664 return dev->bus->self; 665 } 666 667 #ifdef CONFIG_PCI_MSI 668 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 669 { 670 return pci_dev->msi_enabled || pci_dev->msix_enabled; 671 } 672 #else 673 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 674 #endif 675 676 /* Error values that may be returned by PCI functions */ 677 #define PCIBIOS_SUCCESSFUL 0x00 678 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 679 #define PCIBIOS_BAD_VENDOR_ID 0x83 680 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 681 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 682 #define PCIBIOS_SET_FAILED 0x88 683 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 684 685 /* Translate above to generic errno for passing back through non-PCI code */ 686 static inline int pcibios_err_to_errno(int err) 687 { 688 if (err <= PCIBIOS_SUCCESSFUL) 689 return err; /* Assume already errno */ 690 691 switch (err) { 692 case PCIBIOS_FUNC_NOT_SUPPORTED: 693 return -ENOENT; 694 case PCIBIOS_BAD_VENDOR_ID: 695 return -ENOTTY; 696 case PCIBIOS_DEVICE_NOT_FOUND: 697 return -ENODEV; 698 case PCIBIOS_BAD_REGISTER_NUMBER: 699 return -EFAULT; 700 case PCIBIOS_SET_FAILED: 701 return -EIO; 702 case PCIBIOS_BUFFER_TOO_SMALL: 703 return -ENOSPC; 704 } 705 706 return -ERANGE; 707 } 708 709 /* Low-level architecture-dependent routines */ 710 711 struct pci_ops { 712 int (*add_bus)(struct pci_bus *bus); 713 void (*remove_bus)(struct pci_bus *bus); 714 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 715 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 716 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 717 }; 718 719 /* 720 * ACPI needs to be able to access PCI config space before we've done a 721 * PCI bus scan and created pci_bus structures. 722 */ 723 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 724 int reg, int len, u32 *val); 725 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 726 int reg, int len, u32 val); 727 728 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 729 typedef u64 pci_bus_addr_t; 730 #else 731 typedef u32 pci_bus_addr_t; 732 #endif 733 734 struct pci_bus_region { 735 pci_bus_addr_t start; 736 pci_bus_addr_t end; 737 }; 738 739 struct pci_dynids { 740 spinlock_t lock; /* Protects list, index */ 741 struct list_head list; /* For IDs added at runtime */ 742 }; 743 744 745 /* 746 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 747 * a set of callbacks in struct pci_error_handlers, that device driver 748 * will be notified of PCI bus errors, and will be driven to recovery 749 * when an error occurs. 750 */ 751 752 typedef unsigned int __bitwise pci_ers_result_t; 753 754 enum pci_ers_result { 755 /* No result/none/not supported in device driver */ 756 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 757 758 /* Device driver can recover without slot reset */ 759 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 760 761 /* Device driver wants slot to be reset */ 762 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 763 764 /* Device has completely failed, is unrecoverable */ 765 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 766 767 /* Device driver is fully recovered and operational */ 768 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 769 770 /* No AER capabilities registered for the driver */ 771 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 772 }; 773 774 /* PCI bus error event callbacks */ 775 struct pci_error_handlers { 776 /* PCI bus error detected on this device */ 777 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 778 enum pci_channel_state error); 779 780 /* MMIO has been re-enabled, but not DMA */ 781 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 782 783 /* PCI slot has been reset */ 784 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 785 786 /* PCI function reset prepare or completed */ 787 void (*reset_prepare)(struct pci_dev *dev); 788 void (*reset_done)(struct pci_dev *dev); 789 790 /* Device driver may resume normal operations */ 791 void (*resume)(struct pci_dev *dev); 792 }; 793 794 795 struct module; 796 797 /** 798 * struct pci_driver - PCI driver structure 799 * @node: List of driver structures. 800 * @name: Driver name. 801 * @id_table: Pointer to table of device IDs the driver is 802 * interested in. Most drivers should export this 803 * table using MODULE_DEVICE_TABLE(pci,...). 804 * @probe: This probing function gets called (during execution 805 * of pci_register_driver() for already existing 806 * devices or later if a new device gets inserted) for 807 * all PCI devices which match the ID table and are not 808 * "owned" by the other drivers yet. This function gets 809 * passed a "struct pci_dev \*" for each device whose 810 * entry in the ID table matches the device. The probe 811 * function returns zero when the driver chooses to 812 * take "ownership" of the device or an error code 813 * (negative number) otherwise. 814 * The probe function always gets called from process 815 * context, so it can sleep. 816 * @remove: The remove() function gets called whenever a device 817 * being handled by this driver is removed (either during 818 * deregistration of the driver or when it's manually 819 * pulled out of a hot-pluggable slot). 820 * The remove function always gets called from process 821 * context, so it can sleep. 822 * @suspend: Put device into low power state. 823 * @resume: Wake device from low power state. 824 * (Please see Documentation/power/pci.rst for descriptions 825 * of PCI Power Management and the related functions.) 826 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 827 * Intended to stop any idling DMA operations. 828 * Useful for enabling wake-on-lan (NIC) or changing 829 * the power state of a device before reboot. 830 * e.g. drivers/net/e100.c. 831 * @sriov_configure: Optional driver callback to allow configuration of 832 * number of VFs to enable via sysfs "sriov_numvfs" file. 833 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 834 * @groups: Sysfs attribute groups. 835 * @driver: Driver model structure. 836 * @dynids: List of dynamically added device IDs. 837 */ 838 struct pci_driver { 839 struct list_head node; 840 const char *name; 841 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 842 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 843 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 844 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 845 int (*resume)(struct pci_dev *dev); /* Device woken up */ 846 void (*shutdown)(struct pci_dev *dev); 847 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 848 const struct pci_error_handlers *err_handler; 849 const struct attribute_group **groups; 850 struct device_driver driver; 851 struct pci_dynids dynids; 852 }; 853 854 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 855 856 /** 857 * PCI_DEVICE - macro used to describe a specific PCI device 858 * @vend: the 16 bit PCI Vendor ID 859 * @dev: the 16 bit PCI Device ID 860 * 861 * This macro is used to create a struct pci_device_id that matches a 862 * specific device. The subvendor and subdevice fields will be set to 863 * PCI_ANY_ID. 864 */ 865 #define PCI_DEVICE(vend,dev) \ 866 .vendor = (vend), .device = (dev), \ 867 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 868 869 /** 870 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 871 * @vend: the 16 bit PCI Vendor ID 872 * @dev: the 16 bit PCI Device ID 873 * @subvend: the 16 bit PCI Subvendor ID 874 * @subdev: the 16 bit PCI Subdevice ID 875 * 876 * This macro is used to create a struct pci_device_id that matches a 877 * specific device with subsystem information. 878 */ 879 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 880 .vendor = (vend), .device = (dev), \ 881 .subvendor = (subvend), .subdevice = (subdev) 882 883 /** 884 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 885 * @dev_class: the class, subclass, prog-if triple for this device 886 * @dev_class_mask: the class mask for this device 887 * 888 * This macro is used to create a struct pci_device_id that matches a 889 * specific PCI class. The vendor, device, subvendor, and subdevice 890 * fields will be set to PCI_ANY_ID. 891 */ 892 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 893 .class = (dev_class), .class_mask = (dev_class_mask), \ 894 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 895 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 896 897 /** 898 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 899 * @vend: the vendor name 900 * @dev: the 16 bit PCI Device ID 901 * 902 * This macro is used to create a struct pci_device_id that matches a 903 * specific PCI device. The subvendor, and subdevice fields will be set 904 * to PCI_ANY_ID. The macro allows the next field to follow as the device 905 * private data. 906 */ 907 #define PCI_VDEVICE(vend, dev) \ 908 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 909 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 910 911 /** 912 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 913 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 914 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 915 * @data: the driver data to be filled 916 * 917 * This macro is used to create a struct pci_device_id that matches a 918 * specific PCI device. The subvendor, and subdevice fields will be set 919 * to PCI_ANY_ID. 920 */ 921 #define PCI_DEVICE_DATA(vend, dev, data) \ 922 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 923 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 924 .driver_data = (kernel_ulong_t)(data) 925 926 enum { 927 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 928 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 929 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 930 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 931 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 932 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 933 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 934 }; 935 936 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 937 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 938 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 939 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 940 941 /* These external functions are only available when PCI support is enabled */ 942 #ifdef CONFIG_PCI 943 944 extern unsigned int pci_flags; 945 946 static inline void pci_set_flags(int flags) { pci_flags = flags; } 947 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 948 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 949 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 950 951 void pcie_bus_configure_settings(struct pci_bus *bus); 952 953 enum pcie_bus_config_types { 954 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 955 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 956 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 957 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 958 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 959 }; 960 961 extern enum pcie_bus_config_types pcie_bus_config; 962 963 extern struct bus_type pci_bus_type; 964 965 /* Do NOT directly access these two variables, unless you are arch-specific PCI 966 * code, or PCI core code. */ 967 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 968 /* Some device drivers need know if PCI is initiated */ 969 int no_pci_devices(void); 970 971 void pcibios_resource_survey_bus(struct pci_bus *bus); 972 void pcibios_bus_add_device(struct pci_dev *pdev); 973 void pcibios_add_bus(struct pci_bus *bus); 974 void pcibios_remove_bus(struct pci_bus *bus); 975 void pcibios_fixup_bus(struct pci_bus *); 976 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 977 /* Architecture-specific versions may override this (weak) */ 978 char *pcibios_setup(char *str); 979 980 /* Used only when drivers/pci/setup.c is used */ 981 resource_size_t pcibios_align_resource(void *, const struct resource *, 982 resource_size_t, 983 resource_size_t); 984 985 /* Weak but can be overridden by arch */ 986 void pci_fixup_cardbus(struct pci_bus *); 987 988 /* Generic PCI functions used internally */ 989 990 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 991 struct resource *res); 992 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 993 struct pci_bus_region *region); 994 void pcibios_scan_specific_bus(int busn); 995 struct pci_bus *pci_find_bus(int domain, int busnr); 996 void pci_bus_add_devices(const struct pci_bus *bus); 997 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 998 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 999 struct pci_ops *ops, void *sysdata, 1000 struct list_head *resources); 1001 int pci_host_probe(struct pci_host_bridge *bridge); 1002 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1003 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1004 void pci_bus_release_busn_res(struct pci_bus *b); 1005 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1006 struct pci_ops *ops, void *sysdata, 1007 struct list_head *resources); 1008 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1009 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1010 int busnr); 1011 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1012 const char *name, 1013 struct hotplug_slot *hotplug); 1014 void pci_destroy_slot(struct pci_slot *slot); 1015 #ifdef CONFIG_SYSFS 1016 void pci_dev_assign_slot(struct pci_dev *dev); 1017 #else 1018 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1019 #endif 1020 int pci_scan_slot(struct pci_bus *bus, int devfn); 1021 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1022 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1023 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1024 void pci_bus_add_device(struct pci_dev *dev); 1025 void pci_read_bridge_bases(struct pci_bus *child); 1026 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1027 struct resource *res); 1028 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 1029 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1030 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1031 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1032 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1033 void pci_dev_put(struct pci_dev *dev); 1034 void pci_remove_bus(struct pci_bus *b); 1035 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1036 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1037 void pci_stop_root_bus(struct pci_bus *bus); 1038 void pci_remove_root_bus(struct pci_bus *bus); 1039 void pci_setup_cardbus(struct pci_bus *bus); 1040 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1041 void pci_sort_breadthfirst(void); 1042 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1043 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1044 1045 /* Generic PCI functions exported to card drivers */ 1046 1047 enum pci_lost_interrupt_reason { 1048 PCI_LOST_IRQ_NO_INFORMATION = 0, 1049 PCI_LOST_IRQ_DISABLE_MSI, 1050 PCI_LOST_IRQ_DISABLE_MSIX, 1051 PCI_LOST_IRQ_DISABLE_ACPI, 1052 }; 1053 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 1054 int pci_find_capability(struct pci_dev *dev, int cap); 1055 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1056 int pci_find_ext_capability(struct pci_dev *dev, int cap); 1057 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 1058 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1059 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 1060 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1061 1062 u64 pci_get_dsn(struct pci_dev *dev); 1063 1064 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1065 struct pci_dev *from); 1066 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1067 unsigned int ss_vendor, unsigned int ss_device, 1068 struct pci_dev *from); 1069 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1070 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1071 unsigned int devfn); 1072 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1073 int pci_dev_present(const struct pci_device_id *ids); 1074 1075 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1076 int where, u8 *val); 1077 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1078 int where, u16 *val); 1079 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1080 int where, u32 *val); 1081 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1082 int where, u8 val); 1083 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1084 int where, u16 val); 1085 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1086 int where, u32 val); 1087 1088 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1089 int where, int size, u32 *val); 1090 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1091 int where, int size, u32 val); 1092 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1093 int where, int size, u32 *val); 1094 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1095 int where, int size, u32 val); 1096 1097 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1098 1099 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1100 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1101 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1102 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1103 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1104 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1105 1106 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1107 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1108 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1109 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1110 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1111 u16 clear, u16 set); 1112 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1113 u32 clear, u32 set); 1114 1115 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1116 u16 set) 1117 { 1118 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1119 } 1120 1121 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1122 u32 set) 1123 { 1124 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1125 } 1126 1127 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1128 u16 clear) 1129 { 1130 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1131 } 1132 1133 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1134 u32 clear) 1135 { 1136 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1137 } 1138 1139 /* User-space driven config access */ 1140 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1141 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1142 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1143 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1144 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1145 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1146 1147 int __must_check pci_enable_device(struct pci_dev *dev); 1148 int __must_check pci_enable_device_io(struct pci_dev *dev); 1149 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1150 int __must_check pci_reenable_device(struct pci_dev *); 1151 int __must_check pcim_enable_device(struct pci_dev *pdev); 1152 void pcim_pin_device(struct pci_dev *pdev); 1153 1154 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1155 { 1156 /* 1157 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1158 * writable and no quirk has marked the feature broken. 1159 */ 1160 return !pdev->broken_intx_masking; 1161 } 1162 1163 static inline int pci_is_enabled(struct pci_dev *pdev) 1164 { 1165 return (atomic_read(&pdev->enable_cnt) > 0); 1166 } 1167 1168 static inline int pci_is_managed(struct pci_dev *pdev) 1169 { 1170 return pdev->is_managed; 1171 } 1172 1173 void pci_disable_device(struct pci_dev *dev); 1174 1175 extern unsigned int pcibios_max_latency; 1176 void pci_set_master(struct pci_dev *dev); 1177 void pci_clear_master(struct pci_dev *dev); 1178 1179 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1180 int pci_set_cacheline_size(struct pci_dev *dev); 1181 #define HAVE_PCI_SET_MWI 1182 int __must_check pci_set_mwi(struct pci_dev *dev); 1183 int __must_check pcim_set_mwi(struct pci_dev *dev); 1184 int pci_try_set_mwi(struct pci_dev *dev); 1185 void pci_clear_mwi(struct pci_dev *dev); 1186 void pci_intx(struct pci_dev *dev, int enable); 1187 bool pci_check_and_mask_intx(struct pci_dev *dev); 1188 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1189 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1190 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1191 int pcix_get_max_mmrbc(struct pci_dev *dev); 1192 int pcix_get_mmrbc(struct pci_dev *dev); 1193 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1194 int pcie_get_readrq(struct pci_dev *dev); 1195 int pcie_set_readrq(struct pci_dev *dev, int rq); 1196 int pcie_get_mps(struct pci_dev *dev); 1197 int pcie_set_mps(struct pci_dev *dev, int mps); 1198 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1199 enum pci_bus_speed *speed, 1200 enum pcie_link_width *width); 1201 void pcie_print_link_status(struct pci_dev *dev); 1202 bool pcie_has_flr(struct pci_dev *dev); 1203 int pcie_flr(struct pci_dev *dev); 1204 int __pci_reset_function_locked(struct pci_dev *dev); 1205 int pci_reset_function(struct pci_dev *dev); 1206 int pci_reset_function_locked(struct pci_dev *dev); 1207 int pci_try_reset_function(struct pci_dev *dev); 1208 int pci_probe_reset_slot(struct pci_slot *slot); 1209 int pci_probe_reset_bus(struct pci_bus *bus); 1210 int pci_reset_bus(struct pci_dev *dev); 1211 void pci_reset_secondary_bus(struct pci_dev *dev); 1212 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1213 void pci_update_resource(struct pci_dev *dev, int resno); 1214 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1215 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1216 void pci_release_resource(struct pci_dev *dev, int resno); 1217 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1218 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1219 bool pci_device_is_present(struct pci_dev *pdev); 1220 void pci_ignore_hotplug(struct pci_dev *dev); 1221 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1222 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1223 1224 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1225 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1226 const char *fmt, ...); 1227 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1228 1229 /* ROM control related routines */ 1230 int pci_enable_rom(struct pci_dev *pdev); 1231 void pci_disable_rom(struct pci_dev *pdev); 1232 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1233 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1234 1235 /* Power management related routines */ 1236 int pci_save_state(struct pci_dev *dev); 1237 void pci_restore_state(struct pci_dev *dev); 1238 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1239 int pci_load_saved_state(struct pci_dev *dev, 1240 struct pci_saved_state *state); 1241 int pci_load_and_free_saved_state(struct pci_dev *dev, 1242 struct pci_saved_state **state); 1243 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1244 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1245 u16 cap); 1246 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1247 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1248 u16 cap, unsigned int size); 1249 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1250 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1251 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1252 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1253 void pci_pme_active(struct pci_dev *dev, bool enable); 1254 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1255 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1256 int pci_prepare_to_sleep(struct pci_dev *dev); 1257 int pci_back_from_sleep(struct pci_dev *dev); 1258 bool pci_dev_run_wake(struct pci_dev *dev); 1259 void pci_d3cold_enable(struct pci_dev *dev); 1260 void pci_d3cold_disable(struct pci_dev *dev); 1261 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1262 void pci_wakeup_bus(struct pci_bus *bus); 1263 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1264 1265 /* For use by arch with custom probe code */ 1266 void set_pcie_port_type(struct pci_dev *pdev); 1267 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1268 1269 /* Functions for PCI Hotplug drivers to use */ 1270 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1271 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1272 unsigned int pci_rescan_bus(struct pci_bus *bus); 1273 void pci_lock_rescan_remove(void); 1274 void pci_unlock_rescan_remove(void); 1275 1276 /* Vital Product Data routines */ 1277 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1278 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1279 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1280 1281 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1282 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1283 void pci_bus_assign_resources(const struct pci_bus *bus); 1284 void pci_bus_claim_resources(struct pci_bus *bus); 1285 void pci_bus_size_bridges(struct pci_bus *bus); 1286 int pci_claim_resource(struct pci_dev *, int); 1287 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1288 void pci_assign_unassigned_resources(void); 1289 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1290 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1291 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1292 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1293 void pdev_enable_device(struct pci_dev *); 1294 int pci_enable_resources(struct pci_dev *, int mask); 1295 void pci_assign_irq(struct pci_dev *dev); 1296 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1297 #define HAVE_PCI_REQ_REGIONS 2 1298 int __must_check pci_request_regions(struct pci_dev *, const char *); 1299 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1300 void pci_release_regions(struct pci_dev *); 1301 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1302 void pci_release_region(struct pci_dev *, int); 1303 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1304 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1305 void pci_release_selected_regions(struct pci_dev *, int); 1306 1307 /* drivers/pci/bus.c */ 1308 void pci_add_resource(struct list_head *resources, struct resource *res); 1309 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1310 resource_size_t offset); 1311 void pci_free_resource_list(struct list_head *resources); 1312 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1313 unsigned int flags); 1314 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1315 void pci_bus_remove_resources(struct pci_bus *bus); 1316 int devm_request_pci_bus_resources(struct device *dev, 1317 struct list_head *resources); 1318 1319 /* Temporary until new and working PCI SBR API in place */ 1320 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1321 1322 #define pci_bus_for_each_resource(bus, res, i) \ 1323 for (i = 0; \ 1324 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1325 i++) 1326 1327 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1328 struct resource *res, resource_size_t size, 1329 resource_size_t align, resource_size_t min, 1330 unsigned long type_mask, 1331 resource_size_t (*alignf)(void *, 1332 const struct resource *, 1333 resource_size_t, 1334 resource_size_t), 1335 void *alignf_data); 1336 1337 1338 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1339 resource_size_t size); 1340 unsigned long pci_address_to_pio(phys_addr_t addr); 1341 phys_addr_t pci_pio_to_address(unsigned long pio); 1342 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1343 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1344 phys_addr_t phys_addr); 1345 void pci_unmap_iospace(struct resource *res); 1346 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1347 resource_size_t offset, 1348 resource_size_t size); 1349 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1350 struct resource *res); 1351 1352 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1353 { 1354 struct pci_bus_region region; 1355 1356 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1357 return region.start; 1358 } 1359 1360 /* Proper probing supporting hot-pluggable devices */ 1361 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1362 const char *mod_name); 1363 1364 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1365 #define pci_register_driver(driver) \ 1366 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1367 1368 void pci_unregister_driver(struct pci_driver *dev); 1369 1370 /** 1371 * module_pci_driver() - Helper macro for registering a PCI driver 1372 * @__pci_driver: pci_driver struct 1373 * 1374 * Helper macro for PCI drivers which do not do anything special in module 1375 * init/exit. This eliminates a lot of boilerplate. Each module may only 1376 * use this macro once, and calling it replaces module_init() and module_exit() 1377 */ 1378 #define module_pci_driver(__pci_driver) \ 1379 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1380 1381 /** 1382 * builtin_pci_driver() - Helper macro for registering a PCI driver 1383 * @__pci_driver: pci_driver struct 1384 * 1385 * Helper macro for PCI drivers which do not do anything special in their 1386 * init code. This eliminates a lot of boilerplate. Each driver may only 1387 * use this macro once, and calling it replaces device_initcall(...) 1388 */ 1389 #define builtin_pci_driver(__pci_driver) \ 1390 builtin_driver(__pci_driver, pci_register_driver) 1391 1392 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1393 int pci_add_dynid(struct pci_driver *drv, 1394 unsigned int vendor, unsigned int device, 1395 unsigned int subvendor, unsigned int subdevice, 1396 unsigned int class, unsigned int class_mask, 1397 unsigned long driver_data); 1398 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1399 struct pci_dev *dev); 1400 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1401 int pass); 1402 1403 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1404 void *userdata); 1405 int pci_cfg_space_size(struct pci_dev *dev); 1406 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1407 void pci_setup_bridge(struct pci_bus *bus); 1408 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1409 unsigned long type); 1410 1411 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1412 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1413 1414 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1415 unsigned int command_bits, u32 flags); 1416 1417 /* 1418 * Virtual interrupts allow for more interrupts to be allocated 1419 * than the device has interrupts for. These are not programmed 1420 * into the device's MSI-X table and must be handled by some 1421 * other driver means. 1422 */ 1423 #define PCI_IRQ_VIRTUAL (1 << 4) 1424 1425 #define PCI_IRQ_ALL_TYPES \ 1426 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1427 1428 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1429 1430 #include <linux/dmapool.h> 1431 1432 #define pci_pool dma_pool 1433 #define pci_pool_create(name, pdev, size, align, allocation) \ 1434 dma_pool_create(name, &pdev->dev, size, align, allocation) 1435 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1436 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1437 #define pci_pool_zalloc(pool, flags, handle) \ 1438 dma_pool_zalloc(pool, flags, handle) 1439 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1440 1441 struct msix_entry { 1442 u32 vector; /* Kernel uses to write allocated vector */ 1443 u16 entry; /* Driver uses to specify entry, OS writes */ 1444 }; 1445 1446 #ifdef CONFIG_PCI_MSI 1447 int pci_msi_vec_count(struct pci_dev *dev); 1448 void pci_disable_msi(struct pci_dev *dev); 1449 int pci_msix_vec_count(struct pci_dev *dev); 1450 void pci_disable_msix(struct pci_dev *dev); 1451 void pci_restore_msi_state(struct pci_dev *dev); 1452 int pci_msi_enabled(void); 1453 int pci_enable_msi(struct pci_dev *dev); 1454 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1455 int minvec, int maxvec); 1456 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1457 struct msix_entry *entries, int nvec) 1458 { 1459 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1460 if (rc < 0) 1461 return rc; 1462 return 0; 1463 } 1464 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1465 unsigned int max_vecs, unsigned int flags, 1466 struct irq_affinity *affd); 1467 1468 void pci_free_irq_vectors(struct pci_dev *dev); 1469 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1470 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1471 1472 #else 1473 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1474 static inline void pci_disable_msi(struct pci_dev *dev) { } 1475 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1476 static inline void pci_disable_msix(struct pci_dev *dev) { } 1477 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1478 static inline int pci_msi_enabled(void) { return 0; } 1479 static inline int pci_enable_msi(struct pci_dev *dev) 1480 { return -ENOSYS; } 1481 static inline int pci_enable_msix_range(struct pci_dev *dev, 1482 struct msix_entry *entries, int minvec, int maxvec) 1483 { return -ENOSYS; } 1484 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1485 struct msix_entry *entries, int nvec) 1486 { return -ENOSYS; } 1487 1488 static inline int 1489 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1490 unsigned int max_vecs, unsigned int flags, 1491 struct irq_affinity *aff_desc) 1492 { 1493 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1494 return 1; 1495 return -ENOSPC; 1496 } 1497 1498 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1499 { 1500 } 1501 1502 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1503 { 1504 if (WARN_ON_ONCE(nr > 0)) 1505 return -EINVAL; 1506 return dev->irq; 1507 } 1508 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1509 int vec) 1510 { 1511 return cpu_possible_mask; 1512 } 1513 #endif 1514 1515 /** 1516 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1517 * @d: the INTx IRQ domain 1518 * @node: the DT node for the device whose interrupt we're translating 1519 * @intspec: the interrupt specifier data from the DT 1520 * @intsize: the number of entries in @intspec 1521 * @out_hwirq: pointer at which to write the hwirq number 1522 * @out_type: pointer at which to write the interrupt type 1523 * 1524 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1525 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1526 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1527 * INTx value to obtain the hwirq number. 1528 * 1529 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1530 */ 1531 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1532 struct device_node *node, 1533 const u32 *intspec, 1534 unsigned int intsize, 1535 unsigned long *out_hwirq, 1536 unsigned int *out_type) 1537 { 1538 const u32 intx = intspec[0]; 1539 1540 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1541 return -EINVAL; 1542 1543 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1544 return 0; 1545 } 1546 1547 #ifdef CONFIG_PCIEPORTBUS 1548 extern bool pcie_ports_disabled; 1549 extern bool pcie_ports_native; 1550 #else 1551 #define pcie_ports_disabled true 1552 #define pcie_ports_native false 1553 #endif 1554 1555 #define PCIE_LINK_STATE_L0S BIT(0) 1556 #define PCIE_LINK_STATE_L1 BIT(1) 1557 #define PCIE_LINK_STATE_CLKPM BIT(2) 1558 #define PCIE_LINK_STATE_L1_1 BIT(3) 1559 #define PCIE_LINK_STATE_L1_2 BIT(4) 1560 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1561 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1562 1563 #ifdef CONFIG_PCIEASPM 1564 int pci_disable_link_state(struct pci_dev *pdev, int state); 1565 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1566 void pcie_no_aspm(void); 1567 bool pcie_aspm_support_enabled(void); 1568 bool pcie_aspm_enabled(struct pci_dev *pdev); 1569 #else 1570 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1571 { return 0; } 1572 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1573 { return 0; } 1574 static inline void pcie_no_aspm(void) { } 1575 static inline bool pcie_aspm_support_enabled(void) { return false; } 1576 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1577 #endif 1578 1579 #ifdef CONFIG_PCIEAER 1580 bool pci_aer_available(void); 1581 #else 1582 static inline bool pci_aer_available(void) { return false; } 1583 #endif 1584 1585 bool pci_ats_disabled(void); 1586 1587 void pci_cfg_access_lock(struct pci_dev *dev); 1588 bool pci_cfg_access_trylock(struct pci_dev *dev); 1589 void pci_cfg_access_unlock(struct pci_dev *dev); 1590 1591 /* 1592 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1593 * a PCI domain is defined to be a set of PCI buses which share 1594 * configuration space. 1595 */ 1596 #ifdef CONFIG_PCI_DOMAINS 1597 extern int pci_domains_supported; 1598 #else 1599 enum { pci_domains_supported = 0 }; 1600 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1601 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1602 #endif /* CONFIG_PCI_DOMAINS */ 1603 1604 /* 1605 * Generic implementation for PCI domain support. If your 1606 * architecture does not need custom management of PCI 1607 * domains then this implementation will be used 1608 */ 1609 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1610 static inline int pci_domain_nr(struct pci_bus *bus) 1611 { 1612 return bus->domain_nr; 1613 } 1614 #ifdef CONFIG_ACPI 1615 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1616 #else 1617 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1618 { return 0; } 1619 #endif 1620 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1621 #endif 1622 1623 /* Some architectures require additional setup to direct VGA traffic */ 1624 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1625 unsigned int command_bits, u32 flags); 1626 void pci_register_set_vga_state(arch_set_vga_state_t func); 1627 1628 static inline int 1629 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1630 { 1631 return pci_request_selected_regions(pdev, 1632 pci_select_bars(pdev, IORESOURCE_IO), name); 1633 } 1634 1635 static inline void 1636 pci_release_io_regions(struct pci_dev *pdev) 1637 { 1638 return pci_release_selected_regions(pdev, 1639 pci_select_bars(pdev, IORESOURCE_IO)); 1640 } 1641 1642 static inline int 1643 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1644 { 1645 return pci_request_selected_regions(pdev, 1646 pci_select_bars(pdev, IORESOURCE_MEM), name); 1647 } 1648 1649 static inline void 1650 pci_release_mem_regions(struct pci_dev *pdev) 1651 { 1652 return pci_release_selected_regions(pdev, 1653 pci_select_bars(pdev, IORESOURCE_MEM)); 1654 } 1655 1656 #else /* CONFIG_PCI is not enabled */ 1657 1658 static inline void pci_set_flags(int flags) { } 1659 static inline void pci_add_flags(int flags) { } 1660 static inline void pci_clear_flags(int flags) { } 1661 static inline int pci_has_flag(int flag) { return 0; } 1662 1663 /* 1664 * If the system does not have PCI, clearly these return errors. Define 1665 * these as simple inline functions to avoid hair in drivers. 1666 */ 1667 #define _PCI_NOP(o, s, t) \ 1668 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1669 int where, t val) \ 1670 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1671 1672 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1673 _PCI_NOP(o, word, u16 x) \ 1674 _PCI_NOP(o, dword, u32 x) 1675 _PCI_NOP_ALL(read, *) 1676 _PCI_NOP_ALL(write,) 1677 1678 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1679 unsigned int device, 1680 struct pci_dev *from) 1681 { return NULL; } 1682 1683 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1684 unsigned int device, 1685 unsigned int ss_vendor, 1686 unsigned int ss_device, 1687 struct pci_dev *from) 1688 { return NULL; } 1689 1690 static inline struct pci_dev *pci_get_class(unsigned int class, 1691 struct pci_dev *from) 1692 { return NULL; } 1693 1694 #define pci_dev_present(ids) (0) 1695 #define no_pci_devices() (1) 1696 #define pci_dev_put(dev) do { } while (0) 1697 1698 static inline void pci_set_master(struct pci_dev *dev) { } 1699 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1700 static inline void pci_disable_device(struct pci_dev *dev) { } 1701 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1702 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1703 { return -EBUSY; } 1704 static inline int __pci_register_driver(struct pci_driver *drv, 1705 struct module *owner) 1706 { return 0; } 1707 static inline int pci_register_driver(struct pci_driver *drv) 1708 { return 0; } 1709 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1710 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1711 { return 0; } 1712 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1713 int cap) 1714 { return 0; } 1715 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1716 { return 0; } 1717 1718 static inline u64 pci_get_dsn(struct pci_dev *dev) 1719 { return 0; } 1720 1721 /* Power management related routines */ 1722 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1723 static inline void pci_restore_state(struct pci_dev *dev) { } 1724 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1725 { return 0; } 1726 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1727 { return 0; } 1728 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1729 pm_message_t state) 1730 { return PCI_D0; } 1731 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1732 int enable) 1733 { return 0; } 1734 1735 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1736 struct resource *res) 1737 { return NULL; } 1738 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1739 { return -EIO; } 1740 static inline void pci_release_regions(struct pci_dev *dev) { } 1741 1742 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1743 1744 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1745 { return NULL; } 1746 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1747 unsigned int devfn) 1748 { return NULL; } 1749 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1750 unsigned int bus, unsigned int devfn) 1751 { return NULL; } 1752 1753 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1754 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1755 1756 #define dev_is_pci(d) (false) 1757 #define dev_is_pf(d) (false) 1758 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1759 { return false; } 1760 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1761 struct device_node *node, 1762 const u32 *intspec, 1763 unsigned int intsize, 1764 unsigned long *out_hwirq, 1765 unsigned int *out_type) 1766 { return -EINVAL; } 1767 1768 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1769 struct pci_dev *dev) 1770 { return NULL; } 1771 static inline bool pci_ats_disabled(void) { return true; } 1772 1773 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1774 { 1775 return -EINVAL; 1776 } 1777 1778 static inline int 1779 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1780 unsigned int max_vecs, unsigned int flags, 1781 struct irq_affinity *aff_desc) 1782 { 1783 return -ENOSPC; 1784 } 1785 #endif /* CONFIG_PCI */ 1786 1787 static inline int 1788 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1789 unsigned int max_vecs, unsigned int flags) 1790 { 1791 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1792 NULL); 1793 } 1794 1795 /* Include architecture-dependent settings and functions */ 1796 1797 #include <asm/pci.h> 1798 1799 /* These two functions provide almost identical functionality. Depending 1800 * on the architecture, one will be implemented as a wrapper around the 1801 * other (in drivers/pci/mmap.c). 1802 * 1803 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1804 * is expected to be an offset within that region. 1805 * 1806 * pci_mmap_page_range() is the legacy architecture-specific interface, 1807 * which accepts a "user visible" resource address converted by 1808 * pci_resource_to_user(), as used in the legacy mmap() interface in 1809 * /proc/bus/pci/. 1810 */ 1811 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1812 struct vm_area_struct *vma, 1813 enum pci_mmap_state mmap_state, int write_combine); 1814 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1815 struct vm_area_struct *vma, 1816 enum pci_mmap_state mmap_state, int write_combine); 1817 1818 #ifndef arch_can_pci_mmap_wc 1819 #define arch_can_pci_mmap_wc() 0 1820 #endif 1821 1822 #ifndef arch_can_pci_mmap_io 1823 #define arch_can_pci_mmap_io() 0 1824 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1825 #else 1826 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1827 #endif 1828 1829 #ifndef pci_root_bus_fwnode 1830 #define pci_root_bus_fwnode(bus) NULL 1831 #endif 1832 1833 /* 1834 * These helpers provide future and backwards compatibility 1835 * for accessing popular PCI BAR info 1836 */ 1837 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1838 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1839 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1840 #define pci_resource_len(dev,bar) \ 1841 ((pci_resource_start((dev), (bar)) == 0 && \ 1842 pci_resource_end((dev), (bar)) == \ 1843 pci_resource_start((dev), (bar))) ? 0 : \ 1844 \ 1845 (pci_resource_end((dev), (bar)) - \ 1846 pci_resource_start((dev), (bar)) + 1)) 1847 1848 /* 1849 * Similar to the helpers above, these manipulate per-pci_dev 1850 * driver-specific data. They are really just a wrapper around 1851 * the generic device structure functions of these calls. 1852 */ 1853 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1854 { 1855 return dev_get_drvdata(&pdev->dev); 1856 } 1857 1858 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1859 { 1860 dev_set_drvdata(&pdev->dev, data); 1861 } 1862 1863 static inline const char *pci_name(const struct pci_dev *pdev) 1864 { 1865 return dev_name(&pdev->dev); 1866 } 1867 1868 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1869 const struct resource *rsrc, 1870 resource_size_t *start, resource_size_t *end); 1871 1872 /* 1873 * The world is not perfect and supplies us with broken PCI devices. 1874 * For at least a part of these bugs we need a work-around, so both 1875 * generic (drivers/pci/quirks.c) and per-architecture code can define 1876 * fixup hooks to be called for particular buggy devices. 1877 */ 1878 1879 struct pci_fixup { 1880 u16 vendor; /* Or PCI_ANY_ID */ 1881 u16 device; /* Or PCI_ANY_ID */ 1882 u32 class; /* Or PCI_ANY_ID */ 1883 unsigned int class_shift; /* should be 0, 8, 16 */ 1884 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1885 int hook_offset; 1886 #else 1887 void (*hook)(struct pci_dev *dev); 1888 #endif 1889 }; 1890 1891 enum pci_fixup_pass { 1892 pci_fixup_early, /* Before probing BARs */ 1893 pci_fixup_header, /* After reading configuration header */ 1894 pci_fixup_final, /* Final phase of device fixups */ 1895 pci_fixup_enable, /* pci_enable_device() time */ 1896 pci_fixup_resume, /* pci_device_resume() */ 1897 pci_fixup_suspend, /* pci_device_suspend() */ 1898 pci_fixup_resume_early, /* pci_device_resume_early() */ 1899 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1900 }; 1901 1902 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1903 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1904 class_shift, hook) \ 1905 __ADDRESSABLE(hook) \ 1906 asm(".section " #sec ", \"a\" \n" \ 1907 ".balign 16 \n" \ 1908 ".short " #vendor ", " #device " \n" \ 1909 ".long " #class ", " #class_shift " \n" \ 1910 ".long " #hook " - . \n" \ 1911 ".previous \n"); 1912 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1913 class_shift, hook) \ 1914 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1915 class_shift, hook) 1916 #else 1917 /* Anonymous variables would be nice... */ 1918 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1919 class_shift, hook) \ 1920 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1921 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1922 = { vendor, device, class, class_shift, hook }; 1923 #endif 1924 1925 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1926 class_shift, hook) \ 1927 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1928 hook, vendor, device, class, class_shift, hook) 1929 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1930 class_shift, hook) \ 1931 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1932 hook, vendor, device, class, class_shift, hook) 1933 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1934 class_shift, hook) \ 1935 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1936 hook, vendor, device, class, class_shift, hook) 1937 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1938 class_shift, hook) \ 1939 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1940 hook, vendor, device, class, class_shift, hook) 1941 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1942 class_shift, hook) \ 1943 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1944 resume##hook, vendor, device, class, class_shift, hook) 1945 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1946 class_shift, hook) \ 1947 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1948 resume_early##hook, vendor, device, class, class_shift, hook) 1949 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1950 class_shift, hook) \ 1951 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1952 suspend##hook, vendor, device, class, class_shift, hook) 1953 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1954 class_shift, hook) \ 1955 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1956 suspend_late##hook, vendor, device, class, class_shift, hook) 1957 1958 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1959 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1960 hook, vendor, device, PCI_ANY_ID, 0, hook) 1961 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1962 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1963 hook, vendor, device, PCI_ANY_ID, 0, hook) 1964 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1965 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1966 hook, vendor, device, PCI_ANY_ID, 0, hook) 1967 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1968 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1969 hook, vendor, device, PCI_ANY_ID, 0, hook) 1970 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1971 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1972 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1973 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1974 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1975 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1976 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1977 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1978 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1979 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1980 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1981 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1982 1983 #ifdef CONFIG_PCI_QUIRKS 1984 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1985 #else 1986 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1987 struct pci_dev *dev) { } 1988 #endif 1989 1990 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1991 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1992 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1993 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1994 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1995 const char *name); 1996 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1997 1998 extern int pci_pci_problems; 1999 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2000 #define PCIPCI_TRITON 2 2001 #define PCIPCI_NATOMA 4 2002 #define PCIPCI_VIAETBF 8 2003 #define PCIPCI_VSFX 16 2004 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2005 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2006 2007 extern unsigned long pci_cardbus_io_size; 2008 extern unsigned long pci_cardbus_mem_size; 2009 extern u8 pci_dfl_cache_line_size; 2010 extern u8 pci_cache_line_size; 2011 2012 /* Architecture-specific versions may override these (weak) */ 2013 void pcibios_disable_device(struct pci_dev *dev); 2014 void pcibios_set_master(struct pci_dev *dev); 2015 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2016 enum pcie_reset_state state); 2017 int pcibios_add_device(struct pci_dev *dev); 2018 void pcibios_release_device(struct pci_dev *dev); 2019 #ifdef CONFIG_PCI 2020 void pcibios_penalize_isa_irq(int irq, int active); 2021 #else 2022 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2023 #endif 2024 int pcibios_alloc_irq(struct pci_dev *dev); 2025 void pcibios_free_irq(struct pci_dev *dev); 2026 resource_size_t pcibios_default_alignment(void); 2027 2028 #ifdef CONFIG_HIBERNATE_CALLBACKS 2029 extern struct dev_pm_ops pcibios_pm_ops; 2030 #endif 2031 2032 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2033 void __init pci_mmcfg_early_init(void); 2034 void __init pci_mmcfg_late_init(void); 2035 #else 2036 static inline void pci_mmcfg_early_init(void) { } 2037 static inline void pci_mmcfg_late_init(void) { } 2038 #endif 2039 2040 int pci_ext_cfg_avail(void); 2041 2042 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2043 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2044 2045 #ifdef CONFIG_PCI_IOV 2046 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2047 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2048 2049 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2050 void pci_disable_sriov(struct pci_dev *dev); 2051 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2052 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2053 int pci_num_vf(struct pci_dev *dev); 2054 int pci_vfs_assigned(struct pci_dev *dev); 2055 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2056 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2057 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2058 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2059 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2060 2061 /* Arch may override these (weak) */ 2062 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2063 int pcibios_sriov_disable(struct pci_dev *pdev); 2064 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2065 #else 2066 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2067 { 2068 return -ENOSYS; 2069 } 2070 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2071 { 2072 return -ENOSYS; 2073 } 2074 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2075 { return -ENODEV; } 2076 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2077 { 2078 return -ENOSYS; 2079 } 2080 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2081 int id) { } 2082 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2083 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2084 static inline int pci_vfs_assigned(struct pci_dev *dev) 2085 { return 0; } 2086 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2087 { return 0; } 2088 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2089 { return 0; } 2090 #define pci_sriov_configure_simple NULL 2091 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2092 { return 0; } 2093 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2094 #endif 2095 2096 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2097 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2098 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2099 #endif 2100 2101 /** 2102 * pci_pcie_cap - get the saved PCIe capability offset 2103 * @dev: PCI device 2104 * 2105 * PCIe capability offset is calculated at PCI device initialization 2106 * time and saved in the data structure. This function returns saved 2107 * PCIe capability offset. Using this instead of pci_find_capability() 2108 * reduces unnecessary search in the PCI configuration space. If you 2109 * need to calculate PCIe capability offset from raw device for some 2110 * reasons, please use pci_find_capability() instead. 2111 */ 2112 static inline int pci_pcie_cap(struct pci_dev *dev) 2113 { 2114 return dev->pcie_cap; 2115 } 2116 2117 /** 2118 * pci_is_pcie - check if the PCI device is PCI Express capable 2119 * @dev: PCI device 2120 * 2121 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2122 */ 2123 static inline bool pci_is_pcie(struct pci_dev *dev) 2124 { 2125 return pci_pcie_cap(dev); 2126 } 2127 2128 /** 2129 * pcie_caps_reg - get the PCIe Capabilities Register 2130 * @dev: PCI device 2131 */ 2132 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2133 { 2134 return dev->pcie_flags_reg; 2135 } 2136 2137 /** 2138 * pci_pcie_type - get the PCIe device/port type 2139 * @dev: PCI device 2140 */ 2141 static inline int pci_pcie_type(const struct pci_dev *dev) 2142 { 2143 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2144 } 2145 2146 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2147 { 2148 while (1) { 2149 if (!pci_is_pcie(dev)) 2150 break; 2151 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2152 return dev; 2153 if (!dev->bus->self) 2154 break; 2155 dev = dev->bus->self; 2156 } 2157 return NULL; 2158 } 2159 2160 void pci_request_acs(void); 2161 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2162 bool pci_acs_path_enabled(struct pci_dev *start, 2163 struct pci_dev *end, u16 acs_flags); 2164 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2165 2166 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2167 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2168 2169 /* Large Resource Data Type Tag Item Names */ 2170 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2171 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2172 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2173 2174 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2175 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2176 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2177 2178 /* Small Resource Data Type Tag Item Names */ 2179 #define PCI_VPD_STIN_END 0x0f /* End */ 2180 2181 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2182 2183 #define PCI_VPD_SRDT_TIN_MASK 0x78 2184 #define PCI_VPD_SRDT_LEN_MASK 0x07 2185 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2186 2187 #define PCI_VPD_LRDT_TAG_SIZE 3 2188 #define PCI_VPD_SRDT_TAG_SIZE 1 2189 2190 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2191 2192 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2193 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2194 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2195 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2196 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2197 2198 /** 2199 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2200 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2201 * 2202 * Returns the extracted Large Resource Data Type length. 2203 */ 2204 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2205 { 2206 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2207 } 2208 2209 /** 2210 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2211 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2212 * 2213 * Returns the extracted Large Resource Data Type Tag item. 2214 */ 2215 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2216 { 2217 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2218 } 2219 2220 /** 2221 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2222 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2223 * 2224 * Returns the extracted Small Resource Data Type length. 2225 */ 2226 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2227 { 2228 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2229 } 2230 2231 /** 2232 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2233 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2234 * 2235 * Returns the extracted Small Resource Data Type Tag Item. 2236 */ 2237 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2238 { 2239 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2240 } 2241 2242 /** 2243 * pci_vpd_info_field_size - Extracts the information field length 2244 * @info_field: Pointer to the beginning of an information field header 2245 * 2246 * Returns the extracted information field length. 2247 */ 2248 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2249 { 2250 return info_field[2]; 2251 } 2252 2253 /** 2254 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2255 * @buf: Pointer to buffered vpd data 2256 * @off: The offset into the buffer at which to begin the search 2257 * @len: The length of the vpd buffer 2258 * @rdt: The Resource Data Type to search for 2259 * 2260 * Returns the index where the Resource Data Type was found or 2261 * -ENOENT otherwise. 2262 */ 2263 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2264 2265 /** 2266 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2267 * @buf: Pointer to buffered vpd data 2268 * @off: The offset into the buffer at which to begin the search 2269 * @len: The length of the buffer area, relative to off, in which to search 2270 * @kw: The keyword to search for 2271 * 2272 * Returns the index where the information field keyword was found or 2273 * -ENOENT otherwise. 2274 */ 2275 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2276 unsigned int len, const char *kw); 2277 2278 /* PCI <-> OF binding helpers */ 2279 #ifdef CONFIG_OF 2280 struct device_node; 2281 struct irq_domain; 2282 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2283 int pci_parse_request_of_pci_ranges(struct device *dev, 2284 struct list_head *resources, 2285 struct list_head *ib_resources, 2286 struct resource **bus_range); 2287 2288 /* Arch may override this (weak) */ 2289 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2290 2291 #else /* CONFIG_OF */ 2292 static inline struct irq_domain * 2293 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2294 static inline int 2295 pci_parse_request_of_pci_ranges(struct device *dev, 2296 struct list_head *resources, 2297 struct list_head *ib_resources, 2298 struct resource **bus_range) 2299 { 2300 return -EINVAL; 2301 } 2302 #endif /* CONFIG_OF */ 2303 2304 static inline struct device_node * 2305 pci_device_to_OF_node(const struct pci_dev *pdev) 2306 { 2307 return pdev ? pdev->dev.of_node : NULL; 2308 } 2309 2310 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2311 { 2312 return bus ? bus->dev.of_node : NULL; 2313 } 2314 2315 #ifdef CONFIG_ACPI 2316 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2317 2318 void 2319 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2320 bool pci_pr3_present(struct pci_dev *pdev); 2321 #else 2322 static inline struct irq_domain * 2323 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2324 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2325 #endif 2326 2327 #ifdef CONFIG_EEH 2328 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2329 { 2330 return pdev->dev.archdata.edev; 2331 } 2332 #endif 2333 2334 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2335 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2336 int pci_for_each_dma_alias(struct pci_dev *pdev, 2337 int (*fn)(struct pci_dev *pdev, 2338 u16 alias, void *data), void *data); 2339 2340 /* Helper functions for operation of device flag */ 2341 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2342 { 2343 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2344 } 2345 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2346 { 2347 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2348 } 2349 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2350 { 2351 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2352 } 2353 2354 /** 2355 * pci_ari_enabled - query ARI forwarding status 2356 * @bus: the PCI bus 2357 * 2358 * Returns true if ARI forwarding is enabled. 2359 */ 2360 static inline bool pci_ari_enabled(struct pci_bus *bus) 2361 { 2362 return bus->self && bus->self->ari_enabled; 2363 } 2364 2365 /** 2366 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2367 * @pdev: PCI device to check 2368 * 2369 * Walk upwards from @pdev and check for each encountered bridge if it's part 2370 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2371 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2372 */ 2373 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2374 { 2375 struct pci_dev *parent = pdev; 2376 2377 if (pdev->is_thunderbolt) 2378 return true; 2379 2380 while ((parent = pci_upstream_bridge(parent))) 2381 if (parent->is_thunderbolt) 2382 return true; 2383 2384 return false; 2385 } 2386 2387 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2388 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2389 #endif 2390 2391 /* Provide the legacy pci_dma_* API */ 2392 #include <linux/pci-dma-compat.h> 2393 2394 #define pci_printk(level, pdev, fmt, arg...) \ 2395 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2396 2397 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2398 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2399 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2400 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2401 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2402 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2403 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2404 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2405 2406 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2407 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2408 2409 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2410 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2411 2412 #define pci_WARN(pdev, condition, fmt, arg...) \ 2413 WARN(condition, "%s %s: " fmt, \ 2414 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2415 2416 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2417 WARN_ONCE(condition, "%s %s: " fmt, \ 2418 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2419 2420 #endif /* LINUX_PCI_H */ 2421