1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 #include <linux/args.h> 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <linux/msi_api.h> 42 #include <uapi/linux/pci.h> 43 44 #include <linux/pci_ids.h> 45 46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 47 PCI_STATUS_SIG_SYSTEM_ERROR | \ 48 PCI_STATUS_REC_MASTER_ABORT | \ 49 PCI_STATUS_REC_TARGET_ABORT | \ 50 PCI_STATUS_SIG_TARGET_ABORT | \ 51 PCI_STATUS_PARITY) 52 53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 54 #define PCI_NUM_RESET_METHODS 8 55 56 #define PCI_RESET_PROBE true 57 #define PCI_RESET_DO_RESET false 58 59 /* 60 * The PCI interface treats multi-function devices as independent 61 * devices. The slot/function address of each device is encoded 62 * in a single byte as follows: 63 * 64 * 7:3 = slot 65 * 2:0 = function 66 * 67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 68 * In the interest of not exposing interfaces to user-space unnecessarily, 69 * the following kernel-only defines are being added here. 70 */ 71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 74 75 /* pci_slot represents a physical slot */ 76 struct pci_slot { 77 struct pci_bus *bus; /* Bus this slot is on */ 78 struct list_head list; /* Node in list of slots */ 79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 81 struct kobject kobj; 82 }; 83 84 static inline const char *pci_slot_name(const struct pci_slot *slot) 85 { 86 return kobject_name(&slot->kobj); 87 } 88 89 /* File state for mmap()s on /proc/bus/pci/X/Y */ 90 enum pci_mmap_state { 91 pci_mmap_io, 92 pci_mmap_mem 93 }; 94 95 /* For PCI devices, the region numbers are assigned this way: */ 96 enum { 97 /* #0-5: standard PCI resources */ 98 PCI_STD_RESOURCES, 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 100 101 /* #6: expansion ROM resource */ 102 PCI_ROM_RESOURCE, 103 104 /* Device-specific resources */ 105 #ifdef CONFIG_PCI_IOV 106 PCI_IOV_RESOURCES, 107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 108 #endif 109 110 /* PCI-to-PCI (P2P) bridge windows */ 111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 114 115 /* CardBus bridge windows */ 116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 120 121 /* Total number of bridge resources for P2P and CardBus */ 122 #define PCI_BRIDGE_RESOURCE_NUM 4 123 124 /* Resources assigned to buses behind the bridge */ 125 PCI_BRIDGE_RESOURCES, 126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 127 PCI_BRIDGE_RESOURCE_NUM - 1, 128 129 /* Total resources associated with a PCI device */ 130 PCI_NUM_RESOURCES, 131 132 /* Preserve this for compatibility */ 133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 134 }; 135 136 /** 137 * enum pci_interrupt_pin - PCI INTx interrupt values 138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 139 * @PCI_INTERRUPT_INTA: PCI INTA pin 140 * @PCI_INTERRUPT_INTB: PCI INTB pin 141 * @PCI_INTERRUPT_INTC: PCI INTC pin 142 * @PCI_INTERRUPT_INTD: PCI INTD pin 143 * 144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 145 * PCI_INTERRUPT_PIN register. 146 */ 147 enum pci_interrupt_pin { 148 PCI_INTERRUPT_UNKNOWN, 149 PCI_INTERRUPT_INTA, 150 PCI_INTERRUPT_INTB, 151 PCI_INTERRUPT_INTC, 152 PCI_INTERRUPT_INTD, 153 }; 154 155 /* The number of legacy PCI INTx interrupts */ 156 #define PCI_NUM_INTX 4 157 158 /* 159 * Reading from a device that doesn't respond typically returns ~0. A 160 * successful read from a device may also return ~0, so you need additional 161 * information to reliably identify errors. 162 */ 163 #define PCI_ERROR_RESPONSE (~0ULL) 164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 166 167 /* 168 * pci_power_t values must match the bits in the Capabilities PME_Support 169 * and Control/Status PowerState fields in the Power Management capability. 170 */ 171 typedef int __bitwise pci_power_t; 172 173 #define PCI_D0 ((pci_power_t __force) 0) 174 #define PCI_D1 ((pci_power_t __force) 1) 175 #define PCI_D2 ((pci_power_t __force) 2) 176 #define PCI_D3hot ((pci_power_t __force) 3) 177 #define PCI_D3cold ((pci_power_t __force) 4) 178 #define PCI_UNKNOWN ((pci_power_t __force) 5) 179 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 180 181 /* Remember to update this when the list above changes! */ 182 extern const char *pci_power_names[]; 183 184 static inline const char *pci_power_name(pci_power_t state) 185 { 186 return pci_power_names[1 + (__force int) state]; 187 } 188 189 /** 190 * typedef pci_channel_state_t 191 * 192 * The pci_channel state describes connectivity between the CPU and 193 * the PCI device. If some PCI bus between here and the PCI device 194 * has crashed or locked up, this info is reflected here. 195 */ 196 typedef unsigned int __bitwise pci_channel_state_t; 197 198 enum { 199 /* I/O channel is in normal state */ 200 pci_channel_io_normal = (__force pci_channel_state_t) 1, 201 202 /* I/O to channel is blocked */ 203 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 204 205 /* PCI card is dead */ 206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 207 }; 208 209 typedef unsigned int __bitwise pcie_reset_state_t; 210 211 enum pcie_reset_state { 212 /* Reset is NOT asserted (Use to deassert reset) */ 213 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 214 215 /* Use #PERST to reset PCIe device */ 216 pcie_warm_reset = (__force pcie_reset_state_t) 2, 217 218 /* Use PCIe Hot Reset to reset device */ 219 pcie_hot_reset = (__force pcie_reset_state_t) 3 220 }; 221 222 typedef unsigned short __bitwise pci_dev_flags_t; 223 enum pci_dev_flags { 224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 226 /* Device configuration is irrevocably lost if disabled into D3 */ 227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 228 /* Provide indication device is assigned by a Virtual Machine Manager */ 229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 230 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 234 /* Do not use bus resets for device */ 235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 236 /* Do not use PM reset even if device advertises NoSoftRst- */ 237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 238 /* Get VPD from function 0 VPD */ 239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 240 /* A non-root bridge where translation occurs, stop alias search here */ 241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 242 /* Do not use FLR even if device advertises PCI_AF_CAP */ 243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 244 /* Don't use Relaxed Ordering for TLPs directed at this device */ 245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 246 /* Device does honor MSI masking despite saying otherwise */ 247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 248 }; 249 250 enum pci_irq_reroute_variant { 251 INTEL_IRQ_REROUTE_VARIANT = 1, 252 MAX_IRQ_REROUTE_VARIANTS = 3 253 }; 254 255 typedef unsigned short __bitwise pci_bus_flags_t; 256 enum pci_bus_flags { 257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 261 }; 262 263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 264 enum pcie_link_width { 265 PCIE_LNK_WIDTH_RESRV = 0x00, 266 PCIE_LNK_X1 = 0x01, 267 PCIE_LNK_X2 = 0x02, 268 PCIE_LNK_X4 = 0x04, 269 PCIE_LNK_X8 = 0x08, 270 PCIE_LNK_X12 = 0x0c, 271 PCIE_LNK_X16 = 0x10, 272 PCIE_LNK_X32 = 0x20, 273 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 274 }; 275 276 /* See matching string table in pci_speed_string() */ 277 enum pci_bus_speed { 278 PCI_SPEED_33MHz = 0x00, 279 PCI_SPEED_66MHz = 0x01, 280 PCI_SPEED_66MHz_PCIX = 0x02, 281 PCI_SPEED_100MHz_PCIX = 0x03, 282 PCI_SPEED_133MHz_PCIX = 0x04, 283 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 284 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 285 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 286 PCI_SPEED_66MHz_PCIX_266 = 0x09, 287 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 288 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 289 AGP_UNKNOWN = 0x0c, 290 AGP_1X = 0x0d, 291 AGP_2X = 0x0e, 292 AGP_4X = 0x0f, 293 AGP_8X = 0x10, 294 PCI_SPEED_66MHz_PCIX_533 = 0x11, 295 PCI_SPEED_100MHz_PCIX_533 = 0x12, 296 PCI_SPEED_133MHz_PCIX_533 = 0x13, 297 PCIE_SPEED_2_5GT = 0x14, 298 PCIE_SPEED_5_0GT = 0x15, 299 PCIE_SPEED_8_0GT = 0x16, 300 PCIE_SPEED_16_0GT = 0x17, 301 PCIE_SPEED_32_0GT = 0x18, 302 PCIE_SPEED_64_0GT = 0x19, 303 PCI_SPEED_UNKNOWN = 0xff, 304 }; 305 306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 308 309 struct pci_vpd { 310 struct mutex lock; 311 unsigned int len; 312 u8 cap; 313 }; 314 315 struct irq_affinity; 316 struct pcie_link_state; 317 struct pci_sriov; 318 struct pci_p2pdma; 319 struct rcec_ea; 320 321 /* The pci_dev structure describes PCI devices */ 322 struct pci_dev { 323 struct list_head bus_list; /* Node in per-bus list */ 324 struct pci_bus *bus; /* Bus this device is on */ 325 struct pci_bus *subordinate; /* Bus this device bridges to */ 326 327 void *sysdata; /* Hook for sys-specific extension */ 328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 329 struct pci_slot *slot; /* Physical slot this device is in */ 330 331 unsigned int devfn; /* Encoded device & function index */ 332 unsigned short vendor; 333 unsigned short device; 334 unsigned short subsystem_vendor; 335 unsigned short subsystem_device; 336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 337 u8 revision; /* PCI revision, low byte of class word */ 338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 339 #ifdef CONFIG_PCIEAER 340 u16 aer_cap; /* AER capability offset */ 341 struct aer_stats *aer_stats; /* AER stats for this device */ 342 #endif 343 #ifdef CONFIG_PCIEPORTBUS 344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 345 struct pci_dev *rcec; /* Associated RCEC device */ 346 #endif 347 u32 devcap; /* PCIe Device Capabilities */ 348 u8 pcie_cap; /* PCIe capability offset */ 349 u8 msi_cap; /* MSI capability offset */ 350 u8 msix_cap; /* MSI-X capability offset */ 351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 352 u8 rom_base_reg; /* Config register controlling ROM */ 353 u8 pin; /* Interrupt pin this device uses */ 354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 356 357 struct pci_driver *driver; /* Driver bound to this device */ 358 u64 dma_mask; /* Mask of the bits of bus address this 359 device implements. Normally this is 360 0xffffffff. You only need to change 361 this if your device has broken DMA 362 or supports 64-bit transfers. */ 363 364 struct device_dma_parameters dma_parms; 365 366 pci_power_t current_state; /* Current operating state. In ACPI, 367 this is D0-D3, D0 being fully 368 functional, and D3 being off. */ 369 u8 pm_cap; /* PM capability offset */ 370 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 371 unsigned int pme_support:5; /* Bitmask of states from which PME# 372 can be generated */ 373 unsigned int pme_poll:1; /* Poll device's PME status bit */ 374 unsigned int d1_support:1; /* Low power state D1 is supported */ 375 unsigned int d2_support:1; /* Low power state D2 is supported */ 376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 377 unsigned int no_d3cold:1; /* D3cold is forbidden */ 378 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 381 decoding during BAR sizing */ 382 unsigned int wakeup_prepared:1; 383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 386 controlled exclusively by 387 user sysfs */ 388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 389 bit manually */ 390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 392 393 u16 l1ss; /* L1SS Capability pointer */ 394 #ifdef CONFIG_PCIEASPM 395 struct pcie_link_state *link_state; /* ASPM link state */ 396 unsigned int ltr_path:1; /* Latency Tolerance Reporting 397 supported from root to here */ 398 #endif 399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 401 402 pci_channel_state_t error_state; /* Current connectivity state */ 403 struct device dev; /* Generic device interface */ 404 405 int cfg_size; /* Size of config space */ 406 407 /* 408 * Instead of touching interrupt line and base address registers 409 * directly, use the values stored here. They might be different! 410 */ 411 unsigned int irq; 412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ 414 415 bool match_driver; /* Skip attaching driver */ 416 struct lock_class_key cfg_access_key; 417 struct lockdep_map cfg_access_lock; 418 419 unsigned int transparent:1; /* Subtractive decode bridge */ 420 unsigned int io_window:1; /* Bridge has I/O window */ 421 unsigned int pref_window:1; /* Bridge has pref mem window */ 422 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 423 unsigned int multifunction:1; /* Multi-function device */ 424 425 unsigned int is_busmaster:1; /* Is busmaster */ 426 unsigned int no_msi:1; /* May not use MSI */ 427 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 428 unsigned int block_cfg_access:1; /* Config space access blocked */ 429 unsigned int broken_parity_status:1; /* Generates false positive parity */ 430 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 431 unsigned int msi_enabled:1; 432 unsigned int msix_enabled:1; 433 unsigned int ari_enabled:1; /* ARI forwarding */ 434 unsigned int ats_enabled:1; /* Address Translation Svc */ 435 unsigned int pasid_enabled:1; /* Process Address Space ID */ 436 unsigned int pri_enabled:1; /* Page Request Interface */ 437 unsigned int is_managed:1; /* Managed via devres */ 438 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 439 unsigned int needs_freset:1; /* Requires fundamental reset */ 440 unsigned int state_saved:1; 441 unsigned int is_physfn:1; 442 unsigned int is_virtfn:1; 443 unsigned int is_hotplug_bridge:1; 444 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 445 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 446 /* 447 * Devices marked being untrusted are the ones that can potentially 448 * execute DMA attacks and similar. They are typically connected 449 * through external ports such as Thunderbolt but not limited to 450 * that. When an IOMMU is enabled they should be getting full 451 * mappings to make sure they cannot access arbitrary memory. 452 */ 453 unsigned int untrusted:1; 454 /* 455 * Info from the platform, e.g., ACPI or device tree, may mark a 456 * device as "external-facing". An external-facing device is 457 * itself internal but devices downstream from it are external. 458 */ 459 unsigned int external_facing:1; 460 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 461 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 462 unsigned int irq_managed:1; 463 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 464 unsigned int is_probed:1; /* Device probing in progress */ 465 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 466 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 467 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 468 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 469 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ 470 pci_dev_flags_t dev_flags; 471 atomic_t enable_cnt; /* pci_enable_device has been called */ 472 473 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */ 474 u32 saved_config_space[16]; /* Config space saved at suspend time */ 475 struct hlist_head saved_cap_space; 476 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 477 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 478 479 #ifdef CONFIG_HOTPLUG_PCI_PCIE 480 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 481 #endif 482 #ifdef CONFIG_PCIE_PTM 483 u16 ptm_cap; /* PTM Capability */ 484 unsigned int ptm_root:1; 485 unsigned int ptm_enabled:1; 486 u8 ptm_granularity; 487 #endif 488 #ifdef CONFIG_PCI_MSI 489 void __iomem *msix_base; 490 raw_spinlock_t msi_lock; 491 #endif 492 struct pci_vpd vpd; 493 #ifdef CONFIG_PCIE_DPC 494 u16 dpc_cap; 495 unsigned int dpc_rp_extensions:1; 496 u8 dpc_rp_log_size; 497 #endif 498 #ifdef CONFIG_PCI_ATS 499 union { 500 struct pci_sriov *sriov; /* PF: SR-IOV info */ 501 struct pci_dev *physfn; /* VF: related PF */ 502 }; 503 u16 ats_cap; /* ATS Capability offset */ 504 u8 ats_stu; /* ATS Smallest Translation Unit */ 505 #endif 506 #ifdef CONFIG_PCI_PRI 507 u16 pri_cap; /* PRI Capability offset */ 508 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 509 unsigned int pasid_required:1; /* PRG Response PASID Required */ 510 #endif 511 #ifdef CONFIG_PCI_PASID 512 u16 pasid_cap; /* PASID Capability offset */ 513 u16 pasid_features; 514 #endif 515 #ifdef CONFIG_PCI_P2PDMA 516 struct pci_p2pdma __rcu *p2pdma; 517 #endif 518 #ifdef CONFIG_PCI_DOE 519 struct xarray doe_mbs; /* Data Object Exchange mailboxes */ 520 #endif 521 u16 acs_cap; /* ACS Capability offset */ 522 phys_addr_t rom; /* Physical address if not from BAR */ 523 size_t romlen; /* Length if not from BAR */ 524 /* 525 * Driver name to force a match. Do not set directly, because core 526 * frees it. Use driver_set_override() to set or clear it. 527 */ 528 const char *driver_override; 529 530 unsigned long priv_flags; /* Private flags for the PCI driver */ 531 532 /* These methods index pci_reset_fn_methods[] */ 533 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 534 }; 535 536 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 537 { 538 #ifdef CONFIG_PCI_IOV 539 if (dev->is_virtfn) 540 dev = dev->physfn; 541 #endif 542 return dev; 543 } 544 545 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 546 547 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 548 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 549 550 static inline int pci_channel_offline(struct pci_dev *pdev) 551 { 552 return (pdev->error_state != pci_channel_io_normal); 553 } 554 555 /* 556 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 557 * Group number is limited to a 16-bit value, therefore (int)-1 is 558 * not a valid PCI domain number, and can be used as a sentinel 559 * value indicating ->domain_nr is not set by the driver (and 560 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 561 * pci_bus_find_domain_nr()). 562 */ 563 #define PCI_DOMAIN_NR_NOT_SET (-1) 564 565 struct pci_host_bridge { 566 struct device dev; 567 struct pci_bus *bus; /* Root bus */ 568 struct pci_ops *ops; 569 struct pci_ops *child_ops; 570 void *sysdata; 571 int busnr; 572 int domain_nr; 573 struct list_head windows; /* resource_entry */ 574 struct list_head dma_ranges; /* dma ranges resource list */ 575 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 576 int (*map_irq)(const struct pci_dev *, u8, u8); 577 void (*release_fn)(struct pci_host_bridge *); 578 void *release_data; 579 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 580 unsigned int no_ext_tags:1; /* No Extended Tags */ 581 unsigned int no_inc_mrrs:1; /* No Increase MRRS */ 582 unsigned int native_aer:1; /* OS may use PCIe AER */ 583 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 584 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 585 unsigned int native_pme:1; /* OS may use PCIe PME */ 586 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 587 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 588 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ 589 unsigned int preserve_config:1; /* Preserve FW resource setup */ 590 unsigned int size_windows:1; /* Enable root bus sizing */ 591 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 592 593 /* Resource alignment requirements */ 594 resource_size_t (*align_resource)(struct pci_dev *dev, 595 const struct resource *res, 596 resource_size_t start, 597 resource_size_t size, 598 resource_size_t align); 599 unsigned long private[] ____cacheline_aligned; 600 }; 601 602 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 603 604 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 605 { 606 return (void *)bridge->private; 607 } 608 609 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 610 { 611 return container_of(priv, struct pci_host_bridge, private); 612 } 613 614 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 615 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 616 size_t priv); 617 void pci_free_host_bridge(struct pci_host_bridge *bridge); 618 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 619 620 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 621 void (*release_fn)(struct pci_host_bridge *), 622 void *release_data); 623 624 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 625 626 /* 627 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 628 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 629 * buses below host bridges or subtractive decode bridges) go in the list. 630 * Use pci_bus_for_each_resource() to iterate through all the resources. 631 */ 632 633 /* 634 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 635 * and there's no way to program the bridge with the details of the window. 636 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 637 * decode bit set, because they are explicit and can be programmed with _SRS. 638 */ 639 #define PCI_SUBTRACTIVE_DECODE 0x1 640 641 struct pci_bus_resource { 642 struct list_head list; 643 struct resource *res; 644 unsigned int flags; 645 }; 646 647 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 648 649 struct pci_bus { 650 struct list_head node; /* Node in list of buses */ 651 struct pci_bus *parent; /* Parent bus this bridge is on */ 652 struct list_head children; /* List of child buses */ 653 struct list_head devices; /* List of devices on this bus */ 654 struct pci_dev *self; /* Bridge device as seen by parent */ 655 struct list_head slots; /* List of slots on this bus; 656 protected by pci_slot_mutex */ 657 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 658 struct list_head resources; /* Address space routed to this bus */ 659 struct resource busn_res; /* Bus numbers routed to this bus */ 660 661 struct pci_ops *ops; /* Configuration access functions */ 662 void *sysdata; /* Hook for sys-specific extension */ 663 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 664 665 unsigned char number; /* Bus number */ 666 unsigned char primary; /* Number of primary bridge */ 667 unsigned char max_bus_speed; /* enum pci_bus_speed */ 668 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 669 #ifdef CONFIG_PCI_DOMAINS_GENERIC 670 int domain_nr; 671 #endif 672 673 char name[48]; 674 675 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 676 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 677 struct device *bridge; 678 struct device dev; 679 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 680 struct bin_attribute *legacy_mem; /* Legacy mem */ 681 unsigned int is_added:1; 682 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 683 }; 684 685 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 686 687 static inline u16 pci_dev_id(struct pci_dev *dev) 688 { 689 return PCI_DEVID(dev->bus->number, dev->devfn); 690 } 691 692 /* 693 * Returns true if the PCI bus is root (behind host-PCI bridge), 694 * false otherwise 695 * 696 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 697 * This is incorrect because "virtual" buses added for SR-IOV (via 698 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 699 */ 700 static inline bool pci_is_root_bus(struct pci_bus *pbus) 701 { 702 return !(pbus->parent); 703 } 704 705 /** 706 * pci_is_bridge - check if the PCI device is a bridge 707 * @dev: PCI device 708 * 709 * Return true if the PCI device is bridge whether it has subordinate 710 * or not. 711 */ 712 static inline bool pci_is_bridge(struct pci_dev *dev) 713 { 714 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 715 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 716 } 717 718 /** 719 * pci_is_vga - check if the PCI device is a VGA device 720 * @pdev: PCI device 721 * 722 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define 723 * VGA Base Class and Sub-Classes: 724 * 725 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible 726 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code) 727 * 728 * Return true if the PCI device is a VGA device and uses the legacy VGA 729 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and 730 * aliases). 731 */ 732 static inline bool pci_is_vga(struct pci_dev *pdev) 733 { 734 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) 735 return true; 736 737 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA) 738 return true; 739 740 return false; 741 } 742 743 #define for_each_pci_bridge(dev, bus) \ 744 list_for_each_entry(dev, &bus->devices, bus_list) \ 745 if (!pci_is_bridge(dev)) {} else 746 747 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 748 { 749 dev = pci_physfn(dev); 750 if (pci_is_root_bus(dev->bus)) 751 return NULL; 752 753 return dev->bus->self; 754 } 755 756 #ifdef CONFIG_PCI_MSI 757 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 758 { 759 return pci_dev->msi_enabled || pci_dev->msix_enabled; 760 } 761 #else 762 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 763 #endif 764 765 /* Error values that may be returned by PCI functions */ 766 #define PCIBIOS_SUCCESSFUL 0x00 767 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 768 #define PCIBIOS_BAD_VENDOR_ID 0x83 769 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 770 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 771 #define PCIBIOS_SET_FAILED 0x88 772 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 773 774 /* Translate above to generic errno for passing back through non-PCI code */ 775 static inline int pcibios_err_to_errno(int err) 776 { 777 if (err <= PCIBIOS_SUCCESSFUL) 778 return err; /* Assume already errno */ 779 780 switch (err) { 781 case PCIBIOS_FUNC_NOT_SUPPORTED: 782 return -ENOENT; 783 case PCIBIOS_BAD_VENDOR_ID: 784 return -ENOTTY; 785 case PCIBIOS_DEVICE_NOT_FOUND: 786 return -ENODEV; 787 case PCIBIOS_BAD_REGISTER_NUMBER: 788 return -EFAULT; 789 case PCIBIOS_SET_FAILED: 790 return -EIO; 791 case PCIBIOS_BUFFER_TOO_SMALL: 792 return -ENOSPC; 793 } 794 795 return -ERANGE; 796 } 797 798 /* Low-level architecture-dependent routines */ 799 800 struct pci_ops { 801 int (*add_bus)(struct pci_bus *bus); 802 void (*remove_bus)(struct pci_bus *bus); 803 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 804 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 805 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 806 }; 807 808 /* 809 * ACPI needs to be able to access PCI config space before we've done a 810 * PCI bus scan and created pci_bus structures. 811 */ 812 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 813 int reg, int len, u32 *val); 814 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 815 int reg, int len, u32 val); 816 817 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 818 typedef u64 pci_bus_addr_t; 819 #else 820 typedef u32 pci_bus_addr_t; 821 #endif 822 823 struct pci_bus_region { 824 pci_bus_addr_t start; 825 pci_bus_addr_t end; 826 }; 827 828 struct pci_dynids { 829 spinlock_t lock; /* Protects list, index */ 830 struct list_head list; /* For IDs added at runtime */ 831 }; 832 833 834 /* 835 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 836 * a set of callbacks in struct pci_error_handlers, that device driver 837 * will be notified of PCI bus errors, and will be driven to recovery 838 * when an error occurs. 839 */ 840 841 typedef unsigned int __bitwise pci_ers_result_t; 842 843 enum pci_ers_result { 844 /* No result/none/not supported in device driver */ 845 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 846 847 /* Device driver can recover without slot reset */ 848 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 849 850 /* Device driver wants slot to be reset */ 851 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 852 853 /* Device has completely failed, is unrecoverable */ 854 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 855 856 /* Device driver is fully recovered and operational */ 857 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 858 859 /* No AER capabilities registered for the driver */ 860 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 861 }; 862 863 /* PCI bus error event callbacks */ 864 struct pci_error_handlers { 865 /* PCI bus error detected on this device */ 866 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 867 pci_channel_state_t error); 868 869 /* MMIO has been re-enabled, but not DMA */ 870 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 871 872 /* PCI slot has been reset */ 873 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 874 875 /* PCI function reset prepare or completed */ 876 void (*reset_prepare)(struct pci_dev *dev); 877 void (*reset_done)(struct pci_dev *dev); 878 879 /* Device driver may resume normal operations */ 880 void (*resume)(struct pci_dev *dev); 881 882 /* Allow device driver to record more details of a correctable error */ 883 void (*cor_error_detected)(struct pci_dev *dev); 884 }; 885 886 887 struct module; 888 889 /** 890 * struct pci_driver - PCI driver structure 891 * @name: Driver name. 892 * @id_table: Pointer to table of device IDs the driver is 893 * interested in. Most drivers should export this 894 * table using MODULE_DEVICE_TABLE(pci,...). 895 * @probe: This probing function gets called (during execution 896 * of pci_register_driver() for already existing 897 * devices or later if a new device gets inserted) for 898 * all PCI devices which match the ID table and are not 899 * "owned" by the other drivers yet. This function gets 900 * passed a "struct pci_dev \*" for each device whose 901 * entry in the ID table matches the device. The probe 902 * function returns zero when the driver chooses to 903 * take "ownership" of the device or an error code 904 * (negative number) otherwise. 905 * The probe function always gets called from process 906 * context, so it can sleep. 907 * @remove: The remove() function gets called whenever a device 908 * being handled by this driver is removed (either during 909 * deregistration of the driver or when it's manually 910 * pulled out of a hot-pluggable slot). 911 * The remove function always gets called from process 912 * context, so it can sleep. 913 * @suspend: Put device into low power state. 914 * @resume: Wake device from low power state. 915 * (Please see Documentation/power/pci.rst for descriptions 916 * of PCI Power Management and the related functions.) 917 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 918 * Intended to stop any idling DMA operations. 919 * Useful for enabling wake-on-lan (NIC) or changing 920 * the power state of a device before reboot. 921 * e.g. drivers/net/e100.c. 922 * @sriov_configure: Optional driver callback to allow configuration of 923 * number of VFs to enable via sysfs "sriov_numvfs" file. 924 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 925 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 926 * This will change MSI-X Table Size in the VF Message Control 927 * registers. 928 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 929 * MSI-X vectors available for distribution to the VFs. 930 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 931 * @groups: Sysfs attribute groups. 932 * @dev_groups: Attributes attached to the device that will be 933 * created once it is bound to the driver. 934 * @driver: Driver model structure. 935 * @dynids: List of dynamically added device IDs. 936 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. 937 * For most device drivers, no need to care about this flag 938 * as long as all DMAs are handled through the kernel DMA API. 939 * For some special ones, for example VFIO drivers, they know 940 * how to manage the DMA themselves and set this flag so that 941 * the IOMMU layer will allow them to setup and manage their 942 * own I/O address space. 943 */ 944 struct pci_driver { 945 const char *name; 946 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 947 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 948 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 949 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 950 int (*resume)(struct pci_dev *dev); /* Device woken up */ 951 void (*shutdown)(struct pci_dev *dev); 952 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 953 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 954 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 955 const struct pci_error_handlers *err_handler; 956 const struct attribute_group **groups; 957 const struct attribute_group **dev_groups; 958 struct device_driver driver; 959 struct pci_dynids dynids; 960 bool driver_managed_dma; 961 }; 962 963 static inline struct pci_driver *to_pci_driver(struct device_driver *drv) 964 { 965 return drv ? container_of(drv, struct pci_driver, driver) : NULL; 966 } 967 968 /** 969 * PCI_DEVICE - macro used to describe a specific PCI device 970 * @vend: the 16 bit PCI Vendor ID 971 * @dev: the 16 bit PCI Device ID 972 * 973 * This macro is used to create a struct pci_device_id that matches a 974 * specific device. The subvendor and subdevice fields will be set to 975 * PCI_ANY_ID. 976 */ 977 #define PCI_DEVICE(vend,dev) \ 978 .vendor = (vend), .device = (dev), \ 979 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 980 981 /** 982 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 983 * override_only flags. 984 * @vend: the 16 bit PCI Vendor ID 985 * @dev: the 16 bit PCI Device ID 986 * @driver_override: the 32 bit PCI Device override_only 987 * 988 * This macro is used to create a struct pci_device_id that matches only a 989 * driver_override device. The subvendor and subdevice fields will be set to 990 * PCI_ANY_ID. 991 */ 992 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 993 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 994 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 995 996 /** 997 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 998 * "driver_override" PCI device. 999 * @vend: the 16 bit PCI Vendor ID 1000 * @dev: the 16 bit PCI Device ID 1001 * 1002 * This macro is used to create a struct pci_device_id that matches a 1003 * specific device. The subvendor and subdevice fields will be set to 1004 * PCI_ANY_ID and the driver_override will be set to 1005 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 1006 */ 1007 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 1008 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 1009 1010 /** 1011 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 1012 * @vend: the 16 bit PCI Vendor ID 1013 * @dev: the 16 bit PCI Device ID 1014 * @subvend: the 16 bit PCI Subvendor ID 1015 * @subdev: the 16 bit PCI Subdevice ID 1016 * 1017 * This macro is used to create a struct pci_device_id that matches a 1018 * specific device with subsystem information. 1019 */ 1020 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1021 .vendor = (vend), .device = (dev), \ 1022 .subvendor = (subvend), .subdevice = (subdev) 1023 1024 /** 1025 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 1026 * @dev_class: the class, subclass, prog-if triple for this device 1027 * @dev_class_mask: the class mask for this device 1028 * 1029 * This macro is used to create a struct pci_device_id that matches a 1030 * specific PCI class. The vendor, device, subvendor, and subdevice 1031 * fields will be set to PCI_ANY_ID. 1032 */ 1033 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 1034 .class = (dev_class), .class_mask = (dev_class_mask), \ 1035 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1036 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1037 1038 /** 1039 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 1040 * @vend: the vendor name 1041 * @dev: the 16 bit PCI Device ID 1042 * 1043 * This macro is used to create a struct pci_device_id that matches a 1044 * specific PCI device. The subvendor, and subdevice fields will be set 1045 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1046 * private data. 1047 */ 1048 #define PCI_VDEVICE(vend, dev) \ 1049 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1050 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1051 1052 /** 1053 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1054 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1055 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1056 * @data: the driver data to be filled 1057 * 1058 * This macro is used to create a struct pci_device_id that matches a 1059 * specific PCI device. The subvendor, and subdevice fields will be set 1060 * to PCI_ANY_ID. 1061 */ 1062 #define PCI_DEVICE_DATA(vend, dev, data) \ 1063 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1064 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1065 .driver_data = (kernel_ulong_t)(data) 1066 1067 enum { 1068 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1069 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1070 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1071 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1072 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1073 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1074 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1075 }; 1076 1077 #define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */ 1078 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1079 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1080 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1081 1082 /* These external functions are only available when PCI support is enabled */ 1083 #ifdef CONFIG_PCI 1084 1085 extern unsigned int pci_flags; 1086 1087 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1088 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1089 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1090 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1091 1092 void pcie_bus_configure_settings(struct pci_bus *bus); 1093 1094 enum pcie_bus_config_types { 1095 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1096 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1097 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1098 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1099 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1100 }; 1101 1102 extern enum pcie_bus_config_types pcie_bus_config; 1103 1104 extern struct bus_type pci_bus_type; 1105 1106 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1107 * code, or PCI core code. */ 1108 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1109 /* Some device drivers need know if PCI is initiated */ 1110 int no_pci_devices(void); 1111 1112 void pcibios_resource_survey_bus(struct pci_bus *bus); 1113 void pcibios_bus_add_device(struct pci_dev *pdev); 1114 void pcibios_add_bus(struct pci_bus *bus); 1115 void pcibios_remove_bus(struct pci_bus *bus); 1116 void pcibios_fixup_bus(struct pci_bus *); 1117 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1118 /* Architecture-specific versions may override this (weak) */ 1119 char *pcibios_setup(char *str); 1120 1121 /* Used only when drivers/pci/setup.c is used */ 1122 resource_size_t pcibios_align_resource(void *, const struct resource *, 1123 resource_size_t, 1124 resource_size_t); 1125 1126 /* Weak but can be overridden by arch */ 1127 void pci_fixup_cardbus(struct pci_bus *); 1128 1129 /* Generic PCI functions used internally */ 1130 1131 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1132 struct resource *res); 1133 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1134 struct pci_bus_region *region); 1135 void pcibios_scan_specific_bus(int busn); 1136 struct pci_bus *pci_find_bus(int domain, int busnr); 1137 void pci_bus_add_devices(const struct pci_bus *bus); 1138 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1139 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1140 struct pci_ops *ops, void *sysdata, 1141 struct list_head *resources); 1142 int pci_host_probe(struct pci_host_bridge *bridge); 1143 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1144 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1145 void pci_bus_release_busn_res(struct pci_bus *b); 1146 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1147 struct pci_ops *ops, void *sysdata, 1148 struct list_head *resources); 1149 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1150 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1151 int busnr); 1152 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1153 const char *name, 1154 struct hotplug_slot *hotplug); 1155 void pci_destroy_slot(struct pci_slot *slot); 1156 #ifdef CONFIG_SYSFS 1157 void pci_dev_assign_slot(struct pci_dev *dev); 1158 #else 1159 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1160 #endif 1161 int pci_scan_slot(struct pci_bus *bus, int devfn); 1162 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1163 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1164 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1165 void pci_bus_add_device(struct pci_dev *dev); 1166 void pci_read_bridge_bases(struct pci_bus *child); 1167 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1168 struct resource *res); 1169 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1170 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1171 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1172 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1173 void pci_dev_put(struct pci_dev *dev); 1174 DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T)) 1175 void pci_remove_bus(struct pci_bus *b); 1176 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1177 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1178 void pci_stop_root_bus(struct pci_bus *bus); 1179 void pci_remove_root_bus(struct pci_bus *bus); 1180 void pci_setup_cardbus(struct pci_bus *bus); 1181 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1182 void pci_sort_breadthfirst(void); 1183 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1184 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1185 1186 /* Generic PCI functions exported to card drivers */ 1187 1188 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1189 u8 pci_find_capability(struct pci_dev *dev, int cap); 1190 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1191 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1192 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1193 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1194 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1195 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1196 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1197 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1198 1199 u64 pci_get_dsn(struct pci_dev *dev); 1200 1201 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1202 struct pci_dev *from); 1203 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1204 unsigned int ss_vendor, unsigned int ss_device, 1205 struct pci_dev *from); 1206 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1207 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1208 unsigned int devfn); 1209 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1210 struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); 1211 1212 int pci_dev_present(const struct pci_device_id *ids); 1213 1214 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1215 int where, u8 *val); 1216 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1217 int where, u16 *val); 1218 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1219 int where, u32 *val); 1220 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1221 int where, u8 val); 1222 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1223 int where, u16 val); 1224 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1225 int where, u32 val); 1226 1227 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1228 int where, int size, u32 *val); 1229 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1230 int where, int size, u32 val); 1231 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1232 int where, int size, u32 *val); 1233 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1234 int where, int size, u32 val); 1235 1236 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1237 1238 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1239 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1240 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1241 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1242 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1243 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1244 void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos, 1245 u32 clear, u32 set); 1246 1247 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1248 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1249 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1250 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1251 int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, 1252 u16 clear, u16 set); 1253 int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos, 1254 u16 clear, u16 set); 1255 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1256 u32 clear, u32 set); 1257 1258 /** 1259 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers 1260 * @dev: PCI device structure of the PCI Express device 1261 * @pos: PCI Express Capability Register 1262 * @clear: Clear bitmask 1263 * @set: Set bitmask 1264 * 1265 * Perform a Read-Modify-Write (RMW) operation using @clear and @set 1266 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express 1267 * Capability Registers are accessed concurrently in RMW fashion, hence 1268 * require locking which is handled transparently to the caller. 1269 */ 1270 static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, 1271 int pos, 1272 u16 clear, u16 set) 1273 { 1274 switch (pos) { 1275 case PCI_EXP_LNKCTL: 1276 case PCI_EXP_RTCTL: 1277 return pcie_capability_clear_and_set_word_locked(dev, pos, 1278 clear, set); 1279 default: 1280 return pcie_capability_clear_and_set_word_unlocked(dev, pos, 1281 clear, set); 1282 } 1283 } 1284 1285 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1286 u16 set) 1287 { 1288 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1289 } 1290 1291 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1292 u32 set) 1293 { 1294 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1295 } 1296 1297 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1298 u16 clear) 1299 { 1300 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1301 } 1302 1303 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1304 u32 clear) 1305 { 1306 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1307 } 1308 1309 /* User-space driven config access */ 1310 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1311 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1312 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1313 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1314 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1315 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1316 1317 int __must_check pci_enable_device(struct pci_dev *dev); 1318 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1319 int __must_check pci_reenable_device(struct pci_dev *); 1320 int __must_check pcim_enable_device(struct pci_dev *pdev); 1321 void pcim_pin_device(struct pci_dev *pdev); 1322 1323 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1324 { 1325 /* 1326 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1327 * writable and no quirk has marked the feature broken. 1328 */ 1329 return !pdev->broken_intx_masking; 1330 } 1331 1332 static inline int pci_is_enabled(struct pci_dev *pdev) 1333 { 1334 return (atomic_read(&pdev->enable_cnt) > 0); 1335 } 1336 1337 static inline int pci_is_managed(struct pci_dev *pdev) 1338 { 1339 return pdev->is_managed; 1340 } 1341 1342 void pci_disable_device(struct pci_dev *dev); 1343 1344 extern unsigned int pcibios_max_latency; 1345 void pci_set_master(struct pci_dev *dev); 1346 void pci_clear_master(struct pci_dev *dev); 1347 1348 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1349 int pci_set_cacheline_size(struct pci_dev *dev); 1350 int __must_check pci_set_mwi(struct pci_dev *dev); 1351 int __must_check pcim_set_mwi(struct pci_dev *dev); 1352 int pci_try_set_mwi(struct pci_dev *dev); 1353 void pci_clear_mwi(struct pci_dev *dev); 1354 void pci_disable_parity(struct pci_dev *dev); 1355 void pci_intx(struct pci_dev *dev, int enable); 1356 bool pci_check_and_mask_intx(struct pci_dev *dev); 1357 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1358 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1359 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1360 int pcix_get_max_mmrbc(struct pci_dev *dev); 1361 int pcix_get_mmrbc(struct pci_dev *dev); 1362 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1363 int pcie_get_readrq(struct pci_dev *dev); 1364 int pcie_set_readrq(struct pci_dev *dev, int rq); 1365 int pcie_get_mps(struct pci_dev *dev); 1366 int pcie_set_mps(struct pci_dev *dev, int mps); 1367 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1368 enum pci_bus_speed *speed, 1369 enum pcie_link_width *width); 1370 int pcie_link_speed_mbps(struct pci_dev *pdev); 1371 void pcie_print_link_status(struct pci_dev *dev); 1372 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1373 int pcie_flr(struct pci_dev *dev); 1374 int __pci_reset_function_locked(struct pci_dev *dev); 1375 int pci_reset_function(struct pci_dev *dev); 1376 int pci_reset_function_locked(struct pci_dev *dev); 1377 int pci_try_reset_function(struct pci_dev *dev); 1378 int pci_probe_reset_slot(struct pci_slot *slot); 1379 int pci_probe_reset_bus(struct pci_bus *bus); 1380 int pci_reset_bus(struct pci_dev *dev); 1381 void pci_reset_secondary_bus(struct pci_dev *dev); 1382 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1383 void pci_update_resource(struct pci_dev *dev, int resno); 1384 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1385 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1386 void pci_release_resource(struct pci_dev *dev, int resno); 1387 static inline int pci_rebar_bytes_to_size(u64 bytes) 1388 { 1389 bytes = roundup_pow_of_two(bytes); 1390 1391 /* Return BAR size as defined in the resizable BAR specification */ 1392 return max(ilog2(bytes), 20) - 20; 1393 } 1394 1395 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1396 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1397 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1398 bool pci_device_is_present(struct pci_dev *pdev); 1399 void pci_ignore_hotplug(struct pci_dev *dev); 1400 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1401 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1402 1403 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1404 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1405 const char *fmt, ...); 1406 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1407 1408 /* ROM control related routines */ 1409 int pci_enable_rom(struct pci_dev *pdev); 1410 void pci_disable_rom(struct pci_dev *pdev); 1411 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1412 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1413 1414 /* Power management related routines */ 1415 int pci_save_state(struct pci_dev *dev); 1416 void pci_restore_state(struct pci_dev *dev); 1417 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1418 int pci_load_saved_state(struct pci_dev *dev, 1419 struct pci_saved_state *state); 1420 int pci_load_and_free_saved_state(struct pci_dev *dev, 1421 struct pci_saved_state **state); 1422 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1423 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1424 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state); 1425 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1426 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1427 void pci_pme_active(struct pci_dev *dev, bool enable); 1428 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1429 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1430 int pci_prepare_to_sleep(struct pci_dev *dev); 1431 int pci_back_from_sleep(struct pci_dev *dev); 1432 bool pci_dev_run_wake(struct pci_dev *dev); 1433 void pci_d3cold_enable(struct pci_dev *dev); 1434 void pci_d3cold_disable(struct pci_dev *dev); 1435 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1436 void pci_resume_bus(struct pci_bus *bus); 1437 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1438 1439 /* For use by arch with custom probe code */ 1440 void set_pcie_port_type(struct pci_dev *pdev); 1441 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1442 1443 /* Functions for PCI Hotplug drivers to use */ 1444 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1445 unsigned int pci_rescan_bus(struct pci_bus *bus); 1446 void pci_lock_rescan_remove(void); 1447 void pci_unlock_rescan_remove(void); 1448 1449 /* Vital Product Data routines */ 1450 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1451 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1452 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1453 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1454 1455 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1456 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1457 void pci_bus_assign_resources(const struct pci_bus *bus); 1458 void pci_bus_claim_resources(struct pci_bus *bus); 1459 void pci_bus_size_bridges(struct pci_bus *bus); 1460 int pci_claim_resource(struct pci_dev *, int); 1461 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1462 void pci_assign_unassigned_resources(void); 1463 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1464 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1465 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1466 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1467 int pci_enable_resources(struct pci_dev *, int mask); 1468 void pci_assign_irq(struct pci_dev *dev); 1469 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1470 #define HAVE_PCI_REQ_REGIONS 2 1471 int __must_check pci_request_regions(struct pci_dev *, const char *); 1472 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1473 void pci_release_regions(struct pci_dev *); 1474 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1475 void pci_release_region(struct pci_dev *, int); 1476 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1477 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1478 void pci_release_selected_regions(struct pci_dev *, int); 1479 1480 static inline __must_check struct resource * 1481 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, 1482 unsigned int len, const char *name) 1483 { 1484 return __request_region(&pdev->driver_exclusive_resource, offset, len, 1485 name, IORESOURCE_EXCLUSIVE); 1486 } 1487 1488 static inline void pci_release_config_region(struct pci_dev *pdev, 1489 unsigned int offset, 1490 unsigned int len) 1491 { 1492 __release_region(&pdev->driver_exclusive_resource, offset, len); 1493 } 1494 1495 /* drivers/pci/bus.c */ 1496 void pci_add_resource(struct list_head *resources, struct resource *res); 1497 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1498 resource_size_t offset); 1499 void pci_free_resource_list(struct list_head *resources); 1500 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1501 unsigned int flags); 1502 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1503 void pci_bus_remove_resources(struct pci_bus *bus); 1504 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res); 1505 int devm_request_pci_bus_resources(struct device *dev, 1506 struct list_head *resources); 1507 1508 /* Temporary until new and working PCI SBR API in place */ 1509 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1510 1511 #define __pci_bus_for_each_res0(bus, res, ...) \ 1512 for (unsigned int __b = 0; \ 1513 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1514 __b++) 1515 1516 #define __pci_bus_for_each_res1(bus, res, __b) \ 1517 for (__b = 0; \ 1518 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1519 __b++) 1520 1521 /** 1522 * pci_bus_for_each_resource - iterate over PCI bus resources 1523 * @bus: the PCI bus 1524 * @res: pointer to the current resource 1525 * @...: optional index of the current resource 1526 * 1527 * Iterate over PCI bus resources. The first part is to go over PCI bus 1528 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries. 1529 * After that continue with the separate list of the additional resources, 1530 * if not empty. That's why the Logical OR is being used. 1531 * 1532 * Possible usage: 1533 * 1534 * struct pci_bus *bus = ...; 1535 * struct resource *res; 1536 * unsigned int i; 1537 * 1538 * // With optional index 1539 * pci_bus_for_each_resource(bus, res, i) 1540 * pr_info("PCI bus resource[%u]: %pR\n", i, res); 1541 * 1542 * // Without index 1543 * pci_bus_for_each_resource(bus, res) 1544 * _do_something_(res); 1545 */ 1546 #define pci_bus_for_each_resource(bus, res, ...) \ 1547 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 1548 (bus, res, __VA_ARGS__) 1549 1550 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1551 struct resource *res, resource_size_t size, 1552 resource_size_t align, resource_size_t min, 1553 unsigned long type_mask, 1554 resource_size_t (*alignf)(void *, 1555 const struct resource *, 1556 resource_size_t, 1557 resource_size_t), 1558 void *alignf_data); 1559 1560 1561 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1562 resource_size_t size); 1563 unsigned long pci_address_to_pio(phys_addr_t addr); 1564 phys_addr_t pci_pio_to_address(unsigned long pio); 1565 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1566 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1567 phys_addr_t phys_addr); 1568 void pci_unmap_iospace(struct resource *res); 1569 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1570 resource_size_t offset, 1571 resource_size_t size); 1572 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1573 struct resource *res); 1574 1575 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1576 { 1577 struct pci_bus_region region; 1578 1579 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1580 return region.start; 1581 } 1582 1583 /* Proper probing supporting hot-pluggable devices */ 1584 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1585 const char *mod_name); 1586 1587 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1588 #define pci_register_driver(driver) \ 1589 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1590 1591 void pci_unregister_driver(struct pci_driver *dev); 1592 1593 /** 1594 * module_pci_driver() - Helper macro for registering a PCI driver 1595 * @__pci_driver: pci_driver struct 1596 * 1597 * Helper macro for PCI drivers which do not do anything special in module 1598 * init/exit. This eliminates a lot of boilerplate. Each module may only 1599 * use this macro once, and calling it replaces module_init() and module_exit() 1600 */ 1601 #define module_pci_driver(__pci_driver) \ 1602 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1603 1604 /** 1605 * builtin_pci_driver() - Helper macro for registering a PCI driver 1606 * @__pci_driver: pci_driver struct 1607 * 1608 * Helper macro for PCI drivers which do not do anything special in their 1609 * init code. This eliminates a lot of boilerplate. Each driver may only 1610 * use this macro once, and calling it replaces device_initcall(...) 1611 */ 1612 #define builtin_pci_driver(__pci_driver) \ 1613 builtin_driver(__pci_driver, pci_register_driver) 1614 1615 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1616 int pci_add_dynid(struct pci_driver *drv, 1617 unsigned int vendor, unsigned int device, 1618 unsigned int subvendor, unsigned int subdevice, 1619 unsigned int class, unsigned int class_mask, 1620 unsigned long driver_data); 1621 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1622 struct pci_dev *dev); 1623 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1624 int pass); 1625 1626 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1627 void *userdata); 1628 void pci_walk_bus_locked(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1629 void *userdata); 1630 int pci_cfg_space_size(struct pci_dev *dev); 1631 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1632 void pci_setup_bridge(struct pci_bus *bus); 1633 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1634 unsigned long type); 1635 1636 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1637 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1638 1639 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1640 unsigned int command_bits, u32 flags); 1641 1642 /* 1643 * Virtual interrupts allow for more interrupts to be allocated 1644 * than the device has interrupts for. These are not programmed 1645 * into the device's MSI-X table and must be handled by some 1646 * other driver means. 1647 */ 1648 #define PCI_IRQ_VIRTUAL (1 << 4) 1649 1650 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1651 1652 #include <linux/dmapool.h> 1653 1654 struct msix_entry { 1655 u32 vector; /* Kernel uses to write allocated vector */ 1656 u16 entry; /* Driver uses to specify entry, OS writes */ 1657 }; 1658 1659 #ifdef CONFIG_PCI_MSI 1660 int pci_msi_vec_count(struct pci_dev *dev); 1661 void pci_disable_msi(struct pci_dev *dev); 1662 int pci_msix_vec_count(struct pci_dev *dev); 1663 void pci_disable_msix(struct pci_dev *dev); 1664 void pci_restore_msi_state(struct pci_dev *dev); 1665 int pci_msi_enabled(void); 1666 int pci_enable_msi(struct pci_dev *dev); 1667 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1668 int minvec, int maxvec); 1669 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1670 struct msix_entry *entries, int nvec) 1671 { 1672 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1673 if (rc < 0) 1674 return rc; 1675 return 0; 1676 } 1677 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1678 unsigned int max_vecs, unsigned int flags); 1679 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1680 unsigned int max_vecs, unsigned int flags, 1681 struct irq_affinity *affd); 1682 1683 bool pci_msix_can_alloc_dyn(struct pci_dev *dev); 1684 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1685 const struct irq_affinity_desc *affdesc); 1686 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); 1687 1688 void pci_free_irq_vectors(struct pci_dev *dev); 1689 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1690 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1691 1692 #else 1693 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1694 static inline void pci_disable_msi(struct pci_dev *dev) { } 1695 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1696 static inline void pci_disable_msix(struct pci_dev *dev) { } 1697 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1698 static inline int pci_msi_enabled(void) { return 0; } 1699 static inline int pci_enable_msi(struct pci_dev *dev) 1700 { return -ENOSYS; } 1701 static inline int pci_enable_msix_range(struct pci_dev *dev, 1702 struct msix_entry *entries, int minvec, int maxvec) 1703 { return -ENOSYS; } 1704 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1705 struct msix_entry *entries, int nvec) 1706 { return -ENOSYS; } 1707 1708 static inline int 1709 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1710 unsigned int max_vecs, unsigned int flags, 1711 struct irq_affinity *aff_desc) 1712 { 1713 if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq) 1714 return 1; 1715 return -ENOSPC; 1716 } 1717 static inline int 1718 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1719 unsigned int max_vecs, unsigned int flags) 1720 { 1721 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, 1722 flags, NULL); 1723 } 1724 1725 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev) 1726 { return false; } 1727 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1728 const struct irq_affinity_desc *affdesc) 1729 { 1730 struct msi_map map = { .index = -ENOSYS, }; 1731 1732 return map; 1733 } 1734 1735 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map) 1736 { 1737 } 1738 1739 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1740 { 1741 } 1742 1743 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1744 { 1745 if (WARN_ON_ONCE(nr > 0)) 1746 return -EINVAL; 1747 return dev->irq; 1748 } 1749 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1750 int vec) 1751 { 1752 return cpu_possible_mask; 1753 } 1754 #endif 1755 1756 /** 1757 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1758 * @d: the INTx IRQ domain 1759 * @node: the DT node for the device whose interrupt we're translating 1760 * @intspec: the interrupt specifier data from the DT 1761 * @intsize: the number of entries in @intspec 1762 * @out_hwirq: pointer at which to write the hwirq number 1763 * @out_type: pointer at which to write the interrupt type 1764 * 1765 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1766 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1767 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1768 * INTx value to obtain the hwirq number. 1769 * 1770 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1771 */ 1772 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1773 struct device_node *node, 1774 const u32 *intspec, 1775 unsigned int intsize, 1776 unsigned long *out_hwirq, 1777 unsigned int *out_type) 1778 { 1779 const u32 intx = intspec[0]; 1780 1781 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1782 return -EINVAL; 1783 1784 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1785 return 0; 1786 } 1787 1788 #ifdef CONFIG_PCIEPORTBUS 1789 extern bool pcie_ports_disabled; 1790 extern bool pcie_ports_native; 1791 #else 1792 #define pcie_ports_disabled true 1793 #define pcie_ports_native false 1794 #endif 1795 1796 #define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */ 1797 #define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */ 1798 #define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */ 1799 #define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */ 1800 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */ 1801 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */ 1802 #define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\ 1803 PCIE_LINK_STATE_L1 |\ 1804 PCIE_LINK_STATE_L1_1 |\ 1805 PCIE_LINK_STATE_L1_2 |\ 1806 PCIE_LINK_STATE_L1_1_PCIPM |\ 1807 PCIE_LINK_STATE_L1_2_PCIPM) 1808 #define PCIE_LINK_STATE_CLKPM BIT(7) 1809 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\ 1810 PCIE_LINK_STATE_CLKPM) 1811 1812 #ifdef CONFIG_PCIEASPM 1813 int pci_disable_link_state(struct pci_dev *pdev, int state); 1814 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1815 int pci_enable_link_state(struct pci_dev *pdev, int state); 1816 int pci_enable_link_state_locked(struct pci_dev *pdev, int state); 1817 void pcie_no_aspm(void); 1818 bool pcie_aspm_support_enabled(void); 1819 bool pcie_aspm_enabled(struct pci_dev *pdev); 1820 #else 1821 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1822 { return 0; } 1823 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1824 { return 0; } 1825 static inline int pci_enable_link_state(struct pci_dev *pdev, int state) 1826 { return 0; } 1827 static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) 1828 { return 0; } 1829 static inline void pcie_no_aspm(void) { } 1830 static inline bool pcie_aspm_support_enabled(void) { return false; } 1831 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1832 #endif 1833 1834 #ifdef CONFIG_PCIEAER 1835 bool pci_aer_available(void); 1836 #else 1837 static inline bool pci_aer_available(void) { return false; } 1838 #endif 1839 1840 bool pci_ats_disabled(void); 1841 1842 #ifdef CONFIG_PCIE_PTM 1843 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1844 void pci_disable_ptm(struct pci_dev *dev); 1845 bool pcie_ptm_enabled(struct pci_dev *dev); 1846 #else 1847 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1848 { return -EINVAL; } 1849 static inline void pci_disable_ptm(struct pci_dev *dev) { } 1850 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1851 { return false; } 1852 #endif 1853 1854 void pci_cfg_access_lock(struct pci_dev *dev); 1855 bool pci_cfg_access_trylock(struct pci_dev *dev); 1856 void pci_cfg_access_unlock(struct pci_dev *dev); 1857 1858 void pci_dev_lock(struct pci_dev *dev); 1859 int pci_dev_trylock(struct pci_dev *dev); 1860 void pci_dev_unlock(struct pci_dev *dev); 1861 DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T)) 1862 1863 /* 1864 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1865 * a PCI domain is defined to be a set of PCI buses which share 1866 * configuration space. 1867 */ 1868 #ifdef CONFIG_PCI_DOMAINS 1869 extern int pci_domains_supported; 1870 #else 1871 enum { pci_domains_supported = 0 }; 1872 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1873 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1874 #endif /* CONFIG_PCI_DOMAINS */ 1875 1876 /* 1877 * Generic implementation for PCI domain support. If your 1878 * architecture does not need custom management of PCI 1879 * domains then this implementation will be used 1880 */ 1881 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1882 static inline int pci_domain_nr(struct pci_bus *bus) 1883 { 1884 return bus->domain_nr; 1885 } 1886 #ifdef CONFIG_ACPI 1887 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1888 #else 1889 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1890 { return 0; } 1891 #endif 1892 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1893 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent); 1894 #endif 1895 1896 /* Some architectures require additional setup to direct VGA traffic */ 1897 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1898 unsigned int command_bits, u32 flags); 1899 void pci_register_set_vga_state(arch_set_vga_state_t func); 1900 1901 static inline int 1902 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1903 { 1904 return pci_request_selected_regions(pdev, 1905 pci_select_bars(pdev, IORESOURCE_IO), name); 1906 } 1907 1908 static inline void 1909 pci_release_io_regions(struct pci_dev *pdev) 1910 { 1911 return pci_release_selected_regions(pdev, 1912 pci_select_bars(pdev, IORESOURCE_IO)); 1913 } 1914 1915 static inline int 1916 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1917 { 1918 return pci_request_selected_regions(pdev, 1919 pci_select_bars(pdev, IORESOURCE_MEM), name); 1920 } 1921 1922 static inline void 1923 pci_release_mem_regions(struct pci_dev *pdev) 1924 { 1925 return pci_release_selected_regions(pdev, 1926 pci_select_bars(pdev, IORESOURCE_MEM)); 1927 } 1928 1929 #else /* CONFIG_PCI is not enabled */ 1930 1931 static inline void pci_set_flags(int flags) { } 1932 static inline void pci_add_flags(int flags) { } 1933 static inline void pci_clear_flags(int flags) { } 1934 static inline int pci_has_flag(int flag) { return 0; } 1935 1936 /* 1937 * If the system does not have PCI, clearly these return errors. Define 1938 * these as simple inline functions to avoid hair in drivers. 1939 */ 1940 #define _PCI_NOP(o, s, t) \ 1941 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1942 int where, t val) \ 1943 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1944 1945 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1946 _PCI_NOP(o, word, u16 x) \ 1947 _PCI_NOP(o, dword, u32 x) 1948 _PCI_NOP_ALL(read, *) 1949 _PCI_NOP_ALL(write,) 1950 1951 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1952 unsigned int device, 1953 struct pci_dev *from) 1954 { return NULL; } 1955 1956 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1957 unsigned int device, 1958 unsigned int ss_vendor, 1959 unsigned int ss_device, 1960 struct pci_dev *from) 1961 { return NULL; } 1962 1963 static inline struct pci_dev *pci_get_class(unsigned int class, 1964 struct pci_dev *from) 1965 { return NULL; } 1966 1967 static inline struct pci_dev *pci_get_base_class(unsigned int class, 1968 struct pci_dev *from) 1969 { return NULL; } 1970 1971 static inline int pci_dev_present(const struct pci_device_id *ids) 1972 { return 0; } 1973 1974 #define no_pci_devices() (1) 1975 #define pci_dev_put(dev) do { } while (0) 1976 1977 static inline void pci_set_master(struct pci_dev *dev) { } 1978 static inline void pci_clear_master(struct pci_dev *dev) { } 1979 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1980 static inline void pci_disable_device(struct pci_dev *dev) { } 1981 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1982 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1983 { return -EBUSY; } 1984 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 1985 struct module *owner, 1986 const char *mod_name) 1987 { return 0; } 1988 static inline int pci_register_driver(struct pci_driver *drv) 1989 { return 0; } 1990 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1991 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1992 { return 0; } 1993 static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap) 1994 { return 0; } 1995 static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap) 1996 { return 0; } 1997 1998 static inline u64 pci_get_dsn(struct pci_dev *dev) 1999 { return 0; } 2000 2001 /* Power management related routines */ 2002 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 2003 static inline void pci_restore_state(struct pci_dev *dev) { } 2004 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 2005 { return 0; } 2006 static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state) 2007 { return 0; } 2008 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 2009 { return 0; } 2010 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 2011 pm_message_t state) 2012 { return PCI_D0; } 2013 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 2014 int enable) 2015 { return 0; } 2016 2017 static inline struct resource *pci_find_resource(struct pci_dev *dev, 2018 struct resource *res) 2019 { return NULL; } 2020 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 2021 { return -EIO; } 2022 static inline void pci_release_regions(struct pci_dev *dev) { } 2023 2024 static inline int pci_register_io_range(struct fwnode_handle *fwnode, 2025 phys_addr_t addr, resource_size_t size) 2026 { return -EINVAL; } 2027 2028 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 2029 2030 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 2031 { return NULL; } 2032 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 2033 unsigned int devfn) 2034 { return NULL; } 2035 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 2036 unsigned int bus, unsigned int devfn) 2037 { return NULL; } 2038 2039 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2040 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 2041 2042 #define dev_is_pci(d) (false) 2043 #define dev_is_pf(d) (false) 2044 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2045 { return false; } 2046 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 2047 struct device_node *node, 2048 const u32 *intspec, 2049 unsigned int intsize, 2050 unsigned long *out_hwirq, 2051 unsigned int *out_type) 2052 { return -EINVAL; } 2053 2054 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 2055 struct pci_dev *dev) 2056 { return NULL; } 2057 static inline bool pci_ats_disabled(void) { return true; } 2058 2059 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 2060 { 2061 return -EINVAL; 2062 } 2063 2064 static inline int 2065 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 2066 unsigned int max_vecs, unsigned int flags, 2067 struct irq_affinity *aff_desc) 2068 { 2069 return -ENOSPC; 2070 } 2071 static inline int 2072 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 2073 unsigned int max_vecs, unsigned int flags) 2074 { 2075 return -ENOSPC; 2076 } 2077 #endif /* CONFIG_PCI */ 2078 2079 /* Include architecture-dependent settings and functions */ 2080 2081 #include <asm/pci.h> 2082 2083 /* 2084 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 2085 * is expected to be an offset within that region. 2086 * 2087 */ 2088 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 2089 struct vm_area_struct *vma, 2090 enum pci_mmap_state mmap_state, int write_combine); 2091 2092 #ifndef arch_can_pci_mmap_wc 2093 #define arch_can_pci_mmap_wc() 0 2094 #endif 2095 2096 #ifndef arch_can_pci_mmap_io 2097 #define arch_can_pci_mmap_io() 0 2098 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 2099 #else 2100 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 2101 #endif 2102 2103 #ifndef pci_root_bus_fwnode 2104 #define pci_root_bus_fwnode(bus) NULL 2105 #endif 2106 2107 /* 2108 * These helpers provide future and backwards compatibility 2109 * for accessing popular PCI BAR info 2110 */ 2111 #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)]) 2112 #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start) 2113 #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end) 2114 #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags) 2115 #define pci_resource_len(dev,bar) \ 2116 (pci_resource_end((dev), (bar)) ? \ 2117 resource_size(pci_resource_n((dev), (bar))) : 0) 2118 2119 #define __pci_dev_for_each_res0(dev, res, ...) \ 2120 for (unsigned int __b = 0; \ 2121 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2122 __b++) 2123 2124 #define __pci_dev_for_each_res1(dev, res, __b) \ 2125 for (__b = 0; \ 2126 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2127 __b++) 2128 2129 #define pci_dev_for_each_resource(dev, res, ...) \ 2130 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 2131 (dev, res, __VA_ARGS__) 2132 2133 /* 2134 * Similar to the helpers above, these manipulate per-pci_dev 2135 * driver-specific data. They are really just a wrapper around 2136 * the generic device structure functions of these calls. 2137 */ 2138 static inline void *pci_get_drvdata(struct pci_dev *pdev) 2139 { 2140 return dev_get_drvdata(&pdev->dev); 2141 } 2142 2143 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 2144 { 2145 dev_set_drvdata(&pdev->dev, data); 2146 } 2147 2148 static inline const char *pci_name(const struct pci_dev *pdev) 2149 { 2150 return dev_name(&pdev->dev); 2151 } 2152 2153 void pci_resource_to_user(const struct pci_dev *dev, int bar, 2154 const struct resource *rsrc, 2155 resource_size_t *start, resource_size_t *end); 2156 2157 /* 2158 * The world is not perfect and supplies us with broken PCI devices. 2159 * For at least a part of these bugs we need a work-around, so both 2160 * generic (drivers/pci/quirks.c) and per-architecture code can define 2161 * fixup hooks to be called for particular buggy devices. 2162 */ 2163 2164 struct pci_fixup { 2165 u16 vendor; /* Or PCI_ANY_ID */ 2166 u16 device; /* Or PCI_ANY_ID */ 2167 u32 class; /* Or PCI_ANY_ID */ 2168 unsigned int class_shift; /* should be 0, 8, 16 */ 2169 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2170 int hook_offset; 2171 #else 2172 void (*hook)(struct pci_dev *dev); 2173 #endif 2174 }; 2175 2176 enum pci_fixup_pass { 2177 pci_fixup_early, /* Before probing BARs */ 2178 pci_fixup_header, /* After reading configuration header */ 2179 pci_fixup_final, /* Final phase of device fixups */ 2180 pci_fixup_enable, /* pci_enable_device() time */ 2181 pci_fixup_resume, /* pci_device_resume() */ 2182 pci_fixup_suspend, /* pci_device_suspend() */ 2183 pci_fixup_resume_early, /* pci_device_resume_early() */ 2184 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2185 }; 2186 2187 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2188 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2189 class_shift, hook) \ 2190 __ADDRESSABLE(hook) \ 2191 asm(".section " #sec ", \"a\" \n" \ 2192 ".balign 16 \n" \ 2193 ".short " #vendor ", " #device " \n" \ 2194 ".long " #class ", " #class_shift " \n" \ 2195 ".long " #hook " - . \n" \ 2196 ".previous \n"); 2197 2198 /* 2199 * Clang's LTO may rename static functions in C, but has no way to 2200 * handle such renamings when referenced from inline asm. To work 2201 * around this, create global C stubs for these cases. 2202 */ 2203 #ifdef CONFIG_LTO_CLANG 2204 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2205 class_shift, hook, stub) \ 2206 void stub(struct pci_dev *dev); \ 2207 void stub(struct pci_dev *dev) \ 2208 { \ 2209 hook(dev); \ 2210 } \ 2211 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2212 class_shift, stub) 2213 #else 2214 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2215 class_shift, hook, stub) \ 2216 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2217 class_shift, hook) 2218 #endif 2219 2220 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2221 class_shift, hook) \ 2222 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2223 class_shift, hook, __UNIQUE_ID(hook)) 2224 #else 2225 /* Anonymous variables would be nice... */ 2226 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2227 class_shift, hook) \ 2228 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2229 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2230 = { vendor, device, class, class_shift, hook }; 2231 #endif 2232 2233 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2234 class_shift, hook) \ 2235 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2236 hook, vendor, device, class, class_shift, hook) 2237 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2238 class_shift, hook) \ 2239 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2240 hook, vendor, device, class, class_shift, hook) 2241 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2242 class_shift, hook) \ 2243 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2244 hook, vendor, device, class, class_shift, hook) 2245 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2246 class_shift, hook) \ 2247 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2248 hook, vendor, device, class, class_shift, hook) 2249 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2250 class_shift, hook) \ 2251 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2252 resume##hook, vendor, device, class, class_shift, hook) 2253 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2254 class_shift, hook) \ 2255 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2256 resume_early##hook, vendor, device, class, class_shift, hook) 2257 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2258 class_shift, hook) \ 2259 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2260 suspend##hook, vendor, device, class, class_shift, hook) 2261 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2262 class_shift, hook) \ 2263 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2264 suspend_late##hook, vendor, device, class, class_shift, hook) 2265 2266 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2267 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2268 hook, vendor, device, PCI_ANY_ID, 0, hook) 2269 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2270 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2271 hook, vendor, device, PCI_ANY_ID, 0, hook) 2272 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2273 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2274 hook, vendor, device, PCI_ANY_ID, 0, hook) 2275 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2276 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2277 hook, vendor, device, PCI_ANY_ID, 0, hook) 2278 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2279 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2280 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2281 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2282 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2283 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2284 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2285 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2286 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2287 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2288 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2289 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2290 2291 #ifdef CONFIG_PCI_QUIRKS 2292 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2293 #else 2294 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2295 struct pci_dev *dev) { } 2296 #endif 2297 2298 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2299 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2300 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2301 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2302 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2303 const char *name); 2304 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2305 2306 extern int pci_pci_problems; 2307 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2308 #define PCIPCI_TRITON 2 2309 #define PCIPCI_NATOMA 4 2310 #define PCIPCI_VIAETBF 8 2311 #define PCIPCI_VSFX 16 2312 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2313 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2314 2315 extern unsigned long pci_cardbus_io_size; 2316 extern unsigned long pci_cardbus_mem_size; 2317 extern u8 pci_dfl_cache_line_size; 2318 extern u8 pci_cache_line_size; 2319 2320 /* Architecture-specific versions may override these (weak) */ 2321 void pcibios_disable_device(struct pci_dev *dev); 2322 void pcibios_set_master(struct pci_dev *dev); 2323 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2324 enum pcie_reset_state state); 2325 int pcibios_device_add(struct pci_dev *dev); 2326 void pcibios_release_device(struct pci_dev *dev); 2327 #ifdef CONFIG_PCI 2328 void pcibios_penalize_isa_irq(int irq, int active); 2329 #else 2330 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2331 #endif 2332 int pcibios_alloc_irq(struct pci_dev *dev); 2333 void pcibios_free_irq(struct pci_dev *dev); 2334 resource_size_t pcibios_default_alignment(void); 2335 2336 #if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE) 2337 extern int pci_create_resource_files(struct pci_dev *dev); 2338 extern void pci_remove_resource_files(struct pci_dev *dev); 2339 #endif 2340 2341 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2342 void __init pci_mmcfg_early_init(void); 2343 void __init pci_mmcfg_late_init(void); 2344 #else 2345 static inline void pci_mmcfg_early_init(void) { } 2346 static inline void pci_mmcfg_late_init(void) { } 2347 #endif 2348 2349 int pci_ext_cfg_avail(void); 2350 2351 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2352 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2353 2354 #ifdef CONFIG_PCI_IOV 2355 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2356 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2357 int pci_iov_vf_id(struct pci_dev *dev); 2358 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2359 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2360 void pci_disable_sriov(struct pci_dev *dev); 2361 2362 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2363 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2364 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2365 int pci_num_vf(struct pci_dev *dev); 2366 int pci_vfs_assigned(struct pci_dev *dev); 2367 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2368 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2369 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2370 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2371 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2372 2373 /* Arch may override these (weak) */ 2374 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2375 int pcibios_sriov_disable(struct pci_dev *pdev); 2376 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2377 #else 2378 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2379 { 2380 return -ENOSYS; 2381 } 2382 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2383 { 2384 return -ENOSYS; 2385 } 2386 2387 static inline int pci_iov_vf_id(struct pci_dev *dev) 2388 { 2389 return -ENOSYS; 2390 } 2391 2392 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2393 struct pci_driver *pf_driver) 2394 { 2395 return ERR_PTR(-EINVAL); 2396 } 2397 2398 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2399 { return -ENODEV; } 2400 2401 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2402 struct pci_dev *virtfn, int id) 2403 { 2404 return -ENODEV; 2405 } 2406 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2407 { 2408 return -ENOSYS; 2409 } 2410 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2411 int id) { } 2412 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2413 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2414 static inline int pci_vfs_assigned(struct pci_dev *dev) 2415 { return 0; } 2416 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2417 { return 0; } 2418 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2419 { return 0; } 2420 #define pci_sriov_configure_simple NULL 2421 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2422 { return 0; } 2423 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2424 #endif 2425 2426 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2427 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2428 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2429 #endif 2430 2431 /** 2432 * pci_pcie_cap - get the saved PCIe capability offset 2433 * @dev: PCI device 2434 * 2435 * PCIe capability offset is calculated at PCI device initialization 2436 * time and saved in the data structure. This function returns saved 2437 * PCIe capability offset. Using this instead of pci_find_capability() 2438 * reduces unnecessary search in the PCI configuration space. If you 2439 * need to calculate PCIe capability offset from raw device for some 2440 * reasons, please use pci_find_capability() instead. 2441 */ 2442 static inline int pci_pcie_cap(struct pci_dev *dev) 2443 { 2444 return dev->pcie_cap; 2445 } 2446 2447 /** 2448 * pci_is_pcie - check if the PCI device is PCI Express capable 2449 * @dev: PCI device 2450 * 2451 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2452 */ 2453 static inline bool pci_is_pcie(struct pci_dev *dev) 2454 { 2455 return pci_pcie_cap(dev); 2456 } 2457 2458 /** 2459 * pcie_caps_reg - get the PCIe Capabilities Register 2460 * @dev: PCI device 2461 */ 2462 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2463 { 2464 return dev->pcie_flags_reg; 2465 } 2466 2467 /** 2468 * pci_pcie_type - get the PCIe device/port type 2469 * @dev: PCI device 2470 */ 2471 static inline int pci_pcie_type(const struct pci_dev *dev) 2472 { 2473 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2474 } 2475 2476 /** 2477 * pcie_find_root_port - Get the PCIe root port device 2478 * @dev: PCI device 2479 * 2480 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2481 * for a given PCI/PCIe Device. 2482 */ 2483 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2484 { 2485 while (dev) { 2486 if (pci_is_pcie(dev) && 2487 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2488 return dev; 2489 dev = pci_upstream_bridge(dev); 2490 } 2491 2492 return NULL; 2493 } 2494 2495 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 2496 { 2497 /* 2498 * error_state is set in pci_dev_set_io_state() using xchg/cmpxchg() 2499 * and read w/o common lock. READ_ONCE() ensures compiler cannot cache 2500 * the value (e.g. inside the loop in pci_dev_wait()). 2501 */ 2502 return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure; 2503 } 2504 2505 void pci_request_acs(void); 2506 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2507 bool pci_acs_path_enabled(struct pci_dev *start, 2508 struct pci_dev *end, u16 acs_flags); 2509 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2510 2511 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2512 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2513 2514 /* Large Resource Data Type Tag Item Names */ 2515 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2516 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2517 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2518 2519 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2520 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2521 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2522 2523 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2524 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2525 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2526 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2527 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2528 2529 /** 2530 * pci_vpd_alloc - Allocate buffer and read VPD into it 2531 * @dev: PCI device 2532 * @size: pointer to field where VPD length is returned 2533 * 2534 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2535 */ 2536 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2537 2538 /** 2539 * pci_vpd_find_id_string - Locate id string in VPD 2540 * @buf: Pointer to buffered VPD data 2541 * @len: The length of the buffer area in which to search 2542 * @size: Pointer to field where length of id string is returned 2543 * 2544 * Returns the index of the id string or -ENOENT if not found. 2545 */ 2546 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2547 2548 /** 2549 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2550 * @buf: Pointer to buffered VPD data 2551 * @len: The length of the buffer area in which to search 2552 * @kw: The keyword to search for 2553 * @size: Pointer to field where length of found keyword data is returned 2554 * 2555 * Returns the index of the information field keyword data or -ENOENT if 2556 * not found. 2557 */ 2558 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2559 const char *kw, unsigned int *size); 2560 2561 /** 2562 * pci_vpd_check_csum - Check VPD checksum 2563 * @buf: Pointer to buffered VPD data 2564 * @len: VPD size 2565 * 2566 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2567 */ 2568 int pci_vpd_check_csum(const void *buf, unsigned int len); 2569 2570 /* PCI <-> OF binding helpers */ 2571 #ifdef CONFIG_OF 2572 struct device_node; 2573 struct irq_domain; 2574 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2575 bool pci_host_of_has_msi_map(struct device *dev); 2576 2577 /* Arch may override this (weak) */ 2578 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2579 2580 #else /* CONFIG_OF */ 2581 static inline struct irq_domain * 2582 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2583 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2584 #endif /* CONFIG_OF */ 2585 2586 static inline struct device_node * 2587 pci_device_to_OF_node(const struct pci_dev *pdev) 2588 { 2589 return pdev ? pdev->dev.of_node : NULL; 2590 } 2591 2592 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2593 { 2594 return bus ? bus->dev.of_node : NULL; 2595 } 2596 2597 #ifdef CONFIG_ACPI 2598 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2599 2600 void 2601 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2602 bool pci_pr3_present(struct pci_dev *pdev); 2603 #else 2604 static inline struct irq_domain * 2605 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2606 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2607 #endif 2608 2609 #ifdef CONFIG_EEH 2610 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2611 { 2612 return pdev->dev.archdata.edev; 2613 } 2614 #endif 2615 2616 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2617 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2618 int pci_for_each_dma_alias(struct pci_dev *pdev, 2619 int (*fn)(struct pci_dev *pdev, 2620 u16 alias, void *data), void *data); 2621 2622 /* Helper functions for operation of device flag */ 2623 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2624 { 2625 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2626 } 2627 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2628 { 2629 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2630 } 2631 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2632 { 2633 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2634 } 2635 2636 /** 2637 * pci_ari_enabled - query ARI forwarding status 2638 * @bus: the PCI bus 2639 * 2640 * Returns true if ARI forwarding is enabled. 2641 */ 2642 static inline bool pci_ari_enabled(struct pci_bus *bus) 2643 { 2644 return bus->self && bus->self->ari_enabled; 2645 } 2646 2647 /** 2648 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2649 * @pdev: PCI device to check 2650 * 2651 * Walk upwards from @pdev and check for each encountered bridge if it's part 2652 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2653 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2654 */ 2655 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2656 { 2657 struct pci_dev *parent = pdev; 2658 2659 if (pdev->is_thunderbolt) 2660 return true; 2661 2662 while ((parent = pci_upstream_bridge(parent))) 2663 if (parent->is_thunderbolt) 2664 return true; 2665 2666 return false; 2667 } 2668 2669 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2670 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2671 #endif 2672 2673 #include <linux/dma-mapping.h> 2674 2675 #define pci_printk(level, pdev, fmt, arg...) \ 2676 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2677 2678 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2679 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2680 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2681 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2682 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2683 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) 2684 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2685 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2686 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2687 2688 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2689 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2690 2691 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2692 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2693 2694 #define pci_WARN(pdev, condition, fmt, arg...) \ 2695 WARN(condition, "%s %s: " fmt, \ 2696 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2697 2698 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2699 WARN_ONCE(condition, "%s %s: " fmt, \ 2700 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2701 2702 #endif /* LINUX_PCI_H */ 2703