1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 #include <linux/args.h> 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <linux/msi_api.h> 42 #include <uapi/linux/pci.h> 43 44 #include <linux/pci_ids.h> 45 46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 47 PCI_STATUS_SIG_SYSTEM_ERROR | \ 48 PCI_STATUS_REC_MASTER_ABORT | \ 49 PCI_STATUS_REC_TARGET_ABORT | \ 50 PCI_STATUS_SIG_TARGET_ABORT | \ 51 PCI_STATUS_PARITY) 52 53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 54 #define PCI_NUM_RESET_METHODS 7 55 56 #define PCI_RESET_PROBE true 57 #define PCI_RESET_DO_RESET false 58 59 /* 60 * The PCI interface treats multi-function devices as independent 61 * devices. The slot/function address of each device is encoded 62 * in a single byte as follows: 63 * 64 * 7:3 = slot 65 * 2:0 = function 66 * 67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 68 * In the interest of not exposing interfaces to user-space unnecessarily, 69 * the following kernel-only defines are being added here. 70 */ 71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 74 75 /* pci_slot represents a physical slot */ 76 struct pci_slot { 77 struct pci_bus *bus; /* Bus this slot is on */ 78 struct list_head list; /* Node in list of slots */ 79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 81 struct kobject kobj; 82 }; 83 84 static inline const char *pci_slot_name(const struct pci_slot *slot) 85 { 86 return kobject_name(&slot->kobj); 87 } 88 89 /* File state for mmap()s on /proc/bus/pci/X/Y */ 90 enum pci_mmap_state { 91 pci_mmap_io, 92 pci_mmap_mem 93 }; 94 95 /* For PCI devices, the region numbers are assigned this way: */ 96 enum { 97 /* #0-5: standard PCI resources */ 98 PCI_STD_RESOURCES, 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 100 101 /* #6: expansion ROM resource */ 102 PCI_ROM_RESOURCE, 103 104 /* Device-specific resources */ 105 #ifdef CONFIG_PCI_IOV 106 PCI_IOV_RESOURCES, 107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 108 #endif 109 110 /* PCI-to-PCI (P2P) bridge windows */ 111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 114 115 /* CardBus bridge windows */ 116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 120 121 /* Total number of bridge resources for P2P and CardBus */ 122 #define PCI_BRIDGE_RESOURCE_NUM 4 123 124 /* Resources assigned to buses behind the bridge */ 125 PCI_BRIDGE_RESOURCES, 126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 127 PCI_BRIDGE_RESOURCE_NUM - 1, 128 129 /* Total resources associated with a PCI device */ 130 PCI_NUM_RESOURCES, 131 132 /* Preserve this for compatibility */ 133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 134 }; 135 136 /** 137 * enum pci_interrupt_pin - PCI INTx interrupt values 138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 139 * @PCI_INTERRUPT_INTA: PCI INTA pin 140 * @PCI_INTERRUPT_INTB: PCI INTB pin 141 * @PCI_INTERRUPT_INTC: PCI INTC pin 142 * @PCI_INTERRUPT_INTD: PCI INTD pin 143 * 144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 145 * PCI_INTERRUPT_PIN register. 146 */ 147 enum pci_interrupt_pin { 148 PCI_INTERRUPT_UNKNOWN, 149 PCI_INTERRUPT_INTA, 150 PCI_INTERRUPT_INTB, 151 PCI_INTERRUPT_INTC, 152 PCI_INTERRUPT_INTD, 153 }; 154 155 /* The number of legacy PCI INTx interrupts */ 156 #define PCI_NUM_INTX 4 157 158 /* 159 * Reading from a device that doesn't respond typically returns ~0. A 160 * successful read from a device may also return ~0, so you need additional 161 * information to reliably identify errors. 162 */ 163 #define PCI_ERROR_RESPONSE (~0ULL) 164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 166 167 /* 168 * pci_power_t values must match the bits in the Capabilities PME_Support 169 * and Control/Status PowerState fields in the Power Management capability. 170 */ 171 typedef int __bitwise pci_power_t; 172 173 #define PCI_D0 ((pci_power_t __force) 0) 174 #define PCI_D1 ((pci_power_t __force) 1) 175 #define PCI_D2 ((pci_power_t __force) 2) 176 #define PCI_D3hot ((pci_power_t __force) 3) 177 #define PCI_D3cold ((pci_power_t __force) 4) 178 #define PCI_UNKNOWN ((pci_power_t __force) 5) 179 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 180 181 /* Remember to update this when the list above changes! */ 182 extern const char *pci_power_names[]; 183 184 static inline const char *pci_power_name(pci_power_t state) 185 { 186 return pci_power_names[1 + (__force int) state]; 187 } 188 189 /** 190 * typedef pci_channel_state_t 191 * 192 * The pci_channel state describes connectivity between the CPU and 193 * the PCI device. If some PCI bus between here and the PCI device 194 * has crashed or locked up, this info is reflected here. 195 */ 196 typedef unsigned int __bitwise pci_channel_state_t; 197 198 enum { 199 /* I/O channel is in normal state */ 200 pci_channel_io_normal = (__force pci_channel_state_t) 1, 201 202 /* I/O to channel is blocked */ 203 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 204 205 /* PCI card is dead */ 206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 207 }; 208 209 typedef unsigned int __bitwise pcie_reset_state_t; 210 211 enum pcie_reset_state { 212 /* Reset is NOT asserted (Use to deassert reset) */ 213 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 214 215 /* Use #PERST to reset PCIe device */ 216 pcie_warm_reset = (__force pcie_reset_state_t) 2, 217 218 /* Use PCIe Hot Reset to reset device */ 219 pcie_hot_reset = (__force pcie_reset_state_t) 3 220 }; 221 222 typedef unsigned short __bitwise pci_dev_flags_t; 223 enum pci_dev_flags { 224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 226 /* Device configuration is irrevocably lost if disabled into D3 */ 227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 228 /* Provide indication device is assigned by a Virtual Machine Manager */ 229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 230 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 234 /* Do not use bus resets for device */ 235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 236 /* Do not use PM reset even if device advertises NoSoftRst- */ 237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 238 /* Get VPD from function 0 VPD */ 239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 240 /* A non-root bridge where translation occurs, stop alias search here */ 241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 242 /* Do not use FLR even if device advertises PCI_AF_CAP */ 243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 244 /* Don't use Relaxed Ordering for TLPs directed at this device */ 245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 246 /* Device does honor MSI masking despite saying otherwise */ 247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 248 }; 249 250 enum pci_irq_reroute_variant { 251 INTEL_IRQ_REROUTE_VARIANT = 1, 252 MAX_IRQ_REROUTE_VARIANTS = 3 253 }; 254 255 typedef unsigned short __bitwise pci_bus_flags_t; 256 enum pci_bus_flags { 257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 261 }; 262 263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 264 enum pcie_link_width { 265 PCIE_LNK_WIDTH_RESRV = 0x00, 266 PCIE_LNK_X1 = 0x01, 267 PCIE_LNK_X2 = 0x02, 268 PCIE_LNK_X4 = 0x04, 269 PCIE_LNK_X8 = 0x08, 270 PCIE_LNK_X12 = 0x0c, 271 PCIE_LNK_X16 = 0x10, 272 PCIE_LNK_X32 = 0x20, 273 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 274 }; 275 276 /* See matching string table in pci_speed_string() */ 277 enum pci_bus_speed { 278 PCI_SPEED_33MHz = 0x00, 279 PCI_SPEED_66MHz = 0x01, 280 PCI_SPEED_66MHz_PCIX = 0x02, 281 PCI_SPEED_100MHz_PCIX = 0x03, 282 PCI_SPEED_133MHz_PCIX = 0x04, 283 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 284 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 285 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 286 PCI_SPEED_66MHz_PCIX_266 = 0x09, 287 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 288 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 289 AGP_UNKNOWN = 0x0c, 290 AGP_1X = 0x0d, 291 AGP_2X = 0x0e, 292 AGP_4X = 0x0f, 293 AGP_8X = 0x10, 294 PCI_SPEED_66MHz_PCIX_533 = 0x11, 295 PCI_SPEED_100MHz_PCIX_533 = 0x12, 296 PCI_SPEED_133MHz_PCIX_533 = 0x13, 297 PCIE_SPEED_2_5GT = 0x14, 298 PCIE_SPEED_5_0GT = 0x15, 299 PCIE_SPEED_8_0GT = 0x16, 300 PCIE_SPEED_16_0GT = 0x17, 301 PCIE_SPEED_32_0GT = 0x18, 302 PCIE_SPEED_64_0GT = 0x19, 303 PCI_SPEED_UNKNOWN = 0xff, 304 }; 305 306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 308 309 struct pci_vpd { 310 struct mutex lock; 311 unsigned int len; 312 u8 cap; 313 }; 314 315 struct irq_affinity; 316 struct pcie_link_state; 317 struct pci_sriov; 318 struct pci_p2pdma; 319 struct rcec_ea; 320 321 /* The pci_dev structure describes PCI devices */ 322 struct pci_dev { 323 struct list_head bus_list; /* Node in per-bus list */ 324 struct pci_bus *bus; /* Bus this device is on */ 325 struct pci_bus *subordinate; /* Bus this device bridges to */ 326 327 void *sysdata; /* Hook for sys-specific extension */ 328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 329 struct pci_slot *slot; /* Physical slot this device is in */ 330 331 unsigned int devfn; /* Encoded device & function index */ 332 unsigned short vendor; 333 unsigned short device; 334 unsigned short subsystem_vendor; 335 unsigned short subsystem_device; 336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 337 u8 revision; /* PCI revision, low byte of class word */ 338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 339 #ifdef CONFIG_PCIEAER 340 u16 aer_cap; /* AER capability offset */ 341 struct aer_stats *aer_stats; /* AER stats for this device */ 342 #endif 343 #ifdef CONFIG_PCIEPORTBUS 344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 345 struct pci_dev *rcec; /* Associated RCEC device */ 346 #endif 347 u32 devcap; /* PCIe Device Capabilities */ 348 u8 pcie_cap; /* PCIe capability offset */ 349 u8 msi_cap; /* MSI capability offset */ 350 u8 msix_cap; /* MSI-X capability offset */ 351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 352 u8 rom_base_reg; /* Config register controlling ROM */ 353 u8 pin; /* Interrupt pin this device uses */ 354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 356 357 struct pci_driver *driver; /* Driver bound to this device */ 358 u64 dma_mask; /* Mask of the bits of bus address this 359 device implements. Normally this is 360 0xffffffff. You only need to change 361 this if your device has broken DMA 362 or supports 64-bit transfers. */ 363 364 struct device_dma_parameters dma_parms; 365 366 pci_power_t current_state; /* Current operating state. In ACPI, 367 this is D0-D3, D0 being fully 368 functional, and D3 being off. */ 369 u8 pm_cap; /* PM capability offset */ 370 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 371 unsigned int pme_support:5; /* Bitmask of states from which PME# 372 can be generated */ 373 unsigned int pme_poll:1; /* Poll device's PME status bit */ 374 unsigned int d1_support:1; /* Low power state D1 is supported */ 375 unsigned int d2_support:1; /* Low power state D2 is supported */ 376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 377 unsigned int no_d3cold:1; /* D3cold is forbidden */ 378 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 381 decoding during BAR sizing */ 382 unsigned int wakeup_prepared:1; 383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 386 controlled exclusively by 387 user sysfs */ 388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 389 bit manually */ 390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 392 393 #ifdef CONFIG_PCIEASPM 394 struct pcie_link_state *link_state; /* ASPM link state */ 395 u16 l1ss; /* L1SS Capability pointer */ 396 unsigned int ltr_path:1; /* Latency Tolerance Reporting 397 supported from root to here */ 398 #endif 399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 401 402 pci_channel_state_t error_state; /* Current connectivity state */ 403 struct device dev; /* Generic device interface */ 404 405 int cfg_size; /* Size of config space */ 406 407 /* 408 * Instead of touching interrupt line and base address registers 409 * directly, use the values stored here. They might be different! 410 */ 411 unsigned int irq; 412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ 414 415 bool match_driver; /* Skip attaching driver */ 416 417 unsigned int transparent:1; /* Subtractive decode bridge */ 418 unsigned int io_window:1; /* Bridge has I/O window */ 419 unsigned int pref_window:1; /* Bridge has pref mem window */ 420 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 421 unsigned int multifunction:1; /* Multi-function device */ 422 423 unsigned int is_busmaster:1; /* Is busmaster */ 424 unsigned int no_msi:1; /* May not use MSI */ 425 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 426 unsigned int block_cfg_access:1; /* Config space access blocked */ 427 unsigned int broken_parity_status:1; /* Generates false positive parity */ 428 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 429 unsigned int msi_enabled:1; 430 unsigned int msix_enabled:1; 431 unsigned int ari_enabled:1; /* ARI forwarding */ 432 unsigned int ats_enabled:1; /* Address Translation Svc */ 433 unsigned int pasid_enabled:1; /* Process Address Space ID */ 434 unsigned int pri_enabled:1; /* Page Request Interface */ 435 unsigned int is_managed:1; /* Managed via devres */ 436 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 437 unsigned int needs_freset:1; /* Requires fundamental reset */ 438 unsigned int state_saved:1; 439 unsigned int is_physfn:1; 440 unsigned int is_virtfn:1; 441 unsigned int is_hotplug_bridge:1; 442 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 443 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 444 /* 445 * Devices marked being untrusted are the ones that can potentially 446 * execute DMA attacks and similar. They are typically connected 447 * through external ports such as Thunderbolt but not limited to 448 * that. When an IOMMU is enabled they should be getting full 449 * mappings to make sure they cannot access arbitrary memory. 450 */ 451 unsigned int untrusted:1; 452 /* 453 * Info from the platform, e.g., ACPI or device tree, may mark a 454 * device as "external-facing". An external-facing device is 455 * itself internal but devices downstream from it are external. 456 */ 457 unsigned int external_facing:1; 458 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 459 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 460 unsigned int irq_managed:1; 461 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 462 unsigned int is_probed:1; /* Device probing in progress */ 463 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 464 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 465 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 466 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 467 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ 468 pci_dev_flags_t dev_flags; 469 atomic_t enable_cnt; /* pci_enable_device has been called */ 470 471 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */ 472 u32 saved_config_space[16]; /* Config space saved at suspend time */ 473 struct hlist_head saved_cap_space; 474 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 475 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 476 477 #ifdef CONFIG_HOTPLUG_PCI_PCIE 478 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 479 #endif 480 #ifdef CONFIG_PCIE_PTM 481 u16 ptm_cap; /* PTM Capability */ 482 unsigned int ptm_root:1; 483 unsigned int ptm_enabled:1; 484 u8 ptm_granularity; 485 #endif 486 #ifdef CONFIG_PCI_MSI 487 void __iomem *msix_base; 488 raw_spinlock_t msi_lock; 489 #endif 490 struct pci_vpd vpd; 491 #ifdef CONFIG_PCIE_DPC 492 u16 dpc_cap; 493 unsigned int dpc_rp_extensions:1; 494 u8 dpc_rp_log_size; 495 #endif 496 #ifdef CONFIG_PCI_ATS 497 union { 498 struct pci_sriov *sriov; /* PF: SR-IOV info */ 499 struct pci_dev *physfn; /* VF: related PF */ 500 }; 501 u16 ats_cap; /* ATS Capability offset */ 502 u8 ats_stu; /* ATS Smallest Translation Unit */ 503 #endif 504 #ifdef CONFIG_PCI_PRI 505 u16 pri_cap; /* PRI Capability offset */ 506 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 507 unsigned int pasid_required:1; /* PRG Response PASID Required */ 508 #endif 509 #ifdef CONFIG_PCI_PASID 510 u16 pasid_cap; /* PASID Capability offset */ 511 u16 pasid_features; 512 #endif 513 #ifdef CONFIG_PCI_P2PDMA 514 struct pci_p2pdma __rcu *p2pdma; 515 #endif 516 #ifdef CONFIG_PCI_DOE 517 struct xarray doe_mbs; /* Data Object Exchange mailboxes */ 518 #endif 519 u16 acs_cap; /* ACS Capability offset */ 520 phys_addr_t rom; /* Physical address if not from BAR */ 521 size_t romlen; /* Length if not from BAR */ 522 /* 523 * Driver name to force a match. Do not set directly, because core 524 * frees it. Use driver_set_override() to set or clear it. 525 */ 526 const char *driver_override; 527 528 unsigned long priv_flags; /* Private flags for the PCI driver */ 529 530 /* These methods index pci_reset_fn_methods[] */ 531 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 532 }; 533 534 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 535 { 536 #ifdef CONFIG_PCI_IOV 537 if (dev->is_virtfn) 538 dev = dev->physfn; 539 #endif 540 return dev; 541 } 542 543 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 544 545 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 546 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 547 548 static inline int pci_channel_offline(struct pci_dev *pdev) 549 { 550 return (pdev->error_state != pci_channel_io_normal); 551 } 552 553 /* 554 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 555 * Group number is limited to a 16-bit value, therefore (int)-1 is 556 * not a valid PCI domain number, and can be used as a sentinel 557 * value indicating ->domain_nr is not set by the driver (and 558 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 559 * pci_bus_find_domain_nr()). 560 */ 561 #define PCI_DOMAIN_NR_NOT_SET (-1) 562 563 struct pci_host_bridge { 564 struct device dev; 565 struct pci_bus *bus; /* Root bus */ 566 struct pci_ops *ops; 567 struct pci_ops *child_ops; 568 void *sysdata; 569 int busnr; 570 int domain_nr; 571 struct list_head windows; /* resource_entry */ 572 struct list_head dma_ranges; /* dma ranges resource list */ 573 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 574 int (*map_irq)(const struct pci_dev *, u8, u8); 575 void (*release_fn)(struct pci_host_bridge *); 576 void *release_data; 577 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 578 unsigned int no_ext_tags:1; /* No Extended Tags */ 579 unsigned int no_inc_mrrs:1; /* No Increase MRRS */ 580 unsigned int native_aer:1; /* OS may use PCIe AER */ 581 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 582 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 583 unsigned int native_pme:1; /* OS may use PCIe PME */ 584 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 585 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 586 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ 587 unsigned int preserve_config:1; /* Preserve FW resource setup */ 588 unsigned int size_windows:1; /* Enable root bus sizing */ 589 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 590 591 /* Resource alignment requirements */ 592 resource_size_t (*align_resource)(struct pci_dev *dev, 593 const struct resource *res, 594 resource_size_t start, 595 resource_size_t size, 596 resource_size_t align); 597 unsigned long private[] ____cacheline_aligned; 598 }; 599 600 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 601 602 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 603 { 604 return (void *)bridge->private; 605 } 606 607 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 608 { 609 return container_of(priv, struct pci_host_bridge, private); 610 } 611 612 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 613 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 614 size_t priv); 615 void pci_free_host_bridge(struct pci_host_bridge *bridge); 616 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 617 618 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 619 void (*release_fn)(struct pci_host_bridge *), 620 void *release_data); 621 622 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 623 624 /* 625 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 626 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 627 * buses below host bridges or subtractive decode bridges) go in the list. 628 * Use pci_bus_for_each_resource() to iterate through all the resources. 629 */ 630 631 /* 632 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 633 * and there's no way to program the bridge with the details of the window. 634 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 635 * decode bit set, because they are explicit and can be programmed with _SRS. 636 */ 637 #define PCI_SUBTRACTIVE_DECODE 0x1 638 639 struct pci_bus_resource { 640 struct list_head list; 641 struct resource *res; 642 unsigned int flags; 643 }; 644 645 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 646 647 struct pci_bus { 648 struct list_head node; /* Node in list of buses */ 649 struct pci_bus *parent; /* Parent bus this bridge is on */ 650 struct list_head children; /* List of child buses */ 651 struct list_head devices; /* List of devices on this bus */ 652 struct pci_dev *self; /* Bridge device as seen by parent */ 653 struct list_head slots; /* List of slots on this bus; 654 protected by pci_slot_mutex */ 655 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 656 struct list_head resources; /* Address space routed to this bus */ 657 struct resource busn_res; /* Bus numbers routed to this bus */ 658 659 struct pci_ops *ops; /* Configuration access functions */ 660 void *sysdata; /* Hook for sys-specific extension */ 661 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 662 663 unsigned char number; /* Bus number */ 664 unsigned char primary; /* Number of primary bridge */ 665 unsigned char max_bus_speed; /* enum pci_bus_speed */ 666 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 667 #ifdef CONFIG_PCI_DOMAINS_GENERIC 668 int domain_nr; 669 #endif 670 671 char name[48]; 672 673 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 674 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 675 struct device *bridge; 676 struct device dev; 677 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 678 struct bin_attribute *legacy_mem; /* Legacy mem */ 679 unsigned int is_added:1; 680 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 681 }; 682 683 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 684 685 static inline u16 pci_dev_id(struct pci_dev *dev) 686 { 687 return PCI_DEVID(dev->bus->number, dev->devfn); 688 } 689 690 /* 691 * Returns true if the PCI bus is root (behind host-PCI bridge), 692 * false otherwise 693 * 694 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 695 * This is incorrect because "virtual" buses added for SR-IOV (via 696 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 697 */ 698 static inline bool pci_is_root_bus(struct pci_bus *pbus) 699 { 700 return !(pbus->parent); 701 } 702 703 /** 704 * pci_is_bridge - check if the PCI device is a bridge 705 * @dev: PCI device 706 * 707 * Return true if the PCI device is bridge whether it has subordinate 708 * or not. 709 */ 710 static inline bool pci_is_bridge(struct pci_dev *dev) 711 { 712 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 713 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 714 } 715 716 /** 717 * pci_is_vga - check if the PCI device is a VGA device 718 * 719 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define 720 * VGA Base Class and Sub-Classes: 721 * 722 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible 723 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code) 724 * 725 * Return true if the PCI device is a VGA device and uses the legacy VGA 726 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and 727 * aliases). 728 */ 729 static inline bool pci_is_vga(struct pci_dev *pdev) 730 { 731 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) 732 return true; 733 734 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA) 735 return true; 736 737 return false; 738 } 739 740 #define for_each_pci_bridge(dev, bus) \ 741 list_for_each_entry(dev, &bus->devices, bus_list) \ 742 if (!pci_is_bridge(dev)) {} else 743 744 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 745 { 746 dev = pci_physfn(dev); 747 if (pci_is_root_bus(dev->bus)) 748 return NULL; 749 750 return dev->bus->self; 751 } 752 753 #ifdef CONFIG_PCI_MSI 754 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 755 { 756 return pci_dev->msi_enabled || pci_dev->msix_enabled; 757 } 758 #else 759 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 760 #endif 761 762 /* Error values that may be returned by PCI functions */ 763 #define PCIBIOS_SUCCESSFUL 0x00 764 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 765 #define PCIBIOS_BAD_VENDOR_ID 0x83 766 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 767 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 768 #define PCIBIOS_SET_FAILED 0x88 769 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 770 771 /* Translate above to generic errno for passing back through non-PCI code */ 772 static inline int pcibios_err_to_errno(int err) 773 { 774 if (err <= PCIBIOS_SUCCESSFUL) 775 return err; /* Assume already errno */ 776 777 switch (err) { 778 case PCIBIOS_FUNC_NOT_SUPPORTED: 779 return -ENOENT; 780 case PCIBIOS_BAD_VENDOR_ID: 781 return -ENOTTY; 782 case PCIBIOS_DEVICE_NOT_FOUND: 783 return -ENODEV; 784 case PCIBIOS_BAD_REGISTER_NUMBER: 785 return -EFAULT; 786 case PCIBIOS_SET_FAILED: 787 return -EIO; 788 case PCIBIOS_BUFFER_TOO_SMALL: 789 return -ENOSPC; 790 } 791 792 return -ERANGE; 793 } 794 795 /* Low-level architecture-dependent routines */ 796 797 struct pci_ops { 798 int (*add_bus)(struct pci_bus *bus); 799 void (*remove_bus)(struct pci_bus *bus); 800 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 801 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 802 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 803 }; 804 805 /* 806 * ACPI needs to be able to access PCI config space before we've done a 807 * PCI bus scan and created pci_bus structures. 808 */ 809 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 810 int reg, int len, u32 *val); 811 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 812 int reg, int len, u32 val); 813 814 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 815 typedef u64 pci_bus_addr_t; 816 #else 817 typedef u32 pci_bus_addr_t; 818 #endif 819 820 struct pci_bus_region { 821 pci_bus_addr_t start; 822 pci_bus_addr_t end; 823 }; 824 825 struct pci_dynids { 826 spinlock_t lock; /* Protects list, index */ 827 struct list_head list; /* For IDs added at runtime */ 828 }; 829 830 831 /* 832 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 833 * a set of callbacks in struct pci_error_handlers, that device driver 834 * will be notified of PCI bus errors, and will be driven to recovery 835 * when an error occurs. 836 */ 837 838 typedef unsigned int __bitwise pci_ers_result_t; 839 840 enum pci_ers_result { 841 /* No result/none/not supported in device driver */ 842 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 843 844 /* Device driver can recover without slot reset */ 845 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 846 847 /* Device driver wants slot to be reset */ 848 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 849 850 /* Device has completely failed, is unrecoverable */ 851 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 852 853 /* Device driver is fully recovered and operational */ 854 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 855 856 /* No AER capabilities registered for the driver */ 857 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 858 }; 859 860 /* PCI bus error event callbacks */ 861 struct pci_error_handlers { 862 /* PCI bus error detected on this device */ 863 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 864 pci_channel_state_t error); 865 866 /* MMIO has been re-enabled, but not DMA */ 867 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 868 869 /* PCI slot has been reset */ 870 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 871 872 /* PCI function reset prepare or completed */ 873 void (*reset_prepare)(struct pci_dev *dev); 874 void (*reset_done)(struct pci_dev *dev); 875 876 /* Device driver may resume normal operations */ 877 void (*resume)(struct pci_dev *dev); 878 879 /* Allow device driver to record more details of a correctable error */ 880 void (*cor_error_detected)(struct pci_dev *dev); 881 }; 882 883 884 struct module; 885 886 /** 887 * struct pci_driver - PCI driver structure 888 * @node: List of driver structures. 889 * @name: Driver name. 890 * @id_table: Pointer to table of device IDs the driver is 891 * interested in. Most drivers should export this 892 * table using MODULE_DEVICE_TABLE(pci,...). 893 * @probe: This probing function gets called (during execution 894 * of pci_register_driver() for already existing 895 * devices or later if a new device gets inserted) for 896 * all PCI devices which match the ID table and are not 897 * "owned" by the other drivers yet. This function gets 898 * passed a "struct pci_dev \*" for each device whose 899 * entry in the ID table matches the device. The probe 900 * function returns zero when the driver chooses to 901 * take "ownership" of the device or an error code 902 * (negative number) otherwise. 903 * The probe function always gets called from process 904 * context, so it can sleep. 905 * @remove: The remove() function gets called whenever a device 906 * being handled by this driver is removed (either during 907 * deregistration of the driver or when it's manually 908 * pulled out of a hot-pluggable slot). 909 * The remove function always gets called from process 910 * context, so it can sleep. 911 * @suspend: Put device into low power state. 912 * @resume: Wake device from low power state. 913 * (Please see Documentation/power/pci.rst for descriptions 914 * of PCI Power Management and the related functions.) 915 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 916 * Intended to stop any idling DMA operations. 917 * Useful for enabling wake-on-lan (NIC) or changing 918 * the power state of a device before reboot. 919 * e.g. drivers/net/e100.c. 920 * @sriov_configure: Optional driver callback to allow configuration of 921 * number of VFs to enable via sysfs "sriov_numvfs" file. 922 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 923 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 924 * This will change MSI-X Table Size in the VF Message Control 925 * registers. 926 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 927 * MSI-X vectors available for distribution to the VFs. 928 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 929 * @groups: Sysfs attribute groups. 930 * @dev_groups: Attributes attached to the device that will be 931 * created once it is bound to the driver. 932 * @driver: Driver model structure. 933 * @dynids: List of dynamically added device IDs. 934 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. 935 * For most device drivers, no need to care about this flag 936 * as long as all DMAs are handled through the kernel DMA API. 937 * For some special ones, for example VFIO drivers, they know 938 * how to manage the DMA themselves and set this flag so that 939 * the IOMMU layer will allow them to setup and manage their 940 * own I/O address space. 941 */ 942 struct pci_driver { 943 struct list_head node; 944 const char *name; 945 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 946 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 947 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 948 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 949 int (*resume)(struct pci_dev *dev); /* Device woken up */ 950 void (*shutdown)(struct pci_dev *dev); 951 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 952 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 953 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 954 const struct pci_error_handlers *err_handler; 955 const struct attribute_group **groups; 956 const struct attribute_group **dev_groups; 957 struct device_driver driver; 958 struct pci_dynids dynids; 959 bool driver_managed_dma; 960 }; 961 962 static inline struct pci_driver *to_pci_driver(struct device_driver *drv) 963 { 964 return drv ? container_of(drv, struct pci_driver, driver) : NULL; 965 } 966 967 /** 968 * PCI_DEVICE - macro used to describe a specific PCI device 969 * @vend: the 16 bit PCI Vendor ID 970 * @dev: the 16 bit PCI Device ID 971 * 972 * This macro is used to create a struct pci_device_id that matches a 973 * specific device. The subvendor and subdevice fields will be set to 974 * PCI_ANY_ID. 975 */ 976 #define PCI_DEVICE(vend,dev) \ 977 .vendor = (vend), .device = (dev), \ 978 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 979 980 /** 981 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 982 * override_only flags. 983 * @vend: the 16 bit PCI Vendor ID 984 * @dev: the 16 bit PCI Device ID 985 * @driver_override: the 32 bit PCI Device override_only 986 * 987 * This macro is used to create a struct pci_device_id that matches only a 988 * driver_override device. The subvendor and subdevice fields will be set to 989 * PCI_ANY_ID. 990 */ 991 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 992 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 993 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 994 995 /** 996 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 997 * "driver_override" PCI device. 998 * @vend: the 16 bit PCI Vendor ID 999 * @dev: the 16 bit PCI Device ID 1000 * 1001 * This macro is used to create a struct pci_device_id that matches a 1002 * specific device. The subvendor and subdevice fields will be set to 1003 * PCI_ANY_ID and the driver_override will be set to 1004 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 1005 */ 1006 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 1007 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 1008 1009 /** 1010 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 1011 * @vend: the 16 bit PCI Vendor ID 1012 * @dev: the 16 bit PCI Device ID 1013 * @subvend: the 16 bit PCI Subvendor ID 1014 * @subdev: the 16 bit PCI Subdevice ID 1015 * 1016 * This macro is used to create a struct pci_device_id that matches a 1017 * specific device with subsystem information. 1018 */ 1019 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1020 .vendor = (vend), .device = (dev), \ 1021 .subvendor = (subvend), .subdevice = (subdev) 1022 1023 /** 1024 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 1025 * @dev_class: the class, subclass, prog-if triple for this device 1026 * @dev_class_mask: the class mask for this device 1027 * 1028 * This macro is used to create a struct pci_device_id that matches a 1029 * specific PCI class. The vendor, device, subvendor, and subdevice 1030 * fields will be set to PCI_ANY_ID. 1031 */ 1032 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 1033 .class = (dev_class), .class_mask = (dev_class_mask), \ 1034 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1035 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1036 1037 /** 1038 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 1039 * @vend: the vendor name 1040 * @dev: the 16 bit PCI Device ID 1041 * 1042 * This macro is used to create a struct pci_device_id that matches a 1043 * specific PCI device. The subvendor, and subdevice fields will be set 1044 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1045 * private data. 1046 */ 1047 #define PCI_VDEVICE(vend, dev) \ 1048 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1049 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1050 1051 /** 1052 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1053 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1054 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1055 * @data: the driver data to be filled 1056 * 1057 * This macro is used to create a struct pci_device_id that matches a 1058 * specific PCI device. The subvendor, and subdevice fields will be set 1059 * to PCI_ANY_ID. 1060 */ 1061 #define PCI_DEVICE_DATA(vend, dev, data) \ 1062 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1063 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1064 .driver_data = (kernel_ulong_t)(data) 1065 1066 enum { 1067 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1068 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1069 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1070 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1071 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1072 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1073 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1074 }; 1075 1076 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1077 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1078 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1079 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1080 1081 /* These external functions are only available when PCI support is enabled */ 1082 #ifdef CONFIG_PCI 1083 1084 extern unsigned int pci_flags; 1085 1086 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1087 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1088 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1089 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1090 1091 void pcie_bus_configure_settings(struct pci_bus *bus); 1092 1093 enum pcie_bus_config_types { 1094 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1095 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1096 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1097 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1098 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1099 }; 1100 1101 extern enum pcie_bus_config_types pcie_bus_config; 1102 1103 extern struct bus_type pci_bus_type; 1104 1105 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1106 * code, or PCI core code. */ 1107 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1108 /* Some device drivers need know if PCI is initiated */ 1109 int no_pci_devices(void); 1110 1111 void pcibios_resource_survey_bus(struct pci_bus *bus); 1112 void pcibios_bus_add_device(struct pci_dev *pdev); 1113 void pcibios_add_bus(struct pci_bus *bus); 1114 void pcibios_remove_bus(struct pci_bus *bus); 1115 void pcibios_fixup_bus(struct pci_bus *); 1116 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1117 /* Architecture-specific versions may override this (weak) */ 1118 char *pcibios_setup(char *str); 1119 1120 /* Used only when drivers/pci/setup.c is used */ 1121 resource_size_t pcibios_align_resource(void *, const struct resource *, 1122 resource_size_t, 1123 resource_size_t); 1124 1125 /* Weak but can be overridden by arch */ 1126 void pci_fixup_cardbus(struct pci_bus *); 1127 1128 /* Generic PCI functions used internally */ 1129 1130 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1131 struct resource *res); 1132 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1133 struct pci_bus_region *region); 1134 void pcibios_scan_specific_bus(int busn); 1135 struct pci_bus *pci_find_bus(int domain, int busnr); 1136 void pci_bus_add_devices(const struct pci_bus *bus); 1137 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1138 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1139 struct pci_ops *ops, void *sysdata, 1140 struct list_head *resources); 1141 int pci_host_probe(struct pci_host_bridge *bridge); 1142 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1143 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1144 void pci_bus_release_busn_res(struct pci_bus *b); 1145 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1146 struct pci_ops *ops, void *sysdata, 1147 struct list_head *resources); 1148 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1149 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1150 int busnr); 1151 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1152 const char *name, 1153 struct hotplug_slot *hotplug); 1154 void pci_destroy_slot(struct pci_slot *slot); 1155 #ifdef CONFIG_SYSFS 1156 void pci_dev_assign_slot(struct pci_dev *dev); 1157 #else 1158 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1159 #endif 1160 int pci_scan_slot(struct pci_bus *bus, int devfn); 1161 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1162 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1163 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1164 void pci_bus_add_device(struct pci_dev *dev); 1165 void pci_read_bridge_bases(struct pci_bus *child); 1166 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1167 struct resource *res); 1168 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1169 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1170 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1171 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1172 void pci_dev_put(struct pci_dev *dev); 1173 void pci_remove_bus(struct pci_bus *b); 1174 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1175 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1176 void pci_stop_root_bus(struct pci_bus *bus); 1177 void pci_remove_root_bus(struct pci_bus *bus); 1178 void pci_setup_cardbus(struct pci_bus *bus); 1179 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1180 void pci_sort_breadthfirst(void); 1181 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1182 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1183 1184 /* Generic PCI functions exported to card drivers */ 1185 1186 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1187 u8 pci_find_capability(struct pci_dev *dev, int cap); 1188 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1189 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1190 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1191 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1192 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1193 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1194 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1195 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1196 1197 u64 pci_get_dsn(struct pci_dev *dev); 1198 1199 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1200 struct pci_dev *from); 1201 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1202 unsigned int ss_vendor, unsigned int ss_device, 1203 struct pci_dev *from); 1204 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1205 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1206 unsigned int devfn); 1207 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1208 struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); 1209 1210 int pci_dev_present(const struct pci_device_id *ids); 1211 1212 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1213 int where, u8 *val); 1214 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1215 int where, u16 *val); 1216 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1217 int where, u32 *val); 1218 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1219 int where, u8 val); 1220 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1221 int where, u16 val); 1222 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1223 int where, u32 val); 1224 1225 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1226 int where, int size, u32 *val); 1227 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1228 int where, int size, u32 val); 1229 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1230 int where, int size, u32 *val); 1231 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1232 int where, int size, u32 val); 1233 1234 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1235 1236 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1237 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1238 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1239 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1240 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1241 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1242 void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos, 1243 u32 clear, u32 set); 1244 1245 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1246 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1247 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1248 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1249 int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, 1250 u16 clear, u16 set); 1251 int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos, 1252 u16 clear, u16 set); 1253 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1254 u32 clear, u32 set); 1255 1256 /** 1257 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers 1258 * @dev: PCI device structure of the PCI Express device 1259 * @pos: PCI Express Capability Register 1260 * @clear: Clear bitmask 1261 * @set: Set bitmask 1262 * 1263 * Perform a Read-Modify-Write (RMW) operation using @clear and @set 1264 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express 1265 * Capability Registers are accessed concurrently in RMW fashion, hence 1266 * require locking which is handled transparently to the caller. 1267 */ 1268 static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, 1269 int pos, 1270 u16 clear, u16 set) 1271 { 1272 switch (pos) { 1273 case PCI_EXP_LNKCTL: 1274 case PCI_EXP_RTCTL: 1275 return pcie_capability_clear_and_set_word_locked(dev, pos, 1276 clear, set); 1277 default: 1278 return pcie_capability_clear_and_set_word_unlocked(dev, pos, 1279 clear, set); 1280 } 1281 } 1282 1283 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1284 u16 set) 1285 { 1286 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1287 } 1288 1289 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1290 u32 set) 1291 { 1292 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1293 } 1294 1295 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1296 u16 clear) 1297 { 1298 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1299 } 1300 1301 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1302 u32 clear) 1303 { 1304 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1305 } 1306 1307 /* User-space driven config access */ 1308 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1309 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1310 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1311 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1312 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1313 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1314 1315 int __must_check pci_enable_device(struct pci_dev *dev); 1316 int __must_check pci_enable_device_io(struct pci_dev *dev); 1317 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1318 int __must_check pci_reenable_device(struct pci_dev *); 1319 int __must_check pcim_enable_device(struct pci_dev *pdev); 1320 void pcim_pin_device(struct pci_dev *pdev); 1321 1322 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1323 { 1324 /* 1325 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1326 * writable and no quirk has marked the feature broken. 1327 */ 1328 return !pdev->broken_intx_masking; 1329 } 1330 1331 static inline int pci_is_enabled(struct pci_dev *pdev) 1332 { 1333 return (atomic_read(&pdev->enable_cnt) > 0); 1334 } 1335 1336 static inline int pci_is_managed(struct pci_dev *pdev) 1337 { 1338 return pdev->is_managed; 1339 } 1340 1341 void pci_disable_device(struct pci_dev *dev); 1342 1343 extern unsigned int pcibios_max_latency; 1344 void pci_set_master(struct pci_dev *dev); 1345 void pci_clear_master(struct pci_dev *dev); 1346 1347 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1348 int pci_set_cacheline_size(struct pci_dev *dev); 1349 int __must_check pci_set_mwi(struct pci_dev *dev); 1350 int __must_check pcim_set_mwi(struct pci_dev *dev); 1351 int pci_try_set_mwi(struct pci_dev *dev); 1352 void pci_clear_mwi(struct pci_dev *dev); 1353 void pci_disable_parity(struct pci_dev *dev); 1354 void pci_intx(struct pci_dev *dev, int enable); 1355 bool pci_check_and_mask_intx(struct pci_dev *dev); 1356 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1357 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1358 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1359 int pcix_get_max_mmrbc(struct pci_dev *dev); 1360 int pcix_get_mmrbc(struct pci_dev *dev); 1361 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1362 int pcie_get_readrq(struct pci_dev *dev); 1363 int pcie_set_readrq(struct pci_dev *dev, int rq); 1364 int pcie_get_mps(struct pci_dev *dev); 1365 int pcie_set_mps(struct pci_dev *dev, int mps); 1366 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1367 enum pci_bus_speed *speed, 1368 enum pcie_link_width *width); 1369 void pcie_print_link_status(struct pci_dev *dev); 1370 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1371 int pcie_flr(struct pci_dev *dev); 1372 int __pci_reset_function_locked(struct pci_dev *dev); 1373 int pci_reset_function(struct pci_dev *dev); 1374 int pci_reset_function_locked(struct pci_dev *dev); 1375 int pci_try_reset_function(struct pci_dev *dev); 1376 int pci_probe_reset_slot(struct pci_slot *slot); 1377 int pci_probe_reset_bus(struct pci_bus *bus); 1378 int pci_reset_bus(struct pci_dev *dev); 1379 void pci_reset_secondary_bus(struct pci_dev *dev); 1380 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1381 void pci_update_resource(struct pci_dev *dev, int resno); 1382 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1383 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1384 void pci_release_resource(struct pci_dev *dev, int resno); 1385 static inline int pci_rebar_bytes_to_size(u64 bytes) 1386 { 1387 bytes = roundup_pow_of_two(bytes); 1388 1389 /* Return BAR size as defined in the resizable BAR specification */ 1390 return max(ilog2(bytes), 20) - 20; 1391 } 1392 1393 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1394 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1395 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1396 bool pci_device_is_present(struct pci_dev *pdev); 1397 void pci_ignore_hotplug(struct pci_dev *dev); 1398 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1399 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1400 1401 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1402 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1403 const char *fmt, ...); 1404 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1405 1406 /* ROM control related routines */ 1407 int pci_enable_rom(struct pci_dev *pdev); 1408 void pci_disable_rom(struct pci_dev *pdev); 1409 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1410 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1411 1412 /* Power management related routines */ 1413 int pci_save_state(struct pci_dev *dev); 1414 void pci_restore_state(struct pci_dev *dev); 1415 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1416 int pci_load_saved_state(struct pci_dev *dev, 1417 struct pci_saved_state *state); 1418 int pci_load_and_free_saved_state(struct pci_dev *dev, 1419 struct pci_saved_state **state); 1420 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1421 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1422 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1423 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1424 void pci_pme_active(struct pci_dev *dev, bool enable); 1425 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1426 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1427 int pci_prepare_to_sleep(struct pci_dev *dev); 1428 int pci_back_from_sleep(struct pci_dev *dev); 1429 bool pci_dev_run_wake(struct pci_dev *dev); 1430 void pci_d3cold_enable(struct pci_dev *dev); 1431 void pci_d3cold_disable(struct pci_dev *dev); 1432 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1433 void pci_resume_bus(struct pci_bus *bus); 1434 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1435 1436 /* For use by arch with custom probe code */ 1437 void set_pcie_port_type(struct pci_dev *pdev); 1438 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1439 1440 /* Functions for PCI Hotplug drivers to use */ 1441 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1442 unsigned int pci_rescan_bus(struct pci_bus *bus); 1443 void pci_lock_rescan_remove(void); 1444 void pci_unlock_rescan_remove(void); 1445 1446 /* Vital Product Data routines */ 1447 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1448 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1449 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1450 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1451 1452 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1453 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1454 void pci_bus_assign_resources(const struct pci_bus *bus); 1455 void pci_bus_claim_resources(struct pci_bus *bus); 1456 void pci_bus_size_bridges(struct pci_bus *bus); 1457 int pci_claim_resource(struct pci_dev *, int); 1458 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1459 void pci_assign_unassigned_resources(void); 1460 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1461 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1462 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1463 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1464 int pci_enable_resources(struct pci_dev *, int mask); 1465 void pci_assign_irq(struct pci_dev *dev); 1466 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1467 #define HAVE_PCI_REQ_REGIONS 2 1468 int __must_check pci_request_regions(struct pci_dev *, const char *); 1469 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1470 void pci_release_regions(struct pci_dev *); 1471 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1472 void pci_release_region(struct pci_dev *, int); 1473 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1474 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1475 void pci_release_selected_regions(struct pci_dev *, int); 1476 1477 static inline __must_check struct resource * 1478 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, 1479 unsigned int len, const char *name) 1480 { 1481 return __request_region(&pdev->driver_exclusive_resource, offset, len, 1482 name, IORESOURCE_EXCLUSIVE); 1483 } 1484 1485 static inline void pci_release_config_region(struct pci_dev *pdev, 1486 unsigned int offset, 1487 unsigned int len) 1488 { 1489 __release_region(&pdev->driver_exclusive_resource, offset, len); 1490 } 1491 1492 /* drivers/pci/bus.c */ 1493 void pci_add_resource(struct list_head *resources, struct resource *res); 1494 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1495 resource_size_t offset); 1496 void pci_free_resource_list(struct list_head *resources); 1497 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1498 unsigned int flags); 1499 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1500 void pci_bus_remove_resources(struct pci_bus *bus); 1501 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res); 1502 int devm_request_pci_bus_resources(struct device *dev, 1503 struct list_head *resources); 1504 1505 /* Temporary until new and working PCI SBR API in place */ 1506 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1507 1508 #define __pci_bus_for_each_res0(bus, res, ...) \ 1509 for (unsigned int __b = 0; \ 1510 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1511 __b++) 1512 1513 #define __pci_bus_for_each_res1(bus, res, __b) \ 1514 for (__b = 0; \ 1515 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1516 __b++) 1517 1518 /** 1519 * pci_bus_for_each_resource - iterate over PCI bus resources 1520 * @bus: the PCI bus 1521 * @res: pointer to the current resource 1522 * @...: optional index of the current resource 1523 * 1524 * Iterate over PCI bus resources. The first part is to go over PCI bus 1525 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries. 1526 * After that continue with the separate list of the additional resources, 1527 * if not empty. That's why the Logical OR is being used. 1528 * 1529 * Possible usage: 1530 * 1531 * struct pci_bus *bus = ...; 1532 * struct resource *res; 1533 * unsigned int i; 1534 * 1535 * // With optional index 1536 * pci_bus_for_each_resource(bus, res, i) 1537 * pr_info("PCI bus resource[%u]: %pR\n", i, res); 1538 * 1539 * // Without index 1540 * pci_bus_for_each_resource(bus, res) 1541 * _do_something_(res); 1542 */ 1543 #define pci_bus_for_each_resource(bus, res, ...) \ 1544 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 1545 (bus, res, __VA_ARGS__) 1546 1547 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1548 struct resource *res, resource_size_t size, 1549 resource_size_t align, resource_size_t min, 1550 unsigned long type_mask, 1551 resource_size_t (*alignf)(void *, 1552 const struct resource *, 1553 resource_size_t, 1554 resource_size_t), 1555 void *alignf_data); 1556 1557 1558 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1559 resource_size_t size); 1560 unsigned long pci_address_to_pio(phys_addr_t addr); 1561 phys_addr_t pci_pio_to_address(unsigned long pio); 1562 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1563 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1564 phys_addr_t phys_addr); 1565 void pci_unmap_iospace(struct resource *res); 1566 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1567 resource_size_t offset, 1568 resource_size_t size); 1569 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1570 struct resource *res); 1571 1572 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1573 { 1574 struct pci_bus_region region; 1575 1576 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1577 return region.start; 1578 } 1579 1580 /* Proper probing supporting hot-pluggable devices */ 1581 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1582 const char *mod_name); 1583 1584 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1585 #define pci_register_driver(driver) \ 1586 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1587 1588 void pci_unregister_driver(struct pci_driver *dev); 1589 1590 /** 1591 * module_pci_driver() - Helper macro for registering a PCI driver 1592 * @__pci_driver: pci_driver struct 1593 * 1594 * Helper macro for PCI drivers which do not do anything special in module 1595 * init/exit. This eliminates a lot of boilerplate. Each module may only 1596 * use this macro once, and calling it replaces module_init() and module_exit() 1597 */ 1598 #define module_pci_driver(__pci_driver) \ 1599 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1600 1601 /** 1602 * builtin_pci_driver() - Helper macro for registering a PCI driver 1603 * @__pci_driver: pci_driver struct 1604 * 1605 * Helper macro for PCI drivers which do not do anything special in their 1606 * init code. This eliminates a lot of boilerplate. Each driver may only 1607 * use this macro once, and calling it replaces device_initcall(...) 1608 */ 1609 #define builtin_pci_driver(__pci_driver) \ 1610 builtin_driver(__pci_driver, pci_register_driver) 1611 1612 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1613 int pci_add_dynid(struct pci_driver *drv, 1614 unsigned int vendor, unsigned int device, 1615 unsigned int subvendor, unsigned int subdevice, 1616 unsigned int class, unsigned int class_mask, 1617 unsigned long driver_data); 1618 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1619 struct pci_dev *dev); 1620 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1621 int pass); 1622 1623 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1624 void *userdata); 1625 int pci_cfg_space_size(struct pci_dev *dev); 1626 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1627 void pci_setup_bridge(struct pci_bus *bus); 1628 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1629 unsigned long type); 1630 1631 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1632 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1633 1634 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1635 unsigned int command_bits, u32 flags); 1636 1637 /* 1638 * Virtual interrupts allow for more interrupts to be allocated 1639 * than the device has interrupts for. These are not programmed 1640 * into the device's MSI-X table and must be handled by some 1641 * other driver means. 1642 */ 1643 #define PCI_IRQ_VIRTUAL (1 << 4) 1644 1645 #define PCI_IRQ_ALL_TYPES \ 1646 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1647 1648 #include <linux/dmapool.h> 1649 1650 struct msix_entry { 1651 u32 vector; /* Kernel uses to write allocated vector */ 1652 u16 entry; /* Driver uses to specify entry, OS writes */ 1653 }; 1654 1655 struct msi_domain_template; 1656 1657 #ifdef CONFIG_PCI_MSI 1658 int pci_msi_vec_count(struct pci_dev *dev); 1659 void pci_disable_msi(struct pci_dev *dev); 1660 int pci_msix_vec_count(struct pci_dev *dev); 1661 void pci_disable_msix(struct pci_dev *dev); 1662 void pci_restore_msi_state(struct pci_dev *dev); 1663 int pci_msi_enabled(void); 1664 int pci_enable_msi(struct pci_dev *dev); 1665 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1666 int minvec, int maxvec); 1667 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1668 struct msix_entry *entries, int nvec) 1669 { 1670 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1671 if (rc < 0) 1672 return rc; 1673 return 0; 1674 } 1675 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1676 unsigned int max_vecs, unsigned int flags); 1677 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1678 unsigned int max_vecs, unsigned int flags, 1679 struct irq_affinity *affd); 1680 1681 bool pci_msix_can_alloc_dyn(struct pci_dev *dev); 1682 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1683 const struct irq_affinity_desc *affdesc); 1684 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); 1685 1686 void pci_free_irq_vectors(struct pci_dev *dev); 1687 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1688 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1689 bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template, 1690 unsigned int hwsize, void *data); 1691 struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie, 1692 const struct irq_affinity_desc *affdesc); 1693 void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map); 1694 1695 #else 1696 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1697 static inline void pci_disable_msi(struct pci_dev *dev) { } 1698 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1699 static inline void pci_disable_msix(struct pci_dev *dev) { } 1700 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1701 static inline int pci_msi_enabled(void) { return 0; } 1702 static inline int pci_enable_msi(struct pci_dev *dev) 1703 { return -ENOSYS; } 1704 static inline int pci_enable_msix_range(struct pci_dev *dev, 1705 struct msix_entry *entries, int minvec, int maxvec) 1706 { return -ENOSYS; } 1707 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1708 struct msix_entry *entries, int nvec) 1709 { return -ENOSYS; } 1710 1711 static inline int 1712 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1713 unsigned int max_vecs, unsigned int flags, 1714 struct irq_affinity *aff_desc) 1715 { 1716 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1717 return 1; 1718 return -ENOSPC; 1719 } 1720 static inline int 1721 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1722 unsigned int max_vecs, unsigned int flags) 1723 { 1724 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, 1725 flags, NULL); 1726 } 1727 1728 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev) 1729 { return false; } 1730 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1731 const struct irq_affinity_desc *affdesc) 1732 { 1733 struct msi_map map = { .index = -ENOSYS, }; 1734 1735 return map; 1736 } 1737 1738 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map) 1739 { 1740 } 1741 1742 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1743 { 1744 } 1745 1746 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1747 { 1748 if (WARN_ON_ONCE(nr > 0)) 1749 return -EINVAL; 1750 return dev->irq; 1751 } 1752 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1753 int vec) 1754 { 1755 return cpu_possible_mask; 1756 } 1757 1758 static inline bool pci_create_ims_domain(struct pci_dev *pdev, 1759 const struct msi_domain_template *template, 1760 unsigned int hwsize, void *data) 1761 { return false; } 1762 1763 static inline struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, 1764 union msi_instance_cookie *icookie, 1765 const struct irq_affinity_desc *affdesc) 1766 { 1767 struct msi_map map = { .index = -ENOSYS, }; 1768 1769 return map; 1770 } 1771 1772 static inline void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map) 1773 { 1774 } 1775 1776 #endif 1777 1778 /** 1779 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1780 * @d: the INTx IRQ domain 1781 * @node: the DT node for the device whose interrupt we're translating 1782 * @intspec: the interrupt specifier data from the DT 1783 * @intsize: the number of entries in @intspec 1784 * @out_hwirq: pointer at which to write the hwirq number 1785 * @out_type: pointer at which to write the interrupt type 1786 * 1787 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1788 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1789 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1790 * INTx value to obtain the hwirq number. 1791 * 1792 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1793 */ 1794 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1795 struct device_node *node, 1796 const u32 *intspec, 1797 unsigned int intsize, 1798 unsigned long *out_hwirq, 1799 unsigned int *out_type) 1800 { 1801 const u32 intx = intspec[0]; 1802 1803 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1804 return -EINVAL; 1805 1806 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1807 return 0; 1808 } 1809 1810 #ifdef CONFIG_PCIEPORTBUS 1811 extern bool pcie_ports_disabled; 1812 extern bool pcie_ports_native; 1813 #else 1814 #define pcie_ports_disabled true 1815 #define pcie_ports_native false 1816 #endif 1817 1818 #define PCIE_LINK_STATE_L0S BIT(0) 1819 #define PCIE_LINK_STATE_L1 BIT(1) 1820 #define PCIE_LINK_STATE_CLKPM BIT(2) 1821 #define PCIE_LINK_STATE_L1_1 BIT(3) 1822 #define PCIE_LINK_STATE_L1_2 BIT(4) 1823 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1824 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1825 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\ 1826 PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\ 1827 PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\ 1828 PCIE_LINK_STATE_L1_2_PCIPM) 1829 1830 #ifdef CONFIG_PCIEASPM 1831 int pci_disable_link_state(struct pci_dev *pdev, int state); 1832 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1833 int pci_enable_link_state(struct pci_dev *pdev, int state); 1834 int pci_enable_link_state_locked(struct pci_dev *pdev, int state); 1835 void pcie_no_aspm(void); 1836 bool pcie_aspm_support_enabled(void); 1837 bool pcie_aspm_enabled(struct pci_dev *pdev); 1838 #else 1839 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1840 { return 0; } 1841 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1842 { return 0; } 1843 static inline int pci_enable_link_state(struct pci_dev *pdev, int state) 1844 { return 0; } 1845 static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) 1846 { return 0; } 1847 static inline void pcie_no_aspm(void) { } 1848 static inline bool pcie_aspm_support_enabled(void) { return false; } 1849 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1850 #endif 1851 1852 #ifdef CONFIG_PCIEAER 1853 bool pci_aer_available(void); 1854 #else 1855 static inline bool pci_aer_available(void) { return false; } 1856 #endif 1857 1858 bool pci_ats_disabled(void); 1859 1860 #ifdef CONFIG_PCIE_PTM 1861 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1862 void pci_disable_ptm(struct pci_dev *dev); 1863 bool pcie_ptm_enabled(struct pci_dev *dev); 1864 #else 1865 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1866 { return -EINVAL; } 1867 static inline void pci_disable_ptm(struct pci_dev *dev) { } 1868 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1869 { return false; } 1870 #endif 1871 1872 void pci_cfg_access_lock(struct pci_dev *dev); 1873 bool pci_cfg_access_trylock(struct pci_dev *dev); 1874 void pci_cfg_access_unlock(struct pci_dev *dev); 1875 1876 void pci_dev_lock(struct pci_dev *dev); 1877 int pci_dev_trylock(struct pci_dev *dev); 1878 void pci_dev_unlock(struct pci_dev *dev); 1879 1880 /* 1881 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1882 * a PCI domain is defined to be a set of PCI buses which share 1883 * configuration space. 1884 */ 1885 #ifdef CONFIG_PCI_DOMAINS 1886 extern int pci_domains_supported; 1887 #else 1888 enum { pci_domains_supported = 0 }; 1889 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1890 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1891 #endif /* CONFIG_PCI_DOMAINS */ 1892 1893 /* 1894 * Generic implementation for PCI domain support. If your 1895 * architecture does not need custom management of PCI 1896 * domains then this implementation will be used 1897 */ 1898 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1899 static inline int pci_domain_nr(struct pci_bus *bus) 1900 { 1901 return bus->domain_nr; 1902 } 1903 #ifdef CONFIG_ACPI 1904 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1905 #else 1906 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1907 { return 0; } 1908 #endif 1909 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1910 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent); 1911 #endif 1912 1913 /* Some architectures require additional setup to direct VGA traffic */ 1914 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1915 unsigned int command_bits, u32 flags); 1916 void pci_register_set_vga_state(arch_set_vga_state_t func); 1917 1918 static inline int 1919 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1920 { 1921 return pci_request_selected_regions(pdev, 1922 pci_select_bars(pdev, IORESOURCE_IO), name); 1923 } 1924 1925 static inline void 1926 pci_release_io_regions(struct pci_dev *pdev) 1927 { 1928 return pci_release_selected_regions(pdev, 1929 pci_select_bars(pdev, IORESOURCE_IO)); 1930 } 1931 1932 static inline int 1933 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1934 { 1935 return pci_request_selected_regions(pdev, 1936 pci_select_bars(pdev, IORESOURCE_MEM), name); 1937 } 1938 1939 static inline void 1940 pci_release_mem_regions(struct pci_dev *pdev) 1941 { 1942 return pci_release_selected_regions(pdev, 1943 pci_select_bars(pdev, IORESOURCE_MEM)); 1944 } 1945 1946 #else /* CONFIG_PCI is not enabled */ 1947 1948 static inline void pci_set_flags(int flags) { } 1949 static inline void pci_add_flags(int flags) { } 1950 static inline void pci_clear_flags(int flags) { } 1951 static inline int pci_has_flag(int flag) { return 0; } 1952 1953 /* 1954 * If the system does not have PCI, clearly these return errors. Define 1955 * these as simple inline functions to avoid hair in drivers. 1956 */ 1957 #define _PCI_NOP(o, s, t) \ 1958 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1959 int where, t val) \ 1960 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1961 1962 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1963 _PCI_NOP(o, word, u16 x) \ 1964 _PCI_NOP(o, dword, u32 x) 1965 _PCI_NOP_ALL(read, *) 1966 _PCI_NOP_ALL(write,) 1967 1968 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1969 unsigned int device, 1970 struct pci_dev *from) 1971 { return NULL; } 1972 1973 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1974 unsigned int device, 1975 unsigned int ss_vendor, 1976 unsigned int ss_device, 1977 struct pci_dev *from) 1978 { return NULL; } 1979 1980 static inline struct pci_dev *pci_get_class(unsigned int class, 1981 struct pci_dev *from) 1982 { return NULL; } 1983 1984 static inline struct pci_dev *pci_get_base_class(unsigned int class, 1985 struct pci_dev *from) 1986 { return NULL; } 1987 1988 static inline int pci_dev_present(const struct pci_device_id *ids) 1989 { return 0; } 1990 1991 #define no_pci_devices() (1) 1992 #define pci_dev_put(dev) do { } while (0) 1993 1994 static inline void pci_set_master(struct pci_dev *dev) { } 1995 static inline void pci_clear_master(struct pci_dev *dev) { } 1996 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1997 static inline void pci_disable_device(struct pci_dev *dev) { } 1998 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1999 static inline int pci_assign_resource(struct pci_dev *dev, int i) 2000 { return -EBUSY; } 2001 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 2002 struct module *owner, 2003 const char *mod_name) 2004 { return 0; } 2005 static inline int pci_register_driver(struct pci_driver *drv) 2006 { return 0; } 2007 static inline void pci_unregister_driver(struct pci_driver *drv) { } 2008 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 2009 { return 0; } 2010 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 2011 int cap) 2012 { return 0; } 2013 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 2014 { return 0; } 2015 2016 static inline u64 pci_get_dsn(struct pci_dev *dev) 2017 { return 0; } 2018 2019 /* Power management related routines */ 2020 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 2021 static inline void pci_restore_state(struct pci_dev *dev) { } 2022 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 2023 { return 0; } 2024 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 2025 { return 0; } 2026 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 2027 pm_message_t state) 2028 { return PCI_D0; } 2029 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 2030 int enable) 2031 { return 0; } 2032 2033 static inline struct resource *pci_find_resource(struct pci_dev *dev, 2034 struct resource *res) 2035 { return NULL; } 2036 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 2037 { return -EIO; } 2038 static inline void pci_release_regions(struct pci_dev *dev) { } 2039 2040 static inline int pci_register_io_range(struct fwnode_handle *fwnode, 2041 phys_addr_t addr, resource_size_t size) 2042 { return -EINVAL; } 2043 2044 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 2045 2046 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 2047 { return NULL; } 2048 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 2049 unsigned int devfn) 2050 { return NULL; } 2051 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 2052 unsigned int bus, unsigned int devfn) 2053 { return NULL; } 2054 2055 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2056 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 2057 2058 #define dev_is_pci(d) (false) 2059 #define dev_is_pf(d) (false) 2060 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2061 { return false; } 2062 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 2063 struct device_node *node, 2064 const u32 *intspec, 2065 unsigned int intsize, 2066 unsigned long *out_hwirq, 2067 unsigned int *out_type) 2068 { return -EINVAL; } 2069 2070 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 2071 struct pci_dev *dev) 2072 { return NULL; } 2073 static inline bool pci_ats_disabled(void) { return true; } 2074 2075 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 2076 { 2077 return -EINVAL; 2078 } 2079 2080 static inline int 2081 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 2082 unsigned int max_vecs, unsigned int flags, 2083 struct irq_affinity *aff_desc) 2084 { 2085 return -ENOSPC; 2086 } 2087 static inline int 2088 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 2089 unsigned int max_vecs, unsigned int flags) 2090 { 2091 return -ENOSPC; 2092 } 2093 #endif /* CONFIG_PCI */ 2094 2095 /* Include architecture-dependent settings and functions */ 2096 2097 #include <asm/pci.h> 2098 2099 /* 2100 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 2101 * is expected to be an offset within that region. 2102 * 2103 */ 2104 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 2105 struct vm_area_struct *vma, 2106 enum pci_mmap_state mmap_state, int write_combine); 2107 2108 #ifndef arch_can_pci_mmap_wc 2109 #define arch_can_pci_mmap_wc() 0 2110 #endif 2111 2112 #ifndef arch_can_pci_mmap_io 2113 #define arch_can_pci_mmap_io() 0 2114 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 2115 #else 2116 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 2117 #endif 2118 2119 #ifndef pci_root_bus_fwnode 2120 #define pci_root_bus_fwnode(bus) NULL 2121 #endif 2122 2123 /* 2124 * These helpers provide future and backwards compatibility 2125 * for accessing popular PCI BAR info 2126 */ 2127 #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)]) 2128 #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start) 2129 #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end) 2130 #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags) 2131 #define pci_resource_len(dev,bar) \ 2132 (pci_resource_end((dev), (bar)) ? \ 2133 resource_size(pci_resource_n((dev), (bar))) : 0) 2134 2135 #define __pci_dev_for_each_res0(dev, res, ...) \ 2136 for (unsigned int __b = 0; \ 2137 res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \ 2138 __b++) 2139 2140 #define __pci_dev_for_each_res1(dev, res, __b) \ 2141 for (__b = 0; \ 2142 res = pci_resource_n(dev, __b), __b < PCI_NUM_RESOURCES; \ 2143 __b++) 2144 2145 #define pci_dev_for_each_resource(dev, res, ...) \ 2146 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 2147 (dev, res, __VA_ARGS__) 2148 2149 /* 2150 * Similar to the helpers above, these manipulate per-pci_dev 2151 * driver-specific data. They are really just a wrapper around 2152 * the generic device structure functions of these calls. 2153 */ 2154 static inline void *pci_get_drvdata(struct pci_dev *pdev) 2155 { 2156 return dev_get_drvdata(&pdev->dev); 2157 } 2158 2159 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 2160 { 2161 dev_set_drvdata(&pdev->dev, data); 2162 } 2163 2164 static inline const char *pci_name(const struct pci_dev *pdev) 2165 { 2166 return dev_name(&pdev->dev); 2167 } 2168 2169 void pci_resource_to_user(const struct pci_dev *dev, int bar, 2170 const struct resource *rsrc, 2171 resource_size_t *start, resource_size_t *end); 2172 2173 /* 2174 * The world is not perfect and supplies us with broken PCI devices. 2175 * For at least a part of these bugs we need a work-around, so both 2176 * generic (drivers/pci/quirks.c) and per-architecture code can define 2177 * fixup hooks to be called for particular buggy devices. 2178 */ 2179 2180 struct pci_fixup { 2181 u16 vendor; /* Or PCI_ANY_ID */ 2182 u16 device; /* Or PCI_ANY_ID */ 2183 u32 class; /* Or PCI_ANY_ID */ 2184 unsigned int class_shift; /* should be 0, 8, 16 */ 2185 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2186 int hook_offset; 2187 #else 2188 void (*hook)(struct pci_dev *dev); 2189 #endif 2190 }; 2191 2192 enum pci_fixup_pass { 2193 pci_fixup_early, /* Before probing BARs */ 2194 pci_fixup_header, /* After reading configuration header */ 2195 pci_fixup_final, /* Final phase of device fixups */ 2196 pci_fixup_enable, /* pci_enable_device() time */ 2197 pci_fixup_resume, /* pci_device_resume() */ 2198 pci_fixup_suspend, /* pci_device_suspend() */ 2199 pci_fixup_resume_early, /* pci_device_resume_early() */ 2200 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2201 }; 2202 2203 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2204 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2205 class_shift, hook) \ 2206 __ADDRESSABLE(hook) \ 2207 asm(".section " #sec ", \"a\" \n" \ 2208 ".balign 16 \n" \ 2209 ".short " #vendor ", " #device " \n" \ 2210 ".long " #class ", " #class_shift " \n" \ 2211 ".long " #hook " - . \n" \ 2212 ".previous \n"); 2213 2214 /* 2215 * Clang's LTO may rename static functions in C, but has no way to 2216 * handle such renamings when referenced from inline asm. To work 2217 * around this, create global C stubs for these cases. 2218 */ 2219 #ifdef CONFIG_LTO_CLANG 2220 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2221 class_shift, hook, stub) \ 2222 void stub(struct pci_dev *dev); \ 2223 void stub(struct pci_dev *dev) \ 2224 { \ 2225 hook(dev); \ 2226 } \ 2227 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2228 class_shift, stub) 2229 #else 2230 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2231 class_shift, hook, stub) \ 2232 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2233 class_shift, hook) 2234 #endif 2235 2236 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2237 class_shift, hook) \ 2238 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2239 class_shift, hook, __UNIQUE_ID(hook)) 2240 #else 2241 /* Anonymous variables would be nice... */ 2242 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2243 class_shift, hook) \ 2244 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2245 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2246 = { vendor, device, class, class_shift, hook }; 2247 #endif 2248 2249 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2250 class_shift, hook) \ 2251 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2252 hook, vendor, device, class, class_shift, hook) 2253 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2254 class_shift, hook) \ 2255 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2256 hook, vendor, device, class, class_shift, hook) 2257 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2258 class_shift, hook) \ 2259 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2260 hook, vendor, device, class, class_shift, hook) 2261 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2262 class_shift, hook) \ 2263 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2264 hook, vendor, device, class, class_shift, hook) 2265 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2266 class_shift, hook) \ 2267 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2268 resume##hook, vendor, device, class, class_shift, hook) 2269 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2270 class_shift, hook) \ 2271 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2272 resume_early##hook, vendor, device, class, class_shift, hook) 2273 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2274 class_shift, hook) \ 2275 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2276 suspend##hook, vendor, device, class, class_shift, hook) 2277 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2278 class_shift, hook) \ 2279 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2280 suspend_late##hook, vendor, device, class, class_shift, hook) 2281 2282 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2283 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2284 hook, vendor, device, PCI_ANY_ID, 0, hook) 2285 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2286 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2287 hook, vendor, device, PCI_ANY_ID, 0, hook) 2288 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2289 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2290 hook, vendor, device, PCI_ANY_ID, 0, hook) 2291 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2292 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2293 hook, vendor, device, PCI_ANY_ID, 0, hook) 2294 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2295 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2296 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2297 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2298 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2299 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2300 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2301 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2302 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2303 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2304 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2305 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2306 2307 #ifdef CONFIG_PCI_QUIRKS 2308 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2309 #else 2310 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2311 struct pci_dev *dev) { } 2312 #endif 2313 2314 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2315 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2316 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2317 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2318 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2319 const char *name); 2320 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2321 2322 extern int pci_pci_problems; 2323 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2324 #define PCIPCI_TRITON 2 2325 #define PCIPCI_NATOMA 4 2326 #define PCIPCI_VIAETBF 8 2327 #define PCIPCI_VSFX 16 2328 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2329 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2330 2331 extern unsigned long pci_cardbus_io_size; 2332 extern unsigned long pci_cardbus_mem_size; 2333 extern u8 pci_dfl_cache_line_size; 2334 extern u8 pci_cache_line_size; 2335 2336 /* Architecture-specific versions may override these (weak) */ 2337 void pcibios_disable_device(struct pci_dev *dev); 2338 void pcibios_set_master(struct pci_dev *dev); 2339 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2340 enum pcie_reset_state state); 2341 int pcibios_device_add(struct pci_dev *dev); 2342 void pcibios_release_device(struct pci_dev *dev); 2343 #ifdef CONFIG_PCI 2344 void pcibios_penalize_isa_irq(int irq, int active); 2345 #else 2346 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2347 #endif 2348 int pcibios_alloc_irq(struct pci_dev *dev); 2349 void pcibios_free_irq(struct pci_dev *dev); 2350 resource_size_t pcibios_default_alignment(void); 2351 2352 #if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE) 2353 extern int pci_create_resource_files(struct pci_dev *dev); 2354 extern void pci_remove_resource_files(struct pci_dev *dev); 2355 #endif 2356 2357 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2358 void __init pci_mmcfg_early_init(void); 2359 void __init pci_mmcfg_late_init(void); 2360 #else 2361 static inline void pci_mmcfg_early_init(void) { } 2362 static inline void pci_mmcfg_late_init(void) { } 2363 #endif 2364 2365 int pci_ext_cfg_avail(void); 2366 2367 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2368 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2369 2370 #ifdef CONFIG_PCI_IOV 2371 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2372 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2373 int pci_iov_vf_id(struct pci_dev *dev); 2374 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2375 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2376 void pci_disable_sriov(struct pci_dev *dev); 2377 2378 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2379 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2380 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2381 int pci_num_vf(struct pci_dev *dev); 2382 int pci_vfs_assigned(struct pci_dev *dev); 2383 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2384 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2385 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2386 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2387 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2388 2389 /* Arch may override these (weak) */ 2390 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2391 int pcibios_sriov_disable(struct pci_dev *pdev); 2392 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2393 #else 2394 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2395 { 2396 return -ENOSYS; 2397 } 2398 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2399 { 2400 return -ENOSYS; 2401 } 2402 2403 static inline int pci_iov_vf_id(struct pci_dev *dev) 2404 { 2405 return -ENOSYS; 2406 } 2407 2408 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2409 struct pci_driver *pf_driver) 2410 { 2411 return ERR_PTR(-EINVAL); 2412 } 2413 2414 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2415 { return -ENODEV; } 2416 2417 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2418 struct pci_dev *virtfn, int id) 2419 { 2420 return -ENODEV; 2421 } 2422 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2423 { 2424 return -ENOSYS; 2425 } 2426 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2427 int id) { } 2428 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2429 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2430 static inline int pci_vfs_assigned(struct pci_dev *dev) 2431 { return 0; } 2432 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2433 { return 0; } 2434 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2435 { return 0; } 2436 #define pci_sriov_configure_simple NULL 2437 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2438 { return 0; } 2439 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2440 #endif 2441 2442 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2443 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2444 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2445 #endif 2446 2447 /** 2448 * pci_pcie_cap - get the saved PCIe capability offset 2449 * @dev: PCI device 2450 * 2451 * PCIe capability offset is calculated at PCI device initialization 2452 * time and saved in the data structure. This function returns saved 2453 * PCIe capability offset. Using this instead of pci_find_capability() 2454 * reduces unnecessary search in the PCI configuration space. If you 2455 * need to calculate PCIe capability offset from raw device for some 2456 * reasons, please use pci_find_capability() instead. 2457 */ 2458 static inline int pci_pcie_cap(struct pci_dev *dev) 2459 { 2460 return dev->pcie_cap; 2461 } 2462 2463 /** 2464 * pci_is_pcie - check if the PCI device is PCI Express capable 2465 * @dev: PCI device 2466 * 2467 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2468 */ 2469 static inline bool pci_is_pcie(struct pci_dev *dev) 2470 { 2471 return pci_pcie_cap(dev); 2472 } 2473 2474 /** 2475 * pcie_caps_reg - get the PCIe Capabilities Register 2476 * @dev: PCI device 2477 */ 2478 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2479 { 2480 return dev->pcie_flags_reg; 2481 } 2482 2483 /** 2484 * pci_pcie_type - get the PCIe device/port type 2485 * @dev: PCI device 2486 */ 2487 static inline int pci_pcie_type(const struct pci_dev *dev) 2488 { 2489 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2490 } 2491 2492 /** 2493 * pcie_find_root_port - Get the PCIe root port device 2494 * @dev: PCI device 2495 * 2496 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2497 * for a given PCI/PCIe Device. 2498 */ 2499 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2500 { 2501 while (dev) { 2502 if (pci_is_pcie(dev) && 2503 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2504 return dev; 2505 dev = pci_upstream_bridge(dev); 2506 } 2507 2508 return NULL; 2509 } 2510 2511 void pci_request_acs(void); 2512 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2513 bool pci_acs_path_enabled(struct pci_dev *start, 2514 struct pci_dev *end, u16 acs_flags); 2515 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2516 2517 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2518 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2519 2520 /* Large Resource Data Type Tag Item Names */ 2521 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2522 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2523 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2524 2525 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2526 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2527 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2528 2529 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2530 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2531 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2532 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2533 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2534 2535 /** 2536 * pci_vpd_alloc - Allocate buffer and read VPD into it 2537 * @dev: PCI device 2538 * @size: pointer to field where VPD length is returned 2539 * 2540 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2541 */ 2542 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2543 2544 /** 2545 * pci_vpd_find_id_string - Locate id string in VPD 2546 * @buf: Pointer to buffered VPD data 2547 * @len: The length of the buffer area in which to search 2548 * @size: Pointer to field where length of id string is returned 2549 * 2550 * Returns the index of the id string or -ENOENT if not found. 2551 */ 2552 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2553 2554 /** 2555 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2556 * @buf: Pointer to buffered VPD data 2557 * @len: The length of the buffer area in which to search 2558 * @kw: The keyword to search for 2559 * @size: Pointer to field where length of found keyword data is returned 2560 * 2561 * Returns the index of the information field keyword data or -ENOENT if 2562 * not found. 2563 */ 2564 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2565 const char *kw, unsigned int *size); 2566 2567 /** 2568 * pci_vpd_check_csum - Check VPD checksum 2569 * @buf: Pointer to buffered VPD data 2570 * @len: VPD size 2571 * 2572 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2573 */ 2574 int pci_vpd_check_csum(const void *buf, unsigned int len); 2575 2576 /* PCI <-> OF binding helpers */ 2577 #ifdef CONFIG_OF 2578 struct device_node; 2579 struct irq_domain; 2580 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2581 bool pci_host_of_has_msi_map(struct device *dev); 2582 2583 /* Arch may override this (weak) */ 2584 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2585 2586 #else /* CONFIG_OF */ 2587 static inline struct irq_domain * 2588 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2589 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2590 #endif /* CONFIG_OF */ 2591 2592 static inline struct device_node * 2593 pci_device_to_OF_node(const struct pci_dev *pdev) 2594 { 2595 return pdev ? pdev->dev.of_node : NULL; 2596 } 2597 2598 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2599 { 2600 return bus ? bus->dev.of_node : NULL; 2601 } 2602 2603 #ifdef CONFIG_ACPI 2604 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2605 2606 void 2607 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2608 bool pci_pr3_present(struct pci_dev *pdev); 2609 #else 2610 static inline struct irq_domain * 2611 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2612 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2613 #endif 2614 2615 #ifdef CONFIG_EEH 2616 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2617 { 2618 return pdev->dev.archdata.edev; 2619 } 2620 #endif 2621 2622 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2623 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2624 int pci_for_each_dma_alias(struct pci_dev *pdev, 2625 int (*fn)(struct pci_dev *pdev, 2626 u16 alias, void *data), void *data); 2627 2628 /* Helper functions for operation of device flag */ 2629 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2630 { 2631 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2632 } 2633 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2634 { 2635 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2636 } 2637 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2638 { 2639 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2640 } 2641 2642 /** 2643 * pci_ari_enabled - query ARI forwarding status 2644 * @bus: the PCI bus 2645 * 2646 * Returns true if ARI forwarding is enabled. 2647 */ 2648 static inline bool pci_ari_enabled(struct pci_bus *bus) 2649 { 2650 return bus->self && bus->self->ari_enabled; 2651 } 2652 2653 /** 2654 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2655 * @pdev: PCI device to check 2656 * 2657 * Walk upwards from @pdev and check for each encountered bridge if it's part 2658 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2659 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2660 */ 2661 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2662 { 2663 struct pci_dev *parent = pdev; 2664 2665 if (pdev->is_thunderbolt) 2666 return true; 2667 2668 while ((parent = pci_upstream_bridge(parent))) 2669 if (parent->is_thunderbolt) 2670 return true; 2671 2672 return false; 2673 } 2674 2675 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2676 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2677 #endif 2678 2679 #include <linux/dma-mapping.h> 2680 2681 #define pci_printk(level, pdev, fmt, arg...) \ 2682 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2683 2684 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2685 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2686 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2687 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2688 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2689 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) 2690 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2691 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2692 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2693 2694 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2695 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2696 2697 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2698 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2699 2700 #define pci_WARN(pdev, condition, fmt, arg...) \ 2701 WARN(condition, "%s %s: " fmt, \ 2702 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2703 2704 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2705 WARN_ONCE(condition, "%s %s: " fmt, \ 2706 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2707 2708 #endif /* LINUX_PCI_H */ 2709