1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/interrupt.h> 32 #include <linux/io.h> 33 #include <linux/resource_ext.h> 34 #include <uapi/linux/pci.h> 35 36 #include <linux/pci_ids.h> 37 38 /* 39 * The PCI interface treats multi-function devices as independent 40 * devices. The slot/function address of each device is encoded 41 * in a single byte as follows: 42 * 43 * 7:3 = slot 44 * 2:0 = function 45 * 46 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 47 * In the interest of not exposing interfaces to user-space unnecessarily, 48 * the following kernel-only defines are being added here. 49 */ 50 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 51 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 52 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 53 54 /* pci_slot represents a physical slot */ 55 struct pci_slot { 56 struct pci_bus *bus; /* The bus this slot is on */ 57 struct list_head list; /* node in list of slots on this bus */ 58 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 59 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 60 struct kobject kobj; 61 }; 62 63 static inline const char *pci_slot_name(const struct pci_slot *slot) 64 { 65 return kobject_name(&slot->kobj); 66 } 67 68 /* File state for mmap()s on /proc/bus/pci/X/Y */ 69 enum pci_mmap_state { 70 pci_mmap_io, 71 pci_mmap_mem 72 }; 73 74 /* 75 * For PCI devices, the region numbers are assigned this way: 76 */ 77 enum { 78 /* #0-5: standard PCI resources */ 79 PCI_STD_RESOURCES, 80 PCI_STD_RESOURCE_END = 5, 81 82 /* #6: expansion ROM resource */ 83 PCI_ROM_RESOURCE, 84 85 /* device specific resources */ 86 #ifdef CONFIG_PCI_IOV 87 PCI_IOV_RESOURCES, 88 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 89 #endif 90 91 /* resources assigned to buses behind the bridge */ 92 #define PCI_BRIDGE_RESOURCE_NUM 4 93 94 PCI_BRIDGE_RESOURCES, 95 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 96 PCI_BRIDGE_RESOURCE_NUM - 1, 97 98 /* total resources associated with a PCI device */ 99 PCI_NUM_RESOURCES, 100 101 /* preserve this for compatibility */ 102 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 103 }; 104 105 /* 106 * pci_power_t values must match the bits in the Capabilities PME_Support 107 * and Control/Status PowerState fields in the Power Management capability. 108 */ 109 typedef int __bitwise pci_power_t; 110 111 #define PCI_D0 ((pci_power_t __force) 0) 112 #define PCI_D1 ((pci_power_t __force) 1) 113 #define PCI_D2 ((pci_power_t __force) 2) 114 #define PCI_D3hot ((pci_power_t __force) 3) 115 #define PCI_D3cold ((pci_power_t __force) 4) 116 #define PCI_UNKNOWN ((pci_power_t __force) 5) 117 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 118 119 /* Remember to update this when the list above changes! */ 120 extern const char *pci_power_names[]; 121 122 static inline const char *pci_power_name(pci_power_t state) 123 { 124 return pci_power_names[1 + (__force int) state]; 125 } 126 127 #define PCI_PM_D2_DELAY 200 128 #define PCI_PM_D3_WAIT 10 129 #define PCI_PM_D3COLD_WAIT 100 130 #define PCI_PM_BUS_WAIT 50 131 132 /** The pci_channel state describes connectivity between the CPU and 133 * the pci device. If some PCI bus between here and the pci device 134 * has crashed or locked up, this info is reflected here. 135 */ 136 typedef unsigned int __bitwise pci_channel_state_t; 137 138 enum pci_channel_state { 139 /* I/O channel is in normal state */ 140 pci_channel_io_normal = (__force pci_channel_state_t) 1, 141 142 /* I/O to channel is blocked */ 143 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 144 145 /* PCI card is dead */ 146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 147 }; 148 149 typedef unsigned int __bitwise pcie_reset_state_t; 150 151 enum pcie_reset_state { 152 /* Reset is NOT asserted (Use to deassert reset) */ 153 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 154 155 /* Use #PERST to reset PCIe device */ 156 pcie_warm_reset = (__force pcie_reset_state_t) 2, 157 158 /* Use PCIe Hot Reset to reset device */ 159 pcie_hot_reset = (__force pcie_reset_state_t) 3 160 }; 161 162 typedef unsigned short __bitwise pci_dev_flags_t; 163 enum pci_dev_flags { 164 /* INTX_DISABLE in PCI_COMMAND register disables MSI 165 * generation too. 166 */ 167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 168 /* Device configuration is irrevocably lost if disabled into D3 */ 169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 170 /* Provide indication device is assigned by a Virtual Machine Manager */ 171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 172 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 174 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 175 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 176 /* Do not use bus resets for device */ 177 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 178 /* Do not use PM reset even if device advertises NoSoftRst- */ 179 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 180 /* Get VPD from function 0 VPD */ 181 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 182 /* a non-root bridge where translation occurs, stop alias search here */ 183 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 184 /* Do not use FLR even if device advertises PCI_AF_CAP */ 185 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 186 /* 187 * Resume before calling the driver's system suspend hooks, disabling 188 * the direct_complete optimization. 189 */ 190 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11), 191 /* Don't use Relaxed Ordering for TLPs directed at this device */ 192 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12), 193 }; 194 195 enum pci_irq_reroute_variant { 196 INTEL_IRQ_REROUTE_VARIANT = 1, 197 MAX_IRQ_REROUTE_VARIANTS = 3 198 }; 199 200 typedef unsigned short __bitwise pci_bus_flags_t; 201 enum pci_bus_flags { 202 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 203 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 204 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 205 }; 206 207 /* These values come from the PCI Express Spec */ 208 enum pcie_link_width { 209 PCIE_LNK_WIDTH_RESRV = 0x00, 210 PCIE_LNK_X1 = 0x01, 211 PCIE_LNK_X2 = 0x02, 212 PCIE_LNK_X4 = 0x04, 213 PCIE_LNK_X8 = 0x08, 214 PCIE_LNK_X12 = 0x0C, 215 PCIE_LNK_X16 = 0x10, 216 PCIE_LNK_X32 = 0x20, 217 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 218 }; 219 220 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 221 enum pci_bus_speed { 222 PCI_SPEED_33MHz = 0x00, 223 PCI_SPEED_66MHz = 0x01, 224 PCI_SPEED_66MHz_PCIX = 0x02, 225 PCI_SPEED_100MHz_PCIX = 0x03, 226 PCI_SPEED_133MHz_PCIX = 0x04, 227 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 228 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 229 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 230 PCI_SPEED_66MHz_PCIX_266 = 0x09, 231 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 232 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 233 AGP_UNKNOWN = 0x0c, 234 AGP_1X = 0x0d, 235 AGP_2X = 0x0e, 236 AGP_4X = 0x0f, 237 AGP_8X = 0x10, 238 PCI_SPEED_66MHz_PCIX_533 = 0x11, 239 PCI_SPEED_100MHz_PCIX_533 = 0x12, 240 PCI_SPEED_133MHz_PCIX_533 = 0x13, 241 PCIE_SPEED_2_5GT = 0x14, 242 PCIE_SPEED_5_0GT = 0x15, 243 PCIE_SPEED_8_0GT = 0x16, 244 PCI_SPEED_UNKNOWN = 0xff, 245 }; 246 247 struct pci_cap_saved_data { 248 u16 cap_nr; 249 bool cap_extended; 250 unsigned int size; 251 u32 data[0]; 252 }; 253 254 struct pci_cap_saved_state { 255 struct hlist_node next; 256 struct pci_cap_saved_data cap; 257 }; 258 259 struct irq_affinity; 260 struct pcie_link_state; 261 struct pci_vpd; 262 struct pci_sriov; 263 struct pci_ats; 264 265 /* 266 * The pci_dev structure is used to describe PCI devices. 267 */ 268 struct pci_dev { 269 struct list_head bus_list; /* node in per-bus list */ 270 struct pci_bus *bus; /* bus this device is on */ 271 struct pci_bus *subordinate; /* bus this device bridges to */ 272 273 void *sysdata; /* hook for sys-specific extension */ 274 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 275 struct pci_slot *slot; /* Physical slot this device is in */ 276 277 unsigned int devfn; /* encoded device & function index */ 278 unsigned short vendor; 279 unsigned short device; 280 unsigned short subsystem_vendor; 281 unsigned short subsystem_device; 282 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 283 u8 revision; /* PCI revision, low byte of class word */ 284 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 285 #ifdef CONFIG_PCIEAER 286 u16 aer_cap; /* AER capability offset */ 287 #endif 288 u8 pcie_cap; /* PCIe capability offset */ 289 u8 msi_cap; /* MSI capability offset */ 290 u8 msix_cap; /* MSI-X capability offset */ 291 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 292 u8 rom_base_reg; /* which config register controls the ROM */ 293 u8 pin; /* which interrupt pin this device uses */ 294 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 295 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */ 296 297 struct pci_driver *driver; /* which driver has allocated this device */ 298 u64 dma_mask; /* Mask of the bits of bus address this 299 device implements. Normally this is 300 0xffffffff. You only need to change 301 this if your device has broken DMA 302 or supports 64-bit transfers. */ 303 304 struct device_dma_parameters dma_parms; 305 306 pci_power_t current_state; /* Current operating state. In ACPI-speak, 307 this is D0-D3, D0 being fully functional, 308 and D3 being off. */ 309 u8 pm_cap; /* PM capability offset */ 310 unsigned int pme_support:5; /* Bitmask of states from which PME# 311 can be generated */ 312 unsigned int pme_poll:1; /* Poll device's PME status bit */ 313 unsigned int d1_support:1; /* Low power state D1 is supported */ 314 unsigned int d2_support:1; /* Low power state D2 is supported */ 315 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 316 unsigned int no_d3cold:1; /* D3cold is forbidden */ 317 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 318 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 319 unsigned int mmio_always_on:1; /* disallow turning off io/mem 320 decoding during bar sizing */ 321 unsigned int wakeup_prepared:1; 322 unsigned int runtime_d3cold:1; /* whether go through runtime 323 D3cold, not set for devices 324 powered on/off by the 325 corresponding bridge */ 326 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 327 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 328 controlled exclusively by 329 user sysfs */ 330 unsigned int d3_delay; /* D3->D0 transition time in ms */ 331 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 332 333 #ifdef CONFIG_PCIEASPM 334 struct pcie_link_state *link_state; /* ASPM link state */ 335 #endif 336 337 pci_channel_state_t error_state; /* current connectivity state */ 338 struct device dev; /* Generic device interface */ 339 340 int cfg_size; /* Size of configuration space */ 341 342 /* 343 * Instead of touching interrupt line and base address registers 344 * directly, use the values stored here. They might be different! 345 */ 346 unsigned int irq; 347 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 348 349 bool match_driver; /* Skip attaching driver */ 350 /* These fields are used by common fixups */ 351 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 352 unsigned int multifunction:1;/* Part of multi-function device */ 353 /* keep track of device state */ 354 unsigned int is_added:1; 355 unsigned int is_busmaster:1; /* device is busmaster */ 356 unsigned int no_msi:1; /* device may not use msi */ 357 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 358 unsigned int block_cfg_access:1; /* config space access is blocked */ 359 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 360 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 361 unsigned int msi_enabled:1; 362 unsigned int msix_enabled:1; 363 unsigned int ari_enabled:1; /* ARI forwarding */ 364 unsigned int ats_enabled:1; /* Address Translation Service */ 365 unsigned int pasid_enabled:1; /* Process Address Space ID */ 366 unsigned int pri_enabled:1; /* Page Request Interface */ 367 unsigned int is_managed:1; 368 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 369 unsigned int state_saved:1; 370 unsigned int is_physfn:1; 371 unsigned int is_virtfn:1; 372 unsigned int reset_fn:1; 373 unsigned int is_hotplug_bridge:1; 374 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 375 unsigned int __aer_firmware_first_valid:1; 376 unsigned int __aer_firmware_first:1; 377 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 378 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 379 unsigned int irq_managed:1; 380 unsigned int has_secondary_link:1; 381 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 382 unsigned int is_probed:1; /* device probing in progress */ 383 pci_dev_flags_t dev_flags; 384 atomic_t enable_cnt; /* pci_enable_device has been called */ 385 386 u32 saved_config_space[16]; /* config space saved at suspend time */ 387 struct hlist_head saved_cap_space; 388 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 389 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 390 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 391 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 392 393 #ifdef CONFIG_PCIE_PTM 394 unsigned int ptm_root:1; 395 unsigned int ptm_enabled:1; 396 u8 ptm_granularity; 397 #endif 398 #ifdef CONFIG_PCI_MSI 399 const struct attribute_group **msi_irq_groups; 400 #endif 401 struct pci_vpd *vpd; 402 #ifdef CONFIG_PCI_ATS 403 union { 404 struct pci_sriov *sriov; /* SR-IOV capability related */ 405 struct pci_dev *physfn; /* the PF this VF is associated with */ 406 }; 407 u16 ats_cap; /* ATS Capability offset */ 408 u8 ats_stu; /* ATS Smallest Translation Unit */ 409 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 410 #endif 411 #ifdef CONFIG_PCI_PRI 412 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 413 #endif 414 #ifdef CONFIG_PCI_PASID 415 u16 pasid_features; 416 #endif 417 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 418 size_t romlen; /* Length of ROM if it's not from the BAR */ 419 char *driver_override; /* Driver name to force a match */ 420 421 unsigned long priv_flags; /* Private flags for the pci driver */ 422 }; 423 424 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 425 { 426 #ifdef CONFIG_PCI_IOV 427 if (dev->is_virtfn) 428 dev = dev->physfn; 429 #endif 430 return dev; 431 } 432 433 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 434 435 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 436 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 437 438 static inline int pci_channel_offline(struct pci_dev *pdev) 439 { 440 return (pdev->error_state != pci_channel_io_normal); 441 } 442 443 struct pci_host_bridge { 444 struct device dev; 445 struct pci_bus *bus; /* root bus */ 446 struct pci_ops *ops; 447 void *sysdata; 448 int busnr; 449 struct list_head windows; /* resource_entry */ 450 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */ 451 int (*map_irq)(const struct pci_dev *, u8, u8); 452 void (*release_fn)(struct pci_host_bridge *); 453 void *release_data; 454 struct msi_controller *msi; 455 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 456 /* Resource alignment requirements */ 457 resource_size_t (*align_resource)(struct pci_dev *dev, 458 const struct resource *res, 459 resource_size_t start, 460 resource_size_t size, 461 resource_size_t align); 462 unsigned long private[0] ____cacheline_aligned; 463 }; 464 465 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 466 467 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 468 { 469 return (void *)bridge->private; 470 } 471 472 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 473 { 474 return container_of(priv, struct pci_host_bridge, private); 475 } 476 477 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 478 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 479 size_t priv); 480 void pci_free_host_bridge(struct pci_host_bridge *bridge); 481 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 482 483 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 484 void (*release_fn)(struct pci_host_bridge *), 485 void *release_data); 486 487 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 488 489 /* 490 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 491 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 492 * buses below host bridges or subtractive decode bridges) go in the list. 493 * Use pci_bus_for_each_resource() to iterate through all the resources. 494 */ 495 496 /* 497 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 498 * and there's no way to program the bridge with the details of the window. 499 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 500 * decode bit set, because they are explicit and can be programmed with _SRS. 501 */ 502 #define PCI_SUBTRACTIVE_DECODE 0x1 503 504 struct pci_bus_resource { 505 struct list_head list; 506 struct resource *res; 507 unsigned int flags; 508 }; 509 510 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 511 512 struct pci_bus { 513 struct list_head node; /* node in list of buses */ 514 struct pci_bus *parent; /* parent bus this bridge is on */ 515 struct list_head children; /* list of child buses */ 516 struct list_head devices; /* list of devices on this bus */ 517 struct pci_dev *self; /* bridge device as seen by parent */ 518 struct list_head slots; /* list of slots on this bus; 519 protected by pci_slot_mutex */ 520 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 521 struct list_head resources; /* address space routed to this bus */ 522 struct resource busn_res; /* bus numbers routed to this bus */ 523 524 struct pci_ops *ops; /* configuration access functions */ 525 struct msi_controller *msi; /* MSI controller */ 526 void *sysdata; /* hook for sys-specific extension */ 527 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 528 529 unsigned char number; /* bus number */ 530 unsigned char primary; /* number of primary bridge */ 531 unsigned char max_bus_speed; /* enum pci_bus_speed */ 532 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 533 #ifdef CONFIG_PCI_DOMAINS_GENERIC 534 int domain_nr; 535 #endif 536 537 char name[48]; 538 539 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 540 pci_bus_flags_t bus_flags; /* inherited by child buses */ 541 struct device *bridge; 542 struct device dev; 543 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 544 struct bin_attribute *legacy_mem; /* legacy mem */ 545 unsigned int is_added:1; 546 }; 547 548 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 549 550 /* 551 * Returns true if the PCI bus is root (behind host-PCI bridge), 552 * false otherwise 553 * 554 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 555 * This is incorrect because "virtual" buses added for SR-IOV (via 556 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 557 */ 558 static inline bool pci_is_root_bus(struct pci_bus *pbus) 559 { 560 return !(pbus->parent); 561 } 562 563 /** 564 * pci_is_bridge - check if the PCI device is a bridge 565 * @dev: PCI device 566 * 567 * Return true if the PCI device is bridge whether it has subordinate 568 * or not. 569 */ 570 static inline bool pci_is_bridge(struct pci_dev *dev) 571 { 572 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 573 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 574 } 575 576 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 577 { 578 dev = pci_physfn(dev); 579 if (pci_is_root_bus(dev->bus)) 580 return NULL; 581 582 return dev->bus->self; 583 } 584 585 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 586 void pci_put_host_bridge_device(struct device *dev); 587 588 #ifdef CONFIG_PCI_MSI 589 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 590 { 591 return pci_dev->msi_enabled || pci_dev->msix_enabled; 592 } 593 #else 594 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 595 #endif 596 597 /* 598 * Error values that may be returned by PCI functions. 599 */ 600 #define PCIBIOS_SUCCESSFUL 0x00 601 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 602 #define PCIBIOS_BAD_VENDOR_ID 0x83 603 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 604 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 605 #define PCIBIOS_SET_FAILED 0x88 606 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 607 608 /* 609 * Translate above to generic errno for passing back through non-PCI code. 610 */ 611 static inline int pcibios_err_to_errno(int err) 612 { 613 if (err <= PCIBIOS_SUCCESSFUL) 614 return err; /* Assume already errno */ 615 616 switch (err) { 617 case PCIBIOS_FUNC_NOT_SUPPORTED: 618 return -ENOENT; 619 case PCIBIOS_BAD_VENDOR_ID: 620 return -ENOTTY; 621 case PCIBIOS_DEVICE_NOT_FOUND: 622 return -ENODEV; 623 case PCIBIOS_BAD_REGISTER_NUMBER: 624 return -EFAULT; 625 case PCIBIOS_SET_FAILED: 626 return -EIO; 627 case PCIBIOS_BUFFER_TOO_SMALL: 628 return -ENOSPC; 629 } 630 631 return -ERANGE; 632 } 633 634 /* Low-level architecture-dependent routines */ 635 636 struct pci_ops { 637 int (*add_bus)(struct pci_bus *bus); 638 void (*remove_bus)(struct pci_bus *bus); 639 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 640 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 641 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 642 }; 643 644 /* 645 * ACPI needs to be able to access PCI config space before we've done a 646 * PCI bus scan and created pci_bus structures. 647 */ 648 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 649 int reg, int len, u32 *val); 650 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 651 int reg, int len, u32 val); 652 653 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 654 typedef u64 pci_bus_addr_t; 655 #else 656 typedef u32 pci_bus_addr_t; 657 #endif 658 659 struct pci_bus_region { 660 pci_bus_addr_t start; 661 pci_bus_addr_t end; 662 }; 663 664 struct pci_dynids { 665 spinlock_t lock; /* protects list, index */ 666 struct list_head list; /* for IDs added at runtime */ 667 }; 668 669 670 /* 671 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 672 * a set of callbacks in struct pci_error_handlers, that device driver 673 * will be notified of PCI bus errors, and will be driven to recovery 674 * when an error occurs. 675 */ 676 677 typedef unsigned int __bitwise pci_ers_result_t; 678 679 enum pci_ers_result { 680 /* no result/none/not supported in device driver */ 681 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 682 683 /* Device driver can recover without slot reset */ 684 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 685 686 /* Device driver wants slot to be reset. */ 687 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 688 689 /* Device has completely failed, is unrecoverable */ 690 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 691 692 /* Device driver is fully recovered and operational */ 693 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 694 695 /* No AER capabilities registered for the driver */ 696 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 697 }; 698 699 /* PCI bus error event callbacks */ 700 struct pci_error_handlers { 701 /* PCI bus error detected on this device */ 702 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 703 enum pci_channel_state error); 704 705 /* MMIO has been re-enabled, but not DMA */ 706 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 707 708 /* PCI slot has been reset */ 709 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 710 711 /* PCI function reset prepare or completed */ 712 void (*reset_prepare)(struct pci_dev *dev); 713 void (*reset_done)(struct pci_dev *dev); 714 715 /* Device driver may resume normal operations */ 716 void (*resume)(struct pci_dev *dev); 717 }; 718 719 720 struct module; 721 struct pci_driver { 722 struct list_head node; 723 const char *name; 724 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 725 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 726 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 727 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 728 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 729 int (*resume_early) (struct pci_dev *dev); 730 int (*resume) (struct pci_dev *dev); /* Device woken up */ 731 void (*shutdown) (struct pci_dev *dev); 732 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 733 const struct pci_error_handlers *err_handler; 734 struct device_driver driver; 735 struct pci_dynids dynids; 736 }; 737 738 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 739 740 /** 741 * PCI_DEVICE - macro used to describe a specific pci device 742 * @vend: the 16 bit PCI Vendor ID 743 * @dev: the 16 bit PCI Device ID 744 * 745 * This macro is used to create a struct pci_device_id that matches a 746 * specific device. The subvendor and subdevice fields will be set to 747 * PCI_ANY_ID. 748 */ 749 #define PCI_DEVICE(vend,dev) \ 750 .vendor = (vend), .device = (dev), \ 751 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 752 753 /** 754 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 755 * @vend: the 16 bit PCI Vendor ID 756 * @dev: the 16 bit PCI Device ID 757 * @subvend: the 16 bit PCI Subvendor ID 758 * @subdev: the 16 bit PCI Subdevice ID 759 * 760 * This macro is used to create a struct pci_device_id that matches a 761 * specific device with subsystem information. 762 */ 763 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 764 .vendor = (vend), .device = (dev), \ 765 .subvendor = (subvend), .subdevice = (subdev) 766 767 /** 768 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 769 * @dev_class: the class, subclass, prog-if triple for this device 770 * @dev_class_mask: the class mask for this device 771 * 772 * This macro is used to create a struct pci_device_id that matches a 773 * specific PCI class. The vendor, device, subvendor, and subdevice 774 * fields will be set to PCI_ANY_ID. 775 */ 776 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 777 .class = (dev_class), .class_mask = (dev_class_mask), \ 778 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 779 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 780 781 /** 782 * PCI_VDEVICE - macro used to describe a specific pci device in short form 783 * @vend: the vendor name 784 * @dev: the 16 bit PCI Device ID 785 * 786 * This macro is used to create a struct pci_device_id that matches a 787 * specific PCI device. The subvendor, and subdevice fields will be set 788 * to PCI_ANY_ID. The macro allows the next field to follow as the device 789 * private data. 790 */ 791 792 #define PCI_VDEVICE(vend, dev) \ 793 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 794 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 795 796 enum { 797 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ 798 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ 799 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ 800 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ 801 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ 802 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 803 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ 804 }; 805 806 /* these external functions are only available when PCI support is enabled */ 807 #ifdef CONFIG_PCI 808 809 extern unsigned int pci_flags; 810 811 static inline void pci_set_flags(int flags) { pci_flags = flags; } 812 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 813 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 814 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 815 816 void pcie_bus_configure_settings(struct pci_bus *bus); 817 818 enum pcie_bus_config_types { 819 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 820 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 821 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 822 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 823 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 824 }; 825 826 extern enum pcie_bus_config_types pcie_bus_config; 827 828 extern struct bus_type pci_bus_type; 829 830 /* Do NOT directly access these two variables, unless you are arch-specific PCI 831 * code, or PCI core code. */ 832 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 833 /* Some device drivers need know if PCI is initiated */ 834 int no_pci_devices(void); 835 836 void pcibios_resource_survey_bus(struct pci_bus *bus); 837 void pcibios_bus_add_device(struct pci_dev *pdev); 838 void pcibios_add_bus(struct pci_bus *bus); 839 void pcibios_remove_bus(struct pci_bus *bus); 840 void pcibios_fixup_bus(struct pci_bus *); 841 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 842 /* Architecture-specific versions may override this (weak) */ 843 char *pcibios_setup(char *str); 844 845 /* Used only when drivers/pci/setup.c is used */ 846 resource_size_t pcibios_align_resource(void *, const struct resource *, 847 resource_size_t, 848 resource_size_t); 849 void pcibios_update_irq(struct pci_dev *, int irq); 850 851 /* Weak but can be overriden by arch */ 852 void pci_fixup_cardbus(struct pci_bus *); 853 854 /* Generic PCI functions used internally */ 855 856 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 857 struct resource *res); 858 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 859 struct pci_bus_region *region); 860 void pcibios_scan_specific_bus(int busn); 861 struct pci_bus *pci_find_bus(int domain, int busnr); 862 void pci_bus_add_devices(const struct pci_bus *bus); 863 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 864 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 865 struct pci_ops *ops, void *sysdata, 866 struct list_head *resources); 867 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 868 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 869 void pci_bus_release_busn_res(struct pci_bus *b); 870 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 871 struct pci_ops *ops, void *sysdata, 872 struct list_head *resources); 873 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 874 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 875 int busnr); 876 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 877 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 878 const char *name, 879 struct hotplug_slot *hotplug); 880 void pci_destroy_slot(struct pci_slot *slot); 881 #ifdef CONFIG_SYSFS 882 void pci_dev_assign_slot(struct pci_dev *dev); 883 #else 884 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 885 #endif 886 int pci_scan_slot(struct pci_bus *bus, int devfn); 887 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 888 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 889 unsigned int pci_scan_child_bus(struct pci_bus *bus); 890 void pci_bus_add_device(struct pci_dev *dev); 891 void pci_read_bridge_bases(struct pci_bus *child); 892 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 893 struct resource *res); 894 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 895 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 896 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 897 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 898 struct pci_dev *pci_dev_get(struct pci_dev *dev); 899 void pci_dev_put(struct pci_dev *dev); 900 void pci_remove_bus(struct pci_bus *b); 901 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 902 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 903 void pci_stop_root_bus(struct pci_bus *bus); 904 void pci_remove_root_bus(struct pci_bus *bus); 905 void pci_setup_cardbus(struct pci_bus *bus); 906 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 907 void pci_sort_breadthfirst(void); 908 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 909 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 910 911 /* Generic PCI functions exported to card drivers */ 912 913 enum pci_lost_interrupt_reason { 914 PCI_LOST_IRQ_NO_INFORMATION = 0, 915 PCI_LOST_IRQ_DISABLE_MSI, 916 PCI_LOST_IRQ_DISABLE_MSIX, 917 PCI_LOST_IRQ_DISABLE_ACPI, 918 }; 919 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 920 int pci_find_capability(struct pci_dev *dev, int cap); 921 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 922 int pci_find_ext_capability(struct pci_dev *dev, int cap); 923 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 924 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 925 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 926 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 927 928 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 929 struct pci_dev *from); 930 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 931 unsigned int ss_vendor, unsigned int ss_device, 932 struct pci_dev *from); 933 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 934 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 935 unsigned int devfn); 936 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 937 unsigned int devfn) 938 { 939 return pci_get_domain_bus_and_slot(0, bus, devfn); 940 } 941 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 942 int pci_dev_present(const struct pci_device_id *ids); 943 944 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 945 int where, u8 *val); 946 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 947 int where, u16 *val); 948 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 949 int where, u32 *val); 950 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 951 int where, u8 val); 952 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 953 int where, u16 val); 954 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 955 int where, u32 val); 956 957 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 958 int where, int size, u32 *val); 959 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 960 int where, int size, u32 val); 961 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 962 int where, int size, u32 *val); 963 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 964 int where, int size, u32 val); 965 966 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 967 968 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 969 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 970 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 971 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 972 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 973 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 974 975 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 976 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 977 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 978 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 979 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 980 u16 clear, u16 set); 981 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 982 u32 clear, u32 set); 983 984 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 985 u16 set) 986 { 987 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 988 } 989 990 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 991 u32 set) 992 { 993 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 994 } 995 996 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 997 u16 clear) 998 { 999 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1000 } 1001 1002 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1003 u32 clear) 1004 { 1005 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1006 } 1007 1008 /* user-space driven config access */ 1009 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1010 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1011 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1012 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1013 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1014 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1015 1016 int __must_check pci_enable_device(struct pci_dev *dev); 1017 int __must_check pci_enable_device_io(struct pci_dev *dev); 1018 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1019 int __must_check pci_reenable_device(struct pci_dev *); 1020 int __must_check pcim_enable_device(struct pci_dev *pdev); 1021 void pcim_pin_device(struct pci_dev *pdev); 1022 1023 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1024 { 1025 /* 1026 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1027 * writable and no quirk has marked the feature broken. 1028 */ 1029 return !pdev->broken_intx_masking; 1030 } 1031 1032 static inline int pci_is_enabled(struct pci_dev *pdev) 1033 { 1034 return (atomic_read(&pdev->enable_cnt) > 0); 1035 } 1036 1037 static inline int pci_is_managed(struct pci_dev *pdev) 1038 { 1039 return pdev->is_managed; 1040 } 1041 1042 void pci_disable_device(struct pci_dev *dev); 1043 1044 extern unsigned int pcibios_max_latency; 1045 void pci_set_master(struct pci_dev *dev); 1046 void pci_clear_master(struct pci_dev *dev); 1047 1048 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1049 int pci_set_cacheline_size(struct pci_dev *dev); 1050 #define HAVE_PCI_SET_MWI 1051 int __must_check pci_set_mwi(struct pci_dev *dev); 1052 int pci_try_set_mwi(struct pci_dev *dev); 1053 void pci_clear_mwi(struct pci_dev *dev); 1054 void pci_intx(struct pci_dev *dev, int enable); 1055 bool pci_check_and_mask_intx(struct pci_dev *dev); 1056 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1057 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1058 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1059 int pcix_get_max_mmrbc(struct pci_dev *dev); 1060 int pcix_get_mmrbc(struct pci_dev *dev); 1061 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1062 int pcie_get_readrq(struct pci_dev *dev); 1063 int pcie_set_readrq(struct pci_dev *dev, int rq); 1064 int pcie_get_mps(struct pci_dev *dev); 1065 int pcie_set_mps(struct pci_dev *dev, int mps); 1066 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1067 enum pcie_link_width *width); 1068 void pcie_flr(struct pci_dev *dev); 1069 int __pci_reset_function(struct pci_dev *dev); 1070 int __pci_reset_function_locked(struct pci_dev *dev); 1071 int pci_reset_function(struct pci_dev *dev); 1072 int pci_reset_function_locked(struct pci_dev *dev); 1073 int pci_try_reset_function(struct pci_dev *dev); 1074 int pci_probe_reset_slot(struct pci_slot *slot); 1075 int pci_reset_slot(struct pci_slot *slot); 1076 int pci_try_reset_slot(struct pci_slot *slot); 1077 int pci_probe_reset_bus(struct pci_bus *bus); 1078 int pci_reset_bus(struct pci_bus *bus); 1079 int pci_try_reset_bus(struct pci_bus *bus); 1080 void pci_reset_secondary_bus(struct pci_dev *dev); 1081 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1082 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1083 void pci_update_resource(struct pci_dev *dev, int resno); 1084 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1085 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1086 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1087 bool pci_device_is_present(struct pci_dev *pdev); 1088 void pci_ignore_hotplug(struct pci_dev *dev); 1089 1090 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1091 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1092 const char *fmt, ...); 1093 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1094 1095 /* ROM control related routines */ 1096 int pci_enable_rom(struct pci_dev *pdev); 1097 void pci_disable_rom(struct pci_dev *pdev); 1098 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1099 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1100 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1101 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1102 1103 /* Power management related routines */ 1104 int pci_save_state(struct pci_dev *dev); 1105 void pci_restore_state(struct pci_dev *dev); 1106 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1107 int pci_load_saved_state(struct pci_dev *dev, 1108 struct pci_saved_state *state); 1109 int pci_load_and_free_saved_state(struct pci_dev *dev, 1110 struct pci_saved_state **state); 1111 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1112 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1113 u16 cap); 1114 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1115 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1116 u16 cap, unsigned int size); 1117 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1118 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1119 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1120 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1121 void pci_pme_active(struct pci_dev *dev, bool enable); 1122 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1123 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1124 int pci_prepare_to_sleep(struct pci_dev *dev); 1125 int pci_back_from_sleep(struct pci_dev *dev); 1126 bool pci_dev_run_wake(struct pci_dev *dev); 1127 bool pci_check_pme_status(struct pci_dev *dev); 1128 void pci_pme_wakeup_bus(struct pci_bus *bus); 1129 void pci_d3cold_enable(struct pci_dev *dev); 1130 void pci_d3cold_disable(struct pci_dev *dev); 1131 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1132 1133 /* PCI Virtual Channel */ 1134 int pci_save_vc_state(struct pci_dev *dev); 1135 void pci_restore_vc_state(struct pci_dev *dev); 1136 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1137 1138 /* For use by arch with custom probe code */ 1139 void set_pcie_port_type(struct pci_dev *pdev); 1140 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1141 1142 /* Functions for PCI Hotplug drivers to use */ 1143 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1144 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1145 unsigned int pci_rescan_bus(struct pci_bus *bus); 1146 void pci_lock_rescan_remove(void); 1147 void pci_unlock_rescan_remove(void); 1148 1149 /* Vital product data routines */ 1150 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1151 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1152 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1153 1154 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1155 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1156 void pci_bus_assign_resources(const struct pci_bus *bus); 1157 void pci_bus_claim_resources(struct pci_bus *bus); 1158 void pci_bus_size_bridges(struct pci_bus *bus); 1159 int pci_claim_resource(struct pci_dev *, int); 1160 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1161 void pci_assign_unassigned_resources(void); 1162 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1163 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1164 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1165 void pdev_enable_device(struct pci_dev *); 1166 int pci_enable_resources(struct pci_dev *, int mask); 1167 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1168 int (*)(const struct pci_dev *, u8, u8)); 1169 void pci_assign_irq(struct pci_dev *dev); 1170 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1171 #define HAVE_PCI_REQ_REGIONS 2 1172 int __must_check pci_request_regions(struct pci_dev *, const char *); 1173 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1174 void pci_release_regions(struct pci_dev *); 1175 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1176 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1177 void pci_release_region(struct pci_dev *, int); 1178 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1179 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1180 void pci_release_selected_regions(struct pci_dev *, int); 1181 1182 /* drivers/pci/bus.c */ 1183 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1184 void pci_bus_put(struct pci_bus *bus); 1185 void pci_add_resource(struct list_head *resources, struct resource *res); 1186 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1187 resource_size_t offset); 1188 void pci_free_resource_list(struct list_head *resources); 1189 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1190 unsigned int flags); 1191 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1192 void pci_bus_remove_resources(struct pci_bus *bus); 1193 int devm_request_pci_bus_resources(struct device *dev, 1194 struct list_head *resources); 1195 1196 #define pci_bus_for_each_resource(bus, res, i) \ 1197 for (i = 0; \ 1198 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1199 i++) 1200 1201 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1202 struct resource *res, resource_size_t size, 1203 resource_size_t align, resource_size_t min, 1204 unsigned long type_mask, 1205 resource_size_t (*alignf)(void *, 1206 const struct resource *, 1207 resource_size_t, 1208 resource_size_t), 1209 void *alignf_data); 1210 1211 1212 int pci_register_io_range(phys_addr_t addr, resource_size_t size); 1213 unsigned long pci_address_to_pio(phys_addr_t addr); 1214 phys_addr_t pci_pio_to_address(unsigned long pio); 1215 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1216 void pci_unmap_iospace(struct resource *res); 1217 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1218 resource_size_t offset, 1219 resource_size_t size); 1220 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1221 struct resource *res); 1222 1223 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1224 { 1225 struct pci_bus_region region; 1226 1227 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1228 return region.start; 1229 } 1230 1231 /* Proper probing supporting hot-pluggable devices */ 1232 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1233 const char *mod_name); 1234 1235 /* 1236 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1237 */ 1238 #define pci_register_driver(driver) \ 1239 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1240 1241 void pci_unregister_driver(struct pci_driver *dev); 1242 1243 /** 1244 * module_pci_driver() - Helper macro for registering a PCI driver 1245 * @__pci_driver: pci_driver struct 1246 * 1247 * Helper macro for PCI drivers which do not do anything special in module 1248 * init/exit. This eliminates a lot of boilerplate. Each module may only 1249 * use this macro once, and calling it replaces module_init() and module_exit() 1250 */ 1251 #define module_pci_driver(__pci_driver) \ 1252 module_driver(__pci_driver, pci_register_driver, \ 1253 pci_unregister_driver) 1254 1255 /** 1256 * builtin_pci_driver() - Helper macro for registering a PCI driver 1257 * @__pci_driver: pci_driver struct 1258 * 1259 * Helper macro for PCI drivers which do not do anything special in their 1260 * init code. This eliminates a lot of boilerplate. Each driver may only 1261 * use this macro once, and calling it replaces device_initcall(...) 1262 */ 1263 #define builtin_pci_driver(__pci_driver) \ 1264 builtin_driver(__pci_driver, pci_register_driver) 1265 1266 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1267 int pci_add_dynid(struct pci_driver *drv, 1268 unsigned int vendor, unsigned int device, 1269 unsigned int subvendor, unsigned int subdevice, 1270 unsigned int class, unsigned int class_mask, 1271 unsigned long driver_data); 1272 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1273 struct pci_dev *dev); 1274 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1275 int pass); 1276 1277 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1278 void *userdata); 1279 int pci_cfg_space_size(struct pci_dev *dev); 1280 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1281 void pci_setup_bridge(struct pci_bus *bus); 1282 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1283 unsigned long type); 1284 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1285 1286 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1287 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1288 1289 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1290 unsigned int command_bits, u32 flags); 1291 1292 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ 1293 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ 1294 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ 1295 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ 1296 #define PCI_IRQ_ALL_TYPES \ 1297 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1298 1299 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1300 1301 #include <linux/pci-dma.h> 1302 #include <linux/dmapool.h> 1303 1304 #define pci_pool dma_pool 1305 #define pci_pool_create(name, pdev, size, align, allocation) \ 1306 dma_pool_create(name, &pdev->dev, size, align, allocation) 1307 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1308 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1309 #define pci_pool_zalloc(pool, flags, handle) \ 1310 dma_pool_zalloc(pool, flags, handle) 1311 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1312 1313 struct msix_entry { 1314 u32 vector; /* kernel uses to write allocated vector */ 1315 u16 entry; /* driver uses to specify entry, OS writes */ 1316 }; 1317 1318 #ifdef CONFIG_PCI_MSI 1319 int pci_msi_vec_count(struct pci_dev *dev); 1320 void pci_disable_msi(struct pci_dev *dev); 1321 int pci_msix_vec_count(struct pci_dev *dev); 1322 void pci_disable_msix(struct pci_dev *dev); 1323 void pci_restore_msi_state(struct pci_dev *dev); 1324 int pci_msi_enabled(void); 1325 int pci_enable_msi(struct pci_dev *dev); 1326 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1327 int minvec, int maxvec); 1328 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1329 struct msix_entry *entries, int nvec) 1330 { 1331 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1332 if (rc < 0) 1333 return rc; 1334 return 0; 1335 } 1336 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1337 unsigned int max_vecs, unsigned int flags, 1338 const struct irq_affinity *affd); 1339 1340 void pci_free_irq_vectors(struct pci_dev *dev); 1341 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1342 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1343 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1344 1345 #else 1346 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1347 static inline void pci_disable_msi(struct pci_dev *dev) { } 1348 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1349 static inline void pci_disable_msix(struct pci_dev *dev) { } 1350 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1351 static inline int pci_msi_enabled(void) { return 0; } 1352 static inline int pci_enable_msi(struct pci_dev *dev) 1353 { return -ENOSYS; } 1354 static inline int pci_enable_msix_range(struct pci_dev *dev, 1355 struct msix_entry *entries, int minvec, int maxvec) 1356 { return -ENOSYS; } 1357 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1358 struct msix_entry *entries, int nvec) 1359 { return -ENOSYS; } 1360 1361 static inline int 1362 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1363 unsigned int max_vecs, unsigned int flags, 1364 const struct irq_affinity *aff_desc) 1365 { 1366 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1367 return 1; 1368 return -ENOSPC; 1369 } 1370 1371 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1372 { 1373 } 1374 1375 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1376 { 1377 if (WARN_ON_ONCE(nr > 0)) 1378 return -EINVAL; 1379 return dev->irq; 1380 } 1381 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1382 int vec) 1383 { 1384 return cpu_possible_mask; 1385 } 1386 1387 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1388 { 1389 return first_online_node; 1390 } 1391 #endif 1392 1393 static inline int 1394 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1395 unsigned int max_vecs, unsigned int flags) 1396 { 1397 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1398 NULL); 1399 } 1400 1401 #ifdef CONFIG_PCIEPORTBUS 1402 extern bool pcie_ports_disabled; 1403 extern bool pcie_ports_auto; 1404 #else 1405 #define pcie_ports_disabled true 1406 #define pcie_ports_auto false 1407 #endif 1408 1409 #ifdef CONFIG_PCIEASPM 1410 bool pcie_aspm_support_enabled(void); 1411 #else 1412 static inline bool pcie_aspm_support_enabled(void) { return false; } 1413 #endif 1414 1415 #ifdef CONFIG_PCIEAER 1416 void pci_no_aer(void); 1417 bool pci_aer_available(void); 1418 int pci_aer_init(struct pci_dev *dev); 1419 #else 1420 static inline void pci_no_aer(void) { } 1421 static inline bool pci_aer_available(void) { return false; } 1422 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } 1423 #endif 1424 1425 #ifdef CONFIG_PCIE_ECRC 1426 void pcie_set_ecrc_checking(struct pci_dev *dev); 1427 void pcie_ecrc_get_policy(char *str); 1428 #else 1429 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1430 static inline void pcie_ecrc_get_policy(char *str) { } 1431 #endif 1432 1433 #ifdef CONFIG_HT_IRQ 1434 /* The functions a driver should call */ 1435 int ht_create_irq(struct pci_dev *dev, int idx); 1436 void ht_destroy_irq(unsigned int irq); 1437 #endif /* CONFIG_HT_IRQ */ 1438 1439 #ifdef CONFIG_PCI_ATS 1440 /* Address Translation Service */ 1441 void pci_ats_init(struct pci_dev *dev); 1442 int pci_enable_ats(struct pci_dev *dev, int ps); 1443 void pci_disable_ats(struct pci_dev *dev); 1444 int pci_ats_queue_depth(struct pci_dev *dev); 1445 #else 1446 static inline void pci_ats_init(struct pci_dev *d) { } 1447 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1448 static inline void pci_disable_ats(struct pci_dev *d) { } 1449 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1450 #endif 1451 1452 #ifdef CONFIG_PCIE_PTM 1453 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1454 #else 1455 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1456 { return -EINVAL; } 1457 #endif 1458 1459 void pci_cfg_access_lock(struct pci_dev *dev); 1460 bool pci_cfg_access_trylock(struct pci_dev *dev); 1461 void pci_cfg_access_unlock(struct pci_dev *dev); 1462 1463 /* 1464 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1465 * a PCI domain is defined to be a set of PCI buses which share 1466 * configuration space. 1467 */ 1468 #ifdef CONFIG_PCI_DOMAINS 1469 extern int pci_domains_supported; 1470 int pci_get_new_domain_nr(void); 1471 #else 1472 enum { pci_domains_supported = 0 }; 1473 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1474 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1475 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1476 #endif /* CONFIG_PCI_DOMAINS */ 1477 1478 /* 1479 * Generic implementation for PCI domain support. If your 1480 * architecture does not need custom management of PCI 1481 * domains then this implementation will be used 1482 */ 1483 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1484 static inline int pci_domain_nr(struct pci_bus *bus) 1485 { 1486 return bus->domain_nr; 1487 } 1488 #ifdef CONFIG_ACPI 1489 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1490 #else 1491 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1492 { return 0; } 1493 #endif 1494 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1495 #endif 1496 1497 /* some architectures require additional setup to direct VGA traffic */ 1498 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1499 unsigned int command_bits, u32 flags); 1500 void pci_register_set_vga_state(arch_set_vga_state_t func); 1501 1502 static inline int 1503 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1504 { 1505 return pci_request_selected_regions(pdev, 1506 pci_select_bars(pdev, IORESOURCE_IO), name); 1507 } 1508 1509 static inline void 1510 pci_release_io_regions(struct pci_dev *pdev) 1511 { 1512 return pci_release_selected_regions(pdev, 1513 pci_select_bars(pdev, IORESOURCE_IO)); 1514 } 1515 1516 static inline int 1517 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1518 { 1519 return pci_request_selected_regions(pdev, 1520 pci_select_bars(pdev, IORESOURCE_MEM), name); 1521 } 1522 1523 static inline void 1524 pci_release_mem_regions(struct pci_dev *pdev) 1525 { 1526 return pci_release_selected_regions(pdev, 1527 pci_select_bars(pdev, IORESOURCE_MEM)); 1528 } 1529 1530 #else /* CONFIG_PCI is not enabled */ 1531 1532 static inline void pci_set_flags(int flags) { } 1533 static inline void pci_add_flags(int flags) { } 1534 static inline void pci_clear_flags(int flags) { } 1535 static inline int pci_has_flag(int flag) { return 0; } 1536 1537 /* 1538 * If the system does not have PCI, clearly these return errors. Define 1539 * these as simple inline functions to avoid hair in drivers. 1540 */ 1541 1542 #define _PCI_NOP(o, s, t) \ 1543 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1544 int where, t val) \ 1545 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1546 1547 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1548 _PCI_NOP(o, word, u16 x) \ 1549 _PCI_NOP(o, dword, u32 x) 1550 _PCI_NOP_ALL(read, *) 1551 _PCI_NOP_ALL(write,) 1552 1553 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1554 unsigned int device, 1555 struct pci_dev *from) 1556 { return NULL; } 1557 1558 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1559 unsigned int device, 1560 unsigned int ss_vendor, 1561 unsigned int ss_device, 1562 struct pci_dev *from) 1563 { return NULL; } 1564 1565 static inline struct pci_dev *pci_get_class(unsigned int class, 1566 struct pci_dev *from) 1567 { return NULL; } 1568 1569 #define pci_dev_present(ids) (0) 1570 #define no_pci_devices() (1) 1571 #define pci_dev_put(dev) do { } while (0) 1572 1573 static inline void pci_set_master(struct pci_dev *dev) { } 1574 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1575 static inline void pci_disable_device(struct pci_dev *dev) { } 1576 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1577 { return -EBUSY; } 1578 static inline int __pci_register_driver(struct pci_driver *drv, 1579 struct module *owner) 1580 { return 0; } 1581 static inline int pci_register_driver(struct pci_driver *drv) 1582 { return 0; } 1583 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1584 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1585 { return 0; } 1586 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1587 int cap) 1588 { return 0; } 1589 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1590 { return 0; } 1591 1592 /* Power management related routines */ 1593 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1594 static inline void pci_restore_state(struct pci_dev *dev) { } 1595 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1596 { return 0; } 1597 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1598 { return 0; } 1599 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1600 pm_message_t state) 1601 { return PCI_D0; } 1602 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1603 int enable) 1604 { return 0; } 1605 1606 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1607 struct resource *res) 1608 { return NULL; } 1609 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1610 { return -EIO; } 1611 static inline void pci_release_regions(struct pci_dev *dev) { } 1612 1613 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1614 1615 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1616 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1617 { return 0; } 1618 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1619 1620 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1621 { return NULL; } 1622 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1623 unsigned int devfn) 1624 { return NULL; } 1625 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1626 unsigned int devfn) 1627 { return NULL; } 1628 1629 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1630 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1631 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1632 1633 #define dev_is_pci(d) (false) 1634 #define dev_is_pf(d) (false) 1635 #endif /* CONFIG_PCI */ 1636 1637 /* Include architecture-dependent settings and functions */ 1638 1639 #include <asm/pci.h> 1640 1641 /* These two functions provide almost identical functionality. Depennding 1642 * on the architecture, one will be implemented as a wrapper around the 1643 * other (in drivers/pci/mmap.c). 1644 * 1645 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1646 * is expected to be an offset within that region. 1647 * 1648 * pci_mmap_page_range() is the legacy architecture-specific interface, 1649 * which accepts a "user visible" resource address converted by 1650 * pci_resource_to_user(), as used in the legacy mmap() interface in 1651 * /proc/bus/pci/. 1652 */ 1653 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1654 struct vm_area_struct *vma, 1655 enum pci_mmap_state mmap_state, int write_combine); 1656 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1657 struct vm_area_struct *vma, 1658 enum pci_mmap_state mmap_state, int write_combine); 1659 1660 #ifndef arch_can_pci_mmap_wc 1661 #define arch_can_pci_mmap_wc() 0 1662 #endif 1663 1664 #ifndef arch_can_pci_mmap_io 1665 #define arch_can_pci_mmap_io() 0 1666 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1667 #else 1668 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1669 #endif 1670 1671 #ifndef pci_root_bus_fwnode 1672 #define pci_root_bus_fwnode(bus) NULL 1673 #endif 1674 1675 /* these helpers provide future and backwards compatibility 1676 * for accessing popular PCI BAR info */ 1677 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1678 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1679 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1680 #define pci_resource_len(dev,bar) \ 1681 ((pci_resource_start((dev), (bar)) == 0 && \ 1682 pci_resource_end((dev), (bar)) == \ 1683 pci_resource_start((dev), (bar))) ? 0 : \ 1684 \ 1685 (pci_resource_end((dev), (bar)) - \ 1686 pci_resource_start((dev), (bar)) + 1)) 1687 1688 /* Similar to the helpers above, these manipulate per-pci_dev 1689 * driver-specific data. They are really just a wrapper around 1690 * the generic device structure functions of these calls. 1691 */ 1692 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1693 { 1694 return dev_get_drvdata(&pdev->dev); 1695 } 1696 1697 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1698 { 1699 dev_set_drvdata(&pdev->dev, data); 1700 } 1701 1702 /* If you want to know what to call your pci_dev, ask this function. 1703 * Again, it's a wrapper around the generic device. 1704 */ 1705 static inline const char *pci_name(const struct pci_dev *pdev) 1706 { 1707 return dev_name(&pdev->dev); 1708 } 1709 1710 1711 /* Some archs don't want to expose struct resource to userland as-is 1712 * in sysfs and /proc 1713 */ 1714 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1715 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1716 const struct resource *rsrc, 1717 resource_size_t *start, resource_size_t *end); 1718 #else 1719 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1720 const struct resource *rsrc, resource_size_t *start, 1721 resource_size_t *end) 1722 { 1723 *start = rsrc->start; 1724 *end = rsrc->end; 1725 } 1726 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1727 1728 1729 /* 1730 * The world is not perfect and supplies us with broken PCI devices. 1731 * For at least a part of these bugs we need a work-around, so both 1732 * generic (drivers/pci/quirks.c) and per-architecture code can define 1733 * fixup hooks to be called for particular buggy devices. 1734 */ 1735 1736 struct pci_fixup { 1737 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1738 u16 device; /* You can use PCI_ANY_ID here of course */ 1739 u32 class; /* You can use PCI_ANY_ID here too */ 1740 unsigned int class_shift; /* should be 0, 8, 16 */ 1741 void (*hook)(struct pci_dev *dev); 1742 }; 1743 1744 enum pci_fixup_pass { 1745 pci_fixup_early, /* Before probing BARs */ 1746 pci_fixup_header, /* After reading configuration header */ 1747 pci_fixup_final, /* Final phase of device fixups */ 1748 pci_fixup_enable, /* pci_enable_device() time */ 1749 pci_fixup_resume, /* pci_device_resume() */ 1750 pci_fixup_suspend, /* pci_device_suspend() */ 1751 pci_fixup_resume_early, /* pci_device_resume_early() */ 1752 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1753 }; 1754 1755 /* Anonymous variables would be nice... */ 1756 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1757 class_shift, hook) \ 1758 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1759 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1760 = { vendor, device, class, class_shift, hook }; 1761 1762 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1763 class_shift, hook) \ 1764 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1765 hook, vendor, device, class, class_shift, hook) 1766 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1767 class_shift, hook) \ 1768 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1769 hook, vendor, device, class, class_shift, hook) 1770 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1771 class_shift, hook) \ 1772 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1773 hook, vendor, device, class, class_shift, hook) 1774 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1775 class_shift, hook) \ 1776 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1777 hook, vendor, device, class, class_shift, hook) 1778 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1779 class_shift, hook) \ 1780 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1781 resume##hook, vendor, device, class, \ 1782 class_shift, hook) 1783 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1784 class_shift, hook) \ 1785 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1786 resume_early##hook, vendor, device, \ 1787 class, class_shift, hook) 1788 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1789 class_shift, hook) \ 1790 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1791 suspend##hook, vendor, device, class, \ 1792 class_shift, hook) 1793 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1794 class_shift, hook) \ 1795 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1796 suspend_late##hook, vendor, device, \ 1797 class, class_shift, hook) 1798 1799 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1800 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1801 hook, vendor, device, PCI_ANY_ID, 0, hook) 1802 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1803 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1804 hook, vendor, device, PCI_ANY_ID, 0, hook) 1805 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1806 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1807 hook, vendor, device, PCI_ANY_ID, 0, hook) 1808 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1809 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1810 hook, vendor, device, PCI_ANY_ID, 0, hook) 1811 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1812 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1813 resume##hook, vendor, device, \ 1814 PCI_ANY_ID, 0, hook) 1815 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1816 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1817 resume_early##hook, vendor, device, \ 1818 PCI_ANY_ID, 0, hook) 1819 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1820 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1821 suspend##hook, vendor, device, \ 1822 PCI_ANY_ID, 0, hook) 1823 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1824 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1825 suspend_late##hook, vendor, device, \ 1826 PCI_ANY_ID, 0, hook) 1827 1828 #ifdef CONFIG_PCI_QUIRKS 1829 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1830 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1831 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1832 #else 1833 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1834 struct pci_dev *dev) { } 1835 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1836 u16 acs_flags) 1837 { 1838 return -ENOTTY; 1839 } 1840 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1841 { 1842 return -ENOTTY; 1843 } 1844 #endif 1845 1846 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1847 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1848 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1849 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1850 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1851 const char *name); 1852 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1853 1854 extern int pci_pci_problems; 1855 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1856 #define PCIPCI_TRITON 2 1857 #define PCIPCI_NATOMA 4 1858 #define PCIPCI_VIAETBF 8 1859 #define PCIPCI_VSFX 16 1860 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1861 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1862 1863 extern unsigned long pci_cardbus_io_size; 1864 extern unsigned long pci_cardbus_mem_size; 1865 extern u8 pci_dfl_cache_line_size; 1866 extern u8 pci_cache_line_size; 1867 1868 extern unsigned long pci_hotplug_io_size; 1869 extern unsigned long pci_hotplug_mem_size; 1870 extern unsigned long pci_hotplug_bus_size; 1871 1872 /* Architecture-specific versions may override these (weak) */ 1873 void pcibios_disable_device(struct pci_dev *dev); 1874 void pcibios_set_master(struct pci_dev *dev); 1875 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1876 enum pcie_reset_state state); 1877 int pcibios_add_device(struct pci_dev *dev); 1878 void pcibios_release_device(struct pci_dev *dev); 1879 void pcibios_penalize_isa_irq(int irq, int active); 1880 int pcibios_alloc_irq(struct pci_dev *dev); 1881 void pcibios_free_irq(struct pci_dev *dev); 1882 1883 #ifdef CONFIG_HIBERNATE_CALLBACKS 1884 extern struct dev_pm_ops pcibios_pm_ops; 1885 #endif 1886 1887 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1888 void __init pci_mmcfg_early_init(void); 1889 void __init pci_mmcfg_late_init(void); 1890 #else 1891 static inline void pci_mmcfg_early_init(void) { } 1892 static inline void pci_mmcfg_late_init(void) { } 1893 #endif 1894 1895 int pci_ext_cfg_avail(void); 1896 1897 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1898 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1899 1900 #ifdef CONFIG_PCI_IOV 1901 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1902 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1903 1904 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1905 void pci_disable_sriov(struct pci_dev *dev); 1906 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset); 1907 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset); 1908 int pci_num_vf(struct pci_dev *dev); 1909 int pci_vfs_assigned(struct pci_dev *dev); 1910 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1911 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1912 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1913 #else 1914 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1915 { 1916 return -ENOSYS; 1917 } 1918 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1919 { 1920 return -ENOSYS; 1921 } 1922 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1923 { return -ENODEV; } 1924 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset) 1925 { 1926 return -ENOSYS; 1927 } 1928 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 1929 int id, int reset) { } 1930 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1931 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1932 static inline int pci_vfs_assigned(struct pci_dev *dev) 1933 { return 0; } 1934 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1935 { return 0; } 1936 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1937 { return 0; } 1938 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1939 { return 0; } 1940 #endif 1941 1942 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1943 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1944 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1945 #endif 1946 1947 /** 1948 * pci_pcie_cap - get the saved PCIe capability offset 1949 * @dev: PCI device 1950 * 1951 * PCIe capability offset is calculated at PCI device initialization 1952 * time and saved in the data structure. This function returns saved 1953 * PCIe capability offset. Using this instead of pci_find_capability() 1954 * reduces unnecessary search in the PCI configuration space. If you 1955 * need to calculate PCIe capability offset from raw device for some 1956 * reasons, please use pci_find_capability() instead. 1957 */ 1958 static inline int pci_pcie_cap(struct pci_dev *dev) 1959 { 1960 return dev->pcie_cap; 1961 } 1962 1963 /** 1964 * pci_is_pcie - check if the PCI device is PCI Express capable 1965 * @dev: PCI device 1966 * 1967 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1968 */ 1969 static inline bool pci_is_pcie(struct pci_dev *dev) 1970 { 1971 return pci_pcie_cap(dev); 1972 } 1973 1974 /** 1975 * pcie_caps_reg - get the PCIe Capabilities Register 1976 * @dev: PCI device 1977 */ 1978 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1979 { 1980 return dev->pcie_flags_reg; 1981 } 1982 1983 /** 1984 * pci_pcie_type - get the PCIe device/port type 1985 * @dev: PCI device 1986 */ 1987 static inline int pci_pcie_type(const struct pci_dev *dev) 1988 { 1989 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1990 } 1991 1992 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 1993 { 1994 while (1) { 1995 if (!pci_is_pcie(dev)) 1996 break; 1997 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 1998 return dev; 1999 if (!dev->bus->self) 2000 break; 2001 dev = dev->bus->self; 2002 } 2003 return NULL; 2004 } 2005 2006 void pci_request_acs(void); 2007 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2008 bool pci_acs_path_enabled(struct pci_dev *start, 2009 struct pci_dev *end, u16 acs_flags); 2010 2011 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2012 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2013 2014 /* Large Resource Data Type Tag Item Names */ 2015 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2016 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2017 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2018 2019 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2020 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2021 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2022 2023 /* Small Resource Data Type Tag Item Names */ 2024 #define PCI_VPD_STIN_END 0x0f /* End */ 2025 2026 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2027 2028 #define PCI_VPD_SRDT_TIN_MASK 0x78 2029 #define PCI_VPD_SRDT_LEN_MASK 0x07 2030 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2031 2032 #define PCI_VPD_LRDT_TAG_SIZE 3 2033 #define PCI_VPD_SRDT_TAG_SIZE 1 2034 2035 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2036 2037 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2038 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2039 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2040 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2041 2042 /** 2043 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2044 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2045 * 2046 * Returns the extracted Large Resource Data Type length. 2047 */ 2048 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2049 { 2050 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2051 } 2052 2053 /** 2054 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2055 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2056 * 2057 * Returns the extracted Large Resource Data Type Tag item. 2058 */ 2059 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2060 { 2061 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2062 } 2063 2064 /** 2065 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2066 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 2067 * 2068 * Returns the extracted Small Resource Data Type length. 2069 */ 2070 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2071 { 2072 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2073 } 2074 2075 /** 2076 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2077 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 2078 * 2079 * Returns the extracted Small Resource Data Type Tag Item. 2080 */ 2081 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2082 { 2083 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2084 } 2085 2086 /** 2087 * pci_vpd_info_field_size - Extracts the information field length 2088 * @lrdt: Pointer to the beginning of an information field header 2089 * 2090 * Returns the extracted information field length. 2091 */ 2092 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2093 { 2094 return info_field[2]; 2095 } 2096 2097 /** 2098 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2099 * @buf: Pointer to buffered vpd data 2100 * @off: The offset into the buffer at which to begin the search 2101 * @len: The length of the vpd buffer 2102 * @rdt: The Resource Data Type to search for 2103 * 2104 * Returns the index where the Resource Data Type was found or 2105 * -ENOENT otherwise. 2106 */ 2107 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2108 2109 /** 2110 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2111 * @buf: Pointer to buffered vpd data 2112 * @off: The offset into the buffer at which to begin the search 2113 * @len: The length of the buffer area, relative to off, in which to search 2114 * @kw: The keyword to search for 2115 * 2116 * Returns the index where the information field keyword was found or 2117 * -ENOENT otherwise. 2118 */ 2119 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2120 unsigned int len, const char *kw); 2121 2122 /* PCI <-> OF binding helpers */ 2123 #ifdef CONFIG_OF 2124 struct device_node; 2125 struct irq_domain; 2126 void pci_set_of_node(struct pci_dev *dev); 2127 void pci_release_of_node(struct pci_dev *dev); 2128 void pci_set_bus_of_node(struct pci_bus *bus); 2129 void pci_release_bus_of_node(struct pci_bus *bus); 2130 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2131 2132 /* Arch may override this (weak) */ 2133 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2134 2135 static inline struct device_node * 2136 pci_device_to_OF_node(const struct pci_dev *pdev) 2137 { 2138 return pdev ? pdev->dev.of_node : NULL; 2139 } 2140 2141 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2142 { 2143 return bus ? bus->dev.of_node : NULL; 2144 } 2145 2146 #else /* CONFIG_OF */ 2147 static inline void pci_set_of_node(struct pci_dev *dev) { } 2148 static inline void pci_release_of_node(struct pci_dev *dev) { } 2149 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2150 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2151 static inline struct device_node * 2152 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 2153 static inline struct irq_domain * 2154 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2155 #endif /* CONFIG_OF */ 2156 2157 #ifdef CONFIG_ACPI 2158 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2159 2160 void 2161 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2162 #else 2163 static inline struct irq_domain * 2164 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2165 #endif 2166 2167 #ifdef CONFIG_EEH 2168 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2169 { 2170 return pdev->dev.archdata.edev; 2171 } 2172 #endif 2173 2174 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2175 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2176 int pci_for_each_dma_alias(struct pci_dev *pdev, 2177 int (*fn)(struct pci_dev *pdev, 2178 u16 alias, void *data), void *data); 2179 2180 /* helper functions for operation of device flag */ 2181 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2182 { 2183 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2184 } 2185 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2186 { 2187 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2188 } 2189 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2190 { 2191 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2192 } 2193 2194 /** 2195 * pci_ari_enabled - query ARI forwarding status 2196 * @bus: the PCI bus 2197 * 2198 * Returns true if ARI forwarding is enabled. 2199 */ 2200 static inline bool pci_ari_enabled(struct pci_bus *bus) 2201 { 2202 return bus->self && bus->self->ari_enabled; 2203 } 2204 2205 /** 2206 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2207 * @pdev: PCI device to check 2208 * 2209 * Walk upwards from @pdev and check for each encountered bridge if it's part 2210 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2211 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2212 */ 2213 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2214 { 2215 struct pci_dev *parent = pdev; 2216 2217 if (pdev->is_thunderbolt) 2218 return true; 2219 2220 while ((parent = pci_upstream_bridge(parent))) 2221 if (parent->is_thunderbolt) 2222 return true; 2223 2224 return false; 2225 } 2226 2227 /* provide the legacy pci_dma_* API */ 2228 #include <linux/pci-dma-compat.h> 2229 2230 #endif /* LINUX_PCI_H */ 2231