1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <linux/msi_api.h> 42 #include <uapi/linux/pci.h> 43 44 #include <linux/pci_ids.h> 45 46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 47 PCI_STATUS_SIG_SYSTEM_ERROR | \ 48 PCI_STATUS_REC_MASTER_ABORT | \ 49 PCI_STATUS_REC_TARGET_ABORT | \ 50 PCI_STATUS_SIG_TARGET_ABORT | \ 51 PCI_STATUS_PARITY) 52 53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 54 #define PCI_NUM_RESET_METHODS 7 55 56 #define PCI_RESET_PROBE true 57 #define PCI_RESET_DO_RESET false 58 59 /* 60 * The PCI interface treats multi-function devices as independent 61 * devices. The slot/function address of each device is encoded 62 * in a single byte as follows: 63 * 64 * 7:3 = slot 65 * 2:0 = function 66 * 67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 68 * In the interest of not exposing interfaces to user-space unnecessarily, 69 * the following kernel-only defines are being added here. 70 */ 71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 74 75 /* pci_slot represents a physical slot */ 76 struct pci_slot { 77 struct pci_bus *bus; /* Bus this slot is on */ 78 struct list_head list; /* Node in list of slots */ 79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 81 struct kobject kobj; 82 }; 83 84 static inline const char *pci_slot_name(const struct pci_slot *slot) 85 { 86 return kobject_name(&slot->kobj); 87 } 88 89 /* File state for mmap()s on /proc/bus/pci/X/Y */ 90 enum pci_mmap_state { 91 pci_mmap_io, 92 pci_mmap_mem 93 }; 94 95 /* For PCI devices, the region numbers are assigned this way: */ 96 enum { 97 /* #0-5: standard PCI resources */ 98 PCI_STD_RESOURCES, 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 100 101 /* #6: expansion ROM resource */ 102 PCI_ROM_RESOURCE, 103 104 /* Device-specific resources */ 105 #ifdef CONFIG_PCI_IOV 106 PCI_IOV_RESOURCES, 107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 108 #endif 109 110 /* PCI-to-PCI (P2P) bridge windows */ 111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 114 115 /* CardBus bridge windows */ 116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 120 121 /* Total number of bridge resources for P2P and CardBus */ 122 #define PCI_BRIDGE_RESOURCE_NUM 4 123 124 /* Resources assigned to buses behind the bridge */ 125 PCI_BRIDGE_RESOURCES, 126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 127 PCI_BRIDGE_RESOURCE_NUM - 1, 128 129 /* Total resources associated with a PCI device */ 130 PCI_NUM_RESOURCES, 131 132 /* Preserve this for compatibility */ 133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 134 }; 135 136 /** 137 * enum pci_interrupt_pin - PCI INTx interrupt values 138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 139 * @PCI_INTERRUPT_INTA: PCI INTA pin 140 * @PCI_INTERRUPT_INTB: PCI INTB pin 141 * @PCI_INTERRUPT_INTC: PCI INTC pin 142 * @PCI_INTERRUPT_INTD: PCI INTD pin 143 * 144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 145 * PCI_INTERRUPT_PIN register. 146 */ 147 enum pci_interrupt_pin { 148 PCI_INTERRUPT_UNKNOWN, 149 PCI_INTERRUPT_INTA, 150 PCI_INTERRUPT_INTB, 151 PCI_INTERRUPT_INTC, 152 PCI_INTERRUPT_INTD, 153 }; 154 155 /* The number of legacy PCI INTx interrupts */ 156 #define PCI_NUM_INTX 4 157 158 /* 159 * Reading from a device that doesn't respond typically returns ~0. A 160 * successful read from a device may also return ~0, so you need additional 161 * information to reliably identify errors. 162 */ 163 #define PCI_ERROR_RESPONSE (~0ULL) 164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 166 167 /* 168 * pci_power_t values must match the bits in the Capabilities PME_Support 169 * and Control/Status PowerState fields in the Power Management capability. 170 */ 171 typedef int __bitwise pci_power_t; 172 173 #define PCI_D0 ((pci_power_t __force) 0) 174 #define PCI_D1 ((pci_power_t __force) 1) 175 #define PCI_D2 ((pci_power_t __force) 2) 176 #define PCI_D3hot ((pci_power_t __force) 3) 177 #define PCI_D3cold ((pci_power_t __force) 4) 178 #define PCI_UNKNOWN ((pci_power_t __force) 5) 179 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 180 181 /* Remember to update this when the list above changes! */ 182 extern const char *pci_power_names[]; 183 184 static inline const char *pci_power_name(pci_power_t state) 185 { 186 return pci_power_names[1 + (__force int) state]; 187 } 188 189 /** 190 * typedef pci_channel_state_t 191 * 192 * The pci_channel state describes connectivity between the CPU and 193 * the PCI device. If some PCI bus between here and the PCI device 194 * has crashed or locked up, this info is reflected here. 195 */ 196 typedef unsigned int __bitwise pci_channel_state_t; 197 198 enum { 199 /* I/O channel is in normal state */ 200 pci_channel_io_normal = (__force pci_channel_state_t) 1, 201 202 /* I/O to channel is blocked */ 203 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 204 205 /* PCI card is dead */ 206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 207 }; 208 209 typedef unsigned int __bitwise pcie_reset_state_t; 210 211 enum pcie_reset_state { 212 /* Reset is NOT asserted (Use to deassert reset) */ 213 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 214 215 /* Use #PERST to reset PCIe device */ 216 pcie_warm_reset = (__force pcie_reset_state_t) 2, 217 218 /* Use PCIe Hot Reset to reset device */ 219 pcie_hot_reset = (__force pcie_reset_state_t) 3 220 }; 221 222 typedef unsigned short __bitwise pci_dev_flags_t; 223 enum pci_dev_flags { 224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 226 /* Device configuration is irrevocably lost if disabled into D3 */ 227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 228 /* Provide indication device is assigned by a Virtual Machine Manager */ 229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 230 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 234 /* Do not use bus resets for device */ 235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 236 /* Do not use PM reset even if device advertises NoSoftRst- */ 237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 238 /* Get VPD from function 0 VPD */ 239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 240 /* A non-root bridge where translation occurs, stop alias search here */ 241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 242 /* Do not use FLR even if device advertises PCI_AF_CAP */ 243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 244 /* Don't use Relaxed Ordering for TLPs directed at this device */ 245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 246 /* Device does honor MSI masking despite saying otherwise */ 247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 248 }; 249 250 enum pci_irq_reroute_variant { 251 INTEL_IRQ_REROUTE_VARIANT = 1, 252 MAX_IRQ_REROUTE_VARIANTS = 3 253 }; 254 255 typedef unsigned short __bitwise pci_bus_flags_t; 256 enum pci_bus_flags { 257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 261 }; 262 263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 264 enum pcie_link_width { 265 PCIE_LNK_WIDTH_RESRV = 0x00, 266 PCIE_LNK_X1 = 0x01, 267 PCIE_LNK_X2 = 0x02, 268 PCIE_LNK_X4 = 0x04, 269 PCIE_LNK_X8 = 0x08, 270 PCIE_LNK_X12 = 0x0c, 271 PCIE_LNK_X16 = 0x10, 272 PCIE_LNK_X32 = 0x20, 273 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 274 }; 275 276 /* See matching string table in pci_speed_string() */ 277 enum pci_bus_speed { 278 PCI_SPEED_33MHz = 0x00, 279 PCI_SPEED_66MHz = 0x01, 280 PCI_SPEED_66MHz_PCIX = 0x02, 281 PCI_SPEED_100MHz_PCIX = 0x03, 282 PCI_SPEED_133MHz_PCIX = 0x04, 283 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 284 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 285 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 286 PCI_SPEED_66MHz_PCIX_266 = 0x09, 287 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 288 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 289 AGP_UNKNOWN = 0x0c, 290 AGP_1X = 0x0d, 291 AGP_2X = 0x0e, 292 AGP_4X = 0x0f, 293 AGP_8X = 0x10, 294 PCI_SPEED_66MHz_PCIX_533 = 0x11, 295 PCI_SPEED_100MHz_PCIX_533 = 0x12, 296 PCI_SPEED_133MHz_PCIX_533 = 0x13, 297 PCIE_SPEED_2_5GT = 0x14, 298 PCIE_SPEED_5_0GT = 0x15, 299 PCIE_SPEED_8_0GT = 0x16, 300 PCIE_SPEED_16_0GT = 0x17, 301 PCIE_SPEED_32_0GT = 0x18, 302 PCIE_SPEED_64_0GT = 0x19, 303 PCI_SPEED_UNKNOWN = 0xff, 304 }; 305 306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 308 309 struct pci_vpd { 310 struct mutex lock; 311 unsigned int len; 312 u8 cap; 313 }; 314 315 struct irq_affinity; 316 struct pcie_link_state; 317 struct pci_sriov; 318 struct pci_p2pdma; 319 struct rcec_ea; 320 321 /* The pci_dev structure describes PCI devices */ 322 struct pci_dev { 323 struct list_head bus_list; /* Node in per-bus list */ 324 struct pci_bus *bus; /* Bus this device is on */ 325 struct pci_bus *subordinate; /* Bus this device bridges to */ 326 327 void *sysdata; /* Hook for sys-specific extension */ 328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 329 struct pci_slot *slot; /* Physical slot this device is in */ 330 331 unsigned int devfn; /* Encoded device & function index */ 332 unsigned short vendor; 333 unsigned short device; 334 unsigned short subsystem_vendor; 335 unsigned short subsystem_device; 336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 337 u8 revision; /* PCI revision, low byte of class word */ 338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 339 #ifdef CONFIG_PCIEAER 340 u16 aer_cap; /* AER capability offset */ 341 struct aer_stats *aer_stats; /* AER stats for this device */ 342 #endif 343 #ifdef CONFIG_PCIEPORTBUS 344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 345 struct pci_dev *rcec; /* Associated RCEC device */ 346 #endif 347 u32 devcap; /* PCIe Device Capabilities */ 348 u8 pcie_cap; /* PCIe capability offset */ 349 u8 msi_cap; /* MSI capability offset */ 350 u8 msix_cap; /* MSI-X capability offset */ 351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 352 u8 rom_base_reg; /* Config register controlling ROM */ 353 u8 pin; /* Interrupt pin this device uses */ 354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 356 357 struct pci_driver *driver; /* Driver bound to this device */ 358 u64 dma_mask; /* Mask of the bits of bus address this 359 device implements. Normally this is 360 0xffffffff. You only need to change 361 this if your device has broken DMA 362 or supports 64-bit transfers. */ 363 364 struct device_dma_parameters dma_parms; 365 366 pci_power_t current_state; /* Current operating state. In ACPI, 367 this is D0-D3, D0 being fully 368 functional, and D3 being off. */ 369 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 370 u8 pm_cap; /* PM capability offset */ 371 unsigned int pme_support:5; /* Bitmask of states from which PME# 372 can be generated */ 373 unsigned int pme_poll:1; /* Poll device's PME status bit */ 374 unsigned int d1_support:1; /* Low power state D1 is supported */ 375 unsigned int d2_support:1; /* Low power state D2 is supported */ 376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 377 unsigned int no_d3cold:1; /* D3cold is forbidden */ 378 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 381 decoding during BAR sizing */ 382 unsigned int wakeup_prepared:1; 383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 386 controlled exclusively by 387 user sysfs */ 388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 389 bit manually */ 390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 392 393 #ifdef CONFIG_PCIEASPM 394 struct pcie_link_state *link_state; /* ASPM link state */ 395 unsigned int ltr_path:1; /* Latency Tolerance Reporting 396 supported from root to here */ 397 u16 l1ss; /* L1SS Capability pointer */ 398 #endif 399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 401 402 pci_channel_state_t error_state; /* Current connectivity state */ 403 struct device dev; /* Generic device interface */ 404 405 int cfg_size; /* Size of config space */ 406 407 /* 408 * Instead of touching interrupt line and base address registers 409 * directly, use the values stored here. They might be different! 410 */ 411 unsigned int irq; 412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 413 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ 414 415 bool match_driver; /* Skip attaching driver */ 416 417 unsigned int transparent:1; /* Subtractive decode bridge */ 418 unsigned int io_window:1; /* Bridge has I/O window */ 419 unsigned int pref_window:1; /* Bridge has pref mem window */ 420 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 421 unsigned int multifunction:1; /* Multi-function device */ 422 423 unsigned int is_busmaster:1; /* Is busmaster */ 424 unsigned int no_msi:1; /* May not use MSI */ 425 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 426 unsigned int block_cfg_access:1; /* Config space access blocked */ 427 unsigned int broken_parity_status:1; /* Generates false positive parity */ 428 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 429 unsigned int msi_enabled:1; 430 unsigned int msix_enabled:1; 431 unsigned int ari_enabled:1; /* ARI forwarding */ 432 unsigned int ats_enabled:1; /* Address Translation Svc */ 433 unsigned int pasid_enabled:1; /* Process Address Space ID */ 434 unsigned int pri_enabled:1; /* Page Request Interface */ 435 unsigned int is_managed:1; /* Managed via devres */ 436 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 437 unsigned int needs_freset:1; /* Requires fundamental reset */ 438 unsigned int state_saved:1; 439 unsigned int is_physfn:1; 440 unsigned int is_virtfn:1; 441 unsigned int is_hotplug_bridge:1; 442 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 443 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 444 /* 445 * Devices marked being untrusted are the ones that can potentially 446 * execute DMA attacks and similar. They are typically connected 447 * through external ports such as Thunderbolt but not limited to 448 * that. When an IOMMU is enabled they should be getting full 449 * mappings to make sure they cannot access arbitrary memory. 450 */ 451 unsigned int untrusted:1; 452 /* 453 * Info from the platform, e.g., ACPI or device tree, may mark a 454 * device as "external-facing". An external-facing device is 455 * itself internal but devices downstream from it are external. 456 */ 457 unsigned int external_facing:1; 458 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 459 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 460 unsigned int irq_managed:1; 461 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 462 unsigned int is_probed:1; /* Device probing in progress */ 463 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 464 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 465 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 466 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 467 pci_dev_flags_t dev_flags; 468 atomic_t enable_cnt; /* pci_enable_device has been called */ 469 470 u32 saved_config_space[16]; /* Config space saved at suspend time */ 471 struct hlist_head saved_cap_space; 472 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 473 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 474 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 475 476 #ifdef CONFIG_HOTPLUG_PCI_PCIE 477 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 478 #endif 479 #ifdef CONFIG_PCIE_PTM 480 u16 ptm_cap; /* PTM Capability */ 481 unsigned int ptm_root:1; 482 unsigned int ptm_enabled:1; 483 u8 ptm_granularity; 484 #endif 485 #ifdef CONFIG_PCI_MSI 486 void __iomem *msix_base; 487 raw_spinlock_t msi_lock; 488 #endif 489 struct pci_vpd vpd; 490 #ifdef CONFIG_PCIE_DPC 491 u16 dpc_cap; 492 unsigned int dpc_rp_extensions:1; 493 u8 dpc_rp_log_size; 494 #endif 495 #ifdef CONFIG_PCI_ATS 496 union { 497 struct pci_sriov *sriov; /* PF: SR-IOV info */ 498 struct pci_dev *physfn; /* VF: related PF */ 499 }; 500 u16 ats_cap; /* ATS Capability offset */ 501 u8 ats_stu; /* ATS Smallest Translation Unit */ 502 #endif 503 #ifdef CONFIG_PCI_PRI 504 u16 pri_cap; /* PRI Capability offset */ 505 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 506 unsigned int pasid_required:1; /* PRG Response PASID Required */ 507 #endif 508 #ifdef CONFIG_PCI_PASID 509 u16 pasid_cap; /* PASID Capability offset */ 510 u16 pasid_features; 511 #endif 512 #ifdef CONFIG_PCI_P2PDMA 513 struct pci_p2pdma __rcu *p2pdma; 514 #endif 515 u16 acs_cap; /* ACS Capability offset */ 516 phys_addr_t rom; /* Physical address if not from BAR */ 517 size_t romlen; /* Length if not from BAR */ 518 /* 519 * Driver name to force a match. Do not set directly, because core 520 * frees it. Use driver_set_override() to set or clear it. 521 */ 522 const char *driver_override; 523 524 unsigned long priv_flags; /* Private flags for the PCI driver */ 525 526 /* These methods index pci_reset_fn_methods[] */ 527 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 528 }; 529 530 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 531 { 532 #ifdef CONFIG_PCI_IOV 533 if (dev->is_virtfn) 534 dev = dev->physfn; 535 #endif 536 return dev; 537 } 538 539 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 540 541 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 542 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 543 544 static inline int pci_channel_offline(struct pci_dev *pdev) 545 { 546 return (pdev->error_state != pci_channel_io_normal); 547 } 548 549 /* 550 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 551 * Group number is limited to a 16-bit value, therefore (int)-1 is 552 * not a valid PCI domain number, and can be used as a sentinel 553 * value indicating ->domain_nr is not set by the driver (and 554 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 555 * pci_bus_find_domain_nr()). 556 */ 557 #define PCI_DOMAIN_NR_NOT_SET (-1) 558 559 struct pci_host_bridge { 560 struct device dev; 561 struct pci_bus *bus; /* Root bus */ 562 struct pci_ops *ops; 563 struct pci_ops *child_ops; 564 void *sysdata; 565 int busnr; 566 int domain_nr; 567 struct list_head windows; /* resource_entry */ 568 struct list_head dma_ranges; /* dma ranges resource list */ 569 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 570 int (*map_irq)(const struct pci_dev *, u8, u8); 571 void (*release_fn)(struct pci_host_bridge *); 572 void *release_data; 573 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 574 unsigned int no_ext_tags:1; /* No Extended Tags */ 575 unsigned int no_inc_mrrs:1; /* No Increase MRRS */ 576 unsigned int native_aer:1; /* OS may use PCIe AER */ 577 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 578 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 579 unsigned int native_pme:1; /* OS may use PCIe PME */ 580 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 581 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 582 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ 583 unsigned int preserve_config:1; /* Preserve FW resource setup */ 584 unsigned int size_windows:1; /* Enable root bus sizing */ 585 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 586 587 /* Resource alignment requirements */ 588 resource_size_t (*align_resource)(struct pci_dev *dev, 589 const struct resource *res, 590 resource_size_t start, 591 resource_size_t size, 592 resource_size_t align); 593 unsigned long private[] ____cacheline_aligned; 594 }; 595 596 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 597 598 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 599 { 600 return (void *)bridge->private; 601 } 602 603 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 604 { 605 return container_of(priv, struct pci_host_bridge, private); 606 } 607 608 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 609 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 610 size_t priv); 611 void pci_free_host_bridge(struct pci_host_bridge *bridge); 612 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 613 614 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 615 void (*release_fn)(struct pci_host_bridge *), 616 void *release_data); 617 618 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 619 620 /* 621 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 622 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 623 * buses below host bridges or subtractive decode bridges) go in the list. 624 * Use pci_bus_for_each_resource() to iterate through all the resources. 625 */ 626 627 /* 628 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 629 * and there's no way to program the bridge with the details of the window. 630 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 631 * decode bit set, because they are explicit and can be programmed with _SRS. 632 */ 633 #define PCI_SUBTRACTIVE_DECODE 0x1 634 635 struct pci_bus_resource { 636 struct list_head list; 637 struct resource *res; 638 unsigned int flags; 639 }; 640 641 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 642 643 struct pci_bus { 644 struct list_head node; /* Node in list of buses */ 645 struct pci_bus *parent; /* Parent bus this bridge is on */ 646 struct list_head children; /* List of child buses */ 647 struct list_head devices; /* List of devices on this bus */ 648 struct pci_dev *self; /* Bridge device as seen by parent */ 649 struct list_head slots; /* List of slots on this bus; 650 protected by pci_slot_mutex */ 651 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 652 struct list_head resources; /* Address space routed to this bus */ 653 struct resource busn_res; /* Bus numbers routed to this bus */ 654 655 struct pci_ops *ops; /* Configuration access functions */ 656 void *sysdata; /* Hook for sys-specific extension */ 657 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 658 659 unsigned char number; /* Bus number */ 660 unsigned char primary; /* Number of primary bridge */ 661 unsigned char max_bus_speed; /* enum pci_bus_speed */ 662 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 663 #ifdef CONFIG_PCI_DOMAINS_GENERIC 664 int domain_nr; 665 #endif 666 667 char name[48]; 668 669 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 670 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 671 struct device *bridge; 672 struct device dev; 673 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 674 struct bin_attribute *legacy_mem; /* Legacy mem */ 675 unsigned int is_added:1; 676 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 677 }; 678 679 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 680 681 static inline u16 pci_dev_id(struct pci_dev *dev) 682 { 683 return PCI_DEVID(dev->bus->number, dev->devfn); 684 } 685 686 /* 687 * Returns true if the PCI bus is root (behind host-PCI bridge), 688 * false otherwise 689 * 690 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 691 * This is incorrect because "virtual" buses added for SR-IOV (via 692 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 693 */ 694 static inline bool pci_is_root_bus(struct pci_bus *pbus) 695 { 696 return !(pbus->parent); 697 } 698 699 /** 700 * pci_is_bridge - check if the PCI device is a bridge 701 * @dev: PCI device 702 * 703 * Return true if the PCI device is bridge whether it has subordinate 704 * or not. 705 */ 706 static inline bool pci_is_bridge(struct pci_dev *dev) 707 { 708 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 709 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 710 } 711 712 #define for_each_pci_bridge(dev, bus) \ 713 list_for_each_entry(dev, &bus->devices, bus_list) \ 714 if (!pci_is_bridge(dev)) {} else 715 716 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 717 { 718 dev = pci_physfn(dev); 719 if (pci_is_root_bus(dev->bus)) 720 return NULL; 721 722 return dev->bus->self; 723 } 724 725 #ifdef CONFIG_PCI_MSI 726 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 727 { 728 return pci_dev->msi_enabled || pci_dev->msix_enabled; 729 } 730 #else 731 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 732 #endif 733 734 /* Error values that may be returned by PCI functions */ 735 #define PCIBIOS_SUCCESSFUL 0x00 736 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 737 #define PCIBIOS_BAD_VENDOR_ID 0x83 738 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 739 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 740 #define PCIBIOS_SET_FAILED 0x88 741 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 742 743 /* Translate above to generic errno for passing back through non-PCI code */ 744 static inline int pcibios_err_to_errno(int err) 745 { 746 if (err <= PCIBIOS_SUCCESSFUL) 747 return err; /* Assume already errno */ 748 749 switch (err) { 750 case PCIBIOS_FUNC_NOT_SUPPORTED: 751 return -ENOENT; 752 case PCIBIOS_BAD_VENDOR_ID: 753 return -ENOTTY; 754 case PCIBIOS_DEVICE_NOT_FOUND: 755 return -ENODEV; 756 case PCIBIOS_BAD_REGISTER_NUMBER: 757 return -EFAULT; 758 case PCIBIOS_SET_FAILED: 759 return -EIO; 760 case PCIBIOS_BUFFER_TOO_SMALL: 761 return -ENOSPC; 762 } 763 764 return -ERANGE; 765 } 766 767 /* Low-level architecture-dependent routines */ 768 769 struct pci_ops { 770 int (*add_bus)(struct pci_bus *bus); 771 void (*remove_bus)(struct pci_bus *bus); 772 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 773 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 774 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 775 }; 776 777 /* 778 * ACPI needs to be able to access PCI config space before we've done a 779 * PCI bus scan and created pci_bus structures. 780 */ 781 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 782 int reg, int len, u32 *val); 783 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 784 int reg, int len, u32 val); 785 786 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 787 typedef u64 pci_bus_addr_t; 788 #else 789 typedef u32 pci_bus_addr_t; 790 #endif 791 792 struct pci_bus_region { 793 pci_bus_addr_t start; 794 pci_bus_addr_t end; 795 }; 796 797 struct pci_dynids { 798 spinlock_t lock; /* Protects list, index */ 799 struct list_head list; /* For IDs added at runtime */ 800 }; 801 802 803 /* 804 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 805 * a set of callbacks in struct pci_error_handlers, that device driver 806 * will be notified of PCI bus errors, and will be driven to recovery 807 * when an error occurs. 808 */ 809 810 typedef unsigned int __bitwise pci_ers_result_t; 811 812 enum pci_ers_result { 813 /* No result/none/not supported in device driver */ 814 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 815 816 /* Device driver can recover without slot reset */ 817 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 818 819 /* Device driver wants slot to be reset */ 820 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 821 822 /* Device has completely failed, is unrecoverable */ 823 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 824 825 /* Device driver is fully recovered and operational */ 826 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 827 828 /* No AER capabilities registered for the driver */ 829 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 830 }; 831 832 /* PCI bus error event callbacks */ 833 struct pci_error_handlers { 834 /* PCI bus error detected on this device */ 835 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 836 pci_channel_state_t error); 837 838 /* MMIO has been re-enabled, but not DMA */ 839 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 840 841 /* PCI slot has been reset */ 842 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 843 844 /* PCI function reset prepare or completed */ 845 void (*reset_prepare)(struct pci_dev *dev); 846 void (*reset_done)(struct pci_dev *dev); 847 848 /* Device driver may resume normal operations */ 849 void (*resume)(struct pci_dev *dev); 850 851 /* Allow device driver to record more details of a correctable error */ 852 void (*cor_error_detected)(struct pci_dev *dev); 853 }; 854 855 856 struct module; 857 858 /** 859 * struct pci_driver - PCI driver structure 860 * @node: List of driver structures. 861 * @name: Driver name. 862 * @id_table: Pointer to table of device IDs the driver is 863 * interested in. Most drivers should export this 864 * table using MODULE_DEVICE_TABLE(pci,...). 865 * @probe: This probing function gets called (during execution 866 * of pci_register_driver() for already existing 867 * devices or later if a new device gets inserted) for 868 * all PCI devices which match the ID table and are not 869 * "owned" by the other drivers yet. This function gets 870 * passed a "struct pci_dev \*" for each device whose 871 * entry in the ID table matches the device. The probe 872 * function returns zero when the driver chooses to 873 * take "ownership" of the device or an error code 874 * (negative number) otherwise. 875 * The probe function always gets called from process 876 * context, so it can sleep. 877 * @remove: The remove() function gets called whenever a device 878 * being handled by this driver is removed (either during 879 * deregistration of the driver or when it's manually 880 * pulled out of a hot-pluggable slot). 881 * The remove function always gets called from process 882 * context, so it can sleep. 883 * @suspend: Put device into low power state. 884 * @resume: Wake device from low power state. 885 * (Please see Documentation/power/pci.rst for descriptions 886 * of PCI Power Management and the related functions.) 887 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 888 * Intended to stop any idling DMA operations. 889 * Useful for enabling wake-on-lan (NIC) or changing 890 * the power state of a device before reboot. 891 * e.g. drivers/net/e100.c. 892 * @sriov_configure: Optional driver callback to allow configuration of 893 * number of VFs to enable via sysfs "sriov_numvfs" file. 894 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 895 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 896 * This will change MSI-X Table Size in the VF Message Control 897 * registers. 898 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 899 * MSI-X vectors available for distribution to the VFs. 900 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 901 * @groups: Sysfs attribute groups. 902 * @dev_groups: Attributes attached to the device that will be 903 * created once it is bound to the driver. 904 * @driver: Driver model structure. 905 * @dynids: List of dynamically added device IDs. 906 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. 907 * For most device drivers, no need to care about this flag 908 * as long as all DMAs are handled through the kernel DMA API. 909 * For some special ones, for example VFIO drivers, they know 910 * how to manage the DMA themselves and set this flag so that 911 * the IOMMU layer will allow them to setup and manage their 912 * own I/O address space. 913 */ 914 struct pci_driver { 915 struct list_head node; 916 const char *name; 917 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 918 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 919 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 920 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 921 int (*resume)(struct pci_dev *dev); /* Device woken up */ 922 void (*shutdown)(struct pci_dev *dev); 923 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 924 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 925 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 926 const struct pci_error_handlers *err_handler; 927 const struct attribute_group **groups; 928 const struct attribute_group **dev_groups; 929 struct device_driver driver; 930 struct pci_dynids dynids; 931 bool driver_managed_dma; 932 }; 933 934 static inline struct pci_driver *to_pci_driver(struct device_driver *drv) 935 { 936 return drv ? container_of(drv, struct pci_driver, driver) : NULL; 937 } 938 939 /** 940 * PCI_DEVICE - macro used to describe a specific PCI device 941 * @vend: the 16 bit PCI Vendor ID 942 * @dev: the 16 bit PCI Device ID 943 * 944 * This macro is used to create a struct pci_device_id that matches a 945 * specific device. The subvendor and subdevice fields will be set to 946 * PCI_ANY_ID. 947 */ 948 #define PCI_DEVICE(vend,dev) \ 949 .vendor = (vend), .device = (dev), \ 950 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 951 952 /** 953 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 954 * override_only flags. 955 * @vend: the 16 bit PCI Vendor ID 956 * @dev: the 16 bit PCI Device ID 957 * @driver_override: the 32 bit PCI Device override_only 958 * 959 * This macro is used to create a struct pci_device_id that matches only a 960 * driver_override device. The subvendor and subdevice fields will be set to 961 * PCI_ANY_ID. 962 */ 963 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 964 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 965 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 966 967 /** 968 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 969 * "driver_override" PCI device. 970 * @vend: the 16 bit PCI Vendor ID 971 * @dev: the 16 bit PCI Device ID 972 * 973 * This macro is used to create a struct pci_device_id that matches a 974 * specific device. The subvendor and subdevice fields will be set to 975 * PCI_ANY_ID and the driver_override will be set to 976 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 977 */ 978 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 979 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 980 981 /** 982 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 983 * @vend: the 16 bit PCI Vendor ID 984 * @dev: the 16 bit PCI Device ID 985 * @subvend: the 16 bit PCI Subvendor ID 986 * @subdev: the 16 bit PCI Subdevice ID 987 * 988 * This macro is used to create a struct pci_device_id that matches a 989 * specific device with subsystem information. 990 */ 991 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 992 .vendor = (vend), .device = (dev), \ 993 .subvendor = (subvend), .subdevice = (subdev) 994 995 /** 996 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 997 * @dev_class: the class, subclass, prog-if triple for this device 998 * @dev_class_mask: the class mask for this device 999 * 1000 * This macro is used to create a struct pci_device_id that matches a 1001 * specific PCI class. The vendor, device, subvendor, and subdevice 1002 * fields will be set to PCI_ANY_ID. 1003 */ 1004 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 1005 .class = (dev_class), .class_mask = (dev_class_mask), \ 1006 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1007 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1008 1009 /** 1010 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 1011 * @vend: the vendor name 1012 * @dev: the 16 bit PCI Device ID 1013 * 1014 * This macro is used to create a struct pci_device_id that matches a 1015 * specific PCI device. The subvendor, and subdevice fields will be set 1016 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1017 * private data. 1018 */ 1019 #define PCI_VDEVICE(vend, dev) \ 1020 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1021 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1022 1023 /** 1024 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1025 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1026 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1027 * @data: the driver data to be filled 1028 * 1029 * This macro is used to create a struct pci_device_id that matches a 1030 * specific PCI device. The subvendor, and subdevice fields will be set 1031 * to PCI_ANY_ID. 1032 */ 1033 #define PCI_DEVICE_DATA(vend, dev, data) \ 1034 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1035 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1036 .driver_data = (kernel_ulong_t)(data) 1037 1038 enum { 1039 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1040 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1041 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1042 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1043 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1044 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1045 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1046 }; 1047 1048 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1049 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1050 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1051 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1052 1053 /* These external functions are only available when PCI support is enabled */ 1054 #ifdef CONFIG_PCI 1055 1056 extern unsigned int pci_flags; 1057 1058 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1059 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1060 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1061 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1062 1063 void pcie_bus_configure_settings(struct pci_bus *bus); 1064 1065 enum pcie_bus_config_types { 1066 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1067 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1068 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1069 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1070 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1071 }; 1072 1073 extern enum pcie_bus_config_types pcie_bus_config; 1074 1075 extern struct bus_type pci_bus_type; 1076 1077 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1078 * code, or PCI core code. */ 1079 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1080 /* Some device drivers need know if PCI is initiated */ 1081 int no_pci_devices(void); 1082 1083 void pcibios_resource_survey_bus(struct pci_bus *bus); 1084 void pcibios_bus_add_device(struct pci_dev *pdev); 1085 void pcibios_add_bus(struct pci_bus *bus); 1086 void pcibios_remove_bus(struct pci_bus *bus); 1087 void pcibios_fixup_bus(struct pci_bus *); 1088 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1089 /* Architecture-specific versions may override this (weak) */ 1090 char *pcibios_setup(char *str); 1091 1092 /* Used only when drivers/pci/setup.c is used */ 1093 resource_size_t pcibios_align_resource(void *, const struct resource *, 1094 resource_size_t, 1095 resource_size_t); 1096 1097 /* Weak but can be overridden by arch */ 1098 void pci_fixup_cardbus(struct pci_bus *); 1099 1100 /* Generic PCI functions used internally */ 1101 1102 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1103 struct resource *res); 1104 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1105 struct pci_bus_region *region); 1106 void pcibios_scan_specific_bus(int busn); 1107 struct pci_bus *pci_find_bus(int domain, int busnr); 1108 void pci_bus_add_devices(const struct pci_bus *bus); 1109 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1110 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1111 struct pci_ops *ops, void *sysdata, 1112 struct list_head *resources); 1113 int pci_host_probe(struct pci_host_bridge *bridge); 1114 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1115 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1116 void pci_bus_release_busn_res(struct pci_bus *b); 1117 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1118 struct pci_ops *ops, void *sysdata, 1119 struct list_head *resources); 1120 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1121 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1122 int busnr); 1123 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1124 const char *name, 1125 struct hotplug_slot *hotplug); 1126 void pci_destroy_slot(struct pci_slot *slot); 1127 #ifdef CONFIG_SYSFS 1128 void pci_dev_assign_slot(struct pci_dev *dev); 1129 #else 1130 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1131 #endif 1132 int pci_scan_slot(struct pci_bus *bus, int devfn); 1133 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1134 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1135 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1136 void pci_bus_add_device(struct pci_dev *dev); 1137 void pci_read_bridge_bases(struct pci_bus *child); 1138 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1139 struct resource *res); 1140 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1141 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1142 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1143 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1144 void pci_dev_put(struct pci_dev *dev); 1145 void pci_remove_bus(struct pci_bus *b); 1146 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1147 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1148 void pci_stop_root_bus(struct pci_bus *bus); 1149 void pci_remove_root_bus(struct pci_bus *bus); 1150 void pci_setup_cardbus(struct pci_bus *bus); 1151 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1152 void pci_sort_breadthfirst(void); 1153 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1154 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1155 1156 /* Generic PCI functions exported to card drivers */ 1157 1158 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1159 u8 pci_find_capability(struct pci_dev *dev, int cap); 1160 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1161 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1162 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1163 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1164 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1165 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1166 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1167 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1168 1169 u64 pci_get_dsn(struct pci_dev *dev); 1170 1171 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1172 struct pci_dev *from); 1173 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1174 unsigned int ss_vendor, unsigned int ss_device, 1175 struct pci_dev *from); 1176 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1177 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1178 unsigned int devfn); 1179 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1180 int pci_dev_present(const struct pci_device_id *ids); 1181 1182 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1183 int where, u8 *val); 1184 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1185 int where, u16 *val); 1186 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1187 int where, u32 *val); 1188 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1189 int where, u8 val); 1190 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1191 int where, u16 val); 1192 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1193 int where, u32 val); 1194 1195 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1196 int where, int size, u32 *val); 1197 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1198 int where, int size, u32 val); 1199 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1200 int where, int size, u32 *val); 1201 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1202 int where, int size, u32 val); 1203 1204 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1205 1206 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1207 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1208 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1209 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1210 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1211 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1212 1213 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1214 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1215 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1216 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1217 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1218 u16 clear, u16 set); 1219 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1220 u32 clear, u32 set); 1221 1222 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1223 u16 set) 1224 { 1225 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1226 } 1227 1228 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1229 u32 set) 1230 { 1231 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1232 } 1233 1234 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1235 u16 clear) 1236 { 1237 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1238 } 1239 1240 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1241 u32 clear) 1242 { 1243 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1244 } 1245 1246 /* User-space driven config access */ 1247 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1248 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1249 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1250 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1251 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1252 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1253 1254 int __must_check pci_enable_device(struct pci_dev *dev); 1255 int __must_check pci_enable_device_io(struct pci_dev *dev); 1256 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1257 int __must_check pci_reenable_device(struct pci_dev *); 1258 int __must_check pcim_enable_device(struct pci_dev *pdev); 1259 void pcim_pin_device(struct pci_dev *pdev); 1260 1261 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1262 { 1263 /* 1264 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1265 * writable and no quirk has marked the feature broken. 1266 */ 1267 return !pdev->broken_intx_masking; 1268 } 1269 1270 static inline int pci_is_enabled(struct pci_dev *pdev) 1271 { 1272 return (atomic_read(&pdev->enable_cnt) > 0); 1273 } 1274 1275 static inline int pci_is_managed(struct pci_dev *pdev) 1276 { 1277 return pdev->is_managed; 1278 } 1279 1280 void pci_disable_device(struct pci_dev *dev); 1281 1282 extern unsigned int pcibios_max_latency; 1283 void pci_set_master(struct pci_dev *dev); 1284 void pci_clear_master(struct pci_dev *dev); 1285 1286 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1287 int pci_set_cacheline_size(struct pci_dev *dev); 1288 int __must_check pci_set_mwi(struct pci_dev *dev); 1289 int __must_check pcim_set_mwi(struct pci_dev *dev); 1290 int pci_try_set_mwi(struct pci_dev *dev); 1291 void pci_clear_mwi(struct pci_dev *dev); 1292 void pci_disable_parity(struct pci_dev *dev); 1293 void pci_intx(struct pci_dev *dev, int enable); 1294 bool pci_check_and_mask_intx(struct pci_dev *dev); 1295 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1296 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1297 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1298 int pcix_get_max_mmrbc(struct pci_dev *dev); 1299 int pcix_get_mmrbc(struct pci_dev *dev); 1300 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1301 int pcie_get_readrq(struct pci_dev *dev); 1302 int pcie_set_readrq(struct pci_dev *dev, int rq); 1303 int pcie_get_mps(struct pci_dev *dev); 1304 int pcie_set_mps(struct pci_dev *dev, int mps); 1305 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1306 enum pci_bus_speed *speed, 1307 enum pcie_link_width *width); 1308 void pcie_print_link_status(struct pci_dev *dev); 1309 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1310 int pcie_flr(struct pci_dev *dev); 1311 int __pci_reset_function_locked(struct pci_dev *dev); 1312 int pci_reset_function(struct pci_dev *dev); 1313 int pci_reset_function_locked(struct pci_dev *dev); 1314 int pci_try_reset_function(struct pci_dev *dev); 1315 int pci_probe_reset_slot(struct pci_slot *slot); 1316 int pci_probe_reset_bus(struct pci_bus *bus); 1317 int pci_reset_bus(struct pci_dev *dev); 1318 void pci_reset_secondary_bus(struct pci_dev *dev); 1319 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1320 void pci_update_resource(struct pci_dev *dev, int resno); 1321 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1322 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1323 void pci_release_resource(struct pci_dev *dev, int resno); 1324 static inline int pci_rebar_bytes_to_size(u64 bytes) 1325 { 1326 bytes = roundup_pow_of_two(bytes); 1327 1328 /* Return BAR size as defined in the resizable BAR specification */ 1329 return max(ilog2(bytes), 20) - 20; 1330 } 1331 1332 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1333 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1334 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1335 bool pci_device_is_present(struct pci_dev *pdev); 1336 void pci_ignore_hotplug(struct pci_dev *dev); 1337 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1338 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1339 1340 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1341 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1342 const char *fmt, ...); 1343 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1344 1345 /* ROM control related routines */ 1346 int pci_enable_rom(struct pci_dev *pdev); 1347 void pci_disable_rom(struct pci_dev *pdev); 1348 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1349 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1350 1351 /* Power management related routines */ 1352 int pci_save_state(struct pci_dev *dev); 1353 void pci_restore_state(struct pci_dev *dev); 1354 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1355 int pci_load_saved_state(struct pci_dev *dev, 1356 struct pci_saved_state *state); 1357 int pci_load_and_free_saved_state(struct pci_dev *dev, 1358 struct pci_saved_state **state); 1359 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1360 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1361 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1362 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1363 void pci_pme_active(struct pci_dev *dev, bool enable); 1364 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1365 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1366 int pci_prepare_to_sleep(struct pci_dev *dev); 1367 int pci_back_from_sleep(struct pci_dev *dev); 1368 bool pci_dev_run_wake(struct pci_dev *dev); 1369 void pci_d3cold_enable(struct pci_dev *dev); 1370 void pci_d3cold_disable(struct pci_dev *dev); 1371 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1372 void pci_resume_bus(struct pci_bus *bus); 1373 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1374 1375 /* For use by arch with custom probe code */ 1376 void set_pcie_port_type(struct pci_dev *pdev); 1377 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1378 1379 /* Functions for PCI Hotplug drivers to use */ 1380 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1381 unsigned int pci_rescan_bus(struct pci_bus *bus); 1382 void pci_lock_rescan_remove(void); 1383 void pci_unlock_rescan_remove(void); 1384 1385 /* Vital Product Data routines */ 1386 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1387 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1388 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1389 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1390 1391 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1392 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1393 void pci_bus_assign_resources(const struct pci_bus *bus); 1394 void pci_bus_claim_resources(struct pci_bus *bus); 1395 void pci_bus_size_bridges(struct pci_bus *bus); 1396 int pci_claim_resource(struct pci_dev *, int); 1397 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1398 void pci_assign_unassigned_resources(void); 1399 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1400 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1401 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1402 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1403 void pdev_enable_device(struct pci_dev *); 1404 int pci_enable_resources(struct pci_dev *, int mask); 1405 void pci_assign_irq(struct pci_dev *dev); 1406 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1407 #define HAVE_PCI_REQ_REGIONS 2 1408 int __must_check pci_request_regions(struct pci_dev *, const char *); 1409 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1410 void pci_release_regions(struct pci_dev *); 1411 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1412 void pci_release_region(struct pci_dev *, int); 1413 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1414 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1415 void pci_release_selected_regions(struct pci_dev *, int); 1416 1417 static inline __must_check struct resource * 1418 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, 1419 unsigned int len, const char *name) 1420 { 1421 return __request_region(&pdev->driver_exclusive_resource, offset, len, 1422 name, IORESOURCE_EXCLUSIVE); 1423 } 1424 1425 static inline void pci_release_config_region(struct pci_dev *pdev, 1426 unsigned int offset, 1427 unsigned int len) 1428 { 1429 __release_region(&pdev->driver_exclusive_resource, offset, len); 1430 } 1431 1432 /* drivers/pci/bus.c */ 1433 void pci_add_resource(struct list_head *resources, struct resource *res); 1434 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1435 resource_size_t offset); 1436 void pci_free_resource_list(struct list_head *resources); 1437 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1438 unsigned int flags); 1439 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1440 void pci_bus_remove_resources(struct pci_bus *bus); 1441 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res); 1442 int devm_request_pci_bus_resources(struct device *dev, 1443 struct list_head *resources); 1444 1445 /* Temporary until new and working PCI SBR API in place */ 1446 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1447 1448 #define pci_bus_for_each_resource(bus, res, i) \ 1449 for (i = 0; \ 1450 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1451 i++) 1452 1453 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1454 struct resource *res, resource_size_t size, 1455 resource_size_t align, resource_size_t min, 1456 unsigned long type_mask, 1457 resource_size_t (*alignf)(void *, 1458 const struct resource *, 1459 resource_size_t, 1460 resource_size_t), 1461 void *alignf_data); 1462 1463 1464 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1465 resource_size_t size); 1466 unsigned long pci_address_to_pio(phys_addr_t addr); 1467 phys_addr_t pci_pio_to_address(unsigned long pio); 1468 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1469 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1470 phys_addr_t phys_addr); 1471 void pci_unmap_iospace(struct resource *res); 1472 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1473 resource_size_t offset, 1474 resource_size_t size); 1475 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1476 struct resource *res); 1477 1478 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1479 { 1480 struct pci_bus_region region; 1481 1482 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1483 return region.start; 1484 } 1485 1486 /* Proper probing supporting hot-pluggable devices */ 1487 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1488 const char *mod_name); 1489 1490 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1491 #define pci_register_driver(driver) \ 1492 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1493 1494 void pci_unregister_driver(struct pci_driver *dev); 1495 1496 /** 1497 * module_pci_driver() - Helper macro for registering a PCI driver 1498 * @__pci_driver: pci_driver struct 1499 * 1500 * Helper macro for PCI drivers which do not do anything special in module 1501 * init/exit. This eliminates a lot of boilerplate. Each module may only 1502 * use this macro once, and calling it replaces module_init() and module_exit() 1503 */ 1504 #define module_pci_driver(__pci_driver) \ 1505 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1506 1507 /** 1508 * builtin_pci_driver() - Helper macro for registering a PCI driver 1509 * @__pci_driver: pci_driver struct 1510 * 1511 * Helper macro for PCI drivers which do not do anything special in their 1512 * init code. This eliminates a lot of boilerplate. Each driver may only 1513 * use this macro once, and calling it replaces device_initcall(...) 1514 */ 1515 #define builtin_pci_driver(__pci_driver) \ 1516 builtin_driver(__pci_driver, pci_register_driver) 1517 1518 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1519 int pci_add_dynid(struct pci_driver *drv, 1520 unsigned int vendor, unsigned int device, 1521 unsigned int subvendor, unsigned int subdevice, 1522 unsigned int class, unsigned int class_mask, 1523 unsigned long driver_data); 1524 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1525 struct pci_dev *dev); 1526 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1527 int pass); 1528 1529 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1530 void *userdata); 1531 int pci_cfg_space_size(struct pci_dev *dev); 1532 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1533 void pci_setup_bridge(struct pci_bus *bus); 1534 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1535 unsigned long type); 1536 1537 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1538 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1539 1540 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1541 unsigned int command_bits, u32 flags); 1542 1543 /* 1544 * Virtual interrupts allow for more interrupts to be allocated 1545 * than the device has interrupts for. These are not programmed 1546 * into the device's MSI-X table and must be handled by some 1547 * other driver means. 1548 */ 1549 #define PCI_IRQ_VIRTUAL (1 << 4) 1550 1551 #define PCI_IRQ_ALL_TYPES \ 1552 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1553 1554 #include <linux/dmapool.h> 1555 1556 struct msix_entry { 1557 u32 vector; /* Kernel uses to write allocated vector */ 1558 u16 entry; /* Driver uses to specify entry, OS writes */ 1559 }; 1560 1561 #ifdef CONFIG_PCI_MSI 1562 int pci_msi_vec_count(struct pci_dev *dev); 1563 void pci_disable_msi(struct pci_dev *dev); 1564 int pci_msix_vec_count(struct pci_dev *dev); 1565 void pci_disable_msix(struct pci_dev *dev); 1566 void pci_restore_msi_state(struct pci_dev *dev); 1567 int pci_msi_enabled(void); 1568 int pci_enable_msi(struct pci_dev *dev); 1569 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1570 int minvec, int maxvec); 1571 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1572 struct msix_entry *entries, int nvec) 1573 { 1574 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1575 if (rc < 0) 1576 return rc; 1577 return 0; 1578 } 1579 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1580 unsigned int max_vecs, unsigned int flags); 1581 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1582 unsigned int max_vecs, unsigned int flags, 1583 struct irq_affinity *affd); 1584 1585 bool pci_msix_can_alloc_dyn(struct pci_dev *dev); 1586 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1587 const struct irq_affinity_desc *affdesc); 1588 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); 1589 1590 void pci_free_irq_vectors(struct pci_dev *dev); 1591 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1592 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1593 1594 #else 1595 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1596 static inline void pci_disable_msi(struct pci_dev *dev) { } 1597 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1598 static inline void pci_disable_msix(struct pci_dev *dev) { } 1599 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1600 static inline int pci_msi_enabled(void) { return 0; } 1601 static inline int pci_enable_msi(struct pci_dev *dev) 1602 { return -ENOSYS; } 1603 static inline int pci_enable_msix_range(struct pci_dev *dev, 1604 struct msix_entry *entries, int minvec, int maxvec) 1605 { return -ENOSYS; } 1606 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1607 struct msix_entry *entries, int nvec) 1608 { return -ENOSYS; } 1609 1610 static inline int 1611 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1612 unsigned int max_vecs, unsigned int flags, 1613 struct irq_affinity *aff_desc) 1614 { 1615 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1616 return 1; 1617 return -ENOSPC; 1618 } 1619 static inline int 1620 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1621 unsigned int max_vecs, unsigned int flags) 1622 { 1623 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, 1624 flags, NULL); 1625 } 1626 1627 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev) 1628 { return false; } 1629 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1630 const struct irq_affinity_desc *affdesc) 1631 { 1632 struct msi_map map = { .index = -ENOSYS, }; 1633 1634 return map; 1635 } 1636 1637 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map) 1638 { 1639 } 1640 1641 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1642 { 1643 } 1644 1645 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1646 { 1647 if (WARN_ON_ONCE(nr > 0)) 1648 return -EINVAL; 1649 return dev->irq; 1650 } 1651 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1652 int vec) 1653 { 1654 return cpu_possible_mask; 1655 } 1656 #endif 1657 1658 /** 1659 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1660 * @d: the INTx IRQ domain 1661 * @node: the DT node for the device whose interrupt we're translating 1662 * @intspec: the interrupt specifier data from the DT 1663 * @intsize: the number of entries in @intspec 1664 * @out_hwirq: pointer at which to write the hwirq number 1665 * @out_type: pointer at which to write the interrupt type 1666 * 1667 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1668 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1669 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1670 * INTx value to obtain the hwirq number. 1671 * 1672 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1673 */ 1674 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1675 struct device_node *node, 1676 const u32 *intspec, 1677 unsigned int intsize, 1678 unsigned long *out_hwirq, 1679 unsigned int *out_type) 1680 { 1681 const u32 intx = intspec[0]; 1682 1683 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1684 return -EINVAL; 1685 1686 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1687 return 0; 1688 } 1689 1690 #ifdef CONFIG_PCIEPORTBUS 1691 extern bool pcie_ports_disabled; 1692 extern bool pcie_ports_native; 1693 #else 1694 #define pcie_ports_disabled true 1695 #define pcie_ports_native false 1696 #endif 1697 1698 #define PCIE_LINK_STATE_L0S BIT(0) 1699 #define PCIE_LINK_STATE_L1 BIT(1) 1700 #define PCIE_LINK_STATE_CLKPM BIT(2) 1701 #define PCIE_LINK_STATE_L1_1 BIT(3) 1702 #define PCIE_LINK_STATE_L1_2 BIT(4) 1703 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1704 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1705 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\ 1706 PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\ 1707 PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\ 1708 PCIE_LINK_STATE_L1_2_PCIPM) 1709 1710 #ifdef CONFIG_PCIEASPM 1711 int pci_disable_link_state(struct pci_dev *pdev, int state); 1712 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1713 int pci_enable_link_state(struct pci_dev *pdev, int state); 1714 void pcie_no_aspm(void); 1715 bool pcie_aspm_support_enabled(void); 1716 bool pcie_aspm_enabled(struct pci_dev *pdev); 1717 #else 1718 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1719 { return 0; } 1720 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1721 { return 0; } 1722 static inline int pci_enable_link_state(struct pci_dev *pdev, int state) 1723 { return 0; } 1724 static inline void pcie_no_aspm(void) { } 1725 static inline bool pcie_aspm_support_enabled(void) { return false; } 1726 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1727 #endif 1728 1729 #ifdef CONFIG_PCIEAER 1730 bool pci_aer_available(void); 1731 #else 1732 static inline bool pci_aer_available(void) { return false; } 1733 #endif 1734 1735 bool pci_ats_disabled(void); 1736 1737 #ifdef CONFIG_PCIE_PTM 1738 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1739 void pci_disable_ptm(struct pci_dev *dev); 1740 bool pcie_ptm_enabled(struct pci_dev *dev); 1741 #else 1742 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1743 { return -EINVAL; } 1744 static inline void pci_disable_ptm(struct pci_dev *dev) { } 1745 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1746 { return false; } 1747 #endif 1748 1749 void pci_cfg_access_lock(struct pci_dev *dev); 1750 bool pci_cfg_access_trylock(struct pci_dev *dev); 1751 void pci_cfg_access_unlock(struct pci_dev *dev); 1752 1753 void pci_dev_lock(struct pci_dev *dev); 1754 int pci_dev_trylock(struct pci_dev *dev); 1755 void pci_dev_unlock(struct pci_dev *dev); 1756 1757 /* 1758 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1759 * a PCI domain is defined to be a set of PCI buses which share 1760 * configuration space. 1761 */ 1762 #ifdef CONFIG_PCI_DOMAINS 1763 extern int pci_domains_supported; 1764 #else 1765 enum { pci_domains_supported = 0 }; 1766 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1767 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1768 #endif /* CONFIG_PCI_DOMAINS */ 1769 1770 /* 1771 * Generic implementation for PCI domain support. If your 1772 * architecture does not need custom management of PCI 1773 * domains then this implementation will be used 1774 */ 1775 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1776 static inline int pci_domain_nr(struct pci_bus *bus) 1777 { 1778 return bus->domain_nr; 1779 } 1780 #ifdef CONFIG_ACPI 1781 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1782 #else 1783 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1784 { return 0; } 1785 #endif 1786 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1787 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent); 1788 #endif 1789 1790 /* Some architectures require additional setup to direct VGA traffic */ 1791 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1792 unsigned int command_bits, u32 flags); 1793 void pci_register_set_vga_state(arch_set_vga_state_t func); 1794 1795 static inline int 1796 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1797 { 1798 return pci_request_selected_regions(pdev, 1799 pci_select_bars(pdev, IORESOURCE_IO), name); 1800 } 1801 1802 static inline void 1803 pci_release_io_regions(struct pci_dev *pdev) 1804 { 1805 return pci_release_selected_regions(pdev, 1806 pci_select_bars(pdev, IORESOURCE_IO)); 1807 } 1808 1809 static inline int 1810 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1811 { 1812 return pci_request_selected_regions(pdev, 1813 pci_select_bars(pdev, IORESOURCE_MEM), name); 1814 } 1815 1816 static inline void 1817 pci_release_mem_regions(struct pci_dev *pdev) 1818 { 1819 return pci_release_selected_regions(pdev, 1820 pci_select_bars(pdev, IORESOURCE_MEM)); 1821 } 1822 1823 #else /* CONFIG_PCI is not enabled */ 1824 1825 static inline void pci_set_flags(int flags) { } 1826 static inline void pci_add_flags(int flags) { } 1827 static inline void pci_clear_flags(int flags) { } 1828 static inline int pci_has_flag(int flag) { return 0; } 1829 1830 /* 1831 * If the system does not have PCI, clearly these return errors. Define 1832 * these as simple inline functions to avoid hair in drivers. 1833 */ 1834 #define _PCI_NOP(o, s, t) \ 1835 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1836 int where, t val) \ 1837 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1838 1839 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1840 _PCI_NOP(o, word, u16 x) \ 1841 _PCI_NOP(o, dword, u32 x) 1842 _PCI_NOP_ALL(read, *) 1843 _PCI_NOP_ALL(write,) 1844 1845 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1846 unsigned int device, 1847 struct pci_dev *from) 1848 { return NULL; } 1849 1850 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1851 unsigned int device, 1852 unsigned int ss_vendor, 1853 unsigned int ss_device, 1854 struct pci_dev *from) 1855 { return NULL; } 1856 1857 static inline struct pci_dev *pci_get_class(unsigned int class, 1858 struct pci_dev *from) 1859 { return NULL; } 1860 1861 1862 static inline int pci_dev_present(const struct pci_device_id *ids) 1863 { return 0; } 1864 1865 #define no_pci_devices() (1) 1866 #define pci_dev_put(dev) do { } while (0) 1867 1868 static inline void pci_set_master(struct pci_dev *dev) { } 1869 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1870 static inline void pci_disable_device(struct pci_dev *dev) { } 1871 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1872 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1873 { return -EBUSY; } 1874 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 1875 struct module *owner, 1876 const char *mod_name) 1877 { return 0; } 1878 static inline int pci_register_driver(struct pci_driver *drv) 1879 { return 0; } 1880 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1881 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1882 { return 0; } 1883 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1884 int cap) 1885 { return 0; } 1886 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1887 { return 0; } 1888 1889 static inline u64 pci_get_dsn(struct pci_dev *dev) 1890 { return 0; } 1891 1892 /* Power management related routines */ 1893 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1894 static inline void pci_restore_state(struct pci_dev *dev) { } 1895 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1896 { return 0; } 1897 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1898 { return 0; } 1899 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1900 pm_message_t state) 1901 { return PCI_D0; } 1902 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1903 int enable) 1904 { return 0; } 1905 1906 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1907 struct resource *res) 1908 { return NULL; } 1909 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1910 { return -EIO; } 1911 static inline void pci_release_regions(struct pci_dev *dev) { } 1912 1913 static inline int pci_register_io_range(struct fwnode_handle *fwnode, 1914 phys_addr_t addr, resource_size_t size) 1915 { return -EINVAL; } 1916 1917 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1918 1919 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1920 { return NULL; } 1921 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1922 unsigned int devfn) 1923 { return NULL; } 1924 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1925 unsigned int bus, unsigned int devfn) 1926 { return NULL; } 1927 1928 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1929 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1930 1931 #define dev_is_pci(d) (false) 1932 #define dev_is_pf(d) (false) 1933 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1934 { return false; } 1935 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1936 struct device_node *node, 1937 const u32 *intspec, 1938 unsigned int intsize, 1939 unsigned long *out_hwirq, 1940 unsigned int *out_type) 1941 { return -EINVAL; } 1942 1943 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1944 struct pci_dev *dev) 1945 { return NULL; } 1946 static inline bool pci_ats_disabled(void) { return true; } 1947 1948 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1949 { 1950 return -EINVAL; 1951 } 1952 1953 static inline int 1954 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1955 unsigned int max_vecs, unsigned int flags, 1956 struct irq_affinity *aff_desc) 1957 { 1958 return -ENOSPC; 1959 } 1960 static inline int 1961 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1962 unsigned int max_vecs, unsigned int flags) 1963 { 1964 return -ENOSPC; 1965 } 1966 #endif /* CONFIG_PCI */ 1967 1968 /* Include architecture-dependent settings and functions */ 1969 1970 #include <asm/pci.h> 1971 1972 /* 1973 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1974 * is expected to be an offset within that region. 1975 * 1976 */ 1977 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1978 struct vm_area_struct *vma, 1979 enum pci_mmap_state mmap_state, int write_combine); 1980 1981 #ifndef arch_can_pci_mmap_wc 1982 #define arch_can_pci_mmap_wc() 0 1983 #endif 1984 1985 #ifndef arch_can_pci_mmap_io 1986 #define arch_can_pci_mmap_io() 0 1987 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1988 #else 1989 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1990 #endif 1991 1992 #ifndef pci_root_bus_fwnode 1993 #define pci_root_bus_fwnode(bus) NULL 1994 #endif 1995 1996 /* 1997 * These helpers provide future and backwards compatibility 1998 * for accessing popular PCI BAR info 1999 */ 2000 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 2001 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 2002 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 2003 #define pci_resource_len(dev,bar) \ 2004 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \ 2005 \ 2006 (pci_resource_end((dev), (bar)) - \ 2007 pci_resource_start((dev), (bar)) + 1)) 2008 2009 /* 2010 * Similar to the helpers above, these manipulate per-pci_dev 2011 * driver-specific data. They are really just a wrapper around 2012 * the generic device structure functions of these calls. 2013 */ 2014 static inline void *pci_get_drvdata(struct pci_dev *pdev) 2015 { 2016 return dev_get_drvdata(&pdev->dev); 2017 } 2018 2019 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 2020 { 2021 dev_set_drvdata(&pdev->dev, data); 2022 } 2023 2024 static inline const char *pci_name(const struct pci_dev *pdev) 2025 { 2026 return dev_name(&pdev->dev); 2027 } 2028 2029 void pci_resource_to_user(const struct pci_dev *dev, int bar, 2030 const struct resource *rsrc, 2031 resource_size_t *start, resource_size_t *end); 2032 2033 /* 2034 * The world is not perfect and supplies us with broken PCI devices. 2035 * For at least a part of these bugs we need a work-around, so both 2036 * generic (drivers/pci/quirks.c) and per-architecture code can define 2037 * fixup hooks to be called for particular buggy devices. 2038 */ 2039 2040 struct pci_fixup { 2041 u16 vendor; /* Or PCI_ANY_ID */ 2042 u16 device; /* Or PCI_ANY_ID */ 2043 u32 class; /* Or PCI_ANY_ID */ 2044 unsigned int class_shift; /* should be 0, 8, 16 */ 2045 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2046 int hook_offset; 2047 #else 2048 void (*hook)(struct pci_dev *dev); 2049 #endif 2050 }; 2051 2052 enum pci_fixup_pass { 2053 pci_fixup_early, /* Before probing BARs */ 2054 pci_fixup_header, /* After reading configuration header */ 2055 pci_fixup_final, /* Final phase of device fixups */ 2056 pci_fixup_enable, /* pci_enable_device() time */ 2057 pci_fixup_resume, /* pci_device_resume() */ 2058 pci_fixup_suspend, /* pci_device_suspend() */ 2059 pci_fixup_resume_early, /* pci_device_resume_early() */ 2060 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2061 }; 2062 2063 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2064 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2065 class_shift, hook) \ 2066 __ADDRESSABLE(hook) \ 2067 asm(".section " #sec ", \"a\" \n" \ 2068 ".balign 16 \n" \ 2069 ".short " #vendor ", " #device " \n" \ 2070 ".long " #class ", " #class_shift " \n" \ 2071 ".long " #hook " - . \n" \ 2072 ".previous \n"); 2073 2074 /* 2075 * Clang's LTO may rename static functions in C, but has no way to 2076 * handle such renamings when referenced from inline asm. To work 2077 * around this, create global C stubs for these cases. 2078 */ 2079 #ifdef CONFIG_LTO_CLANG 2080 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2081 class_shift, hook, stub) \ 2082 void stub(struct pci_dev *dev); \ 2083 void stub(struct pci_dev *dev) \ 2084 { \ 2085 hook(dev); \ 2086 } \ 2087 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2088 class_shift, stub) 2089 #else 2090 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2091 class_shift, hook, stub) \ 2092 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2093 class_shift, hook) 2094 #endif 2095 2096 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2097 class_shift, hook) \ 2098 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2099 class_shift, hook, __UNIQUE_ID(hook)) 2100 #else 2101 /* Anonymous variables would be nice... */ 2102 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2103 class_shift, hook) \ 2104 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2105 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2106 = { vendor, device, class, class_shift, hook }; 2107 #endif 2108 2109 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2110 class_shift, hook) \ 2111 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2112 hook, vendor, device, class, class_shift, hook) 2113 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2114 class_shift, hook) \ 2115 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2116 hook, vendor, device, class, class_shift, hook) 2117 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2118 class_shift, hook) \ 2119 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2120 hook, vendor, device, class, class_shift, hook) 2121 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2122 class_shift, hook) \ 2123 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2124 hook, vendor, device, class, class_shift, hook) 2125 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2126 class_shift, hook) \ 2127 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2128 resume##hook, vendor, device, class, class_shift, hook) 2129 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2130 class_shift, hook) \ 2131 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2132 resume_early##hook, vendor, device, class, class_shift, hook) 2133 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2134 class_shift, hook) \ 2135 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2136 suspend##hook, vendor, device, class, class_shift, hook) 2137 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2138 class_shift, hook) \ 2139 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2140 suspend_late##hook, vendor, device, class, class_shift, hook) 2141 2142 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2143 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2144 hook, vendor, device, PCI_ANY_ID, 0, hook) 2145 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2146 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2147 hook, vendor, device, PCI_ANY_ID, 0, hook) 2148 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2149 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2150 hook, vendor, device, PCI_ANY_ID, 0, hook) 2151 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2152 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2153 hook, vendor, device, PCI_ANY_ID, 0, hook) 2154 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2155 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2156 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2157 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2158 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2159 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2160 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2161 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2162 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2163 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2164 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2165 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2166 2167 #ifdef CONFIG_PCI_QUIRKS 2168 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2169 #else 2170 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2171 struct pci_dev *dev) { } 2172 #endif 2173 2174 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2175 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2176 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2177 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2178 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2179 const char *name); 2180 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2181 2182 extern int pci_pci_problems; 2183 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2184 #define PCIPCI_TRITON 2 2185 #define PCIPCI_NATOMA 4 2186 #define PCIPCI_VIAETBF 8 2187 #define PCIPCI_VSFX 16 2188 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2189 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2190 2191 extern unsigned long pci_cardbus_io_size; 2192 extern unsigned long pci_cardbus_mem_size; 2193 extern u8 pci_dfl_cache_line_size; 2194 extern u8 pci_cache_line_size; 2195 2196 /* Architecture-specific versions may override these (weak) */ 2197 void pcibios_disable_device(struct pci_dev *dev); 2198 void pcibios_set_master(struct pci_dev *dev); 2199 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2200 enum pcie_reset_state state); 2201 int pcibios_device_add(struct pci_dev *dev); 2202 void pcibios_release_device(struct pci_dev *dev); 2203 #ifdef CONFIG_PCI 2204 void pcibios_penalize_isa_irq(int irq, int active); 2205 #else 2206 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2207 #endif 2208 int pcibios_alloc_irq(struct pci_dev *dev); 2209 void pcibios_free_irq(struct pci_dev *dev); 2210 resource_size_t pcibios_default_alignment(void); 2211 2212 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2213 void __init pci_mmcfg_early_init(void); 2214 void __init pci_mmcfg_late_init(void); 2215 #else 2216 static inline void pci_mmcfg_early_init(void) { } 2217 static inline void pci_mmcfg_late_init(void) { } 2218 #endif 2219 2220 int pci_ext_cfg_avail(void); 2221 2222 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2223 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2224 2225 #ifdef CONFIG_PCI_IOV 2226 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2227 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2228 int pci_iov_vf_id(struct pci_dev *dev); 2229 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2230 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2231 void pci_disable_sriov(struct pci_dev *dev); 2232 2233 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2234 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2235 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2236 int pci_num_vf(struct pci_dev *dev); 2237 int pci_vfs_assigned(struct pci_dev *dev); 2238 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2239 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2240 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2241 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2242 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2243 2244 /* Arch may override these (weak) */ 2245 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2246 int pcibios_sriov_disable(struct pci_dev *pdev); 2247 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2248 #else 2249 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2250 { 2251 return -ENOSYS; 2252 } 2253 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2254 { 2255 return -ENOSYS; 2256 } 2257 2258 static inline int pci_iov_vf_id(struct pci_dev *dev) 2259 { 2260 return -ENOSYS; 2261 } 2262 2263 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2264 struct pci_driver *pf_driver) 2265 { 2266 return ERR_PTR(-EINVAL); 2267 } 2268 2269 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2270 { return -ENODEV; } 2271 2272 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2273 struct pci_dev *virtfn, int id) 2274 { 2275 return -ENODEV; 2276 } 2277 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2278 { 2279 return -ENOSYS; 2280 } 2281 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2282 int id) { } 2283 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2284 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2285 static inline int pci_vfs_assigned(struct pci_dev *dev) 2286 { return 0; } 2287 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2288 { return 0; } 2289 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2290 { return 0; } 2291 #define pci_sriov_configure_simple NULL 2292 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2293 { return 0; } 2294 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2295 #endif 2296 2297 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2298 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2299 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2300 #endif 2301 2302 /** 2303 * pci_pcie_cap - get the saved PCIe capability offset 2304 * @dev: PCI device 2305 * 2306 * PCIe capability offset is calculated at PCI device initialization 2307 * time and saved in the data structure. This function returns saved 2308 * PCIe capability offset. Using this instead of pci_find_capability() 2309 * reduces unnecessary search in the PCI configuration space. If you 2310 * need to calculate PCIe capability offset from raw device for some 2311 * reasons, please use pci_find_capability() instead. 2312 */ 2313 static inline int pci_pcie_cap(struct pci_dev *dev) 2314 { 2315 return dev->pcie_cap; 2316 } 2317 2318 /** 2319 * pci_is_pcie - check if the PCI device is PCI Express capable 2320 * @dev: PCI device 2321 * 2322 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2323 */ 2324 static inline bool pci_is_pcie(struct pci_dev *dev) 2325 { 2326 return pci_pcie_cap(dev); 2327 } 2328 2329 /** 2330 * pcie_caps_reg - get the PCIe Capabilities Register 2331 * @dev: PCI device 2332 */ 2333 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2334 { 2335 return dev->pcie_flags_reg; 2336 } 2337 2338 /** 2339 * pci_pcie_type - get the PCIe device/port type 2340 * @dev: PCI device 2341 */ 2342 static inline int pci_pcie_type(const struct pci_dev *dev) 2343 { 2344 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2345 } 2346 2347 /** 2348 * pcie_find_root_port - Get the PCIe root port device 2349 * @dev: PCI device 2350 * 2351 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2352 * for a given PCI/PCIe Device. 2353 */ 2354 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2355 { 2356 while (dev) { 2357 if (pci_is_pcie(dev) && 2358 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2359 return dev; 2360 dev = pci_upstream_bridge(dev); 2361 } 2362 2363 return NULL; 2364 } 2365 2366 void pci_request_acs(void); 2367 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2368 bool pci_acs_path_enabled(struct pci_dev *start, 2369 struct pci_dev *end, u16 acs_flags); 2370 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2371 2372 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2373 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2374 2375 /* Large Resource Data Type Tag Item Names */ 2376 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2377 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2378 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2379 2380 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2381 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2382 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2383 2384 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2385 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2386 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2387 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2388 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2389 2390 /** 2391 * pci_vpd_alloc - Allocate buffer and read VPD into it 2392 * @dev: PCI device 2393 * @size: pointer to field where VPD length is returned 2394 * 2395 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2396 */ 2397 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2398 2399 /** 2400 * pci_vpd_find_id_string - Locate id string in VPD 2401 * @buf: Pointer to buffered VPD data 2402 * @len: The length of the buffer area in which to search 2403 * @size: Pointer to field where length of id string is returned 2404 * 2405 * Returns the index of the id string or -ENOENT if not found. 2406 */ 2407 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2408 2409 /** 2410 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2411 * @buf: Pointer to buffered VPD data 2412 * @len: The length of the buffer area in which to search 2413 * @kw: The keyword to search for 2414 * @size: Pointer to field where length of found keyword data is returned 2415 * 2416 * Returns the index of the information field keyword data or -ENOENT if 2417 * not found. 2418 */ 2419 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2420 const char *kw, unsigned int *size); 2421 2422 /** 2423 * pci_vpd_check_csum - Check VPD checksum 2424 * @buf: Pointer to buffered VPD data 2425 * @len: VPD size 2426 * 2427 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2428 */ 2429 int pci_vpd_check_csum(const void *buf, unsigned int len); 2430 2431 /* PCI <-> OF binding helpers */ 2432 #ifdef CONFIG_OF 2433 struct device_node; 2434 struct irq_domain; 2435 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2436 bool pci_host_of_has_msi_map(struct device *dev); 2437 2438 /* Arch may override this (weak) */ 2439 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2440 2441 #else /* CONFIG_OF */ 2442 static inline struct irq_domain * 2443 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2444 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2445 #endif /* CONFIG_OF */ 2446 2447 static inline struct device_node * 2448 pci_device_to_OF_node(const struct pci_dev *pdev) 2449 { 2450 return pdev ? pdev->dev.of_node : NULL; 2451 } 2452 2453 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2454 { 2455 return bus ? bus->dev.of_node : NULL; 2456 } 2457 2458 #ifdef CONFIG_ACPI 2459 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2460 2461 void 2462 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2463 bool pci_pr3_present(struct pci_dev *pdev); 2464 #else 2465 static inline struct irq_domain * 2466 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2467 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2468 #endif 2469 2470 #ifdef CONFIG_EEH 2471 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2472 { 2473 return pdev->dev.archdata.edev; 2474 } 2475 #endif 2476 2477 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2478 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2479 int pci_for_each_dma_alias(struct pci_dev *pdev, 2480 int (*fn)(struct pci_dev *pdev, 2481 u16 alias, void *data), void *data); 2482 2483 /* Helper functions for operation of device flag */ 2484 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2485 { 2486 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2487 } 2488 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2489 { 2490 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2491 } 2492 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2493 { 2494 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2495 } 2496 2497 /** 2498 * pci_ari_enabled - query ARI forwarding status 2499 * @bus: the PCI bus 2500 * 2501 * Returns true if ARI forwarding is enabled. 2502 */ 2503 static inline bool pci_ari_enabled(struct pci_bus *bus) 2504 { 2505 return bus->self && bus->self->ari_enabled; 2506 } 2507 2508 /** 2509 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2510 * @pdev: PCI device to check 2511 * 2512 * Walk upwards from @pdev and check for each encountered bridge if it's part 2513 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2514 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2515 */ 2516 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2517 { 2518 struct pci_dev *parent = pdev; 2519 2520 if (pdev->is_thunderbolt) 2521 return true; 2522 2523 while ((parent = pci_upstream_bridge(parent))) 2524 if (parent->is_thunderbolt) 2525 return true; 2526 2527 return false; 2528 } 2529 2530 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2531 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2532 #endif 2533 2534 struct msi_domain_template; 2535 2536 bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template, 2537 unsigned int hwsize, void *data); 2538 struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie, 2539 const struct irq_affinity_desc *affdesc); 2540 void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map); 2541 2542 #include <linux/dma-mapping.h> 2543 2544 #define pci_printk(level, pdev, fmt, arg...) \ 2545 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2546 2547 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2548 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2549 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2550 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2551 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2552 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) 2553 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2554 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2555 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2556 2557 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2558 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2559 2560 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2561 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2562 2563 #define pci_WARN(pdev, condition, fmt, arg...) \ 2564 WARN(condition, "%s %s: " fmt, \ 2565 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2566 2567 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2568 WARN_ONCE(condition, "%s %s: " fmt, \ 2569 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2570 2571 #endif /* LINUX_PCI_H */ 2572