1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 #include <linux/args.h> 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <linux/msi_api.h> 42 #include <uapi/linux/pci.h> 43 44 #include <linux/pci_ids.h> 45 46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 47 PCI_STATUS_SIG_SYSTEM_ERROR | \ 48 PCI_STATUS_REC_MASTER_ABORT | \ 49 PCI_STATUS_REC_TARGET_ABORT | \ 50 PCI_STATUS_SIG_TARGET_ABORT | \ 51 PCI_STATUS_PARITY) 52 53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 54 #define PCI_NUM_RESET_METHODS 8 55 56 #define PCI_RESET_PROBE true 57 #define PCI_RESET_DO_RESET false 58 59 /* 60 * The PCI interface treats multi-function devices as independent 61 * devices. The slot/function address of each device is encoded 62 * in a single byte as follows: 63 * 64 * 7:3 = slot 65 * 2:0 = function 66 * 67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 68 * In the interest of not exposing interfaces to user-space unnecessarily, 69 * the following kernel-only defines are being added here. 70 */ 71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 74 75 /* pci_slot represents a physical slot */ 76 struct pci_slot { 77 struct pci_bus *bus; /* Bus this slot is on */ 78 struct list_head list; /* Node in list of slots */ 79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 81 struct kobject kobj; 82 }; 83 84 static inline const char *pci_slot_name(const struct pci_slot *slot) 85 { 86 return kobject_name(&slot->kobj); 87 } 88 89 /* File state for mmap()s on /proc/bus/pci/X/Y */ 90 enum pci_mmap_state { 91 pci_mmap_io, 92 pci_mmap_mem 93 }; 94 95 /* For PCI devices, the region numbers are assigned this way: */ 96 enum { 97 /* #0-5: standard PCI resources */ 98 PCI_STD_RESOURCES, 99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 100 101 /* #6: expansion ROM resource */ 102 PCI_ROM_RESOURCE, 103 104 /* Device-specific resources */ 105 #ifdef CONFIG_PCI_IOV 106 PCI_IOV_RESOURCES, 107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 108 #endif 109 110 /* PCI-to-PCI (P2P) bridge windows */ 111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 114 115 /* CardBus bridge windows */ 116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 120 121 /* Total number of bridge resources for P2P and CardBus */ 122 #define PCI_BRIDGE_RESOURCE_NUM 4 123 124 /* Resources assigned to buses behind the bridge */ 125 PCI_BRIDGE_RESOURCES, 126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 127 PCI_BRIDGE_RESOURCE_NUM - 1, 128 129 /* Total resources associated with a PCI device */ 130 PCI_NUM_RESOURCES, 131 132 /* Preserve this for compatibility */ 133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 134 }; 135 136 /** 137 * enum pci_interrupt_pin - PCI INTx interrupt values 138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 139 * @PCI_INTERRUPT_INTA: PCI INTA pin 140 * @PCI_INTERRUPT_INTB: PCI INTB pin 141 * @PCI_INTERRUPT_INTC: PCI INTC pin 142 * @PCI_INTERRUPT_INTD: PCI INTD pin 143 * 144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 145 * PCI_INTERRUPT_PIN register. 146 */ 147 enum pci_interrupt_pin { 148 PCI_INTERRUPT_UNKNOWN, 149 PCI_INTERRUPT_INTA, 150 PCI_INTERRUPT_INTB, 151 PCI_INTERRUPT_INTC, 152 PCI_INTERRUPT_INTD, 153 }; 154 155 /* The number of legacy PCI INTx interrupts */ 156 #define PCI_NUM_INTX 4 157 158 /* 159 * Reading from a device that doesn't respond typically returns ~0. A 160 * successful read from a device may also return ~0, so you need additional 161 * information to reliably identify errors. 162 */ 163 #define PCI_ERROR_RESPONSE (~0ULL) 164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 166 167 /* 168 * pci_power_t values must match the bits in the Capabilities PME_Support 169 * and Control/Status PowerState fields in the Power Management capability. 170 */ 171 typedef int __bitwise pci_power_t; 172 173 #define PCI_D0 ((pci_power_t __force) 0) 174 #define PCI_D1 ((pci_power_t __force) 1) 175 #define PCI_D2 ((pci_power_t __force) 2) 176 #define PCI_D3hot ((pci_power_t __force) 3) 177 #define PCI_D3cold ((pci_power_t __force) 4) 178 #define PCI_UNKNOWN ((pci_power_t __force) 5) 179 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 180 181 /* Remember to update this when the list above changes! */ 182 extern const char *pci_power_names[]; 183 184 static inline const char *pci_power_name(pci_power_t state) 185 { 186 return pci_power_names[1 + (__force int) state]; 187 } 188 189 /** 190 * typedef pci_channel_state_t 191 * 192 * The pci_channel state describes connectivity between the CPU and 193 * the PCI device. If some PCI bus between here and the PCI device 194 * has crashed or locked up, this info is reflected here. 195 */ 196 typedef unsigned int __bitwise pci_channel_state_t; 197 198 enum { 199 /* I/O channel is in normal state */ 200 pci_channel_io_normal = (__force pci_channel_state_t) 1, 201 202 /* I/O to channel is blocked */ 203 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 204 205 /* PCI card is dead */ 206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 207 }; 208 209 typedef unsigned int __bitwise pcie_reset_state_t; 210 211 enum pcie_reset_state { 212 /* Reset is NOT asserted (Use to deassert reset) */ 213 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 214 215 /* Use #PERST to reset PCIe device */ 216 pcie_warm_reset = (__force pcie_reset_state_t) 2, 217 218 /* Use PCIe Hot Reset to reset device */ 219 pcie_hot_reset = (__force pcie_reset_state_t) 3 220 }; 221 222 typedef unsigned short __bitwise pci_dev_flags_t; 223 enum pci_dev_flags { 224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 226 /* Device configuration is irrevocably lost if disabled into D3 */ 227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 228 /* Provide indication device is assigned by a Virtual Machine Manager */ 229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 230 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 234 /* Do not use bus resets for device */ 235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 236 /* Do not use PM reset even if device advertises NoSoftRst- */ 237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 238 /* Get VPD from function 0 VPD */ 239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 240 /* A non-root bridge where translation occurs, stop alias search here */ 241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 242 /* Do not use FLR even if device advertises PCI_AF_CAP */ 243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 244 /* Don't use Relaxed Ordering for TLPs directed at this device */ 245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 246 /* Device does honor MSI masking despite saying otherwise */ 247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 248 }; 249 250 enum pci_irq_reroute_variant { 251 INTEL_IRQ_REROUTE_VARIANT = 1, 252 MAX_IRQ_REROUTE_VARIANTS = 3 253 }; 254 255 typedef unsigned short __bitwise pci_bus_flags_t; 256 enum pci_bus_flags { 257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 261 }; 262 263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 264 enum pcie_link_width { 265 PCIE_LNK_WIDTH_RESRV = 0x00, 266 PCIE_LNK_X1 = 0x01, 267 PCIE_LNK_X2 = 0x02, 268 PCIE_LNK_X4 = 0x04, 269 PCIE_LNK_X8 = 0x08, 270 PCIE_LNK_X12 = 0x0c, 271 PCIE_LNK_X16 = 0x10, 272 PCIE_LNK_X32 = 0x20, 273 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 274 }; 275 276 /* See matching string table in pci_speed_string() */ 277 enum pci_bus_speed { 278 PCI_SPEED_33MHz = 0x00, 279 PCI_SPEED_66MHz = 0x01, 280 PCI_SPEED_66MHz_PCIX = 0x02, 281 PCI_SPEED_100MHz_PCIX = 0x03, 282 PCI_SPEED_133MHz_PCIX = 0x04, 283 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 284 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 285 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 286 PCI_SPEED_66MHz_PCIX_266 = 0x09, 287 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 288 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 289 AGP_UNKNOWN = 0x0c, 290 AGP_1X = 0x0d, 291 AGP_2X = 0x0e, 292 AGP_4X = 0x0f, 293 AGP_8X = 0x10, 294 PCI_SPEED_66MHz_PCIX_533 = 0x11, 295 PCI_SPEED_100MHz_PCIX_533 = 0x12, 296 PCI_SPEED_133MHz_PCIX_533 = 0x13, 297 PCIE_SPEED_2_5GT = 0x14, 298 PCIE_SPEED_5_0GT = 0x15, 299 PCIE_SPEED_8_0GT = 0x16, 300 PCIE_SPEED_16_0GT = 0x17, 301 PCIE_SPEED_32_0GT = 0x18, 302 PCIE_SPEED_64_0GT = 0x19, 303 PCI_SPEED_UNKNOWN = 0xff, 304 }; 305 306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 308 309 struct pci_vpd { 310 struct mutex lock; 311 unsigned int len; 312 u8 cap; 313 }; 314 315 struct irq_affinity; 316 struct pcie_bwctrl_data; 317 struct pcie_link_state; 318 struct pci_sriov; 319 struct pci_p2pdma; 320 struct rcec_ea; 321 322 /* struct pci_dev - describes a PCI device 323 * 324 * @supported_speeds: PCIe Supported Link Speeds Vector (+ reserved 0 at 325 * LSB). 0 when the supported speeds cannot be 326 * determined (e.g., for Root Complex Integrated 327 * Endpoints without the relevant Capability 328 * Registers). 329 */ 330 struct pci_dev { 331 struct list_head bus_list; /* Node in per-bus list */ 332 struct pci_bus *bus; /* Bus this device is on */ 333 struct pci_bus *subordinate; /* Bus this device bridges to */ 334 335 void *sysdata; /* Hook for sys-specific extension */ 336 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 337 struct pci_slot *slot; /* Physical slot this device is in */ 338 339 unsigned int devfn; /* Encoded device & function index */ 340 unsigned short vendor; 341 unsigned short device; 342 unsigned short subsystem_vendor; 343 unsigned short subsystem_device; 344 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 345 u8 revision; /* PCI revision, low byte of class word */ 346 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 347 #ifdef CONFIG_PCIEAER 348 u16 aer_cap; /* AER capability offset */ 349 struct aer_stats *aer_stats; /* AER stats for this device */ 350 #endif 351 #ifdef CONFIG_PCIEPORTBUS 352 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 353 struct pci_dev *rcec; /* Associated RCEC device */ 354 #endif 355 u32 devcap; /* PCIe Device Capabilities */ 356 u8 pcie_cap; /* PCIe capability offset */ 357 u8 msi_cap; /* MSI capability offset */ 358 u8 msix_cap; /* MSI-X capability offset */ 359 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 360 u8 rom_base_reg; /* Config register controlling ROM */ 361 u8 pin; /* Interrupt pin this device uses */ 362 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 363 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 364 365 struct pci_driver *driver; /* Driver bound to this device */ 366 u64 dma_mask; /* Mask of the bits of bus address this 367 device implements. Normally this is 368 0xffffffff. You only need to change 369 this if your device has broken DMA 370 or supports 64-bit transfers. */ 371 372 struct device_dma_parameters dma_parms; 373 374 pci_power_t current_state; /* Current operating state. In ACPI, 375 this is D0-D3, D0 being fully 376 functional, and D3 being off. */ 377 u8 pm_cap; /* PM capability offset */ 378 unsigned int pme_support:5; /* Bitmask of states from which PME# 379 can be generated */ 380 unsigned int pme_poll:1; /* Poll device's PME status bit */ 381 unsigned int pinned:1; /* Whether this dev is pinned */ 382 unsigned int config_rrs_sv:1; /* Config RRS software visibility */ 383 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 384 unsigned int d1_support:1; /* Low power state D1 is supported */ 385 unsigned int d2_support:1; /* Low power state D2 is supported */ 386 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 387 unsigned int no_d3cold:1; /* D3cold is forbidden */ 388 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 389 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 390 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 391 decoding during BAR sizing */ 392 unsigned int wakeup_prepared:1; 393 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 394 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 395 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 396 controlled exclusively by 397 user sysfs */ 398 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 399 bit manually */ 400 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 401 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 402 403 u16 l1ss; /* L1SS Capability pointer */ 404 #ifdef CONFIG_PCIEASPM 405 struct pcie_link_state *link_state; /* ASPM link state */ 406 unsigned int ltr_path:1; /* Latency Tolerance Reporting 407 supported from root to here */ 408 #endif 409 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 410 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 411 412 pci_channel_state_t error_state; /* Current connectivity state */ 413 struct device dev; /* Generic device interface */ 414 415 int cfg_size; /* Size of config space */ 416 417 /* 418 * Instead of touching interrupt line and base address registers 419 * directly, use the values stored here. They might be different! 420 */ 421 unsigned int irq; 422 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 423 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ 424 425 bool match_driver; /* Skip attaching driver */ 426 427 unsigned int transparent:1; /* Subtractive decode bridge */ 428 unsigned int io_window:1; /* Bridge has I/O window */ 429 unsigned int pref_window:1; /* Bridge has pref mem window */ 430 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 431 unsigned int multifunction:1; /* Multi-function device */ 432 433 unsigned int is_busmaster:1; /* Is busmaster */ 434 unsigned int no_msi:1; /* May not use MSI */ 435 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 436 unsigned int block_cfg_access:1; /* Config space access blocked */ 437 unsigned int broken_parity_status:1; /* Generates false positive parity */ 438 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 439 unsigned int msi_enabled:1; 440 unsigned int msix_enabled:1; 441 unsigned int ari_enabled:1; /* ARI forwarding */ 442 unsigned int ats_enabled:1; /* Address Translation Svc */ 443 unsigned int pasid_enabled:1; /* Process Address Space ID */ 444 unsigned int pri_enabled:1; /* Page Request Interface */ 445 unsigned int tph_enabled:1; /* TLP Processing Hints */ 446 unsigned int is_managed:1; /* Managed via devres */ 447 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 448 unsigned int needs_freset:1; /* Requires fundamental reset */ 449 unsigned int state_saved:1; 450 unsigned int is_physfn:1; 451 unsigned int is_virtfn:1; 452 unsigned int is_hotplug_bridge:1; 453 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 454 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 455 /* 456 * Devices marked being untrusted are the ones that can potentially 457 * execute DMA attacks and similar. They are typically connected 458 * through external ports such as Thunderbolt but not limited to 459 * that. When an IOMMU is enabled they should be getting full 460 * mappings to make sure they cannot access arbitrary memory. 461 */ 462 unsigned int untrusted:1; 463 /* 464 * Info from the platform, e.g., ACPI or device tree, may mark a 465 * device as "external-facing". An external-facing device is 466 * itself internal but devices downstream from it are external. 467 */ 468 unsigned int external_facing:1; 469 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 470 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 471 unsigned int irq_managed:1; 472 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 473 unsigned int is_probed:1; /* Device probing in progress */ 474 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 475 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 476 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 477 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 478 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ 479 pci_dev_flags_t dev_flags; 480 atomic_t enable_cnt; /* pci_enable_device has been called */ 481 482 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */ 483 u32 saved_config_space[16]; /* Config space saved at suspend time */ 484 struct hlist_head saved_cap_space; 485 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 486 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 487 488 #ifdef CONFIG_HOTPLUG_PCI_PCIE 489 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 490 #endif 491 #ifdef CONFIG_PCIE_PTM 492 u16 ptm_cap; /* PTM Capability */ 493 unsigned int ptm_root:1; 494 unsigned int ptm_enabled:1; 495 u8 ptm_granularity; 496 #endif 497 #ifdef CONFIG_PCI_MSI 498 void __iomem *msix_base; 499 raw_spinlock_t msi_lock; 500 #endif 501 struct pci_vpd vpd; 502 #ifdef CONFIG_PCIE_DPC 503 u16 dpc_cap; 504 unsigned int dpc_rp_extensions:1; 505 u8 dpc_rp_log_size; 506 #endif 507 struct pcie_bwctrl_data *link_bwctrl; 508 #ifdef CONFIG_PCI_ATS 509 union { 510 struct pci_sriov *sriov; /* PF: SR-IOV info */ 511 struct pci_dev *physfn; /* VF: related PF */ 512 }; 513 u16 ats_cap; /* ATS Capability offset */ 514 u8 ats_stu; /* ATS Smallest Translation Unit */ 515 #endif 516 #ifdef CONFIG_PCI_PRI 517 u16 pri_cap; /* PRI Capability offset */ 518 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 519 unsigned int pasid_required:1; /* PRG Response PASID Required */ 520 #endif 521 #ifdef CONFIG_PCI_PASID 522 u16 pasid_cap; /* PASID Capability offset */ 523 u16 pasid_features; 524 #endif 525 #ifdef CONFIG_PCI_P2PDMA 526 struct pci_p2pdma __rcu *p2pdma; 527 #endif 528 #ifdef CONFIG_PCI_DOE 529 struct xarray doe_mbs; /* Data Object Exchange mailboxes */ 530 #endif 531 #ifdef CONFIG_PCI_NPEM 532 struct npem *npem; /* Native PCIe Enclosure Management */ 533 #endif 534 u16 acs_cap; /* ACS Capability offset */ 535 u8 supported_speeds; /* Supported Link Speeds Vector */ 536 phys_addr_t rom; /* Physical address if not from BAR */ 537 size_t romlen; /* Length if not from BAR */ 538 /* 539 * Driver name to force a match. Do not set directly, because core 540 * frees it. Use driver_set_override() to set or clear it. 541 */ 542 const char *driver_override; 543 544 unsigned long priv_flags; /* Private flags for the PCI driver */ 545 546 /* These methods index pci_reset_fn_methods[] */ 547 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 548 549 #ifdef CONFIG_PCIE_TPH 550 u16 tph_cap; /* TPH capability offset */ 551 u8 tph_mode; /* TPH mode */ 552 u8 tph_req_type; /* TPH requester type */ 553 #endif 554 }; 555 556 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 557 { 558 #ifdef CONFIG_PCI_IOV 559 if (dev->is_virtfn) 560 dev = dev->physfn; 561 #endif 562 return dev; 563 } 564 565 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 566 567 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 568 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 569 570 static inline int pci_channel_offline(struct pci_dev *pdev) 571 { 572 return (pdev->error_state != pci_channel_io_normal); 573 } 574 575 /* 576 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 577 * Group number is limited to a 16-bit value, therefore (int)-1 is 578 * not a valid PCI domain number, and can be used as a sentinel 579 * value indicating ->domain_nr is not set by the driver (and 580 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 581 * pci_bus_find_domain_nr()). 582 */ 583 #define PCI_DOMAIN_NR_NOT_SET (-1) 584 585 struct pci_host_bridge { 586 struct device dev; 587 struct pci_bus *bus; /* Root bus */ 588 struct pci_ops *ops; 589 struct pci_ops *child_ops; 590 void *sysdata; 591 int busnr; 592 int domain_nr; 593 struct list_head windows; /* resource_entry */ 594 struct list_head dma_ranges; /* dma ranges resource list */ 595 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 596 int (*map_irq)(const struct pci_dev *, u8, u8); 597 void (*release_fn)(struct pci_host_bridge *); 598 void *release_data; 599 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 600 unsigned int no_ext_tags:1; /* No Extended Tags */ 601 unsigned int no_inc_mrrs:1; /* No Increase MRRS */ 602 unsigned int native_aer:1; /* OS may use PCIe AER */ 603 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 604 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 605 unsigned int native_pme:1; /* OS may use PCIe PME */ 606 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 607 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 608 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ 609 unsigned int preserve_config:1; /* Preserve FW resource setup */ 610 unsigned int size_windows:1; /* Enable root bus sizing */ 611 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 612 613 /* Resource alignment requirements */ 614 resource_size_t (*align_resource)(struct pci_dev *dev, 615 const struct resource *res, 616 resource_size_t start, 617 resource_size_t size, 618 resource_size_t align); 619 unsigned long private[] ____cacheline_aligned; 620 }; 621 622 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 623 624 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 625 { 626 return (void *)bridge->private; 627 } 628 629 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 630 { 631 return container_of(priv, struct pci_host_bridge, private); 632 } 633 634 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 635 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 636 size_t priv); 637 void pci_free_host_bridge(struct pci_host_bridge *bridge); 638 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 639 640 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 641 void (*release_fn)(struct pci_host_bridge *), 642 void *release_data); 643 644 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 645 646 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 647 648 struct pci_bus { 649 struct list_head node; /* Node in list of buses */ 650 struct pci_bus *parent; /* Parent bus this bridge is on */ 651 struct list_head children; /* List of child buses */ 652 struct list_head devices; /* List of devices on this bus */ 653 struct pci_dev *self; /* Bridge device as seen by parent */ 654 struct list_head slots; /* List of slots on this bus; 655 protected by pci_slot_mutex */ 656 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 657 struct list_head resources; /* Address space routed to this bus */ 658 struct resource busn_res; /* Bus numbers routed to this bus */ 659 660 struct pci_ops *ops; /* Configuration access functions */ 661 void *sysdata; /* Hook for sys-specific extension */ 662 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 663 664 unsigned char number; /* Bus number */ 665 unsigned char primary; /* Number of primary bridge */ 666 unsigned char max_bus_speed; /* enum pci_bus_speed */ 667 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 668 #ifdef CONFIG_PCI_DOMAINS_GENERIC 669 int domain_nr; 670 #endif 671 672 char name[48]; 673 674 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 675 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 676 struct device *bridge; 677 struct device dev; 678 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 679 struct bin_attribute *legacy_mem; /* Legacy mem */ 680 unsigned int is_added:1; 681 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 682 }; 683 684 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 685 686 static inline u16 pci_dev_id(struct pci_dev *dev) 687 { 688 return PCI_DEVID(dev->bus->number, dev->devfn); 689 } 690 691 /* 692 * Returns true if the PCI bus is root (behind host-PCI bridge), 693 * false otherwise 694 * 695 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 696 * This is incorrect because "virtual" buses added for SR-IOV (via 697 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 698 */ 699 static inline bool pci_is_root_bus(struct pci_bus *pbus) 700 { 701 return !(pbus->parent); 702 } 703 704 /** 705 * pci_is_bridge - check if the PCI device is a bridge 706 * @dev: PCI device 707 * 708 * Return true if the PCI device is bridge whether it has subordinate 709 * or not. 710 */ 711 static inline bool pci_is_bridge(struct pci_dev *dev) 712 { 713 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 714 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 715 } 716 717 /** 718 * pci_is_vga - check if the PCI device is a VGA device 719 * @pdev: PCI device 720 * 721 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define 722 * VGA Base Class and Sub-Classes: 723 * 724 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible 725 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code) 726 * 727 * Return true if the PCI device is a VGA device and uses the legacy VGA 728 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and 729 * aliases). 730 */ 731 static inline bool pci_is_vga(struct pci_dev *pdev) 732 { 733 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) 734 return true; 735 736 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA) 737 return true; 738 739 return false; 740 } 741 742 #define for_each_pci_bridge(dev, bus) \ 743 list_for_each_entry(dev, &bus->devices, bus_list) \ 744 if (!pci_is_bridge(dev)) {} else 745 746 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 747 { 748 dev = pci_physfn(dev); 749 if (pci_is_root_bus(dev->bus)) 750 return NULL; 751 752 return dev->bus->self; 753 } 754 755 #ifdef CONFIG_PCI_MSI 756 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 757 { 758 return pci_dev->msi_enabled || pci_dev->msix_enabled; 759 } 760 #else 761 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 762 #endif 763 764 /* Error values that may be returned by PCI functions */ 765 #define PCIBIOS_SUCCESSFUL 0x00 766 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 767 #define PCIBIOS_BAD_VENDOR_ID 0x83 768 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 769 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 770 #define PCIBIOS_SET_FAILED 0x88 771 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 772 773 /* Translate above to generic errno for passing back through non-PCI code */ 774 static inline int pcibios_err_to_errno(int err) 775 { 776 if (err <= PCIBIOS_SUCCESSFUL) 777 return err; /* Assume already errno */ 778 779 switch (err) { 780 case PCIBIOS_FUNC_NOT_SUPPORTED: 781 return -ENOENT; 782 case PCIBIOS_BAD_VENDOR_ID: 783 return -ENOTTY; 784 case PCIBIOS_DEVICE_NOT_FOUND: 785 return -ENODEV; 786 case PCIBIOS_BAD_REGISTER_NUMBER: 787 return -EFAULT; 788 case PCIBIOS_SET_FAILED: 789 return -EIO; 790 case PCIBIOS_BUFFER_TOO_SMALL: 791 return -ENOSPC; 792 } 793 794 return -ERANGE; 795 } 796 797 /* Low-level architecture-dependent routines */ 798 799 struct pci_ops { 800 int (*add_bus)(struct pci_bus *bus); 801 void (*remove_bus)(struct pci_bus *bus); 802 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 803 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 804 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 805 }; 806 807 /* 808 * ACPI needs to be able to access PCI config space before we've done a 809 * PCI bus scan and created pci_bus structures. 810 */ 811 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 812 int reg, int len, u32 *val); 813 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 814 int reg, int len, u32 val); 815 816 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 817 typedef u64 pci_bus_addr_t; 818 #else 819 typedef u32 pci_bus_addr_t; 820 #endif 821 822 struct pci_bus_region { 823 pci_bus_addr_t start; 824 pci_bus_addr_t end; 825 }; 826 827 struct pci_dynids { 828 spinlock_t lock; /* Protects list, index */ 829 struct list_head list; /* For IDs added at runtime */ 830 }; 831 832 833 /* 834 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 835 * a set of callbacks in struct pci_error_handlers, that device driver 836 * will be notified of PCI bus errors, and will be driven to recovery 837 * when an error occurs. 838 */ 839 840 typedef unsigned int __bitwise pci_ers_result_t; 841 842 enum pci_ers_result { 843 /* No result/none/not supported in device driver */ 844 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 845 846 /* Device driver can recover without slot reset */ 847 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 848 849 /* Device driver wants slot to be reset */ 850 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 851 852 /* Device has completely failed, is unrecoverable */ 853 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 854 855 /* Device driver is fully recovered and operational */ 856 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 857 858 /* No AER capabilities registered for the driver */ 859 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 860 }; 861 862 /* PCI bus error event callbacks */ 863 struct pci_error_handlers { 864 /* PCI bus error detected on this device */ 865 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 866 pci_channel_state_t error); 867 868 /* MMIO has been re-enabled, but not DMA */ 869 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 870 871 /* PCI slot has been reset */ 872 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 873 874 /* PCI function reset prepare or completed */ 875 void (*reset_prepare)(struct pci_dev *dev); 876 void (*reset_done)(struct pci_dev *dev); 877 878 /* Device driver may resume normal operations */ 879 void (*resume)(struct pci_dev *dev); 880 881 /* Allow device driver to record more details of a correctable error */ 882 void (*cor_error_detected)(struct pci_dev *dev); 883 }; 884 885 886 struct module; 887 888 /** 889 * struct pci_driver - PCI driver structure 890 * @name: Driver name. 891 * @id_table: Pointer to table of device IDs the driver is 892 * interested in. Most drivers should export this 893 * table using MODULE_DEVICE_TABLE(pci,...). 894 * @probe: This probing function gets called (during execution 895 * of pci_register_driver() for already existing 896 * devices or later if a new device gets inserted) for 897 * all PCI devices which match the ID table and are not 898 * "owned" by the other drivers yet. This function gets 899 * passed a "struct pci_dev \*" for each device whose 900 * entry in the ID table matches the device. The probe 901 * function returns zero when the driver chooses to 902 * take "ownership" of the device or an error code 903 * (negative number) otherwise. 904 * The probe function always gets called from process 905 * context, so it can sleep. 906 * @remove: The remove() function gets called whenever a device 907 * being handled by this driver is removed (either during 908 * deregistration of the driver or when it's manually 909 * pulled out of a hot-pluggable slot). 910 * The remove function always gets called from process 911 * context, so it can sleep. 912 * @suspend: Put device into low power state. 913 * @resume: Wake device from low power state. 914 * (Please see Documentation/power/pci.rst for descriptions 915 * of PCI Power Management and the related functions.) 916 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 917 * Intended to stop any idling DMA operations. 918 * Useful for enabling wake-on-lan (NIC) or changing 919 * the power state of a device before reboot. 920 * e.g. drivers/net/e100.c. 921 * @sriov_configure: Optional driver callback to allow configuration of 922 * number of VFs to enable via sysfs "sriov_numvfs" file. 923 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 924 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 925 * This will change MSI-X Table Size in the VF Message Control 926 * registers. 927 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 928 * MSI-X vectors available for distribution to the VFs. 929 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 930 * @groups: Sysfs attribute groups. 931 * @dev_groups: Attributes attached to the device that will be 932 * created once it is bound to the driver. 933 * @driver: Driver model structure. 934 * @dynids: List of dynamically added device IDs. 935 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. 936 * For most device drivers, no need to care about this flag 937 * as long as all DMAs are handled through the kernel DMA API. 938 * For some special ones, for example VFIO drivers, they know 939 * how to manage the DMA themselves and set this flag so that 940 * the IOMMU layer will allow them to setup and manage their 941 * own I/O address space. 942 */ 943 struct pci_driver { 944 const char *name; 945 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 946 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 947 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 948 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 949 int (*resume)(struct pci_dev *dev); /* Device woken up */ 950 void (*shutdown)(struct pci_dev *dev); 951 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 952 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 953 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 954 const struct pci_error_handlers *err_handler; 955 const struct attribute_group **groups; 956 const struct attribute_group **dev_groups; 957 struct device_driver driver; 958 struct pci_dynids dynids; 959 bool driver_managed_dma; 960 }; 961 962 #define to_pci_driver(__drv) \ 963 ( __drv ? container_of_const(__drv, struct pci_driver, driver) : NULL ) 964 965 /** 966 * PCI_DEVICE - macro used to describe a specific PCI device 967 * @vend: the 16 bit PCI Vendor ID 968 * @dev: the 16 bit PCI Device ID 969 * 970 * This macro is used to create a struct pci_device_id that matches a 971 * specific device. The subvendor and subdevice fields will be set to 972 * PCI_ANY_ID. 973 */ 974 #define PCI_DEVICE(vend,dev) \ 975 .vendor = (vend), .device = (dev), \ 976 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 977 978 /** 979 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 980 * override_only flags. 981 * @vend: the 16 bit PCI Vendor ID 982 * @dev: the 16 bit PCI Device ID 983 * @driver_override: the 32 bit PCI Device override_only 984 * 985 * This macro is used to create a struct pci_device_id that matches only a 986 * driver_override device. The subvendor and subdevice fields will be set to 987 * PCI_ANY_ID. 988 */ 989 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 990 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 991 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 992 993 /** 994 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 995 * "driver_override" PCI device. 996 * @vend: the 16 bit PCI Vendor ID 997 * @dev: the 16 bit PCI Device ID 998 * 999 * This macro is used to create a struct pci_device_id that matches a 1000 * specific device. The subvendor and subdevice fields will be set to 1001 * PCI_ANY_ID and the driver_override will be set to 1002 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 1003 */ 1004 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 1005 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 1006 1007 /** 1008 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 1009 * @vend: the 16 bit PCI Vendor ID 1010 * @dev: the 16 bit PCI Device ID 1011 * @subvend: the 16 bit PCI Subvendor ID 1012 * @subdev: the 16 bit PCI Subdevice ID 1013 * 1014 * This macro is used to create a struct pci_device_id that matches a 1015 * specific device with subsystem information. 1016 */ 1017 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1018 .vendor = (vend), .device = (dev), \ 1019 .subvendor = (subvend), .subdevice = (subdev) 1020 1021 /** 1022 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 1023 * @dev_class: the class, subclass, prog-if triple for this device 1024 * @dev_class_mask: the class mask for this device 1025 * 1026 * This macro is used to create a struct pci_device_id that matches a 1027 * specific PCI class. The vendor, device, subvendor, and subdevice 1028 * fields will be set to PCI_ANY_ID. 1029 */ 1030 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 1031 .class = (dev_class), .class_mask = (dev_class_mask), \ 1032 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1033 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1034 1035 /** 1036 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 1037 * @vend: the vendor name 1038 * @dev: the 16 bit PCI Device ID 1039 * 1040 * This macro is used to create a struct pci_device_id that matches a 1041 * specific PCI device. The subvendor, and subdevice fields will be set 1042 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1043 * private data. 1044 */ 1045 #define PCI_VDEVICE(vend, dev) \ 1046 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1047 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1048 1049 /** 1050 * PCI_VDEVICE_SUB - describe a specific PCI device/subdevice in a short form 1051 * @vend: the vendor name 1052 * @dev: the 16 bit PCI Device ID 1053 * @subvend: the 16 bit PCI Subvendor ID 1054 * @subdev: the 16 bit PCI Subdevice ID 1055 * 1056 * Generate the pci_device_id struct layout for the specific PCI 1057 * device/subdevice. Private data may follow the output. 1058 */ 1059 #define PCI_VDEVICE_SUB(vend, dev, subvend, subdev) \ 1060 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1061 .subvendor = (subvend), .subdevice = (subdev), 0, 0 1062 1063 /** 1064 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1065 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1066 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1067 * @data: the driver data to be filled 1068 * 1069 * This macro is used to create a struct pci_device_id that matches a 1070 * specific PCI device. The subvendor, and subdevice fields will be set 1071 * to PCI_ANY_ID. 1072 */ 1073 #define PCI_DEVICE_DATA(vend, dev, data) \ 1074 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1075 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1076 .driver_data = (kernel_ulong_t)(data) 1077 1078 enum { 1079 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1080 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1081 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1082 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1083 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1084 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1085 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1086 }; 1087 1088 #define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */ 1089 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1090 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1091 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1092 1093 /* These external functions are only available when PCI support is enabled */ 1094 #ifdef CONFIG_PCI 1095 1096 extern unsigned int pci_flags; 1097 1098 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1099 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1100 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1101 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1102 1103 void pcie_bus_configure_settings(struct pci_bus *bus); 1104 1105 enum pcie_bus_config_types { 1106 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1107 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1108 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1109 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1110 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1111 }; 1112 1113 extern enum pcie_bus_config_types pcie_bus_config; 1114 1115 extern const struct bus_type pci_bus_type; 1116 1117 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1118 * code, or PCI core code. */ 1119 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1120 /* Some device drivers need know if PCI is initiated */ 1121 int no_pci_devices(void); 1122 1123 void pcibios_resource_survey_bus(struct pci_bus *bus); 1124 void pcibios_bus_add_device(struct pci_dev *pdev); 1125 void pcibios_add_bus(struct pci_bus *bus); 1126 void pcibios_remove_bus(struct pci_bus *bus); 1127 void pcibios_fixup_bus(struct pci_bus *); 1128 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1129 /* Architecture-specific versions may override this (weak) */ 1130 char *pcibios_setup(char *str); 1131 1132 /* Used only when drivers/pci/setup.c is used */ 1133 resource_size_t pcibios_align_resource(void *, const struct resource *, 1134 resource_size_t, 1135 resource_size_t); 1136 1137 /* Weak but can be overridden by arch */ 1138 void pci_fixup_cardbus(struct pci_bus *); 1139 1140 /* Generic PCI functions used internally */ 1141 1142 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1143 struct resource *res); 1144 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1145 struct pci_bus_region *region); 1146 void pcibios_scan_specific_bus(int busn); 1147 struct pci_bus *pci_find_bus(int domain, int busnr); 1148 void pci_bus_add_devices(const struct pci_bus *bus); 1149 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1150 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1151 struct pci_ops *ops, void *sysdata, 1152 struct list_head *resources); 1153 int pci_host_probe(struct pci_host_bridge *bridge); 1154 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1155 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1156 void pci_bus_release_busn_res(struct pci_bus *b); 1157 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1158 struct pci_ops *ops, void *sysdata, 1159 struct list_head *resources); 1160 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1161 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1162 int busnr); 1163 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1164 const char *name, 1165 struct hotplug_slot *hotplug); 1166 void pci_destroy_slot(struct pci_slot *slot); 1167 #ifdef CONFIG_SYSFS 1168 void pci_dev_assign_slot(struct pci_dev *dev); 1169 #else 1170 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1171 #endif 1172 int pci_scan_slot(struct pci_bus *bus, int devfn); 1173 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1174 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1175 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1176 void pci_bus_add_device(struct pci_dev *dev); 1177 void pci_read_bridge_bases(struct pci_bus *child); 1178 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1179 struct resource *res); 1180 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1181 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1182 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1183 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1184 void pci_dev_put(struct pci_dev *dev); 1185 DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T)) 1186 void pci_remove_bus(struct pci_bus *b); 1187 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1188 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1189 void pci_stop_root_bus(struct pci_bus *bus); 1190 void pci_remove_root_bus(struct pci_bus *bus); 1191 void pci_setup_cardbus(struct pci_bus *bus); 1192 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1193 void pci_sort_breadthfirst(void); 1194 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1195 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1196 1197 /* Generic PCI functions exported to card drivers */ 1198 1199 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1200 u8 pci_find_capability(struct pci_dev *dev, int cap); 1201 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1202 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1203 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1204 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1205 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1206 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1207 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1208 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1209 1210 u64 pci_get_dsn(struct pci_dev *dev); 1211 1212 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1213 struct pci_dev *from); 1214 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1215 unsigned int ss_vendor, unsigned int ss_device, 1216 struct pci_dev *from); 1217 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1218 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1219 unsigned int devfn); 1220 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1221 struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); 1222 1223 int pci_dev_present(const struct pci_device_id *ids); 1224 1225 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1226 int where, u8 *val); 1227 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1228 int where, u16 *val); 1229 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1230 int where, u32 *val); 1231 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1232 int where, u8 val); 1233 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1234 int where, u16 val); 1235 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1236 int where, u32 val); 1237 1238 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1239 int where, int size, u32 *val); 1240 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1241 int where, int size, u32 val); 1242 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1243 int where, int size, u32 *val); 1244 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1245 int where, int size, u32 val); 1246 1247 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1248 1249 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1250 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1251 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1252 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1253 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1254 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1255 void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos, 1256 u32 clear, u32 set); 1257 1258 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1259 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1260 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1261 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1262 int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, 1263 u16 clear, u16 set); 1264 int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos, 1265 u16 clear, u16 set); 1266 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1267 u32 clear, u32 set); 1268 1269 /** 1270 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers 1271 * @dev: PCI device structure of the PCI Express device 1272 * @pos: PCI Express Capability Register 1273 * @clear: Clear bitmask 1274 * @set: Set bitmask 1275 * 1276 * Perform a Read-Modify-Write (RMW) operation using @clear and @set 1277 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express 1278 * Capability Registers are accessed concurrently in RMW fashion, hence 1279 * require locking which is handled transparently to the caller. 1280 */ 1281 static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, 1282 int pos, 1283 u16 clear, u16 set) 1284 { 1285 switch (pos) { 1286 case PCI_EXP_LNKCTL: 1287 case PCI_EXP_LNKCTL2: 1288 case PCI_EXP_RTCTL: 1289 return pcie_capability_clear_and_set_word_locked(dev, pos, 1290 clear, set); 1291 default: 1292 return pcie_capability_clear_and_set_word_unlocked(dev, pos, 1293 clear, set); 1294 } 1295 } 1296 1297 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1298 u16 set) 1299 { 1300 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1301 } 1302 1303 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1304 u32 set) 1305 { 1306 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1307 } 1308 1309 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1310 u16 clear) 1311 { 1312 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1313 } 1314 1315 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1316 u32 clear) 1317 { 1318 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1319 } 1320 1321 /* User-space driven config access */ 1322 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1323 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1324 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1325 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1326 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1327 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1328 1329 int __must_check pci_enable_device(struct pci_dev *dev); 1330 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1331 int __must_check pci_reenable_device(struct pci_dev *); 1332 int __must_check pcim_enable_device(struct pci_dev *pdev); 1333 void pcim_pin_device(struct pci_dev *pdev); 1334 1335 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1336 { 1337 /* 1338 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1339 * writable and no quirk has marked the feature broken. 1340 */ 1341 return !pdev->broken_intx_masking; 1342 } 1343 1344 static inline int pci_is_enabled(struct pci_dev *pdev) 1345 { 1346 return (atomic_read(&pdev->enable_cnt) > 0); 1347 } 1348 1349 static inline int pci_is_managed(struct pci_dev *pdev) 1350 { 1351 return pdev->is_managed; 1352 } 1353 1354 void pci_disable_device(struct pci_dev *dev); 1355 1356 extern unsigned int pcibios_max_latency; 1357 void pci_set_master(struct pci_dev *dev); 1358 void pci_clear_master(struct pci_dev *dev); 1359 1360 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1361 int pci_set_cacheline_size(struct pci_dev *dev); 1362 int __must_check pci_set_mwi(struct pci_dev *dev); 1363 int __must_check pcim_set_mwi(struct pci_dev *dev); 1364 int pci_try_set_mwi(struct pci_dev *dev); 1365 void pci_clear_mwi(struct pci_dev *dev); 1366 void pci_disable_parity(struct pci_dev *dev); 1367 void pci_intx(struct pci_dev *dev, int enable); 1368 bool pci_check_and_mask_intx(struct pci_dev *dev); 1369 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1370 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1371 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1372 int pcix_get_max_mmrbc(struct pci_dev *dev); 1373 int pcix_get_mmrbc(struct pci_dev *dev); 1374 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1375 int pcie_get_readrq(struct pci_dev *dev); 1376 int pcie_set_readrq(struct pci_dev *dev, int rq); 1377 int pcie_get_mps(struct pci_dev *dev); 1378 int pcie_set_mps(struct pci_dev *dev, int mps); 1379 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1380 enum pci_bus_speed *speed, 1381 enum pcie_link_width *width); 1382 int pcie_link_speed_mbps(struct pci_dev *pdev); 1383 void pcie_print_link_status(struct pci_dev *dev); 1384 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1385 int pcie_flr(struct pci_dev *dev); 1386 int __pci_reset_function_locked(struct pci_dev *dev); 1387 int pci_reset_function(struct pci_dev *dev); 1388 int pci_reset_function_locked(struct pci_dev *dev); 1389 int pci_try_reset_function(struct pci_dev *dev); 1390 int pci_probe_reset_slot(struct pci_slot *slot); 1391 int pci_probe_reset_bus(struct pci_bus *bus); 1392 int pci_reset_bus(struct pci_dev *dev); 1393 void pci_reset_secondary_bus(struct pci_dev *dev); 1394 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1395 void pci_update_resource(struct pci_dev *dev, int resno); 1396 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1397 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1398 void pci_release_resource(struct pci_dev *dev, int resno); 1399 static inline int pci_rebar_bytes_to_size(u64 bytes) 1400 { 1401 bytes = roundup_pow_of_two(bytes); 1402 1403 /* Return BAR size as defined in the resizable BAR specification */ 1404 return max(ilog2(bytes), 20) - 20; 1405 } 1406 1407 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1408 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1409 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1410 bool pci_device_is_present(struct pci_dev *pdev); 1411 void pci_ignore_hotplug(struct pci_dev *dev); 1412 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1413 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1414 1415 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1416 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1417 const char *fmt, ...); 1418 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1419 1420 /* ROM control related routines */ 1421 int pci_enable_rom(struct pci_dev *pdev); 1422 void pci_disable_rom(struct pci_dev *pdev); 1423 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1424 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1425 1426 /* Power management related routines */ 1427 int pci_save_state(struct pci_dev *dev); 1428 void pci_restore_state(struct pci_dev *dev); 1429 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1430 int pci_load_saved_state(struct pci_dev *dev, 1431 struct pci_saved_state *state); 1432 int pci_load_and_free_saved_state(struct pci_dev *dev, 1433 struct pci_saved_state **state); 1434 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1435 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1436 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state); 1437 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1438 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1439 void pci_pme_active(struct pci_dev *dev, bool enable); 1440 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1441 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1442 int pci_prepare_to_sleep(struct pci_dev *dev); 1443 int pci_back_from_sleep(struct pci_dev *dev); 1444 bool pci_dev_run_wake(struct pci_dev *dev); 1445 void pci_d3cold_enable(struct pci_dev *dev); 1446 void pci_d3cold_disable(struct pci_dev *dev); 1447 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1448 void pci_resume_bus(struct pci_bus *bus); 1449 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1450 1451 /* For use by arch with custom probe code */ 1452 void set_pcie_port_type(struct pci_dev *pdev); 1453 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1454 1455 /* Functions for PCI Hotplug drivers to use */ 1456 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1457 unsigned int pci_rescan_bus(struct pci_bus *bus); 1458 void pci_lock_rescan_remove(void); 1459 void pci_unlock_rescan_remove(void); 1460 1461 /* Vital Product Data routines */ 1462 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1463 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1464 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1465 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1466 1467 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1468 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1469 void pci_bus_assign_resources(const struct pci_bus *bus); 1470 void pci_bus_claim_resources(struct pci_bus *bus); 1471 void pci_bus_size_bridges(struct pci_bus *bus); 1472 int pci_claim_resource(struct pci_dev *, int); 1473 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1474 void pci_assign_unassigned_resources(void); 1475 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1476 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1477 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1478 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1479 int pci_enable_resources(struct pci_dev *, int mask); 1480 void pci_assign_irq(struct pci_dev *dev); 1481 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1482 #define HAVE_PCI_REQ_REGIONS 2 1483 int __must_check pci_request_regions(struct pci_dev *, const char *); 1484 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1485 void pci_release_regions(struct pci_dev *); 1486 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1487 void pci_release_region(struct pci_dev *, int); 1488 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1489 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1490 void pci_release_selected_regions(struct pci_dev *, int); 1491 1492 static inline __must_check struct resource * 1493 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, 1494 unsigned int len, const char *name) 1495 { 1496 return __request_region(&pdev->driver_exclusive_resource, offset, len, 1497 name, IORESOURCE_EXCLUSIVE); 1498 } 1499 1500 static inline void pci_release_config_region(struct pci_dev *pdev, 1501 unsigned int offset, 1502 unsigned int len) 1503 { 1504 __release_region(&pdev->driver_exclusive_resource, offset, len); 1505 } 1506 1507 /* drivers/pci/bus.c */ 1508 void pci_add_resource(struct list_head *resources, struct resource *res); 1509 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1510 resource_size_t offset); 1511 void pci_free_resource_list(struct list_head *resources); 1512 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res); 1513 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1514 void pci_bus_remove_resources(struct pci_bus *bus); 1515 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res); 1516 int devm_request_pci_bus_resources(struct device *dev, 1517 struct list_head *resources); 1518 1519 /* Temporary until new and working PCI SBR API in place */ 1520 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1521 1522 #define __pci_bus_for_each_res0(bus, res, ...) \ 1523 for (unsigned int __b = 0; \ 1524 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1525 __b++) 1526 1527 #define __pci_bus_for_each_res1(bus, res, __b) \ 1528 for (__b = 0; \ 1529 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1530 __b++) 1531 1532 /** 1533 * pci_bus_for_each_resource - iterate over PCI bus resources 1534 * @bus: the PCI bus 1535 * @res: pointer to the current resource 1536 * @...: optional index of the current resource 1537 * 1538 * Iterate over PCI bus resources. The first part is to go over PCI bus 1539 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries. 1540 * After that continue with the separate list of the additional resources, 1541 * if not empty. That's why the Logical OR is being used. 1542 * 1543 * Possible usage: 1544 * 1545 * struct pci_bus *bus = ...; 1546 * struct resource *res; 1547 * unsigned int i; 1548 * 1549 * // With optional index 1550 * pci_bus_for_each_resource(bus, res, i) 1551 * pr_info("PCI bus resource[%u]: %pR\n", i, res); 1552 * 1553 * // Without index 1554 * pci_bus_for_each_resource(bus, res) 1555 * _do_something_(res); 1556 */ 1557 #define pci_bus_for_each_resource(bus, res, ...) \ 1558 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 1559 (bus, res, __VA_ARGS__) 1560 1561 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1562 struct resource *res, resource_size_t size, 1563 resource_size_t align, resource_size_t min, 1564 unsigned long type_mask, 1565 resource_alignf alignf, 1566 void *alignf_data); 1567 1568 1569 int pci_register_io_range(const struct fwnode_handle *fwnode, phys_addr_t addr, 1570 resource_size_t size); 1571 unsigned long pci_address_to_pio(phys_addr_t addr); 1572 phys_addr_t pci_pio_to_address(unsigned long pio); 1573 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1574 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1575 phys_addr_t phys_addr); 1576 void pci_unmap_iospace(struct resource *res); 1577 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1578 resource_size_t offset, 1579 resource_size_t size); 1580 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1581 struct resource *res); 1582 1583 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1584 { 1585 struct pci_bus_region region; 1586 1587 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1588 return region.start; 1589 } 1590 1591 /* Proper probing supporting hot-pluggable devices */ 1592 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1593 const char *mod_name); 1594 1595 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1596 #define pci_register_driver(driver) \ 1597 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1598 1599 void pci_unregister_driver(struct pci_driver *dev); 1600 1601 /** 1602 * module_pci_driver() - Helper macro for registering a PCI driver 1603 * @__pci_driver: pci_driver struct 1604 * 1605 * Helper macro for PCI drivers which do not do anything special in module 1606 * init/exit. This eliminates a lot of boilerplate. Each module may only 1607 * use this macro once, and calling it replaces module_init() and module_exit() 1608 */ 1609 #define module_pci_driver(__pci_driver) \ 1610 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1611 1612 /** 1613 * builtin_pci_driver() - Helper macro for registering a PCI driver 1614 * @__pci_driver: pci_driver struct 1615 * 1616 * Helper macro for PCI drivers which do not do anything special in their 1617 * init code. This eliminates a lot of boilerplate. Each driver may only 1618 * use this macro once, and calling it replaces device_initcall(...) 1619 */ 1620 #define builtin_pci_driver(__pci_driver) \ 1621 builtin_driver(__pci_driver, pci_register_driver) 1622 1623 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1624 int pci_add_dynid(struct pci_driver *drv, 1625 unsigned int vendor, unsigned int device, 1626 unsigned int subvendor, unsigned int subdevice, 1627 unsigned int class, unsigned int class_mask, 1628 unsigned long driver_data); 1629 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1630 struct pci_dev *dev); 1631 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1632 int pass); 1633 1634 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1635 void *userdata); 1636 int pci_cfg_space_size(struct pci_dev *dev); 1637 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1638 void pci_setup_bridge(struct pci_bus *bus); 1639 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1640 unsigned long type); 1641 1642 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1643 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1644 1645 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1646 unsigned int command_bits, u32 flags); 1647 1648 /* 1649 * Virtual interrupts allow for more interrupts to be allocated 1650 * than the device has interrupts for. These are not programmed 1651 * into the device's MSI-X table and must be handled by some 1652 * other driver means. 1653 */ 1654 #define PCI_IRQ_VIRTUAL (1 << 4) 1655 1656 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1657 1658 #include <linux/dmapool.h> 1659 1660 struct msix_entry { 1661 u32 vector; /* Kernel uses to write allocated vector */ 1662 u16 entry; /* Driver uses to specify entry, OS writes */ 1663 }; 1664 1665 #ifdef CONFIG_PCI_MSI 1666 int pci_msi_vec_count(struct pci_dev *dev); 1667 void pci_disable_msi(struct pci_dev *dev); 1668 int pci_msix_vec_count(struct pci_dev *dev); 1669 void pci_disable_msix(struct pci_dev *dev); 1670 void pci_restore_msi_state(struct pci_dev *dev); 1671 int pci_msi_enabled(void); 1672 int pci_enable_msi(struct pci_dev *dev); 1673 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1674 int minvec, int maxvec); 1675 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1676 struct msix_entry *entries, int nvec) 1677 { 1678 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1679 if (rc < 0) 1680 return rc; 1681 return 0; 1682 } 1683 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1684 unsigned int max_vecs, unsigned int flags); 1685 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1686 unsigned int max_vecs, unsigned int flags, 1687 struct irq_affinity *affd); 1688 1689 bool pci_msix_can_alloc_dyn(struct pci_dev *dev); 1690 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1691 const struct irq_affinity_desc *affdesc); 1692 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); 1693 1694 void pci_free_irq_vectors(struct pci_dev *dev); 1695 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1696 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1697 1698 #else 1699 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1700 static inline void pci_disable_msi(struct pci_dev *dev) { } 1701 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1702 static inline void pci_disable_msix(struct pci_dev *dev) { } 1703 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1704 static inline int pci_msi_enabled(void) { return 0; } 1705 static inline int pci_enable_msi(struct pci_dev *dev) 1706 { return -ENOSYS; } 1707 static inline int pci_enable_msix_range(struct pci_dev *dev, 1708 struct msix_entry *entries, int minvec, int maxvec) 1709 { return -ENOSYS; } 1710 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1711 struct msix_entry *entries, int nvec) 1712 { return -ENOSYS; } 1713 1714 static inline int 1715 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1716 unsigned int max_vecs, unsigned int flags, 1717 struct irq_affinity *aff_desc) 1718 { 1719 if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq) 1720 return 1; 1721 return -ENOSPC; 1722 } 1723 static inline int 1724 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1725 unsigned int max_vecs, unsigned int flags) 1726 { 1727 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, 1728 flags, NULL); 1729 } 1730 1731 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev) 1732 { return false; } 1733 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1734 const struct irq_affinity_desc *affdesc) 1735 { 1736 struct msi_map map = { .index = -ENOSYS, }; 1737 1738 return map; 1739 } 1740 1741 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map) 1742 { 1743 } 1744 1745 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1746 { 1747 } 1748 1749 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1750 { 1751 if (WARN_ON_ONCE(nr > 0)) 1752 return -EINVAL; 1753 return dev->irq; 1754 } 1755 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1756 int vec) 1757 { 1758 return cpu_possible_mask; 1759 } 1760 #endif 1761 1762 /** 1763 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1764 * @d: the INTx IRQ domain 1765 * @node: the DT node for the device whose interrupt we're translating 1766 * @intspec: the interrupt specifier data from the DT 1767 * @intsize: the number of entries in @intspec 1768 * @out_hwirq: pointer at which to write the hwirq number 1769 * @out_type: pointer at which to write the interrupt type 1770 * 1771 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1772 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1773 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1774 * INTx value to obtain the hwirq number. 1775 * 1776 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1777 */ 1778 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1779 struct device_node *node, 1780 const u32 *intspec, 1781 unsigned int intsize, 1782 unsigned long *out_hwirq, 1783 unsigned int *out_type) 1784 { 1785 const u32 intx = intspec[0]; 1786 1787 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1788 return -EINVAL; 1789 1790 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1791 return 0; 1792 } 1793 1794 #ifdef CONFIG_PCIEPORTBUS 1795 extern bool pcie_ports_disabled; 1796 extern bool pcie_ports_native; 1797 1798 int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_req, 1799 bool use_lt); 1800 #else 1801 #define pcie_ports_disabled true 1802 #define pcie_ports_native false 1803 1804 static inline int pcie_set_target_speed(struct pci_dev *port, 1805 enum pci_bus_speed speed_req, 1806 bool use_lt) 1807 { 1808 return -EOPNOTSUPP; 1809 } 1810 #endif 1811 1812 #define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */ 1813 #define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */ 1814 #define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */ 1815 #define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */ 1816 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */ 1817 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */ 1818 #define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\ 1819 PCIE_LINK_STATE_L1 |\ 1820 PCIE_LINK_STATE_L1_1 |\ 1821 PCIE_LINK_STATE_L1_2 |\ 1822 PCIE_LINK_STATE_L1_1_PCIPM |\ 1823 PCIE_LINK_STATE_L1_2_PCIPM) 1824 #define PCIE_LINK_STATE_CLKPM BIT(7) 1825 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\ 1826 PCIE_LINK_STATE_CLKPM) 1827 1828 #ifdef CONFIG_PCIEASPM 1829 int pci_disable_link_state(struct pci_dev *pdev, int state); 1830 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1831 int pci_enable_link_state(struct pci_dev *pdev, int state); 1832 int pci_enable_link_state_locked(struct pci_dev *pdev, int state); 1833 void pcie_no_aspm(void); 1834 bool pcie_aspm_support_enabled(void); 1835 bool pcie_aspm_enabled(struct pci_dev *pdev); 1836 #else 1837 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1838 { return 0; } 1839 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1840 { return 0; } 1841 static inline int pci_enable_link_state(struct pci_dev *pdev, int state) 1842 { return 0; } 1843 static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) 1844 { return 0; } 1845 static inline void pcie_no_aspm(void) { } 1846 static inline bool pcie_aspm_support_enabled(void) { return false; } 1847 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1848 #endif 1849 1850 #ifdef CONFIG_PCIEAER 1851 bool pci_aer_available(void); 1852 #else 1853 static inline bool pci_aer_available(void) { return false; } 1854 #endif 1855 1856 bool pci_ats_disabled(void); 1857 1858 #ifdef CONFIG_PCIE_PTM 1859 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1860 void pci_disable_ptm(struct pci_dev *dev); 1861 bool pcie_ptm_enabled(struct pci_dev *dev); 1862 #else 1863 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1864 { return -EINVAL; } 1865 static inline void pci_disable_ptm(struct pci_dev *dev) { } 1866 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1867 { return false; } 1868 #endif 1869 1870 void pci_cfg_access_lock(struct pci_dev *dev); 1871 bool pci_cfg_access_trylock(struct pci_dev *dev); 1872 void pci_cfg_access_unlock(struct pci_dev *dev); 1873 1874 void pci_dev_lock(struct pci_dev *dev); 1875 int pci_dev_trylock(struct pci_dev *dev); 1876 void pci_dev_unlock(struct pci_dev *dev); 1877 DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T)) 1878 1879 /* 1880 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1881 * a PCI domain is defined to be a set of PCI buses which share 1882 * configuration space. 1883 */ 1884 #ifdef CONFIG_PCI_DOMAINS 1885 extern int pci_domains_supported; 1886 #else 1887 enum { pci_domains_supported = 0 }; 1888 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1889 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1890 #endif /* CONFIG_PCI_DOMAINS */ 1891 1892 /* 1893 * Generic implementation for PCI domain support. If your 1894 * architecture does not need custom management of PCI 1895 * domains then this implementation will be used 1896 */ 1897 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1898 static inline int pci_domain_nr(struct pci_bus *bus) 1899 { 1900 return bus->domain_nr; 1901 } 1902 #ifdef CONFIG_ACPI 1903 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1904 #else 1905 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1906 { return 0; } 1907 #endif 1908 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1909 void pci_bus_release_domain_nr(struct device *parent, int domain_nr); 1910 #endif 1911 1912 /* Some architectures require additional setup to direct VGA traffic */ 1913 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1914 unsigned int command_bits, u32 flags); 1915 void pci_register_set_vga_state(arch_set_vga_state_t func); 1916 1917 static inline int 1918 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1919 { 1920 return pci_request_selected_regions(pdev, 1921 pci_select_bars(pdev, IORESOURCE_IO), name); 1922 } 1923 1924 static inline void 1925 pci_release_io_regions(struct pci_dev *pdev) 1926 { 1927 return pci_release_selected_regions(pdev, 1928 pci_select_bars(pdev, IORESOURCE_IO)); 1929 } 1930 1931 static inline int 1932 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1933 { 1934 return pci_request_selected_regions(pdev, 1935 pci_select_bars(pdev, IORESOURCE_MEM), name); 1936 } 1937 1938 static inline void 1939 pci_release_mem_regions(struct pci_dev *pdev) 1940 { 1941 return pci_release_selected_regions(pdev, 1942 pci_select_bars(pdev, IORESOURCE_MEM)); 1943 } 1944 1945 #else /* CONFIG_PCI is not enabled */ 1946 1947 static inline void pci_set_flags(int flags) { } 1948 static inline void pci_add_flags(int flags) { } 1949 static inline void pci_clear_flags(int flags) { } 1950 static inline int pci_has_flag(int flag) { return 0; } 1951 1952 /* 1953 * If the system does not have PCI, clearly these return errors. Define 1954 * these as simple inline functions to avoid hair in drivers. 1955 */ 1956 #define _PCI_NOP(o, s, t) \ 1957 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1958 int where, t val) \ 1959 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1960 1961 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1962 _PCI_NOP(o, word, u16 x) \ 1963 _PCI_NOP(o, dword, u32 x) 1964 _PCI_NOP_ALL(read, *) 1965 _PCI_NOP_ALL(write,) 1966 1967 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1968 unsigned int device, 1969 struct pci_dev *from) 1970 { return NULL; } 1971 1972 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1973 unsigned int device, 1974 unsigned int ss_vendor, 1975 unsigned int ss_device, 1976 struct pci_dev *from) 1977 { return NULL; } 1978 1979 static inline struct pci_dev *pci_get_class(unsigned int class, 1980 struct pci_dev *from) 1981 { return NULL; } 1982 1983 static inline struct pci_dev *pci_get_base_class(unsigned int class, 1984 struct pci_dev *from) 1985 { return NULL; } 1986 1987 static inline int pci_dev_present(const struct pci_device_id *ids) 1988 { return 0; } 1989 1990 #define no_pci_devices() (1) 1991 #define pci_dev_put(dev) do { } while (0) 1992 1993 static inline void pci_set_master(struct pci_dev *dev) { } 1994 static inline void pci_clear_master(struct pci_dev *dev) { } 1995 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1996 static inline void pci_disable_device(struct pci_dev *dev) { } 1997 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1998 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1999 { return -EBUSY; } 2000 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 2001 struct module *owner, 2002 const char *mod_name) 2003 { return 0; } 2004 static inline int pci_register_driver(struct pci_driver *drv) 2005 { return 0; } 2006 static inline void pci_unregister_driver(struct pci_driver *drv) { } 2007 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 2008 { return 0; } 2009 static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap) 2010 { return 0; } 2011 static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap) 2012 { return 0; } 2013 2014 static inline u64 pci_get_dsn(struct pci_dev *dev) 2015 { return 0; } 2016 2017 /* Power management related routines */ 2018 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 2019 static inline void pci_restore_state(struct pci_dev *dev) { } 2020 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 2021 { return 0; } 2022 static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state) 2023 { return 0; } 2024 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 2025 { return 0; } 2026 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 2027 pm_message_t state) 2028 { return PCI_D0; } 2029 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 2030 int enable) 2031 { return 0; } 2032 2033 static inline struct resource *pci_find_resource(struct pci_dev *dev, 2034 struct resource *res) 2035 { return NULL; } 2036 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 2037 { return -EIO; } 2038 static inline void pci_release_regions(struct pci_dev *dev) { } 2039 2040 static inline int pci_register_io_range(const struct fwnode_handle *fwnode, 2041 phys_addr_t addr, resource_size_t size) 2042 { return -EINVAL; } 2043 2044 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 2045 2046 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 2047 { return NULL; } 2048 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 2049 unsigned int devfn) 2050 { return NULL; } 2051 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 2052 unsigned int bus, unsigned int devfn) 2053 { return NULL; } 2054 2055 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2056 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 2057 2058 #define dev_is_pci(d) (false) 2059 #define dev_is_pf(d) (false) 2060 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2061 { return false; } 2062 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 2063 struct device_node *node, 2064 const u32 *intspec, 2065 unsigned int intsize, 2066 unsigned long *out_hwirq, 2067 unsigned int *out_type) 2068 { return -EINVAL; } 2069 2070 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 2071 struct pci_dev *dev) 2072 { return NULL; } 2073 static inline bool pci_ats_disabled(void) { return true; } 2074 2075 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 2076 { 2077 return -EINVAL; 2078 } 2079 2080 static inline int 2081 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 2082 unsigned int max_vecs, unsigned int flags, 2083 struct irq_affinity *aff_desc) 2084 { 2085 return -ENOSPC; 2086 } 2087 static inline int 2088 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 2089 unsigned int max_vecs, unsigned int flags) 2090 { 2091 return -ENOSPC; 2092 } 2093 #endif /* CONFIG_PCI */ 2094 2095 /* Include architecture-dependent settings and functions */ 2096 2097 #include <asm/pci.h> 2098 2099 /* 2100 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 2101 * is expected to be an offset within that region. 2102 * 2103 */ 2104 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 2105 struct vm_area_struct *vma, 2106 enum pci_mmap_state mmap_state, int write_combine); 2107 2108 #ifndef arch_can_pci_mmap_wc 2109 #define arch_can_pci_mmap_wc() 0 2110 #endif 2111 2112 #ifndef arch_can_pci_mmap_io 2113 #define arch_can_pci_mmap_io() 0 2114 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 2115 #else 2116 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 2117 #endif 2118 2119 #ifndef pci_root_bus_fwnode 2120 #define pci_root_bus_fwnode(bus) NULL 2121 #endif 2122 2123 /* 2124 * These helpers provide future and backwards compatibility 2125 * for accessing popular PCI BAR info 2126 */ 2127 #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)]) 2128 #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start) 2129 #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end) 2130 #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags) 2131 #define pci_resource_len(dev,bar) \ 2132 (pci_resource_end((dev), (bar)) ? \ 2133 resource_size(pci_resource_n((dev), (bar))) : 0) 2134 2135 #define __pci_dev_for_each_res0(dev, res, ...) \ 2136 for (unsigned int __b = 0; \ 2137 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2138 __b++) 2139 2140 #define __pci_dev_for_each_res1(dev, res, __b) \ 2141 for (__b = 0; \ 2142 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2143 __b++) 2144 2145 #define pci_dev_for_each_resource(dev, res, ...) \ 2146 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 2147 (dev, res, __VA_ARGS__) 2148 2149 /* 2150 * Similar to the helpers above, these manipulate per-pci_dev 2151 * driver-specific data. They are really just a wrapper around 2152 * the generic device structure functions of these calls. 2153 */ 2154 static inline void *pci_get_drvdata(struct pci_dev *pdev) 2155 { 2156 return dev_get_drvdata(&pdev->dev); 2157 } 2158 2159 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 2160 { 2161 dev_set_drvdata(&pdev->dev, data); 2162 } 2163 2164 static inline const char *pci_name(const struct pci_dev *pdev) 2165 { 2166 return dev_name(&pdev->dev); 2167 } 2168 2169 void pci_resource_to_user(const struct pci_dev *dev, int bar, 2170 const struct resource *rsrc, 2171 resource_size_t *start, resource_size_t *end); 2172 2173 /* 2174 * The world is not perfect and supplies us with broken PCI devices. 2175 * For at least a part of these bugs we need a work-around, so both 2176 * generic (drivers/pci/quirks.c) and per-architecture code can define 2177 * fixup hooks to be called for particular buggy devices. 2178 */ 2179 2180 struct pci_fixup { 2181 u16 vendor; /* Or PCI_ANY_ID */ 2182 u16 device; /* Or PCI_ANY_ID */ 2183 u32 class; /* Or PCI_ANY_ID */ 2184 unsigned int class_shift; /* should be 0, 8, 16 */ 2185 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2186 int hook_offset; 2187 #else 2188 void (*hook)(struct pci_dev *dev); 2189 #endif 2190 }; 2191 2192 enum pci_fixup_pass { 2193 pci_fixup_early, /* Before probing BARs */ 2194 pci_fixup_header, /* After reading configuration header */ 2195 pci_fixup_final, /* Final phase of device fixups */ 2196 pci_fixup_enable, /* pci_enable_device() time */ 2197 pci_fixup_resume, /* pci_device_resume() */ 2198 pci_fixup_suspend, /* pci_device_suspend() */ 2199 pci_fixup_resume_early, /* pci_device_resume_early() */ 2200 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2201 }; 2202 2203 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2204 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2205 class_shift, hook) \ 2206 __ADDRESSABLE(hook) \ 2207 asm(".section " #sec ", \"a\" \n" \ 2208 ".balign 16 \n" \ 2209 ".short " #vendor ", " #device " \n" \ 2210 ".long " #class ", " #class_shift " \n" \ 2211 ".long " #hook " - . \n" \ 2212 ".previous \n"); 2213 2214 /* 2215 * Clang's LTO may rename static functions in C, but has no way to 2216 * handle such renamings when referenced from inline asm. To work 2217 * around this, create global C stubs for these cases. 2218 */ 2219 #ifdef CONFIG_LTO_CLANG 2220 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2221 class_shift, hook, stub) \ 2222 void stub(struct pci_dev *dev); \ 2223 void stub(struct pci_dev *dev) \ 2224 { \ 2225 hook(dev); \ 2226 } \ 2227 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2228 class_shift, stub) 2229 #else 2230 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2231 class_shift, hook, stub) \ 2232 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2233 class_shift, hook) 2234 #endif 2235 2236 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2237 class_shift, hook) \ 2238 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2239 class_shift, hook, __UNIQUE_ID(hook)) 2240 #else 2241 /* Anonymous variables would be nice... */ 2242 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2243 class_shift, hook) \ 2244 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2245 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2246 = { vendor, device, class, class_shift, hook }; 2247 #endif 2248 2249 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2250 class_shift, hook) \ 2251 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2252 hook, vendor, device, class, class_shift, hook) 2253 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2254 class_shift, hook) \ 2255 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2256 hook, vendor, device, class, class_shift, hook) 2257 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2258 class_shift, hook) \ 2259 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2260 hook, vendor, device, class, class_shift, hook) 2261 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2262 class_shift, hook) \ 2263 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2264 hook, vendor, device, class, class_shift, hook) 2265 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2266 class_shift, hook) \ 2267 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2268 resume##hook, vendor, device, class, class_shift, hook) 2269 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2270 class_shift, hook) \ 2271 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2272 resume_early##hook, vendor, device, class, class_shift, hook) 2273 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2274 class_shift, hook) \ 2275 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2276 suspend##hook, vendor, device, class, class_shift, hook) 2277 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2278 class_shift, hook) \ 2279 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2280 suspend_late##hook, vendor, device, class, class_shift, hook) 2281 2282 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2283 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2284 hook, vendor, device, PCI_ANY_ID, 0, hook) 2285 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2286 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2287 hook, vendor, device, PCI_ANY_ID, 0, hook) 2288 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2289 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2290 hook, vendor, device, PCI_ANY_ID, 0, hook) 2291 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2292 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2293 hook, vendor, device, PCI_ANY_ID, 0, hook) 2294 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2295 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2296 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2297 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2298 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2299 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2300 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2301 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2302 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2303 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2304 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2305 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2306 2307 #ifdef CONFIG_PCI_QUIRKS 2308 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2309 #else 2310 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2311 struct pci_dev *dev) { } 2312 #endif 2313 2314 int pcim_request_all_regions(struct pci_dev *pdev, const char *name); 2315 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2316 void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar, 2317 const char *name); 2318 void pcim_iounmap_region(struct pci_dev *pdev, int bar); 2319 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2320 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2321 int pcim_request_region(struct pci_dev *pdev, int bar, const char *name); 2322 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2323 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2324 void __iomem *pcim_iomap_range(struct pci_dev *pdev, int bar, 2325 unsigned long offset, unsigned long len); 2326 2327 extern int pci_pci_problems; 2328 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2329 #define PCIPCI_TRITON 2 2330 #define PCIPCI_NATOMA 4 2331 #define PCIPCI_VIAETBF 8 2332 #define PCIPCI_VSFX 16 2333 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2334 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2335 2336 extern unsigned long pci_cardbus_io_size; 2337 extern unsigned long pci_cardbus_mem_size; 2338 extern u8 pci_dfl_cache_line_size; 2339 extern u8 pci_cache_line_size; 2340 2341 /* Architecture-specific versions may override these (weak) */ 2342 void pcibios_disable_device(struct pci_dev *dev); 2343 void pcibios_set_master(struct pci_dev *dev); 2344 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2345 enum pcie_reset_state state); 2346 int pcibios_device_add(struct pci_dev *dev); 2347 void pcibios_release_device(struct pci_dev *dev); 2348 #ifdef CONFIG_PCI 2349 void pcibios_penalize_isa_irq(int irq, int active); 2350 #else 2351 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2352 #endif 2353 int pcibios_alloc_irq(struct pci_dev *dev); 2354 void pcibios_free_irq(struct pci_dev *dev); 2355 resource_size_t pcibios_default_alignment(void); 2356 2357 #if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE) 2358 extern int pci_create_resource_files(struct pci_dev *dev); 2359 extern void pci_remove_resource_files(struct pci_dev *dev); 2360 #endif 2361 2362 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2363 void __init pci_mmcfg_early_init(void); 2364 void __init pci_mmcfg_late_init(void); 2365 #else 2366 static inline void pci_mmcfg_early_init(void) { } 2367 static inline void pci_mmcfg_late_init(void) { } 2368 #endif 2369 2370 int pci_ext_cfg_avail(void); 2371 2372 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2373 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2374 2375 #ifdef CONFIG_PCI_IOV 2376 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2377 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2378 int pci_iov_vf_id(struct pci_dev *dev); 2379 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2380 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2381 void pci_disable_sriov(struct pci_dev *dev); 2382 2383 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2384 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2385 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2386 int pci_num_vf(struct pci_dev *dev); 2387 int pci_vfs_assigned(struct pci_dev *dev); 2388 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2389 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2390 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2391 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2392 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2393 2394 /* Arch may override these (weak) */ 2395 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2396 int pcibios_sriov_disable(struct pci_dev *pdev); 2397 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2398 #else 2399 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2400 { 2401 return -ENOSYS; 2402 } 2403 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2404 { 2405 return -ENOSYS; 2406 } 2407 2408 static inline int pci_iov_vf_id(struct pci_dev *dev) 2409 { 2410 return -ENOSYS; 2411 } 2412 2413 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2414 struct pci_driver *pf_driver) 2415 { 2416 return ERR_PTR(-EINVAL); 2417 } 2418 2419 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2420 { return -ENODEV; } 2421 2422 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2423 struct pci_dev *virtfn, int id) 2424 { 2425 return -ENODEV; 2426 } 2427 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2428 { 2429 return -ENOSYS; 2430 } 2431 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2432 int id) { } 2433 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2434 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2435 static inline int pci_vfs_assigned(struct pci_dev *dev) 2436 { return 0; } 2437 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2438 { return 0; } 2439 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2440 { return 0; } 2441 #define pci_sriov_configure_simple NULL 2442 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2443 { return 0; } 2444 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2445 #endif 2446 2447 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2448 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2449 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2450 #endif 2451 2452 /** 2453 * pci_pcie_cap - get the saved PCIe capability offset 2454 * @dev: PCI device 2455 * 2456 * PCIe capability offset is calculated at PCI device initialization 2457 * time and saved in the data structure. This function returns saved 2458 * PCIe capability offset. Using this instead of pci_find_capability() 2459 * reduces unnecessary search in the PCI configuration space. If you 2460 * need to calculate PCIe capability offset from raw device for some 2461 * reasons, please use pci_find_capability() instead. 2462 */ 2463 static inline int pci_pcie_cap(struct pci_dev *dev) 2464 { 2465 return dev->pcie_cap; 2466 } 2467 2468 /** 2469 * pci_is_pcie - check if the PCI device is PCI Express capable 2470 * @dev: PCI device 2471 * 2472 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2473 */ 2474 static inline bool pci_is_pcie(struct pci_dev *dev) 2475 { 2476 return pci_pcie_cap(dev); 2477 } 2478 2479 /** 2480 * pcie_caps_reg - get the PCIe Capabilities Register 2481 * @dev: PCI device 2482 */ 2483 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2484 { 2485 return dev->pcie_flags_reg; 2486 } 2487 2488 /** 2489 * pci_pcie_type - get the PCIe device/port type 2490 * @dev: PCI device 2491 */ 2492 static inline int pci_pcie_type(const struct pci_dev *dev) 2493 { 2494 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2495 } 2496 2497 /** 2498 * pcie_find_root_port - Get the PCIe root port device 2499 * @dev: PCI device 2500 * 2501 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2502 * for a given PCI/PCIe Device. 2503 */ 2504 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2505 { 2506 while (dev) { 2507 if (pci_is_pcie(dev) && 2508 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2509 return dev; 2510 dev = pci_upstream_bridge(dev); 2511 } 2512 2513 return NULL; 2514 } 2515 2516 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 2517 { 2518 /* 2519 * error_state is set in pci_dev_set_io_state() using xchg/cmpxchg() 2520 * and read w/o common lock. READ_ONCE() ensures compiler cannot cache 2521 * the value (e.g. inside the loop in pci_dev_wait()). 2522 */ 2523 return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure; 2524 } 2525 2526 void pci_request_acs(void); 2527 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2528 bool pci_acs_path_enabled(struct pci_dev *start, 2529 struct pci_dev *end, u16 acs_flags); 2530 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2531 2532 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2533 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2534 2535 /* Large Resource Data Type Tag Item Names */ 2536 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2537 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2538 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2539 2540 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2541 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2542 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2543 2544 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2545 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2546 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2547 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2548 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2549 2550 /** 2551 * pci_vpd_alloc - Allocate buffer and read VPD into it 2552 * @dev: PCI device 2553 * @size: pointer to field where VPD length is returned 2554 * 2555 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2556 */ 2557 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2558 2559 /** 2560 * pci_vpd_find_id_string - Locate id string in VPD 2561 * @buf: Pointer to buffered VPD data 2562 * @len: The length of the buffer area in which to search 2563 * @size: Pointer to field where length of id string is returned 2564 * 2565 * Returns the index of the id string or -ENOENT if not found. 2566 */ 2567 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2568 2569 /** 2570 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2571 * @buf: Pointer to buffered VPD data 2572 * @len: The length of the buffer area in which to search 2573 * @kw: The keyword to search for 2574 * @size: Pointer to field where length of found keyword data is returned 2575 * 2576 * Returns the index of the information field keyword data or -ENOENT if 2577 * not found. 2578 */ 2579 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2580 const char *kw, unsigned int *size); 2581 2582 /** 2583 * pci_vpd_check_csum - Check VPD checksum 2584 * @buf: Pointer to buffered VPD data 2585 * @len: VPD size 2586 * 2587 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2588 */ 2589 int pci_vpd_check_csum(const void *buf, unsigned int len); 2590 2591 /* PCI <-> OF binding helpers */ 2592 #ifdef CONFIG_OF 2593 struct device_node; 2594 struct irq_domain; 2595 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2596 bool pci_host_of_has_msi_map(struct device *dev); 2597 2598 /* Arch may override this (weak) */ 2599 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2600 2601 #else /* CONFIG_OF */ 2602 static inline struct irq_domain * 2603 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2604 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2605 #endif /* CONFIG_OF */ 2606 2607 static inline struct device_node * 2608 pci_device_to_OF_node(const struct pci_dev *pdev) 2609 { 2610 return pdev ? pdev->dev.of_node : NULL; 2611 } 2612 2613 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2614 { 2615 return bus ? bus->dev.of_node : NULL; 2616 } 2617 2618 #ifdef CONFIG_ACPI 2619 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2620 2621 void 2622 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2623 bool pci_pr3_present(struct pci_dev *pdev); 2624 #else 2625 static inline struct irq_domain * 2626 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2627 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2628 #endif 2629 2630 #if defined(CONFIG_X86) && defined(CONFIG_ACPI) 2631 bool arch_pci_dev_is_removable(struct pci_dev *pdev); 2632 #else 2633 static inline bool arch_pci_dev_is_removable(struct pci_dev *pdev) { return false; } 2634 #endif 2635 2636 #ifdef CONFIG_EEH 2637 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2638 { 2639 return pdev->dev.archdata.edev; 2640 } 2641 #endif 2642 2643 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2644 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2645 int pci_for_each_dma_alias(struct pci_dev *pdev, 2646 int (*fn)(struct pci_dev *pdev, 2647 u16 alias, void *data), void *data); 2648 2649 /* Helper functions for operation of device flag */ 2650 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2651 { 2652 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2653 } 2654 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2655 { 2656 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2657 } 2658 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2659 { 2660 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2661 } 2662 2663 /** 2664 * pci_ari_enabled - query ARI forwarding status 2665 * @bus: the PCI bus 2666 * 2667 * Returns true if ARI forwarding is enabled. 2668 */ 2669 static inline bool pci_ari_enabled(struct pci_bus *bus) 2670 { 2671 return bus->self && bus->self->ari_enabled; 2672 } 2673 2674 /** 2675 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2676 * @pdev: PCI device to check 2677 * 2678 * Walk upwards from @pdev and check for each encountered bridge if it's part 2679 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2680 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2681 */ 2682 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2683 { 2684 struct pci_dev *parent = pdev; 2685 2686 if (pdev->is_thunderbolt) 2687 return true; 2688 2689 while ((parent = pci_upstream_bridge(parent))) 2690 if (parent->is_thunderbolt) 2691 return true; 2692 2693 return false; 2694 } 2695 2696 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2697 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2698 #endif 2699 2700 #include <linux/dma-mapping.h> 2701 2702 #define pci_printk(level, pdev, fmt, arg...) \ 2703 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2704 2705 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2706 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2707 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2708 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2709 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2710 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) 2711 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2712 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2713 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2714 2715 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2716 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2717 2718 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2719 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2720 2721 #define pci_WARN(pdev, condition, fmt, arg...) \ 2722 WARN(condition, "%s %s: " fmt, \ 2723 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2724 2725 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2726 WARN_ONCE(condition, "%s %s: " fmt, \ 2727 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2728 2729 #endif /* LINUX_PCI_H */ 2730