1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 46 PCI_STATUS_SIG_SYSTEM_ERROR | \ 47 PCI_STATUS_REC_MASTER_ABORT | \ 48 PCI_STATUS_REC_TARGET_ABORT | \ 49 PCI_STATUS_SIG_TARGET_ABORT | \ 50 PCI_STATUS_PARITY) 51 52 /* 53 * The PCI interface treats multi-function devices as independent 54 * devices. The slot/function address of each device is encoded 55 * in a single byte as follows: 56 * 57 * 7:3 = slot 58 * 2:0 = function 59 * 60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 61 * In the interest of not exposing interfaces to user-space unnecessarily, 62 * the following kernel-only defines are being added here. 63 */ 64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 67 68 /* pci_slot represents a physical slot */ 69 struct pci_slot { 70 struct pci_bus *bus; /* Bus this slot is on */ 71 struct list_head list; /* Node in list of slots */ 72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 74 struct kobject kobj; 75 }; 76 77 static inline const char *pci_slot_name(const struct pci_slot *slot) 78 { 79 return kobject_name(&slot->kobj); 80 } 81 82 /* File state for mmap()s on /proc/bus/pci/X/Y */ 83 enum pci_mmap_state { 84 pci_mmap_io, 85 pci_mmap_mem 86 }; 87 88 /* For PCI devices, the region numbers are assigned this way: */ 89 enum { 90 /* #0-5: standard PCI resources */ 91 PCI_STD_RESOURCES, 92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 93 94 /* #6: expansion ROM resource */ 95 PCI_ROM_RESOURCE, 96 97 /* Device-specific resources */ 98 #ifdef CONFIG_PCI_IOV 99 PCI_IOV_RESOURCES, 100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 101 #endif 102 103 /* PCI-to-PCI (P2P) bridge windows */ 104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 107 108 /* CardBus bridge windows */ 109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 113 114 /* Total number of bridge resources for P2P and CardBus */ 115 #define PCI_BRIDGE_RESOURCE_NUM 4 116 117 /* Resources assigned to buses behind the bridge */ 118 PCI_BRIDGE_RESOURCES, 119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 120 PCI_BRIDGE_RESOURCE_NUM - 1, 121 122 /* Total resources associated with a PCI device */ 123 PCI_NUM_RESOURCES, 124 125 /* Preserve this for compatibility */ 126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 127 }; 128 129 /** 130 * enum pci_interrupt_pin - PCI INTx interrupt values 131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 132 * @PCI_INTERRUPT_INTA: PCI INTA pin 133 * @PCI_INTERRUPT_INTB: PCI INTB pin 134 * @PCI_INTERRUPT_INTC: PCI INTC pin 135 * @PCI_INTERRUPT_INTD: PCI INTD pin 136 * 137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 138 * PCI_INTERRUPT_PIN register. 139 */ 140 enum pci_interrupt_pin { 141 PCI_INTERRUPT_UNKNOWN, 142 PCI_INTERRUPT_INTA, 143 PCI_INTERRUPT_INTB, 144 PCI_INTERRUPT_INTC, 145 PCI_INTERRUPT_INTD, 146 }; 147 148 /* The number of legacy PCI INTx interrupts */ 149 #define PCI_NUM_INTX 4 150 151 /* 152 * pci_power_t values must match the bits in the Capabilities PME_Support 153 * and Control/Status PowerState fields in the Power Management capability. 154 */ 155 typedef int __bitwise pci_power_t; 156 157 #define PCI_D0 ((pci_power_t __force) 0) 158 #define PCI_D1 ((pci_power_t __force) 1) 159 #define PCI_D2 ((pci_power_t __force) 2) 160 #define PCI_D3hot ((pci_power_t __force) 3) 161 #define PCI_D3cold ((pci_power_t __force) 4) 162 #define PCI_UNKNOWN ((pci_power_t __force) 5) 163 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 164 165 /* Remember to update this when the list above changes! */ 166 extern const char *pci_power_names[]; 167 168 static inline const char *pci_power_name(pci_power_t state) 169 { 170 return pci_power_names[1 + (__force int) state]; 171 } 172 173 /** 174 * typedef pci_channel_state_t 175 * 176 * The pci_channel state describes connectivity between the CPU and 177 * the PCI device. If some PCI bus between here and the PCI device 178 * has crashed or locked up, this info is reflected here. 179 */ 180 typedef unsigned int __bitwise pci_channel_state_t; 181 182 enum pci_channel_state { 183 /* I/O channel is in normal state */ 184 pci_channel_io_normal = (__force pci_channel_state_t) 1, 185 186 /* I/O to channel is blocked */ 187 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 188 189 /* PCI card is dead */ 190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 191 }; 192 193 typedef unsigned int __bitwise pcie_reset_state_t; 194 195 enum pcie_reset_state { 196 /* Reset is NOT asserted (Use to deassert reset) */ 197 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 198 199 /* Use #PERST to reset PCIe device */ 200 pcie_warm_reset = (__force pcie_reset_state_t) 2, 201 202 /* Use PCIe Hot Reset to reset device */ 203 pcie_hot_reset = (__force pcie_reset_state_t) 3 204 }; 205 206 typedef unsigned short __bitwise pci_dev_flags_t; 207 enum pci_dev_flags { 208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 210 /* Device configuration is irrevocably lost if disabled into D3 */ 211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 212 /* Provide indication device is assigned by a Virtual Machine Manager */ 213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 214 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 218 /* Do not use bus resets for device */ 219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 220 /* Do not use PM reset even if device advertises NoSoftRst- */ 221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 222 /* Get VPD from function 0 VPD */ 223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 224 /* A non-root bridge where translation occurs, stop alias search here */ 225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 226 /* Do not use FLR even if device advertises PCI_AF_CAP */ 227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 228 /* Don't use Relaxed Ordering for TLPs directed at this device */ 229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 230 }; 231 232 enum pci_irq_reroute_variant { 233 INTEL_IRQ_REROUTE_VARIANT = 1, 234 MAX_IRQ_REROUTE_VARIANTS = 3 235 }; 236 237 typedef unsigned short __bitwise pci_bus_flags_t; 238 enum pci_bus_flags { 239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 243 }; 244 245 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 246 enum pcie_link_width { 247 PCIE_LNK_WIDTH_RESRV = 0x00, 248 PCIE_LNK_X1 = 0x01, 249 PCIE_LNK_X2 = 0x02, 250 PCIE_LNK_X4 = 0x04, 251 PCIE_LNK_X8 = 0x08, 252 PCIE_LNK_X12 = 0x0c, 253 PCIE_LNK_X16 = 0x10, 254 PCIE_LNK_X32 = 0x20, 255 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 256 }; 257 258 /* See matching string table in pci_speed_string() */ 259 enum pci_bus_speed { 260 PCI_SPEED_33MHz = 0x00, 261 PCI_SPEED_66MHz = 0x01, 262 PCI_SPEED_66MHz_PCIX = 0x02, 263 PCI_SPEED_100MHz_PCIX = 0x03, 264 PCI_SPEED_133MHz_PCIX = 0x04, 265 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 266 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 267 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 268 PCI_SPEED_66MHz_PCIX_266 = 0x09, 269 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 270 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 271 AGP_UNKNOWN = 0x0c, 272 AGP_1X = 0x0d, 273 AGP_2X = 0x0e, 274 AGP_4X = 0x0f, 275 AGP_8X = 0x10, 276 PCI_SPEED_66MHz_PCIX_533 = 0x11, 277 PCI_SPEED_100MHz_PCIX_533 = 0x12, 278 PCI_SPEED_133MHz_PCIX_533 = 0x13, 279 PCIE_SPEED_2_5GT = 0x14, 280 PCIE_SPEED_5_0GT = 0x15, 281 PCIE_SPEED_8_0GT = 0x16, 282 PCIE_SPEED_16_0GT = 0x17, 283 PCIE_SPEED_32_0GT = 0x18, 284 PCI_SPEED_UNKNOWN = 0xff, 285 }; 286 287 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 288 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 289 290 struct pci_cap_saved_data { 291 u16 cap_nr; 292 bool cap_extended; 293 unsigned int size; 294 u32 data[]; 295 }; 296 297 struct pci_cap_saved_state { 298 struct hlist_node next; 299 struct pci_cap_saved_data cap; 300 }; 301 302 struct irq_affinity; 303 struct pcie_link_state; 304 struct pci_vpd; 305 struct pci_sriov; 306 struct pci_p2pdma; 307 308 /* The pci_dev structure describes PCI devices */ 309 struct pci_dev { 310 struct list_head bus_list; /* Node in per-bus list */ 311 struct pci_bus *bus; /* Bus this device is on */ 312 struct pci_bus *subordinate; /* Bus this device bridges to */ 313 314 void *sysdata; /* Hook for sys-specific extension */ 315 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 316 struct pci_slot *slot; /* Physical slot this device is in */ 317 318 unsigned int devfn; /* Encoded device & function index */ 319 unsigned short vendor; 320 unsigned short device; 321 unsigned short subsystem_vendor; 322 unsigned short subsystem_device; 323 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 324 u8 revision; /* PCI revision, low byte of class word */ 325 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 326 #ifdef CONFIG_PCIEAER 327 u16 aer_cap; /* AER capability offset */ 328 struct aer_stats *aer_stats; /* AER stats for this device */ 329 #endif 330 u8 pcie_cap; /* PCIe capability offset */ 331 u8 msi_cap; /* MSI capability offset */ 332 u8 msix_cap; /* MSI-X capability offset */ 333 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 334 u8 rom_base_reg; /* Config register controlling ROM */ 335 u8 pin; /* Interrupt pin this device uses */ 336 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 337 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 338 339 struct pci_driver *driver; /* Driver bound to this device */ 340 u64 dma_mask; /* Mask of the bits of bus address this 341 device implements. Normally this is 342 0xffffffff. You only need to change 343 this if your device has broken DMA 344 or supports 64-bit transfers. */ 345 346 struct device_dma_parameters dma_parms; 347 348 pci_power_t current_state; /* Current operating state. In ACPI, 349 this is D0-D3, D0 being fully 350 functional, and D3 being off. */ 351 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 352 u8 pm_cap; /* PM capability offset */ 353 unsigned int pme_support:5; /* Bitmask of states from which PME# 354 can be generated */ 355 unsigned int pme_poll:1; /* Poll device's PME status bit */ 356 unsigned int d1_support:1; /* Low power state D1 is supported */ 357 unsigned int d2_support:1; /* Low power state D2 is supported */ 358 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 359 unsigned int no_d3cold:1; /* D3cold is forbidden */ 360 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 361 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 362 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 363 decoding during BAR sizing */ 364 unsigned int wakeup_prepared:1; 365 unsigned int runtime_d3cold:1; /* Whether go through runtime 366 D3cold, not set for devices 367 powered on/off by the 368 corresponding bridge */ 369 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 370 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 371 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 372 controlled exclusively by 373 user sysfs */ 374 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 375 bit manually */ 376 unsigned int d3_delay; /* D3->D0 transition time in ms */ 377 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 378 379 #ifdef CONFIG_PCIEASPM 380 struct pcie_link_state *link_state; /* ASPM link state */ 381 unsigned int ltr_path:1; /* Latency Tolerance Reporting 382 supported from root to here */ 383 #endif 384 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 385 386 pci_channel_state_t error_state; /* Current connectivity state */ 387 struct device dev; /* Generic device interface */ 388 389 int cfg_size; /* Size of config space */ 390 391 /* 392 * Instead of touching interrupt line and base address registers 393 * directly, use the values stored here. They might be different! 394 */ 395 unsigned int irq; 396 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 397 398 bool match_driver; /* Skip attaching driver */ 399 400 unsigned int transparent:1; /* Subtractive decode bridge */ 401 unsigned int io_window:1; /* Bridge has I/O window */ 402 unsigned int pref_window:1; /* Bridge has pref mem window */ 403 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 404 unsigned int multifunction:1; /* Multi-function device */ 405 406 unsigned int is_busmaster:1; /* Is busmaster */ 407 unsigned int no_msi:1; /* May not use MSI */ 408 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 409 unsigned int block_cfg_access:1; /* Config space access blocked */ 410 unsigned int broken_parity_status:1; /* Generates false positive parity */ 411 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 412 unsigned int msi_enabled:1; 413 unsigned int msix_enabled:1; 414 unsigned int ari_enabled:1; /* ARI forwarding */ 415 unsigned int ats_enabled:1; /* Address Translation Svc */ 416 unsigned int pasid_enabled:1; /* Process Address Space ID */ 417 unsigned int pri_enabled:1; /* Page Request Interface */ 418 unsigned int is_managed:1; 419 unsigned int needs_freset:1; /* Requires fundamental reset */ 420 unsigned int state_saved:1; 421 unsigned int is_physfn:1; 422 unsigned int is_virtfn:1; 423 unsigned int reset_fn:1; 424 unsigned int is_hotplug_bridge:1; 425 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 426 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 427 /* 428 * Devices marked being untrusted are the ones that can potentially 429 * execute DMA attacks and similar. They are typically connected 430 * through external ports such as Thunderbolt but not limited to 431 * that. When an IOMMU is enabled they should be getting full 432 * mappings to make sure they cannot access arbitrary memory. 433 */ 434 unsigned int untrusted:1; 435 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 436 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 437 unsigned int irq_managed:1; 438 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 439 unsigned int is_probed:1; /* Device probing in progress */ 440 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 441 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 442 pci_dev_flags_t dev_flags; 443 atomic_t enable_cnt; /* pci_enable_device has been called */ 444 445 u32 saved_config_space[16]; /* Config space saved at suspend time */ 446 struct hlist_head saved_cap_space; 447 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 448 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 449 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 450 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 451 452 #ifdef CONFIG_HOTPLUG_PCI_PCIE 453 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 454 #endif 455 #ifdef CONFIG_PCIE_PTM 456 unsigned int ptm_root:1; 457 unsigned int ptm_enabled:1; 458 u8 ptm_granularity; 459 #endif 460 #ifdef CONFIG_PCI_MSI 461 const struct attribute_group **msi_irq_groups; 462 #endif 463 struct pci_vpd *vpd; 464 #ifdef CONFIG_PCIE_DPC 465 u16 dpc_cap; 466 unsigned int dpc_rp_extensions:1; 467 u8 dpc_rp_log_size; 468 #endif 469 #ifdef CONFIG_PCI_ATS 470 union { 471 struct pci_sriov *sriov; /* PF: SR-IOV info */ 472 struct pci_dev *physfn; /* VF: related PF */ 473 }; 474 u16 ats_cap; /* ATS Capability offset */ 475 u8 ats_stu; /* ATS Smallest Translation Unit */ 476 #endif 477 #ifdef CONFIG_PCI_PRI 478 u16 pri_cap; /* PRI Capability offset */ 479 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 480 unsigned int pasid_required:1; /* PRG Response PASID Required */ 481 #endif 482 #ifdef CONFIG_PCI_PASID 483 u16 pasid_cap; /* PASID Capability offset */ 484 u16 pasid_features; 485 #endif 486 #ifdef CONFIG_PCI_P2PDMA 487 struct pci_p2pdma *p2pdma; 488 #endif 489 phys_addr_t rom; /* Physical address if not from BAR */ 490 size_t romlen; /* Length if not from BAR */ 491 char *driver_override; /* Driver name to force a match */ 492 493 unsigned long priv_flags; /* Private flags for the PCI driver */ 494 }; 495 496 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 497 { 498 #ifdef CONFIG_PCI_IOV 499 if (dev->is_virtfn) 500 dev = dev->physfn; 501 #endif 502 return dev; 503 } 504 505 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 506 507 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 508 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 509 510 static inline int pci_channel_offline(struct pci_dev *pdev) 511 { 512 return (pdev->error_state != pci_channel_io_normal); 513 } 514 515 struct pci_host_bridge { 516 struct device dev; 517 struct pci_bus *bus; /* Root bus */ 518 struct pci_ops *ops; 519 void *sysdata; 520 int busnr; 521 struct list_head windows; /* resource_entry */ 522 struct list_head dma_ranges; /* dma ranges resource list */ 523 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 524 int (*map_irq)(const struct pci_dev *, u8, u8); 525 void (*release_fn)(struct pci_host_bridge *); 526 void *release_data; 527 struct msi_controller *msi; 528 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 529 unsigned int no_ext_tags:1; /* No Extended Tags */ 530 unsigned int native_aer:1; /* OS may use PCIe AER */ 531 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 532 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 533 unsigned int native_pme:1; /* OS may use PCIe PME */ 534 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 535 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 536 unsigned int preserve_config:1; /* Preserve FW resource setup */ 537 unsigned int size_windows:1; /* Enable root bus sizing */ 538 539 /* Resource alignment requirements */ 540 resource_size_t (*align_resource)(struct pci_dev *dev, 541 const struct resource *res, 542 resource_size_t start, 543 resource_size_t size, 544 resource_size_t align); 545 unsigned long private[] ____cacheline_aligned; 546 }; 547 548 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 549 550 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 551 { 552 return (void *)bridge->private; 553 } 554 555 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 556 { 557 return container_of(priv, struct pci_host_bridge, private); 558 } 559 560 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 561 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 562 size_t priv); 563 void pci_free_host_bridge(struct pci_host_bridge *bridge); 564 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 565 566 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 567 void (*release_fn)(struct pci_host_bridge *), 568 void *release_data); 569 570 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 571 572 /* 573 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 574 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 575 * buses below host bridges or subtractive decode bridges) go in the list. 576 * Use pci_bus_for_each_resource() to iterate through all the resources. 577 */ 578 579 /* 580 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 581 * and there's no way to program the bridge with the details of the window. 582 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 583 * decode bit set, because they are explicit and can be programmed with _SRS. 584 */ 585 #define PCI_SUBTRACTIVE_DECODE 0x1 586 587 struct pci_bus_resource { 588 struct list_head list; 589 struct resource *res; 590 unsigned int flags; 591 }; 592 593 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 594 595 struct pci_bus { 596 struct list_head node; /* Node in list of buses */ 597 struct pci_bus *parent; /* Parent bus this bridge is on */ 598 struct list_head children; /* List of child buses */ 599 struct list_head devices; /* List of devices on this bus */ 600 struct pci_dev *self; /* Bridge device as seen by parent */ 601 struct list_head slots; /* List of slots on this bus; 602 protected by pci_slot_mutex */ 603 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 604 struct list_head resources; /* Address space routed to this bus */ 605 struct resource busn_res; /* Bus numbers routed to this bus */ 606 607 struct pci_ops *ops; /* Configuration access functions */ 608 struct msi_controller *msi; /* MSI controller */ 609 void *sysdata; /* Hook for sys-specific extension */ 610 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 611 612 unsigned char number; /* Bus number */ 613 unsigned char primary; /* Number of primary bridge */ 614 unsigned char max_bus_speed; /* enum pci_bus_speed */ 615 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 616 #ifdef CONFIG_PCI_DOMAINS_GENERIC 617 int domain_nr; 618 #endif 619 620 char name[48]; 621 622 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 623 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 624 struct device *bridge; 625 struct device dev; 626 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 627 struct bin_attribute *legacy_mem; /* Legacy mem */ 628 unsigned int is_added:1; 629 }; 630 631 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 632 633 static inline u16 pci_dev_id(struct pci_dev *dev) 634 { 635 return PCI_DEVID(dev->bus->number, dev->devfn); 636 } 637 638 /* 639 * Returns true if the PCI bus is root (behind host-PCI bridge), 640 * false otherwise 641 * 642 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 643 * This is incorrect because "virtual" buses added for SR-IOV (via 644 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 645 */ 646 static inline bool pci_is_root_bus(struct pci_bus *pbus) 647 { 648 return !(pbus->parent); 649 } 650 651 /** 652 * pci_is_bridge - check if the PCI device is a bridge 653 * @dev: PCI device 654 * 655 * Return true if the PCI device is bridge whether it has subordinate 656 * or not. 657 */ 658 static inline bool pci_is_bridge(struct pci_dev *dev) 659 { 660 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 661 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 662 } 663 664 #define for_each_pci_bridge(dev, bus) \ 665 list_for_each_entry(dev, &bus->devices, bus_list) \ 666 if (!pci_is_bridge(dev)) {} else 667 668 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 669 { 670 dev = pci_physfn(dev); 671 if (pci_is_root_bus(dev->bus)) 672 return NULL; 673 674 return dev->bus->self; 675 } 676 677 #ifdef CONFIG_PCI_MSI 678 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 679 { 680 return pci_dev->msi_enabled || pci_dev->msix_enabled; 681 } 682 #else 683 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 684 #endif 685 686 /* Error values that may be returned by PCI functions */ 687 #define PCIBIOS_SUCCESSFUL 0x00 688 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 689 #define PCIBIOS_BAD_VENDOR_ID 0x83 690 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 691 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 692 #define PCIBIOS_SET_FAILED 0x88 693 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 694 695 /* Translate above to generic errno for passing back through non-PCI code */ 696 static inline int pcibios_err_to_errno(int err) 697 { 698 if (err <= PCIBIOS_SUCCESSFUL) 699 return err; /* Assume already errno */ 700 701 switch (err) { 702 case PCIBIOS_FUNC_NOT_SUPPORTED: 703 return -ENOENT; 704 case PCIBIOS_BAD_VENDOR_ID: 705 return -ENOTTY; 706 case PCIBIOS_DEVICE_NOT_FOUND: 707 return -ENODEV; 708 case PCIBIOS_BAD_REGISTER_NUMBER: 709 return -EFAULT; 710 case PCIBIOS_SET_FAILED: 711 return -EIO; 712 case PCIBIOS_BUFFER_TOO_SMALL: 713 return -ENOSPC; 714 } 715 716 return -ERANGE; 717 } 718 719 /* Low-level architecture-dependent routines */ 720 721 struct pci_ops { 722 int (*add_bus)(struct pci_bus *bus); 723 void (*remove_bus)(struct pci_bus *bus); 724 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 725 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 726 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 727 }; 728 729 /* 730 * ACPI needs to be able to access PCI config space before we've done a 731 * PCI bus scan and created pci_bus structures. 732 */ 733 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 734 int reg, int len, u32 *val); 735 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 736 int reg, int len, u32 val); 737 738 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 739 typedef u64 pci_bus_addr_t; 740 #else 741 typedef u32 pci_bus_addr_t; 742 #endif 743 744 struct pci_bus_region { 745 pci_bus_addr_t start; 746 pci_bus_addr_t end; 747 }; 748 749 struct pci_dynids { 750 spinlock_t lock; /* Protects list, index */ 751 struct list_head list; /* For IDs added at runtime */ 752 }; 753 754 755 /* 756 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 757 * a set of callbacks in struct pci_error_handlers, that device driver 758 * will be notified of PCI bus errors, and will be driven to recovery 759 * when an error occurs. 760 */ 761 762 typedef unsigned int __bitwise pci_ers_result_t; 763 764 enum pci_ers_result { 765 /* No result/none/not supported in device driver */ 766 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 767 768 /* Device driver can recover without slot reset */ 769 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 770 771 /* Device driver wants slot to be reset */ 772 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 773 774 /* Device has completely failed, is unrecoverable */ 775 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 776 777 /* Device driver is fully recovered and operational */ 778 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 779 780 /* No AER capabilities registered for the driver */ 781 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 782 }; 783 784 /* PCI bus error event callbacks */ 785 struct pci_error_handlers { 786 /* PCI bus error detected on this device */ 787 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 788 enum pci_channel_state error); 789 790 /* MMIO has been re-enabled, but not DMA */ 791 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 792 793 /* PCI slot has been reset */ 794 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 795 796 /* PCI function reset prepare or completed */ 797 void (*reset_prepare)(struct pci_dev *dev); 798 void (*reset_done)(struct pci_dev *dev); 799 800 /* Device driver may resume normal operations */ 801 void (*resume)(struct pci_dev *dev); 802 }; 803 804 805 struct module; 806 807 /** 808 * struct pci_driver - PCI driver structure 809 * @node: List of driver structures. 810 * @name: Driver name. 811 * @id_table: Pointer to table of device IDs the driver is 812 * interested in. Most drivers should export this 813 * table using MODULE_DEVICE_TABLE(pci,...). 814 * @probe: This probing function gets called (during execution 815 * of pci_register_driver() for already existing 816 * devices or later if a new device gets inserted) for 817 * all PCI devices which match the ID table and are not 818 * "owned" by the other drivers yet. This function gets 819 * passed a "struct pci_dev \*" for each device whose 820 * entry in the ID table matches the device. The probe 821 * function returns zero when the driver chooses to 822 * take "ownership" of the device or an error code 823 * (negative number) otherwise. 824 * The probe function always gets called from process 825 * context, so it can sleep. 826 * @remove: The remove() function gets called whenever a device 827 * being handled by this driver is removed (either during 828 * deregistration of the driver or when it's manually 829 * pulled out of a hot-pluggable slot). 830 * The remove function always gets called from process 831 * context, so it can sleep. 832 * @suspend: Put device into low power state. 833 * @resume: Wake device from low power state. 834 * (Please see Documentation/power/pci.rst for descriptions 835 * of PCI Power Management and the related functions.) 836 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 837 * Intended to stop any idling DMA operations. 838 * Useful for enabling wake-on-lan (NIC) or changing 839 * the power state of a device before reboot. 840 * e.g. drivers/net/e100.c. 841 * @sriov_configure: Optional driver callback to allow configuration of 842 * number of VFs to enable via sysfs "sriov_numvfs" file. 843 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 844 * @groups: Sysfs attribute groups. 845 * @driver: Driver model structure. 846 * @dynids: List of dynamically added device IDs. 847 */ 848 struct pci_driver { 849 struct list_head node; 850 const char *name; 851 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 852 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 853 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 854 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 855 int (*resume)(struct pci_dev *dev); /* Device woken up */ 856 void (*shutdown)(struct pci_dev *dev); 857 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 858 const struct pci_error_handlers *err_handler; 859 const struct attribute_group **groups; 860 struct device_driver driver; 861 struct pci_dynids dynids; 862 }; 863 864 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 865 866 /** 867 * PCI_DEVICE - macro used to describe a specific PCI device 868 * @vend: the 16 bit PCI Vendor ID 869 * @dev: the 16 bit PCI Device ID 870 * 871 * This macro is used to create a struct pci_device_id that matches a 872 * specific device. The subvendor and subdevice fields will be set to 873 * PCI_ANY_ID. 874 */ 875 #define PCI_DEVICE(vend,dev) \ 876 .vendor = (vend), .device = (dev), \ 877 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 878 879 /** 880 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 881 * @vend: the 16 bit PCI Vendor ID 882 * @dev: the 16 bit PCI Device ID 883 * @subvend: the 16 bit PCI Subvendor ID 884 * @subdev: the 16 bit PCI Subdevice ID 885 * 886 * This macro is used to create a struct pci_device_id that matches a 887 * specific device with subsystem information. 888 */ 889 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 890 .vendor = (vend), .device = (dev), \ 891 .subvendor = (subvend), .subdevice = (subdev) 892 893 /** 894 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 895 * @dev_class: the class, subclass, prog-if triple for this device 896 * @dev_class_mask: the class mask for this device 897 * 898 * This macro is used to create a struct pci_device_id that matches a 899 * specific PCI class. The vendor, device, subvendor, and subdevice 900 * fields will be set to PCI_ANY_ID. 901 */ 902 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 903 .class = (dev_class), .class_mask = (dev_class_mask), \ 904 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 905 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 906 907 /** 908 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 909 * @vend: the vendor name 910 * @dev: the 16 bit PCI Device ID 911 * 912 * This macro is used to create a struct pci_device_id that matches a 913 * specific PCI device. The subvendor, and subdevice fields will be set 914 * to PCI_ANY_ID. The macro allows the next field to follow as the device 915 * private data. 916 */ 917 #define PCI_VDEVICE(vend, dev) \ 918 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 919 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 920 921 /** 922 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 923 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 924 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 925 * @data: the driver data to be filled 926 * 927 * This macro is used to create a struct pci_device_id that matches a 928 * specific PCI device. The subvendor, and subdevice fields will be set 929 * to PCI_ANY_ID. 930 */ 931 #define PCI_DEVICE_DATA(vend, dev, data) \ 932 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 933 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 934 .driver_data = (kernel_ulong_t)(data) 935 936 enum { 937 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 938 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 939 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 940 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 941 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 942 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 943 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 944 }; 945 946 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 947 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 948 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 949 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 950 951 /* These external functions are only available when PCI support is enabled */ 952 #ifdef CONFIG_PCI 953 954 extern unsigned int pci_flags; 955 956 static inline void pci_set_flags(int flags) { pci_flags = flags; } 957 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 958 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 959 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 960 961 void pcie_bus_configure_settings(struct pci_bus *bus); 962 963 enum pcie_bus_config_types { 964 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 965 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 966 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 967 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 968 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 969 }; 970 971 extern enum pcie_bus_config_types pcie_bus_config; 972 973 extern struct bus_type pci_bus_type; 974 975 /* Do NOT directly access these two variables, unless you are arch-specific PCI 976 * code, or PCI core code. */ 977 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 978 /* Some device drivers need know if PCI is initiated */ 979 int no_pci_devices(void); 980 981 void pcibios_resource_survey_bus(struct pci_bus *bus); 982 void pcibios_bus_add_device(struct pci_dev *pdev); 983 void pcibios_add_bus(struct pci_bus *bus); 984 void pcibios_remove_bus(struct pci_bus *bus); 985 void pcibios_fixup_bus(struct pci_bus *); 986 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 987 /* Architecture-specific versions may override this (weak) */ 988 char *pcibios_setup(char *str); 989 990 /* Used only when drivers/pci/setup.c is used */ 991 resource_size_t pcibios_align_resource(void *, const struct resource *, 992 resource_size_t, 993 resource_size_t); 994 995 /* Weak but can be overridden by arch */ 996 void pci_fixup_cardbus(struct pci_bus *); 997 998 /* Generic PCI functions used internally */ 999 1000 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1001 struct resource *res); 1002 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1003 struct pci_bus_region *region); 1004 void pcibios_scan_specific_bus(int busn); 1005 struct pci_bus *pci_find_bus(int domain, int busnr); 1006 void pci_bus_add_devices(const struct pci_bus *bus); 1007 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1008 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1009 struct pci_ops *ops, void *sysdata, 1010 struct list_head *resources); 1011 int pci_host_probe(struct pci_host_bridge *bridge); 1012 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1013 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1014 void pci_bus_release_busn_res(struct pci_bus *b); 1015 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1016 struct pci_ops *ops, void *sysdata, 1017 struct list_head *resources); 1018 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1019 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1020 int busnr); 1021 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1022 const char *name, 1023 struct hotplug_slot *hotplug); 1024 void pci_destroy_slot(struct pci_slot *slot); 1025 #ifdef CONFIG_SYSFS 1026 void pci_dev_assign_slot(struct pci_dev *dev); 1027 #else 1028 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1029 #endif 1030 int pci_scan_slot(struct pci_bus *bus, int devfn); 1031 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1032 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1033 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1034 void pci_bus_add_device(struct pci_dev *dev); 1035 void pci_read_bridge_bases(struct pci_bus *child); 1036 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1037 struct resource *res); 1038 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1039 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1040 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1041 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1042 void pci_dev_put(struct pci_dev *dev); 1043 void pci_remove_bus(struct pci_bus *b); 1044 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1045 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1046 void pci_stop_root_bus(struct pci_bus *bus); 1047 void pci_remove_root_bus(struct pci_bus *bus); 1048 void pci_setup_cardbus(struct pci_bus *bus); 1049 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1050 void pci_sort_breadthfirst(void); 1051 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1052 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1053 1054 /* Generic PCI functions exported to card drivers */ 1055 1056 enum pci_lost_interrupt_reason { 1057 PCI_LOST_IRQ_NO_INFORMATION = 0, 1058 PCI_LOST_IRQ_DISABLE_MSI, 1059 PCI_LOST_IRQ_DISABLE_MSIX, 1060 PCI_LOST_IRQ_DISABLE_ACPI, 1061 }; 1062 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 1063 int pci_find_capability(struct pci_dev *dev, int cap); 1064 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1065 int pci_find_ext_capability(struct pci_dev *dev, int cap); 1066 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 1067 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1068 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 1069 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1070 1071 u64 pci_get_dsn(struct pci_dev *dev); 1072 1073 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1074 struct pci_dev *from); 1075 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1076 unsigned int ss_vendor, unsigned int ss_device, 1077 struct pci_dev *from); 1078 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1079 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1080 unsigned int devfn); 1081 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1082 int pci_dev_present(const struct pci_device_id *ids); 1083 1084 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1085 int where, u8 *val); 1086 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1087 int where, u16 *val); 1088 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1089 int where, u32 *val); 1090 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1091 int where, u8 val); 1092 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1093 int where, u16 val); 1094 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1095 int where, u32 val); 1096 1097 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1098 int where, int size, u32 *val); 1099 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1100 int where, int size, u32 val); 1101 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1102 int where, int size, u32 *val); 1103 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1104 int where, int size, u32 val); 1105 1106 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1107 1108 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1109 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1110 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1111 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1112 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1113 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1114 1115 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1116 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1117 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1118 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1119 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1120 u16 clear, u16 set); 1121 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1122 u32 clear, u32 set); 1123 1124 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1125 u16 set) 1126 { 1127 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1128 } 1129 1130 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1131 u32 set) 1132 { 1133 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1134 } 1135 1136 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1137 u16 clear) 1138 { 1139 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1140 } 1141 1142 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1143 u32 clear) 1144 { 1145 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1146 } 1147 1148 /* User-space driven config access */ 1149 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1150 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1151 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1152 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1153 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1154 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1155 1156 int __must_check pci_enable_device(struct pci_dev *dev); 1157 int __must_check pci_enable_device_io(struct pci_dev *dev); 1158 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1159 int __must_check pci_reenable_device(struct pci_dev *); 1160 int __must_check pcim_enable_device(struct pci_dev *pdev); 1161 void pcim_pin_device(struct pci_dev *pdev); 1162 1163 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1164 { 1165 /* 1166 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1167 * writable and no quirk has marked the feature broken. 1168 */ 1169 return !pdev->broken_intx_masking; 1170 } 1171 1172 static inline int pci_is_enabled(struct pci_dev *pdev) 1173 { 1174 return (atomic_read(&pdev->enable_cnt) > 0); 1175 } 1176 1177 static inline int pci_is_managed(struct pci_dev *pdev) 1178 { 1179 return pdev->is_managed; 1180 } 1181 1182 void pci_disable_device(struct pci_dev *dev); 1183 1184 extern unsigned int pcibios_max_latency; 1185 void pci_set_master(struct pci_dev *dev); 1186 void pci_clear_master(struct pci_dev *dev); 1187 1188 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1189 int pci_set_cacheline_size(struct pci_dev *dev); 1190 #define HAVE_PCI_SET_MWI 1191 int __must_check pci_set_mwi(struct pci_dev *dev); 1192 int __must_check pcim_set_mwi(struct pci_dev *dev); 1193 int pci_try_set_mwi(struct pci_dev *dev); 1194 void pci_clear_mwi(struct pci_dev *dev); 1195 void pci_intx(struct pci_dev *dev, int enable); 1196 bool pci_check_and_mask_intx(struct pci_dev *dev); 1197 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1198 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1199 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1200 int pcix_get_max_mmrbc(struct pci_dev *dev); 1201 int pcix_get_mmrbc(struct pci_dev *dev); 1202 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1203 int pcie_get_readrq(struct pci_dev *dev); 1204 int pcie_set_readrq(struct pci_dev *dev, int rq); 1205 int pcie_get_mps(struct pci_dev *dev); 1206 int pcie_set_mps(struct pci_dev *dev, int mps); 1207 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1208 enum pci_bus_speed *speed, 1209 enum pcie_link_width *width); 1210 void pcie_print_link_status(struct pci_dev *dev); 1211 bool pcie_has_flr(struct pci_dev *dev); 1212 int pcie_flr(struct pci_dev *dev); 1213 int __pci_reset_function_locked(struct pci_dev *dev); 1214 int pci_reset_function(struct pci_dev *dev); 1215 int pci_reset_function_locked(struct pci_dev *dev); 1216 int pci_try_reset_function(struct pci_dev *dev); 1217 int pci_probe_reset_slot(struct pci_slot *slot); 1218 int pci_probe_reset_bus(struct pci_bus *bus); 1219 int pci_reset_bus(struct pci_dev *dev); 1220 void pci_reset_secondary_bus(struct pci_dev *dev); 1221 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1222 void pci_update_resource(struct pci_dev *dev, int resno); 1223 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1224 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1225 void pci_release_resource(struct pci_dev *dev, int resno); 1226 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1227 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1228 bool pci_device_is_present(struct pci_dev *pdev); 1229 void pci_ignore_hotplug(struct pci_dev *dev); 1230 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1231 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1232 1233 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1234 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1235 const char *fmt, ...); 1236 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1237 1238 /* ROM control related routines */ 1239 int pci_enable_rom(struct pci_dev *pdev); 1240 void pci_disable_rom(struct pci_dev *pdev); 1241 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1242 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1243 1244 /* Power management related routines */ 1245 int pci_save_state(struct pci_dev *dev); 1246 void pci_restore_state(struct pci_dev *dev); 1247 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1248 int pci_load_saved_state(struct pci_dev *dev, 1249 struct pci_saved_state *state); 1250 int pci_load_and_free_saved_state(struct pci_dev *dev, 1251 struct pci_saved_state **state); 1252 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1253 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1254 u16 cap); 1255 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1256 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1257 u16 cap, unsigned int size); 1258 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1259 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1260 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1261 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1262 void pci_pme_active(struct pci_dev *dev, bool enable); 1263 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1264 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1265 int pci_prepare_to_sleep(struct pci_dev *dev); 1266 int pci_back_from_sleep(struct pci_dev *dev); 1267 bool pci_dev_run_wake(struct pci_dev *dev); 1268 void pci_d3cold_enable(struct pci_dev *dev); 1269 void pci_d3cold_disable(struct pci_dev *dev); 1270 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1271 void pci_wakeup_bus(struct pci_bus *bus); 1272 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1273 1274 /* For use by arch with custom probe code */ 1275 void set_pcie_port_type(struct pci_dev *pdev); 1276 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1277 1278 /* Functions for PCI Hotplug drivers to use */ 1279 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1280 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1281 unsigned int pci_rescan_bus(struct pci_bus *bus); 1282 void pci_lock_rescan_remove(void); 1283 void pci_unlock_rescan_remove(void); 1284 1285 /* Vital Product Data routines */ 1286 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1287 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1288 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1289 1290 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1291 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1292 void pci_bus_assign_resources(const struct pci_bus *bus); 1293 void pci_bus_claim_resources(struct pci_bus *bus); 1294 void pci_bus_size_bridges(struct pci_bus *bus); 1295 int pci_claim_resource(struct pci_dev *, int); 1296 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1297 void pci_assign_unassigned_resources(void); 1298 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1299 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1300 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1301 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1302 void pdev_enable_device(struct pci_dev *); 1303 int pci_enable_resources(struct pci_dev *, int mask); 1304 void pci_assign_irq(struct pci_dev *dev); 1305 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1306 #define HAVE_PCI_REQ_REGIONS 2 1307 int __must_check pci_request_regions(struct pci_dev *, const char *); 1308 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1309 void pci_release_regions(struct pci_dev *); 1310 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1311 void pci_release_region(struct pci_dev *, int); 1312 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1313 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1314 void pci_release_selected_regions(struct pci_dev *, int); 1315 1316 /* drivers/pci/bus.c */ 1317 void pci_add_resource(struct list_head *resources, struct resource *res); 1318 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1319 resource_size_t offset); 1320 void pci_free_resource_list(struct list_head *resources); 1321 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1322 unsigned int flags); 1323 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1324 void pci_bus_remove_resources(struct pci_bus *bus); 1325 int devm_request_pci_bus_resources(struct device *dev, 1326 struct list_head *resources); 1327 1328 /* Temporary until new and working PCI SBR API in place */ 1329 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1330 1331 #define pci_bus_for_each_resource(bus, res, i) \ 1332 for (i = 0; \ 1333 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1334 i++) 1335 1336 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1337 struct resource *res, resource_size_t size, 1338 resource_size_t align, resource_size_t min, 1339 unsigned long type_mask, 1340 resource_size_t (*alignf)(void *, 1341 const struct resource *, 1342 resource_size_t, 1343 resource_size_t), 1344 void *alignf_data); 1345 1346 1347 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1348 resource_size_t size); 1349 unsigned long pci_address_to_pio(phys_addr_t addr); 1350 phys_addr_t pci_pio_to_address(unsigned long pio); 1351 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1352 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1353 phys_addr_t phys_addr); 1354 void pci_unmap_iospace(struct resource *res); 1355 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1356 resource_size_t offset, 1357 resource_size_t size); 1358 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1359 struct resource *res); 1360 1361 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1362 { 1363 struct pci_bus_region region; 1364 1365 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1366 return region.start; 1367 } 1368 1369 /* Proper probing supporting hot-pluggable devices */ 1370 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1371 const char *mod_name); 1372 1373 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1374 #define pci_register_driver(driver) \ 1375 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1376 1377 void pci_unregister_driver(struct pci_driver *dev); 1378 1379 /** 1380 * module_pci_driver() - Helper macro for registering a PCI driver 1381 * @__pci_driver: pci_driver struct 1382 * 1383 * Helper macro for PCI drivers which do not do anything special in module 1384 * init/exit. This eliminates a lot of boilerplate. Each module may only 1385 * use this macro once, and calling it replaces module_init() and module_exit() 1386 */ 1387 #define module_pci_driver(__pci_driver) \ 1388 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1389 1390 /** 1391 * builtin_pci_driver() - Helper macro for registering a PCI driver 1392 * @__pci_driver: pci_driver struct 1393 * 1394 * Helper macro for PCI drivers which do not do anything special in their 1395 * init code. This eliminates a lot of boilerplate. Each driver may only 1396 * use this macro once, and calling it replaces device_initcall(...) 1397 */ 1398 #define builtin_pci_driver(__pci_driver) \ 1399 builtin_driver(__pci_driver, pci_register_driver) 1400 1401 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1402 int pci_add_dynid(struct pci_driver *drv, 1403 unsigned int vendor, unsigned int device, 1404 unsigned int subvendor, unsigned int subdevice, 1405 unsigned int class, unsigned int class_mask, 1406 unsigned long driver_data); 1407 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1408 struct pci_dev *dev); 1409 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1410 int pass); 1411 1412 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1413 void *userdata); 1414 int pci_cfg_space_size(struct pci_dev *dev); 1415 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1416 void pci_setup_bridge(struct pci_bus *bus); 1417 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1418 unsigned long type); 1419 1420 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1421 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1422 1423 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1424 unsigned int command_bits, u32 flags); 1425 1426 /* 1427 * Virtual interrupts allow for more interrupts to be allocated 1428 * than the device has interrupts for. These are not programmed 1429 * into the device's MSI-X table and must be handled by some 1430 * other driver means. 1431 */ 1432 #define PCI_IRQ_VIRTUAL (1 << 4) 1433 1434 #define PCI_IRQ_ALL_TYPES \ 1435 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1436 1437 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1438 1439 #include <linux/dmapool.h> 1440 1441 #define pci_pool dma_pool 1442 #define pci_pool_create(name, pdev, size, align, allocation) \ 1443 dma_pool_create(name, &pdev->dev, size, align, allocation) 1444 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1445 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1446 #define pci_pool_zalloc(pool, flags, handle) \ 1447 dma_pool_zalloc(pool, flags, handle) 1448 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1449 1450 struct msix_entry { 1451 u32 vector; /* Kernel uses to write allocated vector */ 1452 u16 entry; /* Driver uses to specify entry, OS writes */ 1453 }; 1454 1455 #ifdef CONFIG_PCI_MSI 1456 int pci_msi_vec_count(struct pci_dev *dev); 1457 void pci_disable_msi(struct pci_dev *dev); 1458 int pci_msix_vec_count(struct pci_dev *dev); 1459 void pci_disable_msix(struct pci_dev *dev); 1460 void pci_restore_msi_state(struct pci_dev *dev); 1461 int pci_msi_enabled(void); 1462 int pci_enable_msi(struct pci_dev *dev); 1463 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1464 int minvec, int maxvec); 1465 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1466 struct msix_entry *entries, int nvec) 1467 { 1468 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1469 if (rc < 0) 1470 return rc; 1471 return 0; 1472 } 1473 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1474 unsigned int max_vecs, unsigned int flags, 1475 struct irq_affinity *affd); 1476 1477 void pci_free_irq_vectors(struct pci_dev *dev); 1478 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1479 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1480 1481 #else 1482 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1483 static inline void pci_disable_msi(struct pci_dev *dev) { } 1484 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1485 static inline void pci_disable_msix(struct pci_dev *dev) { } 1486 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1487 static inline int pci_msi_enabled(void) { return 0; } 1488 static inline int pci_enable_msi(struct pci_dev *dev) 1489 { return -ENOSYS; } 1490 static inline int pci_enable_msix_range(struct pci_dev *dev, 1491 struct msix_entry *entries, int minvec, int maxvec) 1492 { return -ENOSYS; } 1493 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1494 struct msix_entry *entries, int nvec) 1495 { return -ENOSYS; } 1496 1497 static inline int 1498 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1499 unsigned int max_vecs, unsigned int flags, 1500 struct irq_affinity *aff_desc) 1501 { 1502 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1503 return 1; 1504 return -ENOSPC; 1505 } 1506 1507 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1508 { 1509 } 1510 1511 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1512 { 1513 if (WARN_ON_ONCE(nr > 0)) 1514 return -EINVAL; 1515 return dev->irq; 1516 } 1517 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1518 int vec) 1519 { 1520 return cpu_possible_mask; 1521 } 1522 #endif 1523 1524 /** 1525 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1526 * @d: the INTx IRQ domain 1527 * @node: the DT node for the device whose interrupt we're translating 1528 * @intspec: the interrupt specifier data from the DT 1529 * @intsize: the number of entries in @intspec 1530 * @out_hwirq: pointer at which to write the hwirq number 1531 * @out_type: pointer at which to write the interrupt type 1532 * 1533 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1534 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1535 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1536 * INTx value to obtain the hwirq number. 1537 * 1538 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1539 */ 1540 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1541 struct device_node *node, 1542 const u32 *intspec, 1543 unsigned int intsize, 1544 unsigned long *out_hwirq, 1545 unsigned int *out_type) 1546 { 1547 const u32 intx = intspec[0]; 1548 1549 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1550 return -EINVAL; 1551 1552 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1553 return 0; 1554 } 1555 1556 #ifdef CONFIG_PCIEPORTBUS 1557 extern bool pcie_ports_disabled; 1558 extern bool pcie_ports_native; 1559 #else 1560 #define pcie_ports_disabled true 1561 #define pcie_ports_native false 1562 #endif 1563 1564 #define PCIE_LINK_STATE_L0S BIT(0) 1565 #define PCIE_LINK_STATE_L1 BIT(1) 1566 #define PCIE_LINK_STATE_CLKPM BIT(2) 1567 #define PCIE_LINK_STATE_L1_1 BIT(3) 1568 #define PCIE_LINK_STATE_L1_2 BIT(4) 1569 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1570 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1571 1572 #ifdef CONFIG_PCIEASPM 1573 int pci_disable_link_state(struct pci_dev *pdev, int state); 1574 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1575 void pcie_no_aspm(void); 1576 bool pcie_aspm_support_enabled(void); 1577 bool pcie_aspm_enabled(struct pci_dev *pdev); 1578 #else 1579 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1580 { return 0; } 1581 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1582 { return 0; } 1583 static inline void pcie_no_aspm(void) { } 1584 static inline bool pcie_aspm_support_enabled(void) { return false; } 1585 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1586 #endif 1587 1588 #ifdef CONFIG_PCIEAER 1589 bool pci_aer_available(void); 1590 #else 1591 static inline bool pci_aer_available(void) { return false; } 1592 #endif 1593 1594 bool pci_ats_disabled(void); 1595 1596 void pci_cfg_access_lock(struct pci_dev *dev); 1597 bool pci_cfg_access_trylock(struct pci_dev *dev); 1598 void pci_cfg_access_unlock(struct pci_dev *dev); 1599 1600 /* 1601 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1602 * a PCI domain is defined to be a set of PCI buses which share 1603 * configuration space. 1604 */ 1605 #ifdef CONFIG_PCI_DOMAINS 1606 extern int pci_domains_supported; 1607 #else 1608 enum { pci_domains_supported = 0 }; 1609 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1610 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1611 #endif /* CONFIG_PCI_DOMAINS */ 1612 1613 /* 1614 * Generic implementation for PCI domain support. If your 1615 * architecture does not need custom management of PCI 1616 * domains then this implementation will be used 1617 */ 1618 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1619 static inline int pci_domain_nr(struct pci_bus *bus) 1620 { 1621 return bus->domain_nr; 1622 } 1623 #ifdef CONFIG_ACPI 1624 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1625 #else 1626 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1627 { return 0; } 1628 #endif 1629 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1630 #endif 1631 1632 /* Some architectures require additional setup to direct VGA traffic */ 1633 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1634 unsigned int command_bits, u32 flags); 1635 void pci_register_set_vga_state(arch_set_vga_state_t func); 1636 1637 static inline int 1638 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1639 { 1640 return pci_request_selected_regions(pdev, 1641 pci_select_bars(pdev, IORESOURCE_IO), name); 1642 } 1643 1644 static inline void 1645 pci_release_io_regions(struct pci_dev *pdev) 1646 { 1647 return pci_release_selected_regions(pdev, 1648 pci_select_bars(pdev, IORESOURCE_IO)); 1649 } 1650 1651 static inline int 1652 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1653 { 1654 return pci_request_selected_regions(pdev, 1655 pci_select_bars(pdev, IORESOURCE_MEM), name); 1656 } 1657 1658 static inline void 1659 pci_release_mem_regions(struct pci_dev *pdev) 1660 { 1661 return pci_release_selected_regions(pdev, 1662 pci_select_bars(pdev, IORESOURCE_MEM)); 1663 } 1664 1665 #else /* CONFIG_PCI is not enabled */ 1666 1667 static inline void pci_set_flags(int flags) { } 1668 static inline void pci_add_flags(int flags) { } 1669 static inline void pci_clear_flags(int flags) { } 1670 static inline int pci_has_flag(int flag) { return 0; } 1671 1672 /* 1673 * If the system does not have PCI, clearly these return errors. Define 1674 * these as simple inline functions to avoid hair in drivers. 1675 */ 1676 #define _PCI_NOP(o, s, t) \ 1677 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1678 int where, t val) \ 1679 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1680 1681 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1682 _PCI_NOP(o, word, u16 x) \ 1683 _PCI_NOP(o, dword, u32 x) 1684 _PCI_NOP_ALL(read, *) 1685 _PCI_NOP_ALL(write,) 1686 1687 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1688 unsigned int device, 1689 struct pci_dev *from) 1690 { return NULL; } 1691 1692 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1693 unsigned int device, 1694 unsigned int ss_vendor, 1695 unsigned int ss_device, 1696 struct pci_dev *from) 1697 { return NULL; } 1698 1699 static inline struct pci_dev *pci_get_class(unsigned int class, 1700 struct pci_dev *from) 1701 { return NULL; } 1702 1703 #define pci_dev_present(ids) (0) 1704 #define no_pci_devices() (1) 1705 #define pci_dev_put(dev) do { } while (0) 1706 1707 static inline void pci_set_master(struct pci_dev *dev) { } 1708 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1709 static inline void pci_disable_device(struct pci_dev *dev) { } 1710 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1711 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1712 { return -EBUSY; } 1713 static inline int __pci_register_driver(struct pci_driver *drv, 1714 struct module *owner) 1715 { return 0; } 1716 static inline int pci_register_driver(struct pci_driver *drv) 1717 { return 0; } 1718 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1719 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1720 { return 0; } 1721 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1722 int cap) 1723 { return 0; } 1724 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1725 { return 0; } 1726 1727 static inline u64 pci_get_dsn(struct pci_dev *dev) 1728 { return 0; } 1729 1730 /* Power management related routines */ 1731 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1732 static inline void pci_restore_state(struct pci_dev *dev) { } 1733 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1734 { return 0; } 1735 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1736 { return 0; } 1737 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1738 pm_message_t state) 1739 { return PCI_D0; } 1740 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1741 int enable) 1742 { return 0; } 1743 1744 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1745 struct resource *res) 1746 { return NULL; } 1747 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1748 { return -EIO; } 1749 static inline void pci_release_regions(struct pci_dev *dev) { } 1750 1751 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1752 1753 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1754 { return NULL; } 1755 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1756 unsigned int devfn) 1757 { return NULL; } 1758 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1759 unsigned int bus, unsigned int devfn) 1760 { return NULL; } 1761 1762 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1763 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1764 1765 #define dev_is_pci(d) (false) 1766 #define dev_is_pf(d) (false) 1767 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1768 { return false; } 1769 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1770 struct device_node *node, 1771 const u32 *intspec, 1772 unsigned int intsize, 1773 unsigned long *out_hwirq, 1774 unsigned int *out_type) 1775 { return -EINVAL; } 1776 1777 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1778 struct pci_dev *dev) 1779 { return NULL; } 1780 static inline bool pci_ats_disabled(void) { return true; } 1781 1782 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1783 { 1784 return -EINVAL; 1785 } 1786 1787 static inline int 1788 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1789 unsigned int max_vecs, unsigned int flags, 1790 struct irq_affinity *aff_desc) 1791 { 1792 return -ENOSPC; 1793 } 1794 #endif /* CONFIG_PCI */ 1795 1796 static inline int 1797 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1798 unsigned int max_vecs, unsigned int flags) 1799 { 1800 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1801 NULL); 1802 } 1803 1804 /* Include architecture-dependent settings and functions */ 1805 1806 #include <asm/pci.h> 1807 1808 /* These two functions provide almost identical functionality. Depending 1809 * on the architecture, one will be implemented as a wrapper around the 1810 * other (in drivers/pci/mmap.c). 1811 * 1812 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1813 * is expected to be an offset within that region. 1814 * 1815 * pci_mmap_page_range() is the legacy architecture-specific interface, 1816 * which accepts a "user visible" resource address converted by 1817 * pci_resource_to_user(), as used in the legacy mmap() interface in 1818 * /proc/bus/pci/. 1819 */ 1820 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1821 struct vm_area_struct *vma, 1822 enum pci_mmap_state mmap_state, int write_combine); 1823 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1824 struct vm_area_struct *vma, 1825 enum pci_mmap_state mmap_state, int write_combine); 1826 1827 #ifndef arch_can_pci_mmap_wc 1828 #define arch_can_pci_mmap_wc() 0 1829 #endif 1830 1831 #ifndef arch_can_pci_mmap_io 1832 #define arch_can_pci_mmap_io() 0 1833 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1834 #else 1835 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1836 #endif 1837 1838 #ifndef pci_root_bus_fwnode 1839 #define pci_root_bus_fwnode(bus) NULL 1840 #endif 1841 1842 /* 1843 * These helpers provide future and backwards compatibility 1844 * for accessing popular PCI BAR info 1845 */ 1846 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1847 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1848 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1849 #define pci_resource_len(dev,bar) \ 1850 ((pci_resource_start((dev), (bar)) == 0 && \ 1851 pci_resource_end((dev), (bar)) == \ 1852 pci_resource_start((dev), (bar))) ? 0 : \ 1853 \ 1854 (pci_resource_end((dev), (bar)) - \ 1855 pci_resource_start((dev), (bar)) + 1)) 1856 1857 /* 1858 * Similar to the helpers above, these manipulate per-pci_dev 1859 * driver-specific data. They are really just a wrapper around 1860 * the generic device structure functions of these calls. 1861 */ 1862 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1863 { 1864 return dev_get_drvdata(&pdev->dev); 1865 } 1866 1867 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1868 { 1869 dev_set_drvdata(&pdev->dev, data); 1870 } 1871 1872 static inline const char *pci_name(const struct pci_dev *pdev) 1873 { 1874 return dev_name(&pdev->dev); 1875 } 1876 1877 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1878 const struct resource *rsrc, 1879 resource_size_t *start, resource_size_t *end); 1880 1881 /* 1882 * The world is not perfect and supplies us with broken PCI devices. 1883 * For at least a part of these bugs we need a work-around, so both 1884 * generic (drivers/pci/quirks.c) and per-architecture code can define 1885 * fixup hooks to be called for particular buggy devices. 1886 */ 1887 1888 struct pci_fixup { 1889 u16 vendor; /* Or PCI_ANY_ID */ 1890 u16 device; /* Or PCI_ANY_ID */ 1891 u32 class; /* Or PCI_ANY_ID */ 1892 unsigned int class_shift; /* should be 0, 8, 16 */ 1893 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1894 int hook_offset; 1895 #else 1896 void (*hook)(struct pci_dev *dev); 1897 #endif 1898 }; 1899 1900 enum pci_fixup_pass { 1901 pci_fixup_early, /* Before probing BARs */ 1902 pci_fixup_header, /* After reading configuration header */ 1903 pci_fixup_final, /* Final phase of device fixups */ 1904 pci_fixup_enable, /* pci_enable_device() time */ 1905 pci_fixup_resume, /* pci_device_resume() */ 1906 pci_fixup_suspend, /* pci_device_suspend() */ 1907 pci_fixup_resume_early, /* pci_device_resume_early() */ 1908 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1909 }; 1910 1911 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1912 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1913 class_shift, hook) \ 1914 __ADDRESSABLE(hook) \ 1915 asm(".section " #sec ", \"a\" \n" \ 1916 ".balign 16 \n" \ 1917 ".short " #vendor ", " #device " \n" \ 1918 ".long " #class ", " #class_shift " \n" \ 1919 ".long " #hook " - . \n" \ 1920 ".previous \n"); 1921 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1922 class_shift, hook) \ 1923 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1924 class_shift, hook) 1925 #else 1926 /* Anonymous variables would be nice... */ 1927 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1928 class_shift, hook) \ 1929 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1930 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1931 = { vendor, device, class, class_shift, hook }; 1932 #endif 1933 1934 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1935 class_shift, hook) \ 1936 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1937 hook, vendor, device, class, class_shift, hook) 1938 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1939 class_shift, hook) \ 1940 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1941 hook, vendor, device, class, class_shift, hook) 1942 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1943 class_shift, hook) \ 1944 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1945 hook, vendor, device, class, class_shift, hook) 1946 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1947 class_shift, hook) \ 1948 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1949 hook, vendor, device, class, class_shift, hook) 1950 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1951 class_shift, hook) \ 1952 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1953 resume##hook, vendor, device, class, class_shift, hook) 1954 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1955 class_shift, hook) \ 1956 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1957 resume_early##hook, vendor, device, class, class_shift, hook) 1958 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1959 class_shift, hook) \ 1960 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1961 suspend##hook, vendor, device, class, class_shift, hook) 1962 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1963 class_shift, hook) \ 1964 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1965 suspend_late##hook, vendor, device, class, class_shift, hook) 1966 1967 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1968 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1969 hook, vendor, device, PCI_ANY_ID, 0, hook) 1970 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1971 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1972 hook, vendor, device, PCI_ANY_ID, 0, hook) 1973 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1974 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1975 hook, vendor, device, PCI_ANY_ID, 0, hook) 1976 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1977 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1978 hook, vendor, device, PCI_ANY_ID, 0, hook) 1979 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1980 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1981 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1982 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1983 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1984 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1985 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1986 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1987 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1988 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1989 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1990 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1991 1992 #ifdef CONFIG_PCI_QUIRKS 1993 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1994 #else 1995 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1996 struct pci_dev *dev) { } 1997 #endif 1998 1999 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2000 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2001 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2002 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2003 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2004 const char *name); 2005 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2006 2007 extern int pci_pci_problems; 2008 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2009 #define PCIPCI_TRITON 2 2010 #define PCIPCI_NATOMA 4 2011 #define PCIPCI_VIAETBF 8 2012 #define PCIPCI_VSFX 16 2013 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2014 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2015 2016 extern unsigned long pci_cardbus_io_size; 2017 extern unsigned long pci_cardbus_mem_size; 2018 extern u8 pci_dfl_cache_line_size; 2019 extern u8 pci_cache_line_size; 2020 2021 /* Architecture-specific versions may override these (weak) */ 2022 void pcibios_disable_device(struct pci_dev *dev); 2023 void pcibios_set_master(struct pci_dev *dev); 2024 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2025 enum pcie_reset_state state); 2026 int pcibios_add_device(struct pci_dev *dev); 2027 void pcibios_release_device(struct pci_dev *dev); 2028 #ifdef CONFIG_PCI 2029 void pcibios_penalize_isa_irq(int irq, int active); 2030 #else 2031 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2032 #endif 2033 int pcibios_alloc_irq(struct pci_dev *dev); 2034 void pcibios_free_irq(struct pci_dev *dev); 2035 resource_size_t pcibios_default_alignment(void); 2036 2037 #ifdef CONFIG_HIBERNATE_CALLBACKS 2038 extern struct dev_pm_ops pcibios_pm_ops; 2039 #endif 2040 2041 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2042 void __init pci_mmcfg_early_init(void); 2043 void __init pci_mmcfg_late_init(void); 2044 #else 2045 static inline void pci_mmcfg_early_init(void) { } 2046 static inline void pci_mmcfg_late_init(void) { } 2047 #endif 2048 2049 int pci_ext_cfg_avail(void); 2050 2051 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2052 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2053 2054 #ifdef CONFIG_PCI_IOV 2055 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2056 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2057 2058 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2059 void pci_disable_sriov(struct pci_dev *dev); 2060 2061 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2062 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2063 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2064 int pci_num_vf(struct pci_dev *dev); 2065 int pci_vfs_assigned(struct pci_dev *dev); 2066 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2067 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2068 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2069 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2070 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2071 2072 /* Arch may override these (weak) */ 2073 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2074 int pcibios_sriov_disable(struct pci_dev *pdev); 2075 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2076 #else 2077 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2078 { 2079 return -ENOSYS; 2080 } 2081 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2082 { 2083 return -ENOSYS; 2084 } 2085 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2086 { return -ENODEV; } 2087 2088 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2089 struct pci_dev *virtfn, int id) 2090 { 2091 return -ENODEV; 2092 } 2093 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2094 { 2095 return -ENOSYS; 2096 } 2097 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2098 int id) { } 2099 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2100 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2101 static inline int pci_vfs_assigned(struct pci_dev *dev) 2102 { return 0; } 2103 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2104 { return 0; } 2105 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2106 { return 0; } 2107 #define pci_sriov_configure_simple NULL 2108 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2109 { return 0; } 2110 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2111 #endif 2112 2113 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2114 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2115 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2116 #endif 2117 2118 /** 2119 * pci_pcie_cap - get the saved PCIe capability offset 2120 * @dev: PCI device 2121 * 2122 * PCIe capability offset is calculated at PCI device initialization 2123 * time and saved in the data structure. This function returns saved 2124 * PCIe capability offset. Using this instead of pci_find_capability() 2125 * reduces unnecessary search in the PCI configuration space. If you 2126 * need to calculate PCIe capability offset from raw device for some 2127 * reasons, please use pci_find_capability() instead. 2128 */ 2129 static inline int pci_pcie_cap(struct pci_dev *dev) 2130 { 2131 return dev->pcie_cap; 2132 } 2133 2134 /** 2135 * pci_is_pcie - check if the PCI device is PCI Express capable 2136 * @dev: PCI device 2137 * 2138 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2139 */ 2140 static inline bool pci_is_pcie(struct pci_dev *dev) 2141 { 2142 return pci_pcie_cap(dev); 2143 } 2144 2145 /** 2146 * pcie_caps_reg - get the PCIe Capabilities Register 2147 * @dev: PCI device 2148 */ 2149 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2150 { 2151 return dev->pcie_flags_reg; 2152 } 2153 2154 /** 2155 * pci_pcie_type - get the PCIe device/port type 2156 * @dev: PCI device 2157 */ 2158 static inline int pci_pcie_type(const struct pci_dev *dev) 2159 { 2160 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2161 } 2162 2163 /** 2164 * pcie_find_root_port - Get the PCIe root port device 2165 * @dev: PCI device 2166 * 2167 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2168 * for a given PCI/PCIe Device. 2169 */ 2170 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2171 { 2172 struct pci_dev *bridge = pci_upstream_bridge(dev); 2173 2174 while (bridge) { 2175 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) 2176 return bridge; 2177 bridge = pci_upstream_bridge(bridge); 2178 } 2179 2180 return NULL; 2181 } 2182 2183 void pci_request_acs(void); 2184 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2185 bool pci_acs_path_enabled(struct pci_dev *start, 2186 struct pci_dev *end, u16 acs_flags); 2187 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2188 2189 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2190 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2191 2192 /* Large Resource Data Type Tag Item Names */ 2193 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2194 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2195 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2196 2197 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2198 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2199 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2200 2201 /* Small Resource Data Type Tag Item Names */ 2202 #define PCI_VPD_STIN_END 0x0f /* End */ 2203 2204 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2205 2206 #define PCI_VPD_SRDT_TIN_MASK 0x78 2207 #define PCI_VPD_SRDT_LEN_MASK 0x07 2208 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2209 2210 #define PCI_VPD_LRDT_TAG_SIZE 3 2211 #define PCI_VPD_SRDT_TAG_SIZE 1 2212 2213 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2214 2215 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2216 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2217 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2218 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2219 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2220 2221 /** 2222 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2223 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2224 * 2225 * Returns the extracted Large Resource Data Type length. 2226 */ 2227 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2228 { 2229 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2230 } 2231 2232 /** 2233 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2234 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2235 * 2236 * Returns the extracted Large Resource Data Type Tag item. 2237 */ 2238 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2239 { 2240 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2241 } 2242 2243 /** 2244 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2245 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2246 * 2247 * Returns the extracted Small Resource Data Type length. 2248 */ 2249 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2250 { 2251 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2252 } 2253 2254 /** 2255 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2256 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2257 * 2258 * Returns the extracted Small Resource Data Type Tag Item. 2259 */ 2260 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2261 { 2262 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2263 } 2264 2265 /** 2266 * pci_vpd_info_field_size - Extracts the information field length 2267 * @info_field: Pointer to the beginning of an information field header 2268 * 2269 * Returns the extracted information field length. 2270 */ 2271 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2272 { 2273 return info_field[2]; 2274 } 2275 2276 /** 2277 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2278 * @buf: Pointer to buffered vpd data 2279 * @off: The offset into the buffer at which to begin the search 2280 * @len: The length of the vpd buffer 2281 * @rdt: The Resource Data Type to search for 2282 * 2283 * Returns the index where the Resource Data Type was found or 2284 * -ENOENT otherwise. 2285 */ 2286 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2287 2288 /** 2289 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2290 * @buf: Pointer to buffered vpd data 2291 * @off: The offset into the buffer at which to begin the search 2292 * @len: The length of the buffer area, relative to off, in which to search 2293 * @kw: The keyword to search for 2294 * 2295 * Returns the index where the information field keyword was found or 2296 * -ENOENT otherwise. 2297 */ 2298 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2299 unsigned int len, const char *kw); 2300 2301 /* PCI <-> OF binding helpers */ 2302 #ifdef CONFIG_OF 2303 struct device_node; 2304 struct irq_domain; 2305 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2306 int pci_parse_request_of_pci_ranges(struct device *dev, 2307 struct list_head *resources, 2308 struct list_head *ib_resources, 2309 struct resource **bus_range); 2310 2311 /* Arch may override this (weak) */ 2312 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2313 2314 #else /* CONFIG_OF */ 2315 static inline struct irq_domain * 2316 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2317 static inline int 2318 pci_parse_request_of_pci_ranges(struct device *dev, 2319 struct list_head *resources, 2320 struct list_head *ib_resources, 2321 struct resource **bus_range) 2322 { 2323 return -EINVAL; 2324 } 2325 #endif /* CONFIG_OF */ 2326 2327 static inline struct device_node * 2328 pci_device_to_OF_node(const struct pci_dev *pdev) 2329 { 2330 return pdev ? pdev->dev.of_node : NULL; 2331 } 2332 2333 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2334 { 2335 return bus ? bus->dev.of_node : NULL; 2336 } 2337 2338 #ifdef CONFIG_ACPI 2339 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2340 2341 void 2342 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2343 bool pci_pr3_present(struct pci_dev *pdev); 2344 #else 2345 static inline struct irq_domain * 2346 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2347 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2348 #endif 2349 2350 #ifdef CONFIG_EEH 2351 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2352 { 2353 return pdev->dev.archdata.edev; 2354 } 2355 #endif 2356 2357 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2358 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2359 int pci_for_each_dma_alias(struct pci_dev *pdev, 2360 int (*fn)(struct pci_dev *pdev, 2361 u16 alias, void *data), void *data); 2362 2363 /* Helper functions for operation of device flag */ 2364 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2365 { 2366 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2367 } 2368 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2369 { 2370 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2371 } 2372 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2373 { 2374 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2375 } 2376 2377 /** 2378 * pci_ari_enabled - query ARI forwarding status 2379 * @bus: the PCI bus 2380 * 2381 * Returns true if ARI forwarding is enabled. 2382 */ 2383 static inline bool pci_ari_enabled(struct pci_bus *bus) 2384 { 2385 return bus->self && bus->self->ari_enabled; 2386 } 2387 2388 /** 2389 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2390 * @pdev: PCI device to check 2391 * 2392 * Walk upwards from @pdev and check for each encountered bridge if it's part 2393 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2394 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2395 */ 2396 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2397 { 2398 struct pci_dev *parent = pdev; 2399 2400 if (pdev->is_thunderbolt) 2401 return true; 2402 2403 while ((parent = pci_upstream_bridge(parent))) 2404 if (parent->is_thunderbolt) 2405 return true; 2406 2407 return false; 2408 } 2409 2410 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2411 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2412 #endif 2413 2414 /* Provide the legacy pci_dma_* API */ 2415 #include <linux/pci-dma-compat.h> 2416 2417 #define pci_printk(level, pdev, fmt, arg...) \ 2418 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2419 2420 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2421 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2422 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2423 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2424 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2425 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2426 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2427 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2428 2429 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2430 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2431 2432 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2433 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2434 2435 #define pci_WARN(pdev, condition, fmt, arg...) \ 2436 WARN(condition, "%s %s: " fmt, \ 2437 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2438 2439 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2440 WARN_ONCE(condition, "%s %s: " fmt, \ 2441 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2442 2443 #endif /* LINUX_PCI_H */ 2444