1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * For more information, please consult the following manuals (look at 10 * http://www.pcisig.com/ for how to get them): 11 * 12 * PCI BIOS Specification 13 * PCI Local Bus Specification 14 * PCI to PCI Bridge Specification 15 * PCI System Design Guide 16 */ 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 21 #include <linux/mod_devicetable.h> 22 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/list.h> 27 #include <linux/compiler.h> 28 #include <linux/errno.h> 29 #include <linux/kobject.h> 30 #include <linux/atomic.h> 31 #include <linux/device.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/resource_ext.h> 35 #include <uapi/linux/pci.h> 36 37 #include <linux/pci_ids.h> 38 39 /* 40 * The PCI interface treats multi-function devices as independent 41 * devices. The slot/function address of each device is encoded 42 * in a single byte as follows: 43 * 44 * 7:3 = slot 45 * 2:0 = function 46 * 47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 48 * In the interest of not exposing interfaces to user-space unnecessarily, 49 * the following kernel-only defines are being added here. 50 */ 51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 54 55 /* pci_slot represents a physical slot */ 56 struct pci_slot { 57 struct pci_bus *bus; /* Bus this slot is on */ 58 struct list_head list; /* Node in list of slots */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 61 struct kobject kobj; 62 }; 63 64 static inline const char *pci_slot_name(const struct pci_slot *slot) 65 { 66 return kobject_name(&slot->kobj); 67 } 68 69 /* File state for mmap()s on /proc/bus/pci/X/Y */ 70 enum pci_mmap_state { 71 pci_mmap_io, 72 pci_mmap_mem 73 }; 74 75 /* For PCI devices, the region numbers are assigned this way: */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* Device-specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* Resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* Total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* Preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 /** 105 * enum pci_interrupt_pin - PCI INTx interrupt values 106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 107 * @PCI_INTERRUPT_INTA: PCI INTA pin 108 * @PCI_INTERRUPT_INTB: PCI INTB pin 109 * @PCI_INTERRUPT_INTC: PCI INTC pin 110 * @PCI_INTERRUPT_INTD: PCI INTD pin 111 * 112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 113 * PCI_INTERRUPT_PIN register. 114 */ 115 enum pci_interrupt_pin { 116 PCI_INTERRUPT_UNKNOWN, 117 PCI_INTERRUPT_INTA, 118 PCI_INTERRUPT_INTB, 119 PCI_INTERRUPT_INTC, 120 PCI_INTERRUPT_INTD, 121 }; 122 123 /* The number of legacy PCI INTx interrupts */ 124 #define PCI_NUM_INTX 4 125 126 /* 127 * pci_power_t values must match the bits in the Capabilities PME_Support 128 * and Control/Status PowerState fields in the Power Management capability. 129 */ 130 typedef int __bitwise pci_power_t; 131 132 #define PCI_D0 ((pci_power_t __force) 0) 133 #define PCI_D1 ((pci_power_t __force) 1) 134 #define PCI_D2 ((pci_power_t __force) 2) 135 #define PCI_D3hot ((pci_power_t __force) 3) 136 #define PCI_D3cold ((pci_power_t __force) 4) 137 #define PCI_UNKNOWN ((pci_power_t __force) 5) 138 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 139 140 /* Remember to update this when the list above changes! */ 141 extern const char *pci_power_names[]; 142 143 static inline const char *pci_power_name(pci_power_t state) 144 { 145 return pci_power_names[1 + (__force int) state]; 146 } 147 148 #define PCI_PM_D2_DELAY 200 149 #define PCI_PM_D3_WAIT 10 150 #define PCI_PM_D3COLD_WAIT 100 151 #define PCI_PM_BUS_WAIT 50 152 153 /** 154 * The pci_channel state describes connectivity between the CPU and 155 * the PCI device. If some PCI bus between here and the PCI device 156 * has crashed or locked up, this info is reflected here. 157 */ 158 typedef unsigned int __bitwise pci_channel_state_t; 159 160 enum pci_channel_state { 161 /* I/O channel is in normal state */ 162 pci_channel_io_normal = (__force pci_channel_state_t) 1, 163 164 /* I/O to channel is blocked */ 165 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 166 167 /* PCI card is dead */ 168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 169 }; 170 171 typedef unsigned int __bitwise pcie_reset_state_t; 172 173 enum pcie_reset_state { 174 /* Reset is NOT asserted (Use to deassert reset) */ 175 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 176 177 /* Use #PERST to reset PCIe device */ 178 pcie_warm_reset = (__force pcie_reset_state_t) 2, 179 180 /* Use PCIe Hot Reset to reset device */ 181 pcie_hot_reset = (__force pcie_reset_state_t) 3 182 }; 183 184 typedef unsigned short __bitwise pci_dev_flags_t; 185 enum pci_dev_flags { 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 188 /* Device configuration is irrevocably lost if disabled into D3 */ 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 190 /* Provide indication device is assigned by a Virtual Machine Manager */ 191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 192 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 196 /* Do not use bus resets for device */ 197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 198 /* Do not use PM reset even if device advertises NoSoftRst- */ 199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 200 /* Get VPD from function 0 VPD */ 201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 202 /* A non-root bridge where translation occurs, stop alias search here */ 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 204 /* Do not use FLR even if device advertises PCI_AF_CAP */ 205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 206 /* Don't use Relaxed Ordering for TLPs directed at this device */ 207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 208 }; 209 210 enum pci_irq_reroute_variant { 211 INTEL_IRQ_REROUTE_VARIANT = 1, 212 MAX_IRQ_REROUTE_VARIANTS = 3 213 }; 214 215 typedef unsigned short __bitwise pci_bus_flags_t; 216 enum pci_bus_flags { 217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 221 }; 222 223 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 224 enum pcie_link_width { 225 PCIE_LNK_WIDTH_RESRV = 0x00, 226 PCIE_LNK_X1 = 0x01, 227 PCIE_LNK_X2 = 0x02, 228 PCIE_LNK_X4 = 0x04, 229 PCIE_LNK_X8 = 0x08, 230 PCIE_LNK_X12 = 0x0c, 231 PCIE_LNK_X16 = 0x10, 232 PCIE_LNK_X32 = 0x20, 233 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 234 }; 235 236 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 237 enum pci_bus_speed { 238 PCI_SPEED_33MHz = 0x00, 239 PCI_SPEED_66MHz = 0x01, 240 PCI_SPEED_66MHz_PCIX = 0x02, 241 PCI_SPEED_100MHz_PCIX = 0x03, 242 PCI_SPEED_133MHz_PCIX = 0x04, 243 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 244 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 245 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 246 PCI_SPEED_66MHz_PCIX_266 = 0x09, 247 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 248 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 249 AGP_UNKNOWN = 0x0c, 250 AGP_1X = 0x0d, 251 AGP_2X = 0x0e, 252 AGP_4X = 0x0f, 253 AGP_8X = 0x10, 254 PCI_SPEED_66MHz_PCIX_533 = 0x11, 255 PCI_SPEED_100MHz_PCIX_533 = 0x12, 256 PCI_SPEED_133MHz_PCIX_533 = 0x13, 257 PCIE_SPEED_2_5GT = 0x14, 258 PCIE_SPEED_5_0GT = 0x15, 259 PCIE_SPEED_8_0GT = 0x16, 260 PCIE_SPEED_16_0GT = 0x17, 261 PCI_SPEED_UNKNOWN = 0xff, 262 }; 263 264 struct pci_cap_saved_data { 265 u16 cap_nr; 266 bool cap_extended; 267 unsigned int size; 268 u32 data[0]; 269 }; 270 271 struct pci_cap_saved_state { 272 struct hlist_node next; 273 struct pci_cap_saved_data cap; 274 }; 275 276 struct irq_affinity; 277 struct pcie_link_state; 278 struct pci_vpd; 279 struct pci_sriov; 280 struct pci_ats; 281 282 /* The pci_dev structure describes PCI devices */ 283 struct pci_dev { 284 struct list_head bus_list; /* Node in per-bus list */ 285 struct pci_bus *bus; /* Bus this device is on */ 286 struct pci_bus *subordinate; /* Bus this device bridges to */ 287 288 void *sysdata; /* Hook for sys-specific extension */ 289 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 290 struct pci_slot *slot; /* Physical slot this device is in */ 291 292 unsigned int devfn; /* Encoded device & function index */ 293 unsigned short vendor; 294 unsigned short device; 295 unsigned short subsystem_vendor; 296 unsigned short subsystem_device; 297 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 298 u8 revision; /* PCI revision, low byte of class word */ 299 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 300 #ifdef CONFIG_PCIEAER 301 u16 aer_cap; /* AER capability offset */ 302 #endif 303 u8 pcie_cap; /* PCIe capability offset */ 304 u8 msi_cap; /* MSI capability offset */ 305 u8 msix_cap; /* MSI-X capability offset */ 306 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 307 u8 rom_base_reg; /* Config register controlling ROM */ 308 u8 pin; /* Interrupt pin this device uses */ 309 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 310 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 311 312 struct pci_driver *driver; /* Driver bound to this device */ 313 u64 dma_mask; /* Mask of the bits of bus address this 314 device implements. Normally this is 315 0xffffffff. You only need to change 316 this if your device has broken DMA 317 or supports 64-bit transfers. */ 318 319 struct device_dma_parameters dma_parms; 320 321 pci_power_t current_state; /* Current operating state. In ACPI, 322 this is D0-D3, D0 being fully 323 functional, and D3 being off. */ 324 u8 pm_cap; /* PM capability offset */ 325 unsigned int pme_support:5; /* Bitmask of states from which PME# 326 can be generated */ 327 unsigned int pme_poll:1; /* Poll device's PME status bit */ 328 unsigned int d1_support:1; /* Low power state D1 is supported */ 329 unsigned int d2_support:1; /* Low power state D2 is supported */ 330 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 331 unsigned int no_d3cold:1; /* D3cold is forbidden */ 332 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 333 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 334 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 335 decoding during BAR sizing */ 336 unsigned int wakeup_prepared:1; 337 unsigned int runtime_d3cold:1; /* Whether go through runtime 338 D3cold, not set for devices 339 powered on/off by the 340 corresponding bridge */ 341 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 342 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 343 controlled exclusively by 344 user sysfs */ 345 unsigned int d3_delay; /* D3->D0 transition time in ms */ 346 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 347 348 #ifdef CONFIG_PCIEASPM 349 struct pcie_link_state *link_state; /* ASPM link state */ 350 unsigned int ltr_path:1; /* Latency Tolerance Reporting 351 supported from root to here */ 352 #endif 353 354 pci_channel_state_t error_state; /* Current connectivity state */ 355 struct device dev; /* Generic device interface */ 356 357 int cfg_size; /* Size of config space */ 358 359 /* 360 * Instead of touching interrupt line and base address registers 361 * directly, use the values stored here. They might be different! 362 */ 363 unsigned int irq; 364 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 365 366 bool match_driver; /* Skip attaching driver */ 367 368 unsigned int transparent:1; /* Subtractive decode bridge */ 369 unsigned int multifunction:1; /* Multi-function device */ 370 371 unsigned int is_added:1; 372 unsigned int is_busmaster:1; /* Is busmaster */ 373 unsigned int no_msi:1; /* May not use MSI */ 374 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 375 unsigned int block_cfg_access:1; /* Config space access blocked */ 376 unsigned int broken_parity_status:1; /* Generates false positive parity */ 377 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 378 unsigned int msi_enabled:1; 379 unsigned int msix_enabled:1; 380 unsigned int ari_enabled:1; /* ARI forwarding */ 381 unsigned int ats_enabled:1; /* Address Translation Svc */ 382 unsigned int pasid_enabled:1; /* Process Address Space ID */ 383 unsigned int pri_enabled:1; /* Page Request Interface */ 384 unsigned int is_managed:1; 385 unsigned int needs_freset:1; /* Requires fundamental reset */ 386 unsigned int state_saved:1; 387 unsigned int is_physfn:1; 388 unsigned int is_virtfn:1; 389 unsigned int reset_fn:1; 390 unsigned int is_hotplug_bridge:1; 391 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 392 unsigned int __aer_firmware_first_valid:1; 393 unsigned int __aer_firmware_first:1; 394 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 395 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 396 unsigned int irq_managed:1; 397 unsigned int has_secondary_link:1; 398 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 399 unsigned int is_probed:1; /* Device probing in progress */ 400 pci_dev_flags_t dev_flags; 401 atomic_t enable_cnt; /* pci_enable_device has been called */ 402 403 u32 saved_config_space[16]; /* Config space saved at suspend time */ 404 struct hlist_head saved_cap_space; 405 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 406 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 407 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 408 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 409 410 #ifdef CONFIG_HOTPLUG_PCI_PCIE 411 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 412 #endif 413 #ifdef CONFIG_PCIE_PTM 414 unsigned int ptm_root:1; 415 unsigned int ptm_enabled:1; 416 u8 ptm_granularity; 417 #endif 418 #ifdef CONFIG_PCI_MSI 419 const struct attribute_group **msi_irq_groups; 420 #endif 421 struct pci_vpd *vpd; 422 #ifdef CONFIG_PCI_ATS 423 union { 424 struct pci_sriov *sriov; /* PF: SR-IOV info */ 425 struct pci_dev *physfn; /* VF: related PF */ 426 }; 427 u16 ats_cap; /* ATS Capability offset */ 428 u8 ats_stu; /* ATS Smallest Translation Unit */ 429 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ 430 #endif 431 #ifdef CONFIG_PCI_PRI 432 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 433 #endif 434 #ifdef CONFIG_PCI_PASID 435 u16 pasid_features; 436 #endif 437 phys_addr_t rom; /* Physical address if not from BAR */ 438 size_t romlen; /* Length if not from BAR */ 439 char *driver_override; /* Driver name to force a match */ 440 441 unsigned long priv_flags; /* Private flags for the PCI driver */ 442 }; 443 444 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 445 { 446 #ifdef CONFIG_PCI_IOV 447 if (dev->is_virtfn) 448 dev = dev->physfn; 449 #endif 450 return dev; 451 } 452 453 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 454 455 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 456 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 457 458 static inline int pci_channel_offline(struct pci_dev *pdev) 459 { 460 return (pdev->error_state != pci_channel_io_normal); 461 } 462 463 struct pci_host_bridge { 464 struct device dev; 465 struct pci_bus *bus; /* Root bus */ 466 struct pci_ops *ops; 467 void *sysdata; 468 int busnr; 469 struct list_head windows; /* resource_entry */ 470 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 471 int (*map_irq)(const struct pci_dev *, u8, u8); 472 void (*release_fn)(struct pci_host_bridge *); 473 void *release_data; 474 struct msi_controller *msi; 475 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 476 unsigned int no_ext_tags:1; /* No Extended Tags */ 477 unsigned int native_aer:1; /* OS may use PCIe AER */ 478 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 479 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 480 unsigned int native_pme:1; /* OS may use PCIe PME */ 481 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 482 /* Resource alignment requirements */ 483 resource_size_t (*align_resource)(struct pci_dev *dev, 484 const struct resource *res, 485 resource_size_t start, 486 resource_size_t size, 487 resource_size_t align); 488 unsigned long private[0] ____cacheline_aligned; 489 }; 490 491 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 492 493 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 494 { 495 return (void *)bridge->private; 496 } 497 498 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 499 { 500 return container_of(priv, struct pci_host_bridge, private); 501 } 502 503 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 504 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 505 size_t priv); 506 void pci_free_host_bridge(struct pci_host_bridge *bridge); 507 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 508 509 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 510 void (*release_fn)(struct pci_host_bridge *), 511 void *release_data); 512 513 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 514 515 /* 516 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 517 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 518 * buses below host bridges or subtractive decode bridges) go in the list. 519 * Use pci_bus_for_each_resource() to iterate through all the resources. 520 */ 521 522 /* 523 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 524 * and there's no way to program the bridge with the details of the window. 525 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 526 * decode bit set, because they are explicit and can be programmed with _SRS. 527 */ 528 #define PCI_SUBTRACTIVE_DECODE 0x1 529 530 struct pci_bus_resource { 531 struct list_head list; 532 struct resource *res; 533 unsigned int flags; 534 }; 535 536 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 537 538 struct pci_bus { 539 struct list_head node; /* Node in list of buses */ 540 struct pci_bus *parent; /* Parent bus this bridge is on */ 541 struct list_head children; /* List of child buses */ 542 struct list_head devices; /* List of devices on this bus */ 543 struct pci_dev *self; /* Bridge device as seen by parent */ 544 struct list_head slots; /* List of slots on this bus; 545 protected by pci_slot_mutex */ 546 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 547 struct list_head resources; /* Address space routed to this bus */ 548 struct resource busn_res; /* Bus numbers routed to this bus */ 549 550 struct pci_ops *ops; /* Configuration access functions */ 551 struct msi_controller *msi; /* MSI controller */ 552 void *sysdata; /* Hook for sys-specific extension */ 553 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 554 555 unsigned char number; /* Bus number */ 556 unsigned char primary; /* Number of primary bridge */ 557 unsigned char max_bus_speed; /* enum pci_bus_speed */ 558 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 559 #ifdef CONFIG_PCI_DOMAINS_GENERIC 560 int domain_nr; 561 #endif 562 563 char name[48]; 564 565 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 566 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 567 struct device *bridge; 568 struct device dev; 569 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 570 struct bin_attribute *legacy_mem; /* Legacy mem */ 571 unsigned int is_added:1; 572 }; 573 574 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 575 576 /* 577 * Returns true if the PCI bus is root (behind host-PCI bridge), 578 * false otherwise 579 * 580 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 581 * This is incorrect because "virtual" buses added for SR-IOV (via 582 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 583 */ 584 static inline bool pci_is_root_bus(struct pci_bus *pbus) 585 { 586 return !(pbus->parent); 587 } 588 589 /** 590 * pci_is_bridge - check if the PCI device is a bridge 591 * @dev: PCI device 592 * 593 * Return true if the PCI device is bridge whether it has subordinate 594 * or not. 595 */ 596 static inline bool pci_is_bridge(struct pci_dev *dev) 597 { 598 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 599 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 600 } 601 602 #define for_each_pci_bridge(dev, bus) \ 603 list_for_each_entry(dev, &bus->devices, bus_list) \ 604 if (!pci_is_bridge(dev)) {} else 605 606 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 607 { 608 dev = pci_physfn(dev); 609 if (pci_is_root_bus(dev->bus)) 610 return NULL; 611 612 return dev->bus->self; 613 } 614 615 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 616 void pci_put_host_bridge_device(struct device *dev); 617 618 #ifdef CONFIG_PCI_MSI 619 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 620 { 621 return pci_dev->msi_enabled || pci_dev->msix_enabled; 622 } 623 #else 624 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 625 #endif 626 627 /* Error values that may be returned by PCI functions */ 628 #define PCIBIOS_SUCCESSFUL 0x00 629 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 630 #define PCIBIOS_BAD_VENDOR_ID 0x83 631 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 632 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 633 #define PCIBIOS_SET_FAILED 0x88 634 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 635 636 /* Translate above to generic errno for passing back through non-PCI code */ 637 static inline int pcibios_err_to_errno(int err) 638 { 639 if (err <= PCIBIOS_SUCCESSFUL) 640 return err; /* Assume already errno */ 641 642 switch (err) { 643 case PCIBIOS_FUNC_NOT_SUPPORTED: 644 return -ENOENT; 645 case PCIBIOS_BAD_VENDOR_ID: 646 return -ENOTTY; 647 case PCIBIOS_DEVICE_NOT_FOUND: 648 return -ENODEV; 649 case PCIBIOS_BAD_REGISTER_NUMBER: 650 return -EFAULT; 651 case PCIBIOS_SET_FAILED: 652 return -EIO; 653 case PCIBIOS_BUFFER_TOO_SMALL: 654 return -ENOSPC; 655 } 656 657 return -ERANGE; 658 } 659 660 /* Low-level architecture-dependent routines */ 661 662 struct pci_ops { 663 int (*add_bus)(struct pci_bus *bus); 664 void (*remove_bus)(struct pci_bus *bus); 665 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 666 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 667 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 668 }; 669 670 /* 671 * ACPI needs to be able to access PCI config space before we've done a 672 * PCI bus scan and created pci_bus structures. 673 */ 674 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 675 int reg, int len, u32 *val); 676 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 677 int reg, int len, u32 val); 678 679 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 680 typedef u64 pci_bus_addr_t; 681 #else 682 typedef u32 pci_bus_addr_t; 683 #endif 684 685 struct pci_bus_region { 686 pci_bus_addr_t start; 687 pci_bus_addr_t end; 688 }; 689 690 struct pci_dynids { 691 spinlock_t lock; /* Protects list, index */ 692 struct list_head list; /* For IDs added at runtime */ 693 }; 694 695 696 /* 697 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 698 * a set of callbacks in struct pci_error_handlers, that device driver 699 * will be notified of PCI bus errors, and will be driven to recovery 700 * when an error occurs. 701 */ 702 703 typedef unsigned int __bitwise pci_ers_result_t; 704 705 enum pci_ers_result { 706 /* No result/none/not supported in device driver */ 707 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 708 709 /* Device driver can recover without slot reset */ 710 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 711 712 /* Device driver wants slot to be reset */ 713 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 714 715 /* Device has completely failed, is unrecoverable */ 716 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 717 718 /* Device driver is fully recovered and operational */ 719 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 720 721 /* No AER capabilities registered for the driver */ 722 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 723 }; 724 725 /* PCI bus error event callbacks */ 726 struct pci_error_handlers { 727 /* PCI bus error detected on this device */ 728 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 729 enum pci_channel_state error); 730 731 /* MMIO has been re-enabled, but not DMA */ 732 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 733 734 /* PCI slot has been reset */ 735 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 736 737 /* PCI function reset prepare or completed */ 738 void (*reset_prepare)(struct pci_dev *dev); 739 void (*reset_done)(struct pci_dev *dev); 740 741 /* Device driver may resume normal operations */ 742 void (*resume)(struct pci_dev *dev); 743 }; 744 745 746 struct module; 747 struct pci_driver { 748 struct list_head node; 749 const char *name; 750 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 751 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 752 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 753 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 754 int (*suspend_late)(struct pci_dev *dev, pm_message_t state); 755 int (*resume_early)(struct pci_dev *dev); 756 int (*resume) (struct pci_dev *dev); /* Device woken up */ 757 void (*shutdown) (struct pci_dev *dev); 758 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */ 759 const struct pci_error_handlers *err_handler; 760 const struct attribute_group **groups; 761 struct device_driver driver; 762 struct pci_dynids dynids; 763 }; 764 765 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 766 767 /** 768 * PCI_DEVICE - macro used to describe a specific PCI device 769 * @vend: the 16 bit PCI Vendor ID 770 * @dev: the 16 bit PCI Device ID 771 * 772 * This macro is used to create a struct pci_device_id that matches a 773 * specific device. The subvendor and subdevice fields will be set to 774 * PCI_ANY_ID. 775 */ 776 #define PCI_DEVICE(vend,dev) \ 777 .vendor = (vend), .device = (dev), \ 778 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 779 780 /** 781 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 782 * @vend: the 16 bit PCI Vendor ID 783 * @dev: the 16 bit PCI Device ID 784 * @subvend: the 16 bit PCI Subvendor ID 785 * @subdev: the 16 bit PCI Subdevice ID 786 * 787 * This macro is used to create a struct pci_device_id that matches a 788 * specific device with subsystem information. 789 */ 790 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 791 .vendor = (vend), .device = (dev), \ 792 .subvendor = (subvend), .subdevice = (subdev) 793 794 /** 795 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 796 * @dev_class: the class, subclass, prog-if triple for this device 797 * @dev_class_mask: the class mask for this device 798 * 799 * This macro is used to create a struct pci_device_id that matches a 800 * specific PCI class. The vendor, device, subvendor, and subdevice 801 * fields will be set to PCI_ANY_ID. 802 */ 803 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 804 .class = (dev_class), .class_mask = (dev_class_mask), \ 805 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 806 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 807 808 /** 809 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 810 * @vend: the vendor name 811 * @dev: the 16 bit PCI Device ID 812 * 813 * This macro is used to create a struct pci_device_id that matches a 814 * specific PCI device. The subvendor, and subdevice fields will be set 815 * to PCI_ANY_ID. The macro allows the next field to follow as the device 816 * private data. 817 */ 818 #define PCI_VDEVICE(vend, dev) \ 819 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 820 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 821 822 enum { 823 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 824 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 825 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 826 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 827 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 828 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 829 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 830 }; 831 832 /* These external functions are only available when PCI support is enabled */ 833 #ifdef CONFIG_PCI 834 835 extern unsigned int pci_flags; 836 837 static inline void pci_set_flags(int flags) { pci_flags = flags; } 838 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 839 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 840 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 841 842 void pcie_bus_configure_settings(struct pci_bus *bus); 843 844 enum pcie_bus_config_types { 845 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 846 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 847 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 848 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 849 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 850 }; 851 852 extern enum pcie_bus_config_types pcie_bus_config; 853 854 extern struct bus_type pci_bus_type; 855 856 /* Do NOT directly access these two variables, unless you are arch-specific PCI 857 * code, or PCI core code. */ 858 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 859 /* Some device drivers need know if PCI is initiated */ 860 int no_pci_devices(void); 861 862 void pcibios_resource_survey_bus(struct pci_bus *bus); 863 void pcibios_bus_add_device(struct pci_dev *pdev); 864 void pcibios_add_bus(struct pci_bus *bus); 865 void pcibios_remove_bus(struct pci_bus *bus); 866 void pcibios_fixup_bus(struct pci_bus *); 867 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 868 /* Architecture-specific versions may override this (weak) */ 869 char *pcibios_setup(char *str); 870 871 /* Used only when drivers/pci/setup.c is used */ 872 resource_size_t pcibios_align_resource(void *, const struct resource *, 873 resource_size_t, 874 resource_size_t); 875 876 /* Weak but can be overriden by arch */ 877 void pci_fixup_cardbus(struct pci_bus *); 878 879 /* Generic PCI functions used internally */ 880 881 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 882 struct resource *res); 883 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 884 struct pci_bus_region *region); 885 void pcibios_scan_specific_bus(int busn); 886 struct pci_bus *pci_find_bus(int domain, int busnr); 887 void pci_bus_add_devices(const struct pci_bus *bus); 888 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 889 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 890 struct pci_ops *ops, void *sysdata, 891 struct list_head *resources); 892 int pci_host_probe(struct pci_host_bridge *bridge); 893 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 894 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 895 void pci_bus_release_busn_res(struct pci_bus *b); 896 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 897 struct pci_ops *ops, void *sysdata, 898 struct list_head *resources); 899 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 900 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 901 int busnr); 902 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 903 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 904 const char *name, 905 struct hotplug_slot *hotplug); 906 void pci_destroy_slot(struct pci_slot *slot); 907 #ifdef CONFIG_SYSFS 908 void pci_dev_assign_slot(struct pci_dev *dev); 909 #else 910 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 911 #endif 912 int pci_scan_slot(struct pci_bus *bus, int devfn); 913 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 914 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 915 unsigned int pci_scan_child_bus(struct pci_bus *bus); 916 void pci_bus_add_device(struct pci_dev *dev); 917 void pci_read_bridge_bases(struct pci_bus *child); 918 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 919 struct resource *res); 920 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 921 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 922 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 923 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 924 struct pci_dev *pci_dev_get(struct pci_dev *dev); 925 void pci_dev_put(struct pci_dev *dev); 926 void pci_remove_bus(struct pci_bus *b); 927 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 928 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 929 void pci_stop_root_bus(struct pci_bus *bus); 930 void pci_remove_root_bus(struct pci_bus *bus); 931 void pci_setup_cardbus(struct pci_bus *bus); 932 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 933 void pci_sort_breadthfirst(void); 934 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 935 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 936 937 /* Generic PCI functions exported to card drivers */ 938 939 enum pci_lost_interrupt_reason { 940 PCI_LOST_IRQ_NO_INFORMATION = 0, 941 PCI_LOST_IRQ_DISABLE_MSI, 942 PCI_LOST_IRQ_DISABLE_MSIX, 943 PCI_LOST_IRQ_DISABLE_ACPI, 944 }; 945 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 946 int pci_find_capability(struct pci_dev *dev, int cap); 947 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 948 int pci_find_ext_capability(struct pci_dev *dev, int cap); 949 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 950 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 951 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 952 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 953 954 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 955 struct pci_dev *from); 956 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 957 unsigned int ss_vendor, unsigned int ss_device, 958 struct pci_dev *from); 959 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 960 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 961 unsigned int devfn); 962 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 963 int pci_dev_present(const struct pci_device_id *ids); 964 965 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 966 int where, u8 *val); 967 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 968 int where, u16 *val); 969 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 970 int where, u32 *val); 971 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 972 int where, u8 val); 973 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 974 int where, u16 val); 975 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 976 int where, u32 val); 977 978 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 979 int where, int size, u32 *val); 980 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 981 int where, int size, u32 val); 982 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 983 int where, int size, u32 *val); 984 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 985 int where, int size, u32 val); 986 987 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 988 989 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 990 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 991 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 992 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 993 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 994 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 995 996 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 997 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 998 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 999 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1000 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1001 u16 clear, u16 set); 1002 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1003 u32 clear, u32 set); 1004 1005 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1006 u16 set) 1007 { 1008 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1009 } 1010 1011 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1012 u32 set) 1013 { 1014 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1015 } 1016 1017 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1018 u16 clear) 1019 { 1020 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1021 } 1022 1023 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1024 u32 clear) 1025 { 1026 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1027 } 1028 1029 /* User-space driven config access */ 1030 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1031 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1032 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1033 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1034 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1035 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1036 1037 int __must_check pci_enable_device(struct pci_dev *dev); 1038 int __must_check pci_enable_device_io(struct pci_dev *dev); 1039 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1040 int __must_check pci_reenable_device(struct pci_dev *); 1041 int __must_check pcim_enable_device(struct pci_dev *pdev); 1042 void pcim_pin_device(struct pci_dev *pdev); 1043 1044 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1045 { 1046 /* 1047 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1048 * writable and no quirk has marked the feature broken. 1049 */ 1050 return !pdev->broken_intx_masking; 1051 } 1052 1053 static inline int pci_is_enabled(struct pci_dev *pdev) 1054 { 1055 return (atomic_read(&pdev->enable_cnt) > 0); 1056 } 1057 1058 static inline int pci_is_managed(struct pci_dev *pdev) 1059 { 1060 return pdev->is_managed; 1061 } 1062 1063 void pci_disable_device(struct pci_dev *dev); 1064 1065 extern unsigned int pcibios_max_latency; 1066 void pci_set_master(struct pci_dev *dev); 1067 void pci_clear_master(struct pci_dev *dev); 1068 1069 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1070 int pci_set_cacheline_size(struct pci_dev *dev); 1071 #define HAVE_PCI_SET_MWI 1072 int __must_check pci_set_mwi(struct pci_dev *dev); 1073 int __must_check pcim_set_mwi(struct pci_dev *dev); 1074 int pci_try_set_mwi(struct pci_dev *dev); 1075 void pci_clear_mwi(struct pci_dev *dev); 1076 void pci_intx(struct pci_dev *dev, int enable); 1077 bool pci_check_and_mask_intx(struct pci_dev *dev); 1078 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1079 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1080 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1081 int pcix_get_max_mmrbc(struct pci_dev *dev); 1082 int pcix_get_mmrbc(struct pci_dev *dev); 1083 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1084 int pcie_get_readrq(struct pci_dev *dev); 1085 int pcie_set_readrq(struct pci_dev *dev, int rq); 1086 int pcie_get_mps(struct pci_dev *dev); 1087 int pcie_set_mps(struct pci_dev *dev, int mps); 1088 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1089 enum pci_bus_speed *speed, 1090 enum pcie_link_width *width); 1091 void pcie_print_link_status(struct pci_dev *dev); 1092 int pcie_flr(struct pci_dev *dev); 1093 int __pci_reset_function_locked(struct pci_dev *dev); 1094 int pci_reset_function(struct pci_dev *dev); 1095 int pci_reset_function_locked(struct pci_dev *dev); 1096 int pci_try_reset_function(struct pci_dev *dev); 1097 int pci_probe_reset_slot(struct pci_slot *slot); 1098 int pci_reset_slot(struct pci_slot *slot); 1099 int pci_try_reset_slot(struct pci_slot *slot); 1100 int pci_probe_reset_bus(struct pci_bus *bus); 1101 int pci_reset_bus(struct pci_bus *bus); 1102 int pci_try_reset_bus(struct pci_bus *bus); 1103 void pci_reset_secondary_bus(struct pci_dev *dev); 1104 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1105 int pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1106 void pci_update_resource(struct pci_dev *dev, int resno); 1107 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1108 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1109 void pci_release_resource(struct pci_dev *dev, int resno); 1110 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1111 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1112 bool pci_device_is_present(struct pci_dev *pdev); 1113 void pci_ignore_hotplug(struct pci_dev *dev); 1114 1115 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1116 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1117 const char *fmt, ...); 1118 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1119 1120 /* ROM control related routines */ 1121 int pci_enable_rom(struct pci_dev *pdev); 1122 void pci_disable_rom(struct pci_dev *pdev); 1123 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1124 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1125 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1126 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1127 1128 /* Power management related routines */ 1129 int pci_save_state(struct pci_dev *dev); 1130 void pci_restore_state(struct pci_dev *dev); 1131 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1132 int pci_load_saved_state(struct pci_dev *dev, 1133 struct pci_saved_state *state); 1134 int pci_load_and_free_saved_state(struct pci_dev *dev, 1135 struct pci_saved_state **state); 1136 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1137 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1138 u16 cap); 1139 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1140 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1141 u16 cap, unsigned int size); 1142 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1143 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1144 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1145 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1146 void pci_pme_active(struct pci_dev *dev, bool enable); 1147 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1148 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1149 int pci_prepare_to_sleep(struct pci_dev *dev); 1150 int pci_back_from_sleep(struct pci_dev *dev); 1151 bool pci_dev_run_wake(struct pci_dev *dev); 1152 bool pci_check_pme_status(struct pci_dev *dev); 1153 void pci_pme_wakeup_bus(struct pci_bus *bus); 1154 void pci_d3cold_enable(struct pci_dev *dev); 1155 void pci_d3cold_disable(struct pci_dev *dev); 1156 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1157 void pci_wakeup_bus(struct pci_bus *bus); 1158 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1159 1160 /* PCI Virtual Channel */ 1161 int pci_save_vc_state(struct pci_dev *dev); 1162 void pci_restore_vc_state(struct pci_dev *dev); 1163 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1164 1165 /* For use by arch with custom probe code */ 1166 void set_pcie_port_type(struct pci_dev *pdev); 1167 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1168 1169 /* Functions for PCI Hotplug drivers to use */ 1170 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1171 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1172 unsigned int pci_rescan_bus(struct pci_bus *bus); 1173 void pci_lock_rescan_remove(void); 1174 void pci_unlock_rescan_remove(void); 1175 1176 /* Vital Product Data routines */ 1177 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1178 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1179 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1180 1181 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1182 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1183 void pci_bus_assign_resources(const struct pci_bus *bus); 1184 void pci_bus_claim_resources(struct pci_bus *bus); 1185 void pci_bus_size_bridges(struct pci_bus *bus); 1186 int pci_claim_resource(struct pci_dev *, int); 1187 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1188 void pci_assign_unassigned_resources(void); 1189 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1190 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1191 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1192 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1193 void pdev_enable_device(struct pci_dev *); 1194 int pci_enable_resources(struct pci_dev *, int mask); 1195 void pci_assign_irq(struct pci_dev *dev); 1196 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1197 #define HAVE_PCI_REQ_REGIONS 2 1198 int __must_check pci_request_regions(struct pci_dev *, const char *); 1199 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1200 void pci_release_regions(struct pci_dev *); 1201 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1202 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1203 void pci_release_region(struct pci_dev *, int); 1204 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1205 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1206 void pci_release_selected_regions(struct pci_dev *, int); 1207 1208 /* drivers/pci/bus.c */ 1209 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1210 void pci_bus_put(struct pci_bus *bus); 1211 void pci_add_resource(struct list_head *resources, struct resource *res); 1212 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1213 resource_size_t offset); 1214 void pci_free_resource_list(struct list_head *resources); 1215 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1216 unsigned int flags); 1217 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1218 void pci_bus_remove_resources(struct pci_bus *bus); 1219 int devm_request_pci_bus_resources(struct device *dev, 1220 struct list_head *resources); 1221 1222 #define pci_bus_for_each_resource(bus, res, i) \ 1223 for (i = 0; \ 1224 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1225 i++) 1226 1227 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1228 struct resource *res, resource_size_t size, 1229 resource_size_t align, resource_size_t min, 1230 unsigned long type_mask, 1231 resource_size_t (*alignf)(void *, 1232 const struct resource *, 1233 resource_size_t, 1234 resource_size_t), 1235 void *alignf_data); 1236 1237 1238 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1239 resource_size_t size); 1240 unsigned long pci_address_to_pio(phys_addr_t addr); 1241 phys_addr_t pci_pio_to_address(unsigned long pio); 1242 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1243 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1244 phys_addr_t phys_addr); 1245 void pci_unmap_iospace(struct resource *res); 1246 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1247 resource_size_t offset, 1248 resource_size_t size); 1249 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1250 struct resource *res); 1251 1252 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1253 { 1254 struct pci_bus_region region; 1255 1256 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1257 return region.start; 1258 } 1259 1260 /* Proper probing supporting hot-pluggable devices */ 1261 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1262 const char *mod_name); 1263 1264 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1265 #define pci_register_driver(driver) \ 1266 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1267 1268 void pci_unregister_driver(struct pci_driver *dev); 1269 1270 /** 1271 * module_pci_driver() - Helper macro for registering a PCI driver 1272 * @__pci_driver: pci_driver struct 1273 * 1274 * Helper macro for PCI drivers which do not do anything special in module 1275 * init/exit. This eliminates a lot of boilerplate. Each module may only 1276 * use this macro once, and calling it replaces module_init() and module_exit() 1277 */ 1278 #define module_pci_driver(__pci_driver) \ 1279 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1280 1281 /** 1282 * builtin_pci_driver() - Helper macro for registering a PCI driver 1283 * @__pci_driver: pci_driver struct 1284 * 1285 * Helper macro for PCI drivers which do not do anything special in their 1286 * init code. This eliminates a lot of boilerplate. Each driver may only 1287 * use this macro once, and calling it replaces device_initcall(...) 1288 */ 1289 #define builtin_pci_driver(__pci_driver) \ 1290 builtin_driver(__pci_driver, pci_register_driver) 1291 1292 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1293 int pci_add_dynid(struct pci_driver *drv, 1294 unsigned int vendor, unsigned int device, 1295 unsigned int subvendor, unsigned int subdevice, 1296 unsigned int class, unsigned int class_mask, 1297 unsigned long driver_data); 1298 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1299 struct pci_dev *dev); 1300 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1301 int pass); 1302 1303 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1304 void *userdata); 1305 int pci_cfg_space_size(struct pci_dev *dev); 1306 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1307 void pci_setup_bridge(struct pci_bus *bus); 1308 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1309 unsigned long type); 1310 1311 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1312 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1313 1314 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1315 unsigned int command_bits, u32 flags); 1316 1317 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1318 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1319 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1320 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1321 #define PCI_IRQ_ALL_TYPES \ 1322 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1323 1324 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1325 1326 #include <linux/pci-dma.h> 1327 #include <linux/dmapool.h> 1328 1329 #define pci_pool dma_pool 1330 #define pci_pool_create(name, pdev, size, align, allocation) \ 1331 dma_pool_create(name, &pdev->dev, size, align, allocation) 1332 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1333 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1334 #define pci_pool_zalloc(pool, flags, handle) \ 1335 dma_pool_zalloc(pool, flags, handle) 1336 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1337 1338 struct msix_entry { 1339 u32 vector; /* Kernel uses to write allocated vector */ 1340 u16 entry; /* Driver uses to specify entry, OS writes */ 1341 }; 1342 1343 #ifdef CONFIG_PCI_MSI 1344 int pci_msi_vec_count(struct pci_dev *dev); 1345 void pci_disable_msi(struct pci_dev *dev); 1346 int pci_msix_vec_count(struct pci_dev *dev); 1347 void pci_disable_msix(struct pci_dev *dev); 1348 void pci_restore_msi_state(struct pci_dev *dev); 1349 int pci_msi_enabled(void); 1350 int pci_enable_msi(struct pci_dev *dev); 1351 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1352 int minvec, int maxvec); 1353 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1354 struct msix_entry *entries, int nvec) 1355 { 1356 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1357 if (rc < 0) 1358 return rc; 1359 return 0; 1360 } 1361 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1362 unsigned int max_vecs, unsigned int flags, 1363 const struct irq_affinity *affd); 1364 1365 void pci_free_irq_vectors(struct pci_dev *dev); 1366 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1367 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1368 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1369 1370 #else 1371 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1372 static inline void pci_disable_msi(struct pci_dev *dev) { } 1373 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1374 static inline void pci_disable_msix(struct pci_dev *dev) { } 1375 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1376 static inline int pci_msi_enabled(void) { return 0; } 1377 static inline int pci_enable_msi(struct pci_dev *dev) 1378 { return -ENOSYS; } 1379 static inline int pci_enable_msix_range(struct pci_dev *dev, 1380 struct msix_entry *entries, int minvec, int maxvec) 1381 { return -ENOSYS; } 1382 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1383 struct msix_entry *entries, int nvec) 1384 { return -ENOSYS; } 1385 1386 static inline int 1387 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1388 unsigned int max_vecs, unsigned int flags, 1389 const struct irq_affinity *aff_desc) 1390 { 1391 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1392 return 1; 1393 return -ENOSPC; 1394 } 1395 1396 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1397 { 1398 } 1399 1400 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1401 { 1402 if (WARN_ON_ONCE(nr > 0)) 1403 return -EINVAL; 1404 return dev->irq; 1405 } 1406 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1407 int vec) 1408 { 1409 return cpu_possible_mask; 1410 } 1411 1412 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1413 { 1414 return first_online_node; 1415 } 1416 #endif 1417 1418 static inline int 1419 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1420 unsigned int max_vecs, unsigned int flags) 1421 { 1422 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1423 NULL); 1424 } 1425 1426 /** 1427 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1428 * @d: the INTx IRQ domain 1429 * @node: the DT node for the device whose interrupt we're translating 1430 * @intspec: the interrupt specifier data from the DT 1431 * @intsize: the number of entries in @intspec 1432 * @out_hwirq: pointer at which to write the hwirq number 1433 * @out_type: pointer at which to write the interrupt type 1434 * 1435 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1436 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1437 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1438 * INTx value to obtain the hwirq number. 1439 * 1440 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1441 */ 1442 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1443 struct device_node *node, 1444 const u32 *intspec, 1445 unsigned int intsize, 1446 unsigned long *out_hwirq, 1447 unsigned int *out_type) 1448 { 1449 const u32 intx = intspec[0]; 1450 1451 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1452 return -EINVAL; 1453 1454 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1455 return 0; 1456 } 1457 1458 #ifdef CONFIG_PCIEPORTBUS 1459 extern bool pcie_ports_disabled; 1460 extern bool pcie_ports_native; 1461 #else 1462 #define pcie_ports_disabled true 1463 #define pcie_ports_native false 1464 #endif 1465 1466 #ifdef CONFIG_PCIEASPM 1467 bool pcie_aspm_support_enabled(void); 1468 #else 1469 static inline bool pcie_aspm_support_enabled(void) { return false; } 1470 #endif 1471 1472 #ifdef CONFIG_PCIEAER 1473 void pci_no_aer(void); 1474 bool pci_aer_available(void); 1475 int pci_aer_init(struct pci_dev *dev); 1476 #else 1477 static inline void pci_no_aer(void) { } 1478 static inline bool pci_aer_available(void) { return false; } 1479 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } 1480 #endif 1481 1482 #ifdef CONFIG_PCIE_ECRC 1483 void pcie_set_ecrc_checking(struct pci_dev *dev); 1484 void pcie_ecrc_get_policy(char *str); 1485 #else 1486 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1487 static inline void pcie_ecrc_get_policy(char *str) { } 1488 #endif 1489 1490 bool pci_ats_disabled(void); 1491 1492 #ifdef CONFIG_PCI_ATS 1493 /* Address Translation Service */ 1494 void pci_ats_init(struct pci_dev *dev); 1495 int pci_enable_ats(struct pci_dev *dev, int ps); 1496 void pci_disable_ats(struct pci_dev *dev); 1497 int pci_ats_queue_depth(struct pci_dev *dev); 1498 #else 1499 static inline void pci_ats_init(struct pci_dev *d) { } 1500 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1501 static inline void pci_disable_ats(struct pci_dev *d) { } 1502 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1503 #endif 1504 1505 #ifdef CONFIG_PCIE_PTM 1506 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1507 #else 1508 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1509 { return -EINVAL; } 1510 #endif 1511 1512 void pci_cfg_access_lock(struct pci_dev *dev); 1513 bool pci_cfg_access_trylock(struct pci_dev *dev); 1514 void pci_cfg_access_unlock(struct pci_dev *dev); 1515 1516 /* 1517 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1518 * a PCI domain is defined to be a set of PCI buses which share 1519 * configuration space. 1520 */ 1521 #ifdef CONFIG_PCI_DOMAINS 1522 extern int pci_domains_supported; 1523 #else 1524 enum { pci_domains_supported = 0 }; 1525 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1526 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1527 #endif /* CONFIG_PCI_DOMAINS */ 1528 1529 /* 1530 * Generic implementation for PCI domain support. If your 1531 * architecture does not need custom management of PCI 1532 * domains then this implementation will be used 1533 */ 1534 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1535 static inline int pci_domain_nr(struct pci_bus *bus) 1536 { 1537 return bus->domain_nr; 1538 } 1539 #ifdef CONFIG_ACPI 1540 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1541 #else 1542 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1543 { return 0; } 1544 #endif 1545 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1546 #endif 1547 1548 /* Some architectures require additional setup to direct VGA traffic */ 1549 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1550 unsigned int command_bits, u32 flags); 1551 void pci_register_set_vga_state(arch_set_vga_state_t func); 1552 1553 static inline int 1554 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1555 { 1556 return pci_request_selected_regions(pdev, 1557 pci_select_bars(pdev, IORESOURCE_IO), name); 1558 } 1559 1560 static inline void 1561 pci_release_io_regions(struct pci_dev *pdev) 1562 { 1563 return pci_release_selected_regions(pdev, 1564 pci_select_bars(pdev, IORESOURCE_IO)); 1565 } 1566 1567 static inline int 1568 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1569 { 1570 return pci_request_selected_regions(pdev, 1571 pci_select_bars(pdev, IORESOURCE_MEM), name); 1572 } 1573 1574 static inline void 1575 pci_release_mem_regions(struct pci_dev *pdev) 1576 { 1577 return pci_release_selected_regions(pdev, 1578 pci_select_bars(pdev, IORESOURCE_MEM)); 1579 } 1580 1581 #else /* CONFIG_PCI is not enabled */ 1582 1583 static inline void pci_set_flags(int flags) { } 1584 static inline void pci_add_flags(int flags) { } 1585 static inline void pci_clear_flags(int flags) { } 1586 static inline int pci_has_flag(int flag) { return 0; } 1587 1588 /* 1589 * If the system does not have PCI, clearly these return errors. Define 1590 * these as simple inline functions to avoid hair in drivers. 1591 */ 1592 #define _PCI_NOP(o, s, t) \ 1593 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1594 int where, t val) \ 1595 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1596 1597 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1598 _PCI_NOP(o, word, u16 x) \ 1599 _PCI_NOP(o, dword, u32 x) 1600 _PCI_NOP_ALL(read, *) 1601 _PCI_NOP_ALL(write,) 1602 1603 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1604 unsigned int device, 1605 struct pci_dev *from) 1606 { return NULL; } 1607 1608 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1609 unsigned int device, 1610 unsigned int ss_vendor, 1611 unsigned int ss_device, 1612 struct pci_dev *from) 1613 { return NULL; } 1614 1615 static inline struct pci_dev *pci_get_class(unsigned int class, 1616 struct pci_dev *from) 1617 { return NULL; } 1618 1619 #define pci_dev_present(ids) (0) 1620 #define no_pci_devices() (1) 1621 #define pci_dev_put(dev) do { } while (0) 1622 1623 static inline void pci_set_master(struct pci_dev *dev) { } 1624 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1625 static inline void pci_disable_device(struct pci_dev *dev) { } 1626 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1627 { return -EBUSY; } 1628 static inline int __pci_register_driver(struct pci_driver *drv, 1629 struct module *owner) 1630 { return 0; } 1631 static inline int pci_register_driver(struct pci_driver *drv) 1632 { return 0; } 1633 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1634 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1635 { return 0; } 1636 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1637 int cap) 1638 { return 0; } 1639 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1640 { return 0; } 1641 1642 /* Power management related routines */ 1643 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1644 static inline void pci_restore_state(struct pci_dev *dev) { } 1645 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1646 { return 0; } 1647 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1648 { return 0; } 1649 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1650 pm_message_t state) 1651 { return PCI_D0; } 1652 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1653 int enable) 1654 { return 0; } 1655 1656 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1657 struct resource *res) 1658 { return NULL; } 1659 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1660 { return -EIO; } 1661 static inline void pci_release_regions(struct pci_dev *dev) { } 1662 1663 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1664 1665 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1666 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1667 { return 0; } 1668 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1669 1670 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1671 { return NULL; } 1672 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1673 unsigned int devfn) 1674 { return NULL; } 1675 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1676 unsigned int bus, unsigned int devfn) 1677 { return NULL; } 1678 1679 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1680 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1681 1682 #define dev_is_pci(d) (false) 1683 #define dev_is_pf(d) (false) 1684 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1685 { return false; } 1686 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1687 struct device_node *node, 1688 const u32 *intspec, 1689 unsigned int intsize, 1690 unsigned long *out_hwirq, 1691 unsigned int *out_type) 1692 { return -EINVAL; } 1693 #endif /* CONFIG_PCI */ 1694 1695 /* Include architecture-dependent settings and functions */ 1696 1697 #include <asm/pci.h> 1698 1699 /* These two functions provide almost identical functionality. Depennding 1700 * on the architecture, one will be implemented as a wrapper around the 1701 * other (in drivers/pci/mmap.c). 1702 * 1703 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1704 * is expected to be an offset within that region. 1705 * 1706 * pci_mmap_page_range() is the legacy architecture-specific interface, 1707 * which accepts a "user visible" resource address converted by 1708 * pci_resource_to_user(), as used in the legacy mmap() interface in 1709 * /proc/bus/pci/. 1710 */ 1711 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1712 struct vm_area_struct *vma, 1713 enum pci_mmap_state mmap_state, int write_combine); 1714 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1715 struct vm_area_struct *vma, 1716 enum pci_mmap_state mmap_state, int write_combine); 1717 1718 #ifndef arch_can_pci_mmap_wc 1719 #define arch_can_pci_mmap_wc() 0 1720 #endif 1721 1722 #ifndef arch_can_pci_mmap_io 1723 #define arch_can_pci_mmap_io() 0 1724 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1725 #else 1726 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1727 #endif 1728 1729 #ifndef pci_root_bus_fwnode 1730 #define pci_root_bus_fwnode(bus) NULL 1731 #endif 1732 1733 /* 1734 * These helpers provide future and backwards compatibility 1735 * for accessing popular PCI BAR info 1736 */ 1737 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1738 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1739 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1740 #define pci_resource_len(dev,bar) \ 1741 ((pci_resource_start((dev), (bar)) == 0 && \ 1742 pci_resource_end((dev), (bar)) == \ 1743 pci_resource_start((dev), (bar))) ? 0 : \ 1744 \ 1745 (pci_resource_end((dev), (bar)) - \ 1746 pci_resource_start((dev), (bar)) + 1)) 1747 1748 /* 1749 * Similar to the helpers above, these manipulate per-pci_dev 1750 * driver-specific data. They are really just a wrapper around 1751 * the generic device structure functions of these calls. 1752 */ 1753 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1754 { 1755 return dev_get_drvdata(&pdev->dev); 1756 } 1757 1758 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1759 { 1760 dev_set_drvdata(&pdev->dev, data); 1761 } 1762 1763 static inline const char *pci_name(const struct pci_dev *pdev) 1764 { 1765 return dev_name(&pdev->dev); 1766 } 1767 1768 1769 /* 1770 * Some archs don't want to expose struct resource to userland as-is 1771 * in sysfs and /proc 1772 */ 1773 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1774 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1775 const struct resource *rsrc, 1776 resource_size_t *start, resource_size_t *end); 1777 #else 1778 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1779 const struct resource *rsrc, resource_size_t *start, 1780 resource_size_t *end) 1781 { 1782 *start = rsrc->start; 1783 *end = rsrc->end; 1784 } 1785 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1786 1787 1788 /* 1789 * The world is not perfect and supplies us with broken PCI devices. 1790 * For at least a part of these bugs we need a work-around, so both 1791 * generic (drivers/pci/quirks.c) and per-architecture code can define 1792 * fixup hooks to be called for particular buggy devices. 1793 */ 1794 1795 struct pci_fixup { 1796 u16 vendor; /* Or PCI_ANY_ID */ 1797 u16 device; /* Or PCI_ANY_ID */ 1798 u32 class; /* Or PCI_ANY_ID */ 1799 unsigned int class_shift; /* should be 0, 8, 16 */ 1800 void (*hook)(struct pci_dev *dev); 1801 }; 1802 1803 enum pci_fixup_pass { 1804 pci_fixup_early, /* Before probing BARs */ 1805 pci_fixup_header, /* After reading configuration header */ 1806 pci_fixup_final, /* Final phase of device fixups */ 1807 pci_fixup_enable, /* pci_enable_device() time */ 1808 pci_fixup_resume, /* pci_device_resume() */ 1809 pci_fixup_suspend, /* pci_device_suspend() */ 1810 pci_fixup_resume_early, /* pci_device_resume_early() */ 1811 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1812 }; 1813 1814 /* Anonymous variables would be nice... */ 1815 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1816 class_shift, hook) \ 1817 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1818 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1819 = { vendor, device, class, class_shift, hook }; 1820 1821 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1822 class_shift, hook) \ 1823 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1824 hook, vendor, device, class, class_shift, hook) 1825 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1826 class_shift, hook) \ 1827 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1828 hook, vendor, device, class, class_shift, hook) 1829 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1830 class_shift, hook) \ 1831 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1832 hook, vendor, device, class, class_shift, hook) 1833 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1834 class_shift, hook) \ 1835 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1836 hook, vendor, device, class, class_shift, hook) 1837 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1838 class_shift, hook) \ 1839 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1840 resume##hook, vendor, device, class, class_shift, hook) 1841 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1842 class_shift, hook) \ 1843 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1844 resume_early##hook, vendor, device, class, class_shift, hook) 1845 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1846 class_shift, hook) \ 1847 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1848 suspend##hook, vendor, device, class, class_shift, hook) 1849 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1850 class_shift, hook) \ 1851 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1852 suspend_late##hook, vendor, device, class, class_shift, hook) 1853 1854 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1855 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1856 hook, vendor, device, PCI_ANY_ID, 0, hook) 1857 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1858 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1859 hook, vendor, device, PCI_ANY_ID, 0, hook) 1860 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1861 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1862 hook, vendor, device, PCI_ANY_ID, 0, hook) 1863 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1864 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1865 hook, vendor, device, PCI_ANY_ID, 0, hook) 1866 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1868 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1869 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1870 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1871 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1872 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1873 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1874 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1875 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1876 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1877 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1878 1879 #ifdef CONFIG_PCI_QUIRKS 1880 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1881 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1882 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1883 #else 1884 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1885 struct pci_dev *dev) { } 1886 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1887 u16 acs_flags) 1888 { 1889 return -ENOTTY; 1890 } 1891 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1892 { 1893 return -ENOTTY; 1894 } 1895 #endif 1896 1897 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1898 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1899 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1900 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1901 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1902 const char *name); 1903 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1904 1905 extern int pci_pci_problems; 1906 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1907 #define PCIPCI_TRITON 2 1908 #define PCIPCI_NATOMA 4 1909 #define PCIPCI_VIAETBF 8 1910 #define PCIPCI_VSFX 16 1911 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1912 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1913 1914 extern unsigned long pci_cardbus_io_size; 1915 extern unsigned long pci_cardbus_mem_size; 1916 extern u8 pci_dfl_cache_line_size; 1917 extern u8 pci_cache_line_size; 1918 1919 extern unsigned long pci_hotplug_io_size; 1920 extern unsigned long pci_hotplug_mem_size; 1921 extern unsigned long pci_hotplug_bus_size; 1922 1923 /* Architecture-specific versions may override these (weak) */ 1924 void pcibios_disable_device(struct pci_dev *dev); 1925 void pcibios_set_master(struct pci_dev *dev); 1926 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1927 enum pcie_reset_state state); 1928 int pcibios_add_device(struct pci_dev *dev); 1929 void pcibios_release_device(struct pci_dev *dev); 1930 void pcibios_penalize_isa_irq(int irq, int active); 1931 int pcibios_alloc_irq(struct pci_dev *dev); 1932 void pcibios_free_irq(struct pci_dev *dev); 1933 resource_size_t pcibios_default_alignment(void); 1934 1935 #ifdef CONFIG_HIBERNATE_CALLBACKS 1936 extern struct dev_pm_ops pcibios_pm_ops; 1937 #endif 1938 1939 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1940 void __init pci_mmcfg_early_init(void); 1941 void __init pci_mmcfg_late_init(void); 1942 #else 1943 static inline void pci_mmcfg_early_init(void) { } 1944 static inline void pci_mmcfg_late_init(void) { } 1945 #endif 1946 1947 int pci_ext_cfg_avail(void); 1948 1949 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1950 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1951 1952 #ifdef CONFIG_PCI_IOV 1953 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1954 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1955 1956 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1957 void pci_disable_sriov(struct pci_dev *dev); 1958 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 1959 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 1960 int pci_num_vf(struct pci_dev *dev); 1961 int pci_vfs_assigned(struct pci_dev *dev); 1962 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1963 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1964 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 1965 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1966 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 1967 1968 /* Arch may override these (weak) */ 1969 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 1970 int pcibios_sriov_disable(struct pci_dev *pdev); 1971 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1972 #else 1973 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1974 { 1975 return -ENOSYS; 1976 } 1977 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1978 { 1979 return -ENOSYS; 1980 } 1981 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1982 { return -ENODEV; } 1983 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 1984 { 1985 return -ENOSYS; 1986 } 1987 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 1988 int id) { } 1989 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1990 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1991 static inline int pci_vfs_assigned(struct pci_dev *dev) 1992 { return 0; } 1993 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1994 { return 0; } 1995 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1996 { return 0; } 1997 #define pci_sriov_configure_simple NULL 1998 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1999 { return 0; } 2000 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2001 #endif 2002 2003 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2004 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2005 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2006 #endif 2007 2008 /** 2009 * pci_pcie_cap - get the saved PCIe capability offset 2010 * @dev: PCI device 2011 * 2012 * PCIe capability offset is calculated at PCI device initialization 2013 * time and saved in the data structure. This function returns saved 2014 * PCIe capability offset. Using this instead of pci_find_capability() 2015 * reduces unnecessary search in the PCI configuration space. If you 2016 * need to calculate PCIe capability offset from raw device for some 2017 * reasons, please use pci_find_capability() instead. 2018 */ 2019 static inline int pci_pcie_cap(struct pci_dev *dev) 2020 { 2021 return dev->pcie_cap; 2022 } 2023 2024 /** 2025 * pci_is_pcie - check if the PCI device is PCI Express capable 2026 * @dev: PCI device 2027 * 2028 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2029 */ 2030 static inline bool pci_is_pcie(struct pci_dev *dev) 2031 { 2032 return pci_pcie_cap(dev); 2033 } 2034 2035 /** 2036 * pcie_caps_reg - get the PCIe Capabilities Register 2037 * @dev: PCI device 2038 */ 2039 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2040 { 2041 return dev->pcie_flags_reg; 2042 } 2043 2044 /** 2045 * pci_pcie_type - get the PCIe device/port type 2046 * @dev: PCI device 2047 */ 2048 static inline int pci_pcie_type(const struct pci_dev *dev) 2049 { 2050 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2051 } 2052 2053 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2054 { 2055 while (1) { 2056 if (!pci_is_pcie(dev)) 2057 break; 2058 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2059 return dev; 2060 if (!dev->bus->self) 2061 break; 2062 dev = dev->bus->self; 2063 } 2064 return NULL; 2065 } 2066 2067 void pci_request_acs(void); 2068 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2069 bool pci_acs_path_enabled(struct pci_dev *start, 2070 struct pci_dev *end, u16 acs_flags); 2071 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2072 2073 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2074 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2075 2076 /* Large Resource Data Type Tag Item Names */ 2077 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2078 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2079 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2080 2081 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2082 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2083 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2084 2085 /* Small Resource Data Type Tag Item Names */ 2086 #define PCI_VPD_STIN_END 0x0f /* End */ 2087 2088 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2089 2090 #define PCI_VPD_SRDT_TIN_MASK 0x78 2091 #define PCI_VPD_SRDT_LEN_MASK 0x07 2092 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2093 2094 #define PCI_VPD_LRDT_TAG_SIZE 3 2095 #define PCI_VPD_SRDT_TAG_SIZE 1 2096 2097 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2098 2099 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2100 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2101 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2102 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2103 2104 /** 2105 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2106 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2107 * 2108 * Returns the extracted Large Resource Data Type length. 2109 */ 2110 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2111 { 2112 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2113 } 2114 2115 /** 2116 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2117 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2118 * 2119 * Returns the extracted Large Resource Data Type Tag item. 2120 */ 2121 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2122 { 2123 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2124 } 2125 2126 /** 2127 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2128 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2129 * 2130 * Returns the extracted Small Resource Data Type length. 2131 */ 2132 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2133 { 2134 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2135 } 2136 2137 /** 2138 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2139 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2140 * 2141 * Returns the extracted Small Resource Data Type Tag Item. 2142 */ 2143 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2144 { 2145 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2146 } 2147 2148 /** 2149 * pci_vpd_info_field_size - Extracts the information field length 2150 * @lrdt: Pointer to the beginning of an information field header 2151 * 2152 * Returns the extracted information field length. 2153 */ 2154 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2155 { 2156 return info_field[2]; 2157 } 2158 2159 /** 2160 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2161 * @buf: Pointer to buffered vpd data 2162 * @off: The offset into the buffer at which to begin the search 2163 * @len: The length of the vpd buffer 2164 * @rdt: The Resource Data Type to search for 2165 * 2166 * Returns the index where the Resource Data Type was found or 2167 * -ENOENT otherwise. 2168 */ 2169 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2170 2171 /** 2172 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2173 * @buf: Pointer to buffered vpd data 2174 * @off: The offset into the buffer at which to begin the search 2175 * @len: The length of the buffer area, relative to off, in which to search 2176 * @kw: The keyword to search for 2177 * 2178 * Returns the index where the information field keyword was found or 2179 * -ENOENT otherwise. 2180 */ 2181 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2182 unsigned int len, const char *kw); 2183 2184 /* PCI <-> OF binding helpers */ 2185 #ifdef CONFIG_OF 2186 struct device_node; 2187 struct irq_domain; 2188 void pci_set_of_node(struct pci_dev *dev); 2189 void pci_release_of_node(struct pci_dev *dev); 2190 void pci_set_bus_of_node(struct pci_bus *bus); 2191 void pci_release_bus_of_node(struct pci_bus *bus); 2192 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2193 int pci_parse_request_of_pci_ranges(struct device *dev, 2194 struct list_head *resources, 2195 struct resource **bus_range); 2196 2197 /* Arch may override this (weak) */ 2198 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2199 2200 #else /* CONFIG_OF */ 2201 static inline void pci_set_of_node(struct pci_dev *dev) { } 2202 static inline void pci_release_of_node(struct pci_dev *dev) { } 2203 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2204 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2205 static inline struct irq_domain * 2206 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2207 static inline int pci_parse_request_of_pci_ranges(struct device *dev, 2208 struct list_head *resources, 2209 struct resource **bus_range) 2210 { 2211 return -EINVAL; 2212 } 2213 #endif /* CONFIG_OF */ 2214 2215 static inline struct device_node * 2216 pci_device_to_OF_node(const struct pci_dev *pdev) 2217 { 2218 return pdev ? pdev->dev.of_node : NULL; 2219 } 2220 2221 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2222 { 2223 return bus ? bus->dev.of_node : NULL; 2224 } 2225 2226 #ifdef CONFIG_ACPI 2227 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2228 2229 void 2230 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2231 #else 2232 static inline struct irq_domain * 2233 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2234 #endif 2235 2236 #ifdef CONFIG_EEH 2237 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2238 { 2239 return pdev->dev.archdata.edev; 2240 } 2241 #endif 2242 2243 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2244 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2245 int pci_for_each_dma_alias(struct pci_dev *pdev, 2246 int (*fn)(struct pci_dev *pdev, 2247 u16 alias, void *data), void *data); 2248 2249 /* Helper functions for operation of device flag */ 2250 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2251 { 2252 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2253 } 2254 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2255 { 2256 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2257 } 2258 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2259 { 2260 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2261 } 2262 2263 /** 2264 * pci_ari_enabled - query ARI forwarding status 2265 * @bus: the PCI bus 2266 * 2267 * Returns true if ARI forwarding is enabled. 2268 */ 2269 static inline bool pci_ari_enabled(struct pci_bus *bus) 2270 { 2271 return bus->self && bus->self->ari_enabled; 2272 } 2273 2274 /** 2275 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2276 * @pdev: PCI device to check 2277 * 2278 * Walk upwards from @pdev and check for each encountered bridge if it's part 2279 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2280 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2281 */ 2282 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2283 { 2284 struct pci_dev *parent = pdev; 2285 2286 if (pdev->is_thunderbolt) 2287 return true; 2288 2289 while ((parent = pci_upstream_bridge(parent))) 2290 if (parent->is_thunderbolt) 2291 return true; 2292 2293 return false; 2294 } 2295 2296 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2297 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2298 #endif 2299 2300 /* Provide the legacy pci_dma_* API */ 2301 #include <linux/pci-dma-compat.h> 2302 2303 #define pci_printk(level, pdev, fmt, arg...) \ 2304 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2305 2306 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2307 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2308 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2309 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2310 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2311 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2312 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2313 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2314 2315 #endif /* LINUX_PCI_H */ 2316