1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 #include <linux/pci_regs.h> /* The pci register defines */ 21 22 /* 23 * The PCI interface treats multi-function devices as independent 24 * devices. The slot/function address of each device is encoded 25 * in a single byte as follows: 26 * 27 * 7:3 = slot 28 * 2:0 = function 29 */ 30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 32 #define PCI_FUNC(devfn) ((devfn) & 0x07) 33 34 /* Ioctls for /proc/bus/pci/X/Y nodes. */ 35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) 36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ 37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ 38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ 39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ 40 41 #ifdef __KERNEL__ 42 43 #include <linux/mod_devicetable.h> 44 45 #include <linux/types.h> 46 #include <linux/init.h> 47 #include <linux/ioport.h> 48 #include <linux/list.h> 49 #include <linux/compiler.h> 50 #include <linux/errno.h> 51 #include <linux/kobject.h> 52 #include <asm/atomic.h> 53 #include <linux/device.h> 54 #include <linux/io.h> 55 #include <linux/irqreturn.h> 56 57 /* Include the ID list */ 58 #include <linux/pci_ids.h> 59 60 /* pci_slot represents a physical slot */ 61 struct pci_slot { 62 struct pci_bus *bus; /* The bus this slot is on */ 63 struct list_head list; /* node in list of slots on this bus */ 64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 66 struct kobject kobj; 67 }; 68 69 static inline const char *pci_slot_name(const struct pci_slot *slot) 70 { 71 return kobject_name(&slot->kobj); 72 } 73 74 /* File state for mmap()s on /proc/bus/pci/X/Y */ 75 enum pci_mmap_state { 76 pci_mmap_io, 77 pci_mmap_mem 78 }; 79 80 /* This defines the direction arg to the DMA mapping routines. */ 81 #define PCI_DMA_BIDIRECTIONAL 0 82 #define PCI_DMA_TODEVICE 1 83 #define PCI_DMA_FROMDEVICE 2 84 #define PCI_DMA_NONE 3 85 86 /* 87 * For PCI devices, the region numbers are assigned this way: 88 */ 89 enum { 90 /* #0-5: standard PCI resources */ 91 PCI_STD_RESOURCES, 92 PCI_STD_RESOURCE_END = 5, 93 94 /* #6: expansion ROM resource */ 95 PCI_ROM_RESOURCE, 96 97 /* device specific resources */ 98 #ifdef CONFIG_PCI_IOV 99 PCI_IOV_RESOURCES, 100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 101 #endif 102 103 /* resources assigned to buses behind the bridge */ 104 #define PCI_BRIDGE_RESOURCE_NUM 4 105 106 PCI_BRIDGE_RESOURCES, 107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 108 PCI_BRIDGE_RESOURCE_NUM - 1, 109 110 /* total resources associated with a PCI device */ 111 PCI_NUM_RESOURCES, 112 113 /* preserve this for compatibility */ 114 DEVICE_COUNT_RESOURCE 115 }; 116 117 typedef int __bitwise pci_power_t; 118 119 #define PCI_D0 ((pci_power_t __force) 0) 120 #define PCI_D1 ((pci_power_t __force) 1) 121 #define PCI_D2 ((pci_power_t __force) 2) 122 #define PCI_D3hot ((pci_power_t __force) 3) 123 #define PCI_D3cold ((pci_power_t __force) 4) 124 #define PCI_UNKNOWN ((pci_power_t __force) 5) 125 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 126 127 /* Remember to update this when the list above changes! */ 128 extern const char *pci_power_names[]; 129 130 static inline const char *pci_power_name(pci_power_t state) 131 { 132 return pci_power_names[1 + (int) state]; 133 } 134 135 #define PCI_PM_D2_DELAY 200 136 #define PCI_PM_D3_WAIT 10 137 #define PCI_PM_BUS_WAIT 50 138 139 /** The pci_channel state describes connectivity between the CPU and 140 * the pci device. If some PCI bus between here and the pci device 141 * has crashed or locked up, this info is reflected here. 142 */ 143 typedef unsigned int __bitwise pci_channel_state_t; 144 145 enum pci_channel_state { 146 /* I/O channel is in normal state */ 147 pci_channel_io_normal = (__force pci_channel_state_t) 1, 148 149 /* I/O to channel is blocked */ 150 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 151 152 /* PCI card is dead */ 153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 154 }; 155 156 typedef unsigned int __bitwise pcie_reset_state_t; 157 158 enum pcie_reset_state { 159 /* Reset is NOT asserted (Use to deassert reset) */ 160 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 161 162 /* Use #PERST to reset PCI-E device */ 163 pcie_warm_reset = (__force pcie_reset_state_t) 2, 164 165 /* Use PCI-E Hot Reset to reset device */ 166 pcie_hot_reset = (__force pcie_reset_state_t) 3 167 }; 168 169 typedef unsigned short __bitwise pci_dev_flags_t; 170 enum pci_dev_flags { 171 /* INTX_DISABLE in PCI_COMMAND register disables MSI 172 * generation too. 173 */ 174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, 175 /* Device configuration is irrevocably lost if disabled into D3 */ 176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, 177 }; 178 179 enum pci_irq_reroute_variant { 180 INTEL_IRQ_REROUTE_VARIANT = 1, 181 MAX_IRQ_REROUTE_VARIANTS = 3 182 }; 183 184 typedef unsigned short __bitwise pci_bus_flags_t; 185 enum pci_bus_flags { 186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 188 }; 189 190 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 191 enum pci_bus_speed { 192 PCI_SPEED_33MHz = 0x00, 193 PCI_SPEED_66MHz = 0x01, 194 PCI_SPEED_66MHz_PCIX = 0x02, 195 PCI_SPEED_100MHz_PCIX = 0x03, 196 PCI_SPEED_133MHz_PCIX = 0x04, 197 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 198 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 199 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 200 PCI_SPEED_66MHz_PCIX_266 = 0x09, 201 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 202 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 203 AGP_UNKNOWN = 0x0c, 204 AGP_1X = 0x0d, 205 AGP_2X = 0x0e, 206 AGP_4X = 0x0f, 207 AGP_8X = 0x10, 208 PCI_SPEED_66MHz_PCIX_533 = 0x11, 209 PCI_SPEED_100MHz_PCIX_533 = 0x12, 210 PCI_SPEED_133MHz_PCIX_533 = 0x13, 211 PCIE_SPEED_2_5GT = 0x14, 212 PCIE_SPEED_5_0GT = 0x15, 213 PCIE_SPEED_8_0GT = 0x16, 214 PCI_SPEED_UNKNOWN = 0xff, 215 }; 216 217 struct pci_cap_saved_state { 218 struct hlist_node next; 219 char cap_nr; 220 u32 data[0]; 221 }; 222 223 struct pcie_link_state; 224 struct pci_vpd; 225 struct pci_sriov; 226 struct pci_ats; 227 228 /* 229 * The pci_dev structure is used to describe PCI devices. 230 */ 231 struct pci_dev { 232 struct list_head bus_list; /* node in per-bus list */ 233 struct pci_bus *bus; /* bus this device is on */ 234 struct pci_bus *subordinate; /* bus this device bridges to */ 235 236 void *sysdata; /* hook for sys-specific extension */ 237 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 238 struct pci_slot *slot; /* Physical slot this device is in */ 239 240 unsigned int devfn; /* encoded device & function index */ 241 unsigned short vendor; 242 unsigned short device; 243 unsigned short subsystem_vendor; 244 unsigned short subsystem_device; 245 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 246 u8 revision; /* PCI revision, low byte of class word */ 247 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 248 u8 pcie_cap; /* PCI-E capability offset */ 249 u8 pcie_type; /* PCI-E device/port type */ 250 u8 rom_base_reg; /* which config register controls the ROM */ 251 u8 pin; /* which interrupt pin this device uses */ 252 253 struct pci_driver *driver; /* which driver has allocated this device */ 254 u64 dma_mask; /* Mask of the bits of bus address this 255 device implements. Normally this is 256 0xffffffff. You only need to change 257 this if your device has broken DMA 258 or supports 64-bit transfers. */ 259 260 struct device_dma_parameters dma_parms; 261 262 pci_power_t current_state; /* Current operating state. In ACPI-speak, 263 this is D0-D3, D0 being fully functional, 264 and D3 being off. */ 265 int pm_cap; /* PM capability offset in the 266 configuration space */ 267 unsigned int pme_support:5; /* Bitmask of states from which PME# 268 can be generated */ 269 unsigned int pme_interrupt:1; 270 unsigned int d1_support:1; /* Low power state D1 is supported */ 271 unsigned int d2_support:1; /* Low power state D2 is supported */ 272 unsigned int no_d1d2:1; /* Only allow D0 and D3 */ 273 unsigned int mmio_always_on:1; /* disallow turning off io/mem 274 decoding during bar sizing */ 275 unsigned int wakeup_prepared:1; 276 unsigned int d3_delay; /* D3->D0 transition time in ms */ 277 278 #ifdef CONFIG_PCIEASPM 279 struct pcie_link_state *link_state; /* ASPM link state. */ 280 #endif 281 282 pci_channel_state_t error_state; /* current connectivity state */ 283 struct device dev; /* Generic device interface */ 284 285 int cfg_size; /* Size of configuration space */ 286 287 /* 288 * Instead of touching interrupt line and base address registers 289 * directly, use the values stored here. They might be different! 290 */ 291 unsigned int irq; 292 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 293 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */ 294 295 /* These fields are used by common fixups */ 296 unsigned int transparent:1; /* Transparent PCI bridge */ 297 unsigned int multifunction:1;/* Part of multi-function device */ 298 /* keep track of device state */ 299 unsigned int is_added:1; 300 unsigned int is_busmaster:1; /* device is busmaster */ 301 unsigned int no_msi:1; /* device may not use msi */ 302 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ 303 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 304 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 305 unsigned int msi_enabled:1; 306 unsigned int msix_enabled:1; 307 unsigned int ari_enabled:1; /* ARI forwarding */ 308 unsigned int is_managed:1; 309 unsigned int is_pcie:1; /* Obsolete. Will be removed. 310 Use pci_is_pcie() instead */ 311 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 312 unsigned int state_saved:1; 313 unsigned int is_physfn:1; 314 unsigned int is_virtfn:1; 315 unsigned int reset_fn:1; 316 unsigned int is_hotplug_bridge:1; 317 unsigned int __aer_firmware_first_valid:1; 318 unsigned int __aer_firmware_first:1; 319 pci_dev_flags_t dev_flags; 320 atomic_t enable_cnt; /* pci_enable_device has been called */ 321 322 u32 saved_config_space[16]; /* config space saved at suspend time */ 323 struct hlist_head saved_cap_space; 324 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 325 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 326 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 327 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 328 #ifdef CONFIG_PCI_MSI 329 struct list_head msi_list; 330 #endif 331 struct pci_vpd *vpd; 332 #ifdef CONFIG_PCI_IOV 333 union { 334 struct pci_sriov *sriov; /* SR-IOV capability related */ 335 struct pci_dev *physfn; /* the PF this VF is associated with */ 336 }; 337 struct pci_ats *ats; /* Address Translation Service */ 338 #endif 339 }; 340 341 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 342 { 343 #ifdef CONFIG_PCI_IOV 344 if (dev->is_virtfn) 345 dev = dev->physfn; 346 #endif 347 348 return dev; 349 } 350 351 extern struct pci_dev *alloc_pci_dev(void); 352 353 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) 354 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 355 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 356 357 static inline int pci_channel_offline(struct pci_dev *pdev) 358 { 359 return (pdev->error_state != pci_channel_io_normal); 360 } 361 362 static inline struct pci_cap_saved_state *pci_find_saved_cap( 363 struct pci_dev *pci_dev, char cap) 364 { 365 struct pci_cap_saved_state *tmp; 366 struct hlist_node *pos; 367 368 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { 369 if (tmp->cap_nr == cap) 370 return tmp; 371 } 372 return NULL; 373 } 374 375 static inline void pci_add_saved_cap(struct pci_dev *pci_dev, 376 struct pci_cap_saved_state *new_cap) 377 { 378 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); 379 } 380 381 /* 382 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 383 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 384 * buses below host bridges or subtractive decode bridges) go in the list. 385 * Use pci_bus_for_each_resource() to iterate through all the resources. 386 */ 387 388 /* 389 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 390 * and there's no way to program the bridge with the details of the window. 391 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 392 * decode bit set, because they are explicit and can be programmed with _SRS. 393 */ 394 #define PCI_SUBTRACTIVE_DECODE 0x1 395 396 struct pci_bus_resource { 397 struct list_head list; 398 struct resource *res; 399 unsigned int flags; 400 }; 401 402 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 403 404 struct pci_bus { 405 struct list_head node; /* node in list of buses */ 406 struct pci_bus *parent; /* parent bus this bridge is on */ 407 struct list_head children; /* list of child buses */ 408 struct list_head devices; /* list of devices on this bus */ 409 struct pci_dev *self; /* bridge device as seen by parent */ 410 struct list_head slots; /* list of slots on this bus */ 411 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 412 struct list_head resources; /* address space routed to this bus */ 413 414 struct pci_ops *ops; /* configuration access functions */ 415 void *sysdata; /* hook for sys-specific extension */ 416 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 417 418 unsigned char number; /* bus number */ 419 unsigned char primary; /* number of primary bridge */ 420 unsigned char secondary; /* number of secondary bridge */ 421 unsigned char subordinate; /* max number of subordinate buses */ 422 unsigned char max_bus_speed; /* enum pci_bus_speed */ 423 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 424 425 char name[48]; 426 427 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 428 pci_bus_flags_t bus_flags; /* Inherited by child busses */ 429 struct device *bridge; 430 struct device dev; 431 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 432 struct bin_attribute *legacy_mem; /* legacy mem */ 433 unsigned int is_added:1; 434 }; 435 436 #define pci_bus_b(n) list_entry(n, struct pci_bus, node) 437 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 438 439 /* 440 * Returns true if the pci bus is root (behind host-pci bridge), 441 * false otherwise 442 */ 443 static inline bool pci_is_root_bus(struct pci_bus *pbus) 444 { 445 return !(pbus->parent); 446 } 447 448 #ifdef CONFIG_PCI_MSI 449 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 450 { 451 return pci_dev->msi_enabled || pci_dev->msix_enabled; 452 } 453 #else 454 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 455 #endif 456 457 /* 458 * Error values that may be returned by PCI functions. 459 */ 460 #define PCIBIOS_SUCCESSFUL 0x00 461 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 462 #define PCIBIOS_BAD_VENDOR_ID 0x83 463 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 464 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 465 #define PCIBIOS_SET_FAILED 0x88 466 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 467 468 /* Low-level architecture-dependent routines */ 469 470 struct pci_ops { 471 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 472 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 473 }; 474 475 /* 476 * ACPI needs to be able to access PCI config space before we've done a 477 * PCI bus scan and created pci_bus structures. 478 */ 479 extern int raw_pci_read(unsigned int domain, unsigned int bus, 480 unsigned int devfn, int reg, int len, u32 *val); 481 extern int raw_pci_write(unsigned int domain, unsigned int bus, 482 unsigned int devfn, int reg, int len, u32 val); 483 484 struct pci_bus_region { 485 resource_size_t start; 486 resource_size_t end; 487 }; 488 489 struct pci_dynids { 490 spinlock_t lock; /* protects list, index */ 491 struct list_head list; /* for IDs added at runtime */ 492 }; 493 494 /* ---------------------------------------------------------------- */ 495 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 496 * a set of callbacks in struct pci_error_handlers, then that device driver 497 * will be notified of PCI bus errors, and will be driven to recovery 498 * when an error occurs. 499 */ 500 501 typedef unsigned int __bitwise pci_ers_result_t; 502 503 enum pci_ers_result { 504 /* no result/none/not supported in device driver */ 505 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 506 507 /* Device driver can recover without slot reset */ 508 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 509 510 /* Device driver wants slot to be reset. */ 511 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 512 513 /* Device has completely failed, is unrecoverable */ 514 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 515 516 /* Device driver is fully recovered and operational */ 517 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 518 }; 519 520 /* PCI bus error event callbacks */ 521 struct pci_error_handlers { 522 /* PCI bus error detected on this device */ 523 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 524 enum pci_channel_state error); 525 526 /* MMIO has been re-enabled, but not DMA */ 527 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 528 529 /* PCI Express link has been reset */ 530 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 531 532 /* PCI slot has been reset */ 533 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 534 535 /* Device driver may resume normal operations */ 536 void (*resume)(struct pci_dev *dev); 537 }; 538 539 /* ---------------------------------------------------------------- */ 540 541 struct module; 542 struct pci_driver { 543 struct list_head node; 544 const char *name; 545 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 546 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 547 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 548 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 549 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 550 int (*resume_early) (struct pci_dev *dev); 551 int (*resume) (struct pci_dev *dev); /* Device woken up */ 552 void (*shutdown) (struct pci_dev *dev); 553 struct pci_error_handlers *err_handler; 554 struct device_driver driver; 555 struct pci_dynids dynids; 556 }; 557 558 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 559 560 /** 561 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 562 * @_table: device table name 563 * 564 * This macro is used to create a struct pci_device_id array (a device table) 565 * in a generic manner. 566 */ 567 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 568 const struct pci_device_id _table[] __devinitconst 569 570 /** 571 * PCI_DEVICE - macro used to describe a specific pci device 572 * @vend: the 16 bit PCI Vendor ID 573 * @dev: the 16 bit PCI Device ID 574 * 575 * This macro is used to create a struct pci_device_id that matches a 576 * specific device. The subvendor and subdevice fields will be set to 577 * PCI_ANY_ID. 578 */ 579 #define PCI_DEVICE(vend,dev) \ 580 .vendor = (vend), .device = (dev), \ 581 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 582 583 /** 584 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 585 * @dev_class: the class, subclass, prog-if triple for this device 586 * @dev_class_mask: the class mask for this device 587 * 588 * This macro is used to create a struct pci_device_id that matches a 589 * specific PCI class. The vendor, device, subvendor, and subdevice 590 * fields will be set to PCI_ANY_ID. 591 */ 592 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 593 .class = (dev_class), .class_mask = (dev_class_mask), \ 594 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 595 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 596 597 /** 598 * PCI_VDEVICE - macro used to describe a specific pci device in short form 599 * @vendor: the vendor name 600 * @device: the 16 bit PCI Device ID 601 * 602 * This macro is used to create a struct pci_device_id that matches a 603 * specific PCI device. The subvendor, and subdevice fields will be set 604 * to PCI_ANY_ID. The macro allows the next field to follow as the device 605 * private data. 606 */ 607 608 #define PCI_VDEVICE(vendor, device) \ 609 PCI_VENDOR_ID_##vendor, (device), \ 610 PCI_ANY_ID, PCI_ANY_ID, 0, 0 611 612 /* these external functions are only available when PCI support is enabled */ 613 #ifdef CONFIG_PCI 614 615 extern struct bus_type pci_bus_type; 616 617 /* Do NOT directly access these two variables, unless you are arch specific pci 618 * code, or pci core code. */ 619 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 620 /* Some device drivers need know if pci is initiated */ 621 extern int no_pci_devices(void); 622 623 void pcibios_fixup_bus(struct pci_bus *); 624 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 625 char *pcibios_setup(char *str); 626 627 /* Used only when drivers/pci/setup.c is used */ 628 resource_size_t pcibios_align_resource(void *, const struct resource *, 629 resource_size_t, 630 resource_size_t); 631 void pcibios_update_irq(struct pci_dev *, int irq); 632 633 /* Weak but can be overriden by arch */ 634 void pci_fixup_cardbus(struct pci_bus *); 635 636 /* Generic PCI functions used internally */ 637 638 void pcibios_scan_specific_bus(int busn); 639 extern struct pci_bus *pci_find_bus(int domain, int busnr); 640 void pci_bus_add_devices(const struct pci_bus *bus); 641 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, 642 struct pci_ops *ops, void *sysdata); 643 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, 644 void *sysdata) 645 { 646 struct pci_bus *root_bus; 647 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); 648 if (root_bus) 649 pci_bus_add_devices(root_bus); 650 return root_bus; 651 } 652 struct pci_bus *pci_create_bus(struct device *parent, int bus, 653 struct pci_ops *ops, void *sysdata); 654 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 655 int busnr); 656 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 657 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 658 const char *name, 659 struct hotplug_slot *hotplug); 660 void pci_destroy_slot(struct pci_slot *slot); 661 void pci_renumber_slot(struct pci_slot *slot, int slot_nr); 662 int pci_scan_slot(struct pci_bus *bus, int devfn); 663 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 664 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 665 unsigned int pci_scan_child_bus(struct pci_bus *bus); 666 int __must_check pci_bus_add_device(struct pci_dev *dev); 667 void pci_read_bridge_bases(struct pci_bus *child); 668 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 669 struct resource *res); 670 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); 671 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 672 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 673 extern struct pci_dev *pci_dev_get(struct pci_dev *dev); 674 extern void pci_dev_put(struct pci_dev *dev); 675 extern void pci_remove_bus(struct pci_bus *b); 676 extern void pci_remove_bus_device(struct pci_dev *dev); 677 extern void pci_stop_bus_device(struct pci_dev *dev); 678 void pci_setup_cardbus(struct pci_bus *bus); 679 extern void pci_sort_breadthfirst(void); 680 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 681 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 682 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 683 684 /* Generic PCI functions exported to card drivers */ 685 686 enum pci_lost_interrupt_reason { 687 PCI_LOST_IRQ_NO_INFORMATION = 0, 688 PCI_LOST_IRQ_DISABLE_MSI, 689 PCI_LOST_IRQ_DISABLE_MSIX, 690 PCI_LOST_IRQ_DISABLE_ACPI, 691 }; 692 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 693 int pci_find_capability(struct pci_dev *dev, int cap); 694 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 695 int pci_find_ext_capability(struct pci_dev *dev, int cap); 696 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn, 697 int cap); 698 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 699 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 700 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 701 702 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 703 struct pci_dev *from); 704 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 705 unsigned int ss_vendor, unsigned int ss_device, 706 struct pci_dev *from); 707 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 708 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 709 unsigned int devfn); 710 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 711 unsigned int devfn) 712 { 713 return pci_get_domain_bus_and_slot(0, bus, devfn); 714 } 715 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 716 int pci_dev_present(const struct pci_device_id *ids); 717 718 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 719 int where, u8 *val); 720 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 721 int where, u16 *val); 722 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 723 int where, u32 *val); 724 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 725 int where, u8 val); 726 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 727 int where, u16 val); 728 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 729 int where, u32 val); 730 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 731 732 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) 733 { 734 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 735 } 736 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) 737 { 738 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 739 } 740 static inline int pci_read_config_dword(struct pci_dev *dev, int where, 741 u32 *val) 742 { 743 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 744 } 745 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) 746 { 747 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 748 } 749 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) 750 { 751 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 752 } 753 static inline int pci_write_config_dword(struct pci_dev *dev, int where, 754 u32 val) 755 { 756 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 757 } 758 759 int __must_check pci_enable_device(struct pci_dev *dev); 760 int __must_check pci_enable_device_io(struct pci_dev *dev); 761 int __must_check pci_enable_device_mem(struct pci_dev *dev); 762 int __must_check pci_reenable_device(struct pci_dev *); 763 int __must_check pcim_enable_device(struct pci_dev *pdev); 764 void pcim_pin_device(struct pci_dev *pdev); 765 766 static inline int pci_is_enabled(struct pci_dev *pdev) 767 { 768 return (atomic_read(&pdev->enable_cnt) > 0); 769 } 770 771 static inline int pci_is_managed(struct pci_dev *pdev) 772 { 773 return pdev->is_managed; 774 } 775 776 void pci_disable_device(struct pci_dev *dev); 777 void pci_set_master(struct pci_dev *dev); 778 void pci_clear_master(struct pci_dev *dev); 779 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 780 int pci_set_cacheline_size(struct pci_dev *dev); 781 #define HAVE_PCI_SET_MWI 782 int __must_check pci_set_mwi(struct pci_dev *dev); 783 int pci_try_set_mwi(struct pci_dev *dev); 784 void pci_clear_mwi(struct pci_dev *dev); 785 void pci_intx(struct pci_dev *dev, int enable); 786 void pci_msi_off(struct pci_dev *dev); 787 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 788 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 789 int pcix_get_max_mmrbc(struct pci_dev *dev); 790 int pcix_get_mmrbc(struct pci_dev *dev); 791 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 792 int pcie_get_readrq(struct pci_dev *dev); 793 int pcie_set_readrq(struct pci_dev *dev, int rq); 794 int __pci_reset_function(struct pci_dev *dev); 795 int pci_reset_function(struct pci_dev *dev); 796 void pci_update_resource(struct pci_dev *dev, int resno); 797 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 798 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 799 800 /* ROM control related routines */ 801 int pci_enable_rom(struct pci_dev *pdev); 802 void pci_disable_rom(struct pci_dev *pdev); 803 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 804 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 805 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 806 807 /* Power management related routines */ 808 int pci_save_state(struct pci_dev *dev); 809 void pci_restore_state(struct pci_dev *dev); 810 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 811 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 812 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 813 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 814 void pci_pme_active(struct pci_dev *dev, bool enable); 815 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 816 bool runtime, bool enable); 817 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 818 pci_power_t pci_target_state(struct pci_dev *dev); 819 int pci_prepare_to_sleep(struct pci_dev *dev); 820 int pci_back_from_sleep(struct pci_dev *dev); 821 bool pci_dev_run_wake(struct pci_dev *dev); 822 bool pci_check_pme_status(struct pci_dev *dev); 823 void pci_pme_wakeup_bus(struct pci_bus *bus); 824 825 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 826 bool enable) 827 { 828 return __pci_enable_wake(dev, state, false, enable); 829 } 830 831 /* For use by arch with custom probe code */ 832 void set_pcie_port_type(struct pci_dev *pdev); 833 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 834 835 /* Functions for PCI Hotplug drivers to use */ 836 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 837 #ifdef CONFIG_HOTPLUG 838 unsigned int pci_rescan_bus(struct pci_bus *bus); 839 #endif 840 841 /* Vital product data routines */ 842 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 843 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 844 int pci_vpd_truncate(struct pci_dev *dev, size_t size); 845 846 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 847 void pci_bus_assign_resources(const struct pci_bus *bus); 848 void pci_bus_size_bridges(struct pci_bus *bus); 849 int pci_claim_resource(struct pci_dev *, int); 850 void pci_assign_unassigned_resources(void); 851 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 852 void pdev_enable_device(struct pci_dev *); 853 void pdev_sort_resources(struct pci_dev *, struct resource_list *); 854 int pci_enable_resources(struct pci_dev *, int mask); 855 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 856 int (*)(struct pci_dev *, u8, u8)); 857 #define HAVE_PCI_REQ_REGIONS 2 858 int __must_check pci_request_regions(struct pci_dev *, const char *); 859 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 860 void pci_release_regions(struct pci_dev *); 861 int __must_check pci_request_region(struct pci_dev *, int, const char *); 862 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 863 void pci_release_region(struct pci_dev *, int); 864 int pci_request_selected_regions(struct pci_dev *, int, const char *); 865 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 866 void pci_release_selected_regions(struct pci_dev *, int); 867 868 /* drivers/pci/bus.c */ 869 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 870 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 871 void pci_bus_remove_resources(struct pci_bus *bus); 872 873 #define pci_bus_for_each_resource(bus, res, i) \ 874 for (i = 0; \ 875 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 876 i++) 877 878 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 879 struct resource *res, resource_size_t size, 880 resource_size_t align, resource_size_t min, 881 unsigned int type_mask, 882 resource_size_t (*alignf)(void *, 883 const struct resource *, 884 resource_size_t, 885 resource_size_t), 886 void *alignf_data); 887 void pci_enable_bridges(struct pci_bus *bus); 888 889 /* Proper probing supporting hot-pluggable devices */ 890 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 891 const char *mod_name); 892 893 /* 894 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 895 */ 896 #define pci_register_driver(driver) \ 897 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 898 899 void pci_unregister_driver(struct pci_driver *dev); 900 void pci_remove_behind_bridge(struct pci_dev *dev); 901 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 902 int pci_add_dynid(struct pci_driver *drv, 903 unsigned int vendor, unsigned int device, 904 unsigned int subvendor, unsigned int subdevice, 905 unsigned int class, unsigned int class_mask, 906 unsigned long driver_data); 907 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 908 struct pci_dev *dev); 909 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 910 int pass); 911 912 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 913 void *userdata); 914 int pci_cfg_space_size_ext(struct pci_dev *dev); 915 int pci_cfg_space_size(struct pci_dev *dev); 916 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 917 918 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 919 unsigned int command_bits, bool change_bridge); 920 /* kmem_cache style wrapper around pci_alloc_consistent() */ 921 922 #include <linux/pci-dma.h> 923 #include <linux/dmapool.h> 924 925 #define pci_pool dma_pool 926 #define pci_pool_create(name, pdev, size, align, allocation) \ 927 dma_pool_create(name, &pdev->dev, size, align, allocation) 928 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 929 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 930 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 931 932 enum pci_dma_burst_strategy { 933 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, 934 strategy_parameter is N/A */ 935 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter 936 byte boundaries */ 937 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of 938 strategy_parameter byte boundaries */ 939 }; 940 941 struct msix_entry { 942 u32 vector; /* kernel uses to write allocated vector */ 943 u16 entry; /* driver uses to specify entry, OS writes */ 944 }; 945 946 947 #ifndef CONFIG_PCI_MSI 948 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) 949 { 950 return -1; 951 } 952 953 static inline void pci_msi_shutdown(struct pci_dev *dev) 954 { } 955 static inline void pci_disable_msi(struct pci_dev *dev) 956 { } 957 958 static inline int pci_msix_table_size(struct pci_dev *dev) 959 { 960 return 0; 961 } 962 static inline int pci_enable_msix(struct pci_dev *dev, 963 struct msix_entry *entries, int nvec) 964 { 965 return -1; 966 } 967 968 static inline void pci_msix_shutdown(struct pci_dev *dev) 969 { } 970 static inline void pci_disable_msix(struct pci_dev *dev) 971 { } 972 973 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) 974 { } 975 976 static inline void pci_restore_msi_state(struct pci_dev *dev) 977 { } 978 static inline int pci_msi_enabled(void) 979 { 980 return 0; 981 } 982 #else 983 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); 984 extern void pci_msi_shutdown(struct pci_dev *dev); 985 extern void pci_disable_msi(struct pci_dev *dev); 986 extern int pci_msix_table_size(struct pci_dev *dev); 987 extern int pci_enable_msix(struct pci_dev *dev, 988 struct msix_entry *entries, int nvec); 989 extern void pci_msix_shutdown(struct pci_dev *dev); 990 extern void pci_disable_msix(struct pci_dev *dev); 991 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); 992 extern void pci_restore_msi_state(struct pci_dev *dev); 993 extern int pci_msi_enabled(void); 994 #endif 995 996 #ifdef CONFIG_PCIEPORTBUS 997 extern bool pcie_ports_disabled; 998 extern bool pcie_ports_auto; 999 #else 1000 #define pcie_ports_disabled true 1001 #define pcie_ports_auto false 1002 #endif 1003 1004 #ifndef CONFIG_PCIEASPM 1005 static inline int pcie_aspm_enabled(void) 1006 { 1007 return 0; 1008 } 1009 #else 1010 extern int pcie_aspm_enabled(void); 1011 #endif 1012 1013 #ifdef CONFIG_PCIEAER 1014 void pci_no_aer(void); 1015 bool pci_aer_available(void); 1016 #else 1017 static inline void pci_no_aer(void) { } 1018 static inline bool pci_aer_available(void) { return false; } 1019 #endif 1020 1021 #ifndef CONFIG_PCIE_ECRC 1022 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) 1023 { 1024 return; 1025 } 1026 static inline void pcie_ecrc_get_policy(char *str) {}; 1027 #else 1028 extern void pcie_set_ecrc_checking(struct pci_dev *dev); 1029 extern void pcie_ecrc_get_policy(char *str); 1030 #endif 1031 1032 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) 1033 1034 #ifdef CONFIG_HT_IRQ 1035 /* The functions a driver should call */ 1036 int ht_create_irq(struct pci_dev *dev, int idx); 1037 void ht_destroy_irq(unsigned int irq); 1038 #endif /* CONFIG_HT_IRQ */ 1039 1040 extern void pci_block_user_cfg_access(struct pci_dev *dev); 1041 extern void pci_unblock_user_cfg_access(struct pci_dev *dev); 1042 1043 /* 1044 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1045 * a PCI domain is defined to be a set of PCI busses which share 1046 * configuration space. 1047 */ 1048 #ifdef CONFIG_PCI_DOMAINS 1049 extern int pci_domains_supported; 1050 #else 1051 enum { pci_domains_supported = 0 }; 1052 static inline int pci_domain_nr(struct pci_bus *bus) 1053 { 1054 return 0; 1055 } 1056 1057 static inline int pci_proc_domain(struct pci_bus *bus) 1058 { 1059 return 0; 1060 } 1061 #endif /* CONFIG_PCI_DOMAINS */ 1062 1063 /* some architectures require additional setup to direct VGA traffic */ 1064 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1065 unsigned int command_bits, bool change_bridge); 1066 extern void pci_register_set_vga_state(arch_set_vga_state_t func); 1067 1068 #else /* CONFIG_PCI is not enabled */ 1069 1070 /* 1071 * If the system does not have PCI, clearly these return errors. Define 1072 * these as simple inline functions to avoid hair in drivers. 1073 */ 1074 1075 #define _PCI_NOP(o, s, t) \ 1076 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1077 int where, t val) \ 1078 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1079 1080 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1081 _PCI_NOP(o, word, u16 x) \ 1082 _PCI_NOP(o, dword, u32 x) 1083 _PCI_NOP_ALL(read, *) 1084 _PCI_NOP_ALL(write,) 1085 1086 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1087 unsigned int device, 1088 struct pci_dev *from) 1089 { 1090 return NULL; 1091 } 1092 1093 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1094 unsigned int device, 1095 unsigned int ss_vendor, 1096 unsigned int ss_device, 1097 struct pci_dev *from) 1098 { 1099 return NULL; 1100 } 1101 1102 static inline struct pci_dev *pci_get_class(unsigned int class, 1103 struct pci_dev *from) 1104 { 1105 return NULL; 1106 } 1107 1108 #define pci_dev_present(ids) (0) 1109 #define no_pci_devices() (1) 1110 #define pci_dev_put(dev) do { } while (0) 1111 1112 static inline void pci_set_master(struct pci_dev *dev) 1113 { } 1114 1115 static inline int pci_enable_device(struct pci_dev *dev) 1116 { 1117 return -EIO; 1118 } 1119 1120 static inline void pci_disable_device(struct pci_dev *dev) 1121 { } 1122 1123 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1124 { 1125 return -EIO; 1126 } 1127 1128 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1129 { 1130 return -EIO; 1131 } 1132 1133 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1134 unsigned int size) 1135 { 1136 return -EIO; 1137 } 1138 1139 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1140 unsigned long mask) 1141 { 1142 return -EIO; 1143 } 1144 1145 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1146 { 1147 return -EBUSY; 1148 } 1149 1150 static inline int __pci_register_driver(struct pci_driver *drv, 1151 struct module *owner) 1152 { 1153 return 0; 1154 } 1155 1156 static inline int pci_register_driver(struct pci_driver *drv) 1157 { 1158 return 0; 1159 } 1160 1161 static inline void pci_unregister_driver(struct pci_driver *drv) 1162 { } 1163 1164 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1165 { 1166 return 0; 1167 } 1168 1169 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1170 int cap) 1171 { 1172 return 0; 1173 } 1174 1175 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1176 { 1177 return 0; 1178 } 1179 1180 /* Power management related routines */ 1181 static inline int pci_save_state(struct pci_dev *dev) 1182 { 1183 return 0; 1184 } 1185 1186 static inline void pci_restore_state(struct pci_dev *dev) 1187 { } 1188 1189 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1190 { 1191 return 0; 1192 } 1193 1194 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1195 { 1196 return 0; 1197 } 1198 1199 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1200 pm_message_t state) 1201 { 1202 return PCI_D0; 1203 } 1204 1205 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1206 int enable) 1207 { 1208 return 0; 1209 } 1210 1211 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1212 { 1213 return -EIO; 1214 } 1215 1216 static inline void pci_release_regions(struct pci_dev *dev) 1217 { } 1218 1219 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 1220 1221 static inline void pci_block_user_cfg_access(struct pci_dev *dev) 1222 { } 1223 1224 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) 1225 { } 1226 1227 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1228 { return NULL; } 1229 1230 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1231 unsigned int devfn) 1232 { return NULL; } 1233 1234 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1235 unsigned int devfn) 1236 { return NULL; } 1237 1238 static inline int pci_domain_nr(struct pci_bus *bus) 1239 { return 0; } 1240 1241 #define dev_is_pci(d) (false) 1242 #define dev_is_pf(d) (false) 1243 #define dev_num_vf(d) (0) 1244 #endif /* CONFIG_PCI */ 1245 1246 /* Include architecture-dependent settings and functions */ 1247 1248 #include <asm/pci.h> 1249 1250 #ifndef PCIBIOS_MAX_MEM_32 1251 #define PCIBIOS_MAX_MEM_32 (-1) 1252 #endif 1253 1254 /* these helpers provide future and backwards compatibility 1255 * for accessing popular PCI BAR info */ 1256 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1257 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1258 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1259 #define pci_resource_len(dev,bar) \ 1260 ((pci_resource_start((dev), (bar)) == 0 && \ 1261 pci_resource_end((dev), (bar)) == \ 1262 pci_resource_start((dev), (bar))) ? 0 : \ 1263 \ 1264 (pci_resource_end((dev), (bar)) - \ 1265 pci_resource_start((dev), (bar)) + 1)) 1266 1267 /* Similar to the helpers above, these manipulate per-pci_dev 1268 * driver-specific data. They are really just a wrapper around 1269 * the generic device structure functions of these calls. 1270 */ 1271 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1272 { 1273 return dev_get_drvdata(&pdev->dev); 1274 } 1275 1276 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1277 { 1278 dev_set_drvdata(&pdev->dev, data); 1279 } 1280 1281 /* If you want to know what to call your pci_dev, ask this function. 1282 * Again, it's a wrapper around the generic device. 1283 */ 1284 static inline const char *pci_name(const struct pci_dev *pdev) 1285 { 1286 return dev_name(&pdev->dev); 1287 } 1288 1289 1290 /* Some archs don't want to expose struct resource to userland as-is 1291 * in sysfs and /proc 1292 */ 1293 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1294 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1295 const struct resource *rsrc, resource_size_t *start, 1296 resource_size_t *end) 1297 { 1298 *start = rsrc->start; 1299 *end = rsrc->end; 1300 } 1301 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1302 1303 1304 /* 1305 * The world is not perfect and supplies us with broken PCI devices. 1306 * For at least a part of these bugs we need a work-around, so both 1307 * generic (drivers/pci/quirks.c) and per-architecture code can define 1308 * fixup hooks to be called for particular buggy devices. 1309 */ 1310 1311 struct pci_fixup { 1312 u16 vendor, device; /* You can use PCI_ANY_ID here of course */ 1313 void (*hook)(struct pci_dev *dev); 1314 }; 1315 1316 enum pci_fixup_pass { 1317 pci_fixup_early, /* Before probing BARs */ 1318 pci_fixup_header, /* After reading configuration header */ 1319 pci_fixup_final, /* Final phase of device fixups */ 1320 pci_fixup_enable, /* pci_enable_device() time */ 1321 pci_fixup_resume, /* pci_device_resume() */ 1322 pci_fixup_suspend, /* pci_device_suspend */ 1323 pci_fixup_resume_early, /* pci_device_resume_early() */ 1324 }; 1325 1326 /* Anonymous variables would be nice... */ 1327 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ 1328 static const struct pci_fixup __pci_fixup_##name __used \ 1329 __attribute__((__section__(#section))) = { vendor, device, hook }; 1330 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1331 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1332 vendor##device##hook, vendor, device, hook) 1333 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1334 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1335 vendor##device##hook, vendor, device, hook) 1336 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1337 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1338 vendor##device##hook, vendor, device, hook) 1339 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1340 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1341 vendor##device##hook, vendor, device, hook) 1342 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1343 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1344 resume##vendor##device##hook, vendor, device, hook) 1345 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1346 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1347 resume_early##vendor##device##hook, vendor, device, hook) 1348 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1349 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1350 suspend##vendor##device##hook, vendor, device, hook) 1351 1352 #ifdef CONFIG_PCI_QUIRKS 1353 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1354 #else 1355 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1356 struct pci_dev *dev) {} 1357 #endif 1358 1359 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1360 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1361 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1362 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); 1363 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, 1364 const char *name); 1365 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); 1366 1367 extern int pci_pci_problems; 1368 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1369 #define PCIPCI_TRITON 2 1370 #define PCIPCI_NATOMA 4 1371 #define PCIPCI_VIAETBF 8 1372 #define PCIPCI_VSFX 16 1373 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1374 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1375 1376 extern unsigned long pci_cardbus_io_size; 1377 extern unsigned long pci_cardbus_mem_size; 1378 extern u8 __devinitdata pci_dfl_cache_line_size; 1379 extern u8 pci_cache_line_size; 1380 1381 extern unsigned long pci_hotplug_io_size; 1382 extern unsigned long pci_hotplug_mem_size; 1383 1384 int pcibios_add_platform_entries(struct pci_dev *dev); 1385 void pcibios_disable_device(struct pci_dev *dev); 1386 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1387 enum pcie_reset_state state); 1388 1389 #ifdef CONFIG_PCI_MMCONFIG 1390 extern void __init pci_mmcfg_early_init(void); 1391 extern void __init pci_mmcfg_late_init(void); 1392 #else 1393 static inline void pci_mmcfg_early_init(void) { } 1394 static inline void pci_mmcfg_late_init(void) { } 1395 #endif 1396 1397 int pci_ext_cfg_avail(struct pci_dev *dev); 1398 1399 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1400 1401 #ifdef CONFIG_PCI_IOV 1402 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1403 extern void pci_disable_sriov(struct pci_dev *dev); 1404 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev); 1405 extern int pci_num_vf(struct pci_dev *dev); 1406 #else 1407 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1408 { 1409 return -ENODEV; 1410 } 1411 static inline void pci_disable_sriov(struct pci_dev *dev) 1412 { 1413 } 1414 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) 1415 { 1416 return IRQ_NONE; 1417 } 1418 static inline int pci_num_vf(struct pci_dev *dev) 1419 { 1420 return 0; 1421 } 1422 #endif 1423 1424 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1425 extern void pci_hp_create_module_link(struct pci_slot *pci_slot); 1426 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1427 #endif 1428 1429 /** 1430 * pci_pcie_cap - get the saved PCIe capability offset 1431 * @dev: PCI device 1432 * 1433 * PCIe capability offset is calculated at PCI device initialization 1434 * time and saved in the data structure. This function returns saved 1435 * PCIe capability offset. Using this instead of pci_find_capability() 1436 * reduces unnecessary search in the PCI configuration space. If you 1437 * need to calculate PCIe capability offset from raw device for some 1438 * reasons, please use pci_find_capability() instead. 1439 */ 1440 static inline int pci_pcie_cap(struct pci_dev *dev) 1441 { 1442 return dev->pcie_cap; 1443 } 1444 1445 /** 1446 * pci_is_pcie - check if the PCI device is PCI Express capable 1447 * @dev: PCI device 1448 * 1449 * Retrun true if the PCI device is PCI Express capable, false otherwise. 1450 */ 1451 static inline bool pci_is_pcie(struct pci_dev *dev) 1452 { 1453 return !!pci_pcie_cap(dev); 1454 } 1455 1456 void pci_request_acs(void); 1457 1458 1459 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1460 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) 1461 1462 /* Large Resource Data Type Tag Item Names */ 1463 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1464 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1465 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1466 1467 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1468 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1469 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1470 1471 /* Small Resource Data Type Tag Item Names */ 1472 #define PCI_VPD_STIN_END 0x78 /* End */ 1473 1474 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1475 1476 #define PCI_VPD_SRDT_TIN_MASK 0x78 1477 #define PCI_VPD_SRDT_LEN_MASK 0x07 1478 1479 #define PCI_VPD_LRDT_TAG_SIZE 3 1480 #define PCI_VPD_SRDT_TAG_SIZE 1 1481 1482 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1483 1484 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1485 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1486 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1487 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1488 1489 /** 1490 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1491 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1492 * 1493 * Returns the extracted Large Resource Data Type length. 1494 */ 1495 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1496 { 1497 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1498 } 1499 1500 /** 1501 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1502 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1503 * 1504 * Returns the extracted Small Resource Data Type length. 1505 */ 1506 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1507 { 1508 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1509 } 1510 1511 /** 1512 * pci_vpd_info_field_size - Extracts the information field length 1513 * @lrdt: Pointer to the beginning of an information field header 1514 * 1515 * Returns the extracted information field length. 1516 */ 1517 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1518 { 1519 return info_field[2]; 1520 } 1521 1522 /** 1523 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1524 * @buf: Pointer to buffered vpd data 1525 * @off: The offset into the buffer at which to begin the search 1526 * @len: The length of the vpd buffer 1527 * @rdt: The Resource Data Type to search for 1528 * 1529 * Returns the index where the Resource Data Type was found or 1530 * -ENOENT otherwise. 1531 */ 1532 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1533 1534 /** 1535 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1536 * @buf: Pointer to buffered vpd data 1537 * @off: The offset into the buffer at which to begin the search 1538 * @len: The length of the buffer area, relative to off, in which to search 1539 * @kw: The keyword to search for 1540 * 1541 * Returns the index where the information field keyword was found or 1542 * -ENOENT otherwise. 1543 */ 1544 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1545 unsigned int len, const char *kw); 1546 1547 #endif /* __KERNEL__ */ 1548 #endif /* LINUX_PCI_H */ 1549