1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 #include <linux/pci_regs.h> /* The pci register defines */ 21 22 /* 23 * The PCI interface treats multi-function devices as independent 24 * devices. The slot/function address of each device is encoded 25 * in a single byte as follows: 26 * 27 * 7:3 = slot 28 * 2:0 = function 29 */ 30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 32 #define PCI_FUNC(devfn) ((devfn) & 0x07) 33 34 /* Ioctls for /proc/bus/pci/X/Y nodes. */ 35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) 36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ 37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ 38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ 39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ 40 41 #ifdef __KERNEL__ 42 43 #include <linux/mod_devicetable.h> 44 45 #include <linux/types.h> 46 #include <linux/init.h> 47 #include <linux/ioport.h> 48 #include <linux/list.h> 49 #include <linux/compiler.h> 50 #include <linux/errno.h> 51 #include <linux/kobject.h> 52 #include <asm/atomic.h> 53 #include <linux/device.h> 54 #include <linux/io.h> 55 #include <linux/irqreturn.h> 56 57 /* Include the ID list */ 58 #include <linux/pci_ids.h> 59 60 /* pci_slot represents a physical slot */ 61 struct pci_slot { 62 struct pci_bus *bus; /* The bus this slot is on */ 63 struct list_head list; /* node in list of slots on this bus */ 64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 66 struct kobject kobj; 67 }; 68 69 static inline const char *pci_slot_name(const struct pci_slot *slot) 70 { 71 return kobject_name(&slot->kobj); 72 } 73 74 /* File state for mmap()s on /proc/bus/pci/X/Y */ 75 enum pci_mmap_state { 76 pci_mmap_io, 77 pci_mmap_mem 78 }; 79 80 /* This defines the direction arg to the DMA mapping routines. */ 81 #define PCI_DMA_BIDIRECTIONAL 0 82 #define PCI_DMA_TODEVICE 1 83 #define PCI_DMA_FROMDEVICE 2 84 #define PCI_DMA_NONE 3 85 86 /* 87 * For PCI devices, the region numbers are assigned this way: 88 */ 89 enum { 90 /* #0-5: standard PCI resources */ 91 PCI_STD_RESOURCES, 92 PCI_STD_RESOURCE_END = 5, 93 94 /* #6: expansion ROM resource */ 95 PCI_ROM_RESOURCE, 96 97 /* device specific resources */ 98 #ifdef CONFIG_PCI_IOV 99 PCI_IOV_RESOURCES, 100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 101 #endif 102 103 /* resources assigned to buses behind the bridge */ 104 #define PCI_BRIDGE_RESOURCE_NUM 4 105 106 PCI_BRIDGE_RESOURCES, 107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 108 PCI_BRIDGE_RESOURCE_NUM - 1, 109 110 /* total resources associated with a PCI device */ 111 PCI_NUM_RESOURCES, 112 113 /* preserve this for compatibility */ 114 DEVICE_COUNT_RESOURCE 115 }; 116 117 typedef int __bitwise pci_power_t; 118 119 #define PCI_D0 ((pci_power_t __force) 0) 120 #define PCI_D1 ((pci_power_t __force) 1) 121 #define PCI_D2 ((pci_power_t __force) 2) 122 #define PCI_D3hot ((pci_power_t __force) 3) 123 #define PCI_D3cold ((pci_power_t __force) 4) 124 #define PCI_UNKNOWN ((pci_power_t __force) 5) 125 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 126 127 /* Remember to update this when the list above changes! */ 128 extern const char *pci_power_names[]; 129 130 static inline const char *pci_power_name(pci_power_t state) 131 { 132 return pci_power_names[1 + (int) state]; 133 } 134 135 #define PCI_PM_D2_DELAY 200 136 #define PCI_PM_D3_WAIT 10 137 #define PCI_PM_BUS_WAIT 50 138 139 /** The pci_channel state describes connectivity between the CPU and 140 * the pci device. If some PCI bus between here and the pci device 141 * has crashed or locked up, this info is reflected here. 142 */ 143 typedef unsigned int __bitwise pci_channel_state_t; 144 145 enum pci_channel_state { 146 /* I/O channel is in normal state */ 147 pci_channel_io_normal = (__force pci_channel_state_t) 1, 148 149 /* I/O to channel is blocked */ 150 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 151 152 /* PCI card is dead */ 153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 154 }; 155 156 typedef unsigned int __bitwise pcie_reset_state_t; 157 158 enum pcie_reset_state { 159 /* Reset is NOT asserted (Use to deassert reset) */ 160 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 161 162 /* Use #PERST to reset PCI-E device */ 163 pcie_warm_reset = (__force pcie_reset_state_t) 2, 164 165 /* Use PCI-E Hot Reset to reset device */ 166 pcie_hot_reset = (__force pcie_reset_state_t) 3 167 }; 168 169 typedef unsigned short __bitwise pci_dev_flags_t; 170 enum pci_dev_flags { 171 /* INTX_DISABLE in PCI_COMMAND register disables MSI 172 * generation too. 173 */ 174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, 175 /* Device configuration is irrevocably lost if disabled into D3 */ 176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, 177 }; 178 179 enum pci_irq_reroute_variant { 180 INTEL_IRQ_REROUTE_VARIANT = 1, 181 MAX_IRQ_REROUTE_VARIANTS = 3 182 }; 183 184 typedef unsigned short __bitwise pci_bus_flags_t; 185 enum pci_bus_flags { 186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 188 }; 189 190 struct pci_cap_saved_state { 191 struct hlist_node next; 192 char cap_nr; 193 u32 data[0]; 194 }; 195 196 struct pcie_link_state; 197 struct pci_vpd; 198 struct pci_sriov; 199 struct pci_ats; 200 201 /* 202 * The pci_dev structure is used to describe PCI devices. 203 */ 204 struct pci_dev { 205 struct list_head bus_list; /* node in per-bus list */ 206 struct pci_bus *bus; /* bus this device is on */ 207 struct pci_bus *subordinate; /* bus this device bridges to */ 208 209 void *sysdata; /* hook for sys-specific extension */ 210 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 211 struct pci_slot *slot; /* Physical slot this device is in */ 212 213 unsigned int devfn; /* encoded device & function index */ 214 unsigned short vendor; 215 unsigned short device; 216 unsigned short subsystem_vendor; 217 unsigned short subsystem_device; 218 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 219 u8 revision; /* PCI revision, low byte of class word */ 220 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 221 u8 pcie_cap; /* PCI-E capability offset */ 222 u8 pcie_type; /* PCI-E device/port type */ 223 u8 rom_base_reg; /* which config register controls the ROM */ 224 u8 pin; /* which interrupt pin this device uses */ 225 226 struct pci_driver *driver; /* which driver has allocated this device */ 227 u64 dma_mask; /* Mask of the bits of bus address this 228 device implements. Normally this is 229 0xffffffff. You only need to change 230 this if your device has broken DMA 231 or supports 64-bit transfers. */ 232 233 struct device_dma_parameters dma_parms; 234 235 pci_power_t current_state; /* Current operating state. In ACPI-speak, 236 this is D0-D3, D0 being fully functional, 237 and D3 being off. */ 238 int pm_cap; /* PM capability offset in the 239 configuration space */ 240 unsigned int pme_support:5; /* Bitmask of states from which PME# 241 can be generated */ 242 unsigned int d1_support:1; /* Low power state D1 is supported */ 243 unsigned int d2_support:1; /* Low power state D2 is supported */ 244 unsigned int no_d1d2:1; /* Only allow D0 and D3 */ 245 unsigned int wakeup_prepared:1; 246 247 #ifdef CONFIG_PCIEASPM 248 struct pcie_link_state *link_state; /* ASPM link state. */ 249 #endif 250 251 pci_channel_state_t error_state; /* current connectivity state */ 252 struct device dev; /* Generic device interface */ 253 254 int cfg_size; /* Size of configuration space */ 255 256 /* 257 * Instead of touching interrupt line and base address registers 258 * directly, use the values stored here. They might be different! 259 */ 260 unsigned int irq; 261 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 262 263 /* These fields are used by common fixups */ 264 unsigned int transparent:1; /* Transparent PCI bridge */ 265 unsigned int multifunction:1;/* Part of multi-function device */ 266 /* keep track of device state */ 267 unsigned int is_added:1; 268 unsigned int is_busmaster:1; /* device is busmaster */ 269 unsigned int no_msi:1; /* device may not use msi */ 270 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ 271 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 272 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 273 unsigned int msi_enabled:1; 274 unsigned int msix_enabled:1; 275 unsigned int ari_enabled:1; /* ARI forwarding */ 276 unsigned int is_managed:1; 277 unsigned int is_pcie:1; 278 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 279 unsigned int state_saved:1; 280 unsigned int is_physfn:1; 281 unsigned int is_virtfn:1; 282 unsigned int reset_fn:1; 283 unsigned int is_hotplug_bridge:1; 284 unsigned int aer_firmware_first:1; 285 pci_dev_flags_t dev_flags; 286 atomic_t enable_cnt; /* pci_enable_device has been called */ 287 288 u32 saved_config_space[16]; /* config space saved at suspend time */ 289 struct hlist_head saved_cap_space; 290 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 291 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 292 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 293 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 294 #ifdef CONFIG_PCI_MSI 295 struct list_head msi_list; 296 #endif 297 struct pci_vpd *vpd; 298 #ifdef CONFIG_PCI_IOV 299 union { 300 struct pci_sriov *sriov; /* SR-IOV capability related */ 301 struct pci_dev *physfn; /* the PF this VF is associated with */ 302 }; 303 struct pci_ats *ats; /* Address Translation Service */ 304 #endif 305 }; 306 307 extern struct pci_dev *alloc_pci_dev(void); 308 309 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) 310 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 311 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 312 313 static inline int pci_channel_offline(struct pci_dev *pdev) 314 { 315 return (pdev->error_state != pci_channel_io_normal); 316 } 317 318 static inline struct pci_cap_saved_state *pci_find_saved_cap( 319 struct pci_dev *pci_dev, char cap) 320 { 321 struct pci_cap_saved_state *tmp; 322 struct hlist_node *pos; 323 324 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { 325 if (tmp->cap_nr == cap) 326 return tmp; 327 } 328 return NULL; 329 } 330 331 static inline void pci_add_saved_cap(struct pci_dev *pci_dev, 332 struct pci_cap_saved_state *new_cap) 333 { 334 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); 335 } 336 337 #ifndef PCI_BUS_NUM_RESOURCES 338 #define PCI_BUS_NUM_RESOURCES 16 339 #endif 340 341 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 342 343 struct pci_bus { 344 struct list_head node; /* node in list of buses */ 345 struct pci_bus *parent; /* parent bus this bridge is on */ 346 struct list_head children; /* list of child buses */ 347 struct list_head devices; /* list of devices on this bus */ 348 struct pci_dev *self; /* bridge device as seen by parent */ 349 struct list_head slots; /* list of slots on this bus */ 350 struct resource *resource[PCI_BUS_NUM_RESOURCES]; 351 /* address space routed to this bus */ 352 353 struct pci_ops *ops; /* configuration access functions */ 354 void *sysdata; /* hook for sys-specific extension */ 355 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 356 357 unsigned char number; /* bus number */ 358 unsigned char primary; /* number of primary bridge */ 359 unsigned char secondary; /* number of secondary bridge */ 360 unsigned char subordinate; /* max number of subordinate buses */ 361 362 char name[48]; 363 364 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 365 pci_bus_flags_t bus_flags; /* Inherited by child busses */ 366 struct device *bridge; 367 struct device dev; 368 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 369 struct bin_attribute *legacy_mem; /* legacy mem */ 370 unsigned int is_added:1; 371 }; 372 373 #define pci_bus_b(n) list_entry(n, struct pci_bus, node) 374 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 375 376 /* 377 * Returns true if the pci bus is root (behind host-pci bridge), 378 * false otherwise 379 */ 380 static inline bool pci_is_root_bus(struct pci_bus *pbus) 381 { 382 return !(pbus->parent); 383 } 384 385 #ifdef CONFIG_PCI_MSI 386 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 387 { 388 return pci_dev->msi_enabled || pci_dev->msix_enabled; 389 } 390 #else 391 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 392 #endif 393 394 /* 395 * Error values that may be returned by PCI functions. 396 */ 397 #define PCIBIOS_SUCCESSFUL 0x00 398 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 399 #define PCIBIOS_BAD_VENDOR_ID 0x83 400 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 401 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 402 #define PCIBIOS_SET_FAILED 0x88 403 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 404 405 /* Low-level architecture-dependent routines */ 406 407 struct pci_ops { 408 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 409 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 410 }; 411 412 /* 413 * ACPI needs to be able to access PCI config space before we've done a 414 * PCI bus scan and created pci_bus structures. 415 */ 416 extern int raw_pci_read(unsigned int domain, unsigned int bus, 417 unsigned int devfn, int reg, int len, u32 *val); 418 extern int raw_pci_write(unsigned int domain, unsigned int bus, 419 unsigned int devfn, int reg, int len, u32 val); 420 421 struct pci_bus_region { 422 resource_size_t start; 423 resource_size_t end; 424 }; 425 426 struct pci_dynids { 427 spinlock_t lock; /* protects list, index */ 428 struct list_head list; /* for IDs added at runtime */ 429 }; 430 431 /* ---------------------------------------------------------------- */ 432 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 433 * a set of callbacks in struct pci_error_handlers, then that device driver 434 * will be notified of PCI bus errors, and will be driven to recovery 435 * when an error occurs. 436 */ 437 438 typedef unsigned int __bitwise pci_ers_result_t; 439 440 enum pci_ers_result { 441 /* no result/none/not supported in device driver */ 442 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 443 444 /* Device driver can recover without slot reset */ 445 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 446 447 /* Device driver wants slot to be reset. */ 448 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 449 450 /* Device has completely failed, is unrecoverable */ 451 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 452 453 /* Device driver is fully recovered and operational */ 454 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 455 }; 456 457 /* PCI bus error event callbacks */ 458 struct pci_error_handlers { 459 /* PCI bus error detected on this device */ 460 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 461 enum pci_channel_state error); 462 463 /* MMIO has been re-enabled, but not DMA */ 464 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 465 466 /* PCI Express link has been reset */ 467 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 468 469 /* PCI slot has been reset */ 470 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 471 472 /* Device driver may resume normal operations */ 473 void (*resume)(struct pci_dev *dev); 474 }; 475 476 /* ---------------------------------------------------------------- */ 477 478 struct module; 479 struct pci_driver { 480 struct list_head node; 481 char *name; 482 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 483 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 484 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 485 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 486 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 487 int (*resume_early) (struct pci_dev *dev); 488 int (*resume) (struct pci_dev *dev); /* Device woken up */ 489 void (*shutdown) (struct pci_dev *dev); 490 struct pci_error_handlers *err_handler; 491 struct device_driver driver; 492 struct pci_dynids dynids; 493 }; 494 495 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 496 497 /** 498 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 499 * @_table: device table name 500 * 501 * This macro is used to create a struct pci_device_id array (a device table) 502 * in a generic manner. 503 */ 504 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 505 const struct pci_device_id _table[] __devinitconst 506 507 /** 508 * PCI_DEVICE - macro used to describe a specific pci device 509 * @vend: the 16 bit PCI Vendor ID 510 * @dev: the 16 bit PCI Device ID 511 * 512 * This macro is used to create a struct pci_device_id that matches a 513 * specific device. The subvendor and subdevice fields will be set to 514 * PCI_ANY_ID. 515 */ 516 #define PCI_DEVICE(vend,dev) \ 517 .vendor = (vend), .device = (dev), \ 518 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 519 520 /** 521 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 522 * @dev_class: the class, subclass, prog-if triple for this device 523 * @dev_class_mask: the class mask for this device 524 * 525 * This macro is used to create a struct pci_device_id that matches a 526 * specific PCI class. The vendor, device, subvendor, and subdevice 527 * fields will be set to PCI_ANY_ID. 528 */ 529 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 530 .class = (dev_class), .class_mask = (dev_class_mask), \ 531 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 532 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 533 534 /** 535 * PCI_VDEVICE - macro used to describe a specific pci device in short form 536 * @vendor: the vendor name 537 * @device: the 16 bit PCI Device ID 538 * 539 * This macro is used to create a struct pci_device_id that matches a 540 * specific PCI device. The subvendor, and subdevice fields will be set 541 * to PCI_ANY_ID. The macro allows the next field to follow as the device 542 * private data. 543 */ 544 545 #define PCI_VDEVICE(vendor, device) \ 546 PCI_VENDOR_ID_##vendor, (device), \ 547 PCI_ANY_ID, PCI_ANY_ID, 0, 0 548 549 /* these external functions are only available when PCI support is enabled */ 550 #ifdef CONFIG_PCI 551 552 extern struct bus_type pci_bus_type; 553 554 /* Do NOT directly access these two variables, unless you are arch specific pci 555 * code, or pci core code. */ 556 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 557 /* Some device drivers need know if pci is initiated */ 558 extern int no_pci_devices(void); 559 560 void pcibios_fixup_bus(struct pci_bus *); 561 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 562 char *pcibios_setup(char *str); 563 564 /* Used only when drivers/pci/setup.c is used */ 565 void pcibios_align_resource(void *, struct resource *, resource_size_t, 566 resource_size_t); 567 void pcibios_update_irq(struct pci_dev *, int irq); 568 569 /* Generic PCI functions used internally */ 570 571 extern struct pci_bus *pci_find_bus(int domain, int busnr); 572 void pci_bus_add_devices(const struct pci_bus *bus); 573 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, 574 struct pci_ops *ops, void *sysdata); 575 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, 576 void *sysdata) 577 { 578 struct pci_bus *root_bus; 579 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); 580 if (root_bus) 581 pci_bus_add_devices(root_bus); 582 return root_bus; 583 } 584 struct pci_bus *pci_create_bus(struct device *parent, int bus, 585 struct pci_ops *ops, void *sysdata); 586 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 587 int busnr); 588 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 589 const char *name, 590 struct hotplug_slot *hotplug); 591 void pci_destroy_slot(struct pci_slot *slot); 592 void pci_renumber_slot(struct pci_slot *slot, int slot_nr); 593 int pci_scan_slot(struct pci_bus *bus, int devfn); 594 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 595 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 596 unsigned int pci_scan_child_bus(struct pci_bus *bus); 597 int __must_check pci_bus_add_device(struct pci_dev *dev); 598 void pci_read_bridge_bases(struct pci_bus *child); 599 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 600 struct resource *res); 601 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); 602 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 603 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 604 extern struct pci_dev *pci_dev_get(struct pci_dev *dev); 605 extern void pci_dev_put(struct pci_dev *dev); 606 extern void pci_remove_bus(struct pci_bus *b); 607 extern void pci_remove_bus_device(struct pci_dev *dev); 608 extern void pci_stop_bus_device(struct pci_dev *dev); 609 void pci_setup_cardbus(struct pci_bus *bus); 610 extern void pci_sort_breadthfirst(void); 611 612 /* Generic PCI functions exported to card drivers */ 613 614 #ifdef CONFIG_PCI_LEGACY 615 struct pci_dev __deprecated *pci_find_device(unsigned int vendor, 616 unsigned int device, 617 struct pci_dev *from); 618 #endif /* CONFIG_PCI_LEGACY */ 619 620 enum pci_lost_interrupt_reason { 621 PCI_LOST_IRQ_NO_INFORMATION = 0, 622 PCI_LOST_IRQ_DISABLE_MSI, 623 PCI_LOST_IRQ_DISABLE_MSIX, 624 PCI_LOST_IRQ_DISABLE_ACPI, 625 }; 626 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 627 int pci_find_capability(struct pci_dev *dev, int cap); 628 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 629 int pci_find_ext_capability(struct pci_dev *dev, int cap); 630 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 631 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 632 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 633 634 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 635 struct pci_dev *from); 636 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 637 unsigned int ss_vendor, unsigned int ss_device, 638 struct pci_dev *from); 639 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 640 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 641 unsigned int devfn); 642 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 643 unsigned int devfn) 644 { 645 return pci_get_domain_bus_and_slot(0, bus, devfn); 646 } 647 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 648 int pci_dev_present(const struct pci_device_id *ids); 649 650 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 651 int where, u8 *val); 652 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 653 int where, u16 *val); 654 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 655 int where, u32 *val); 656 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 657 int where, u8 val); 658 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 659 int where, u16 val); 660 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 661 int where, u32 val); 662 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 663 664 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) 665 { 666 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 667 } 668 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) 669 { 670 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 671 } 672 static inline int pci_read_config_dword(struct pci_dev *dev, int where, 673 u32 *val) 674 { 675 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 676 } 677 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) 678 { 679 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 680 } 681 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) 682 { 683 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 684 } 685 static inline int pci_write_config_dword(struct pci_dev *dev, int where, 686 u32 val) 687 { 688 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 689 } 690 691 int __must_check pci_enable_device(struct pci_dev *dev); 692 int __must_check pci_enable_device_io(struct pci_dev *dev); 693 int __must_check pci_enable_device_mem(struct pci_dev *dev); 694 int __must_check pci_reenable_device(struct pci_dev *); 695 int __must_check pcim_enable_device(struct pci_dev *pdev); 696 void pcim_pin_device(struct pci_dev *pdev); 697 698 static inline int pci_is_enabled(struct pci_dev *pdev) 699 { 700 return (atomic_read(&pdev->enable_cnt) > 0); 701 } 702 703 static inline int pci_is_managed(struct pci_dev *pdev) 704 { 705 return pdev->is_managed; 706 } 707 708 void pci_disable_device(struct pci_dev *dev); 709 void pci_set_master(struct pci_dev *dev); 710 void pci_clear_master(struct pci_dev *dev); 711 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 712 int pci_set_cacheline_size(struct pci_dev *dev); 713 #define HAVE_PCI_SET_MWI 714 int __must_check pci_set_mwi(struct pci_dev *dev); 715 int pci_try_set_mwi(struct pci_dev *dev); 716 void pci_clear_mwi(struct pci_dev *dev); 717 void pci_intx(struct pci_dev *dev, int enable); 718 void pci_msi_off(struct pci_dev *dev); 719 int pci_set_dma_mask(struct pci_dev *dev, u64 mask); 720 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); 721 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 722 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 723 int pcix_get_max_mmrbc(struct pci_dev *dev); 724 int pcix_get_mmrbc(struct pci_dev *dev); 725 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 726 int pcie_get_readrq(struct pci_dev *dev); 727 int pcie_set_readrq(struct pci_dev *dev, int rq); 728 int __pci_reset_function(struct pci_dev *dev); 729 int pci_reset_function(struct pci_dev *dev); 730 void pci_update_resource(struct pci_dev *dev, int resno); 731 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 732 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 733 734 /* ROM control related routines */ 735 int pci_enable_rom(struct pci_dev *pdev); 736 void pci_disable_rom(struct pci_dev *pdev); 737 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 738 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 739 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 740 741 /* Power management related routines */ 742 int pci_save_state(struct pci_dev *dev); 743 int pci_restore_state(struct pci_dev *dev); 744 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 745 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 746 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 747 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 748 void pci_pme_active(struct pci_dev *dev, bool enable); 749 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 750 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 751 pci_power_t pci_target_state(struct pci_dev *dev); 752 int pci_prepare_to_sleep(struct pci_dev *dev); 753 int pci_back_from_sleep(struct pci_dev *dev); 754 755 /* Functions for PCI Hotplug drivers to use */ 756 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 757 #ifdef CONFIG_HOTPLUG 758 unsigned int pci_rescan_bus(struct pci_bus *bus); 759 #endif 760 761 /* Vital product data routines */ 762 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 763 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 764 int pci_vpd_truncate(struct pci_dev *dev, size_t size); 765 766 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 767 void pci_bus_assign_resources(const struct pci_bus *bus); 768 void pci_bus_size_bridges(struct pci_bus *bus); 769 int pci_claim_resource(struct pci_dev *, int); 770 void pci_assign_unassigned_resources(void); 771 void pdev_enable_device(struct pci_dev *); 772 void pdev_sort_resources(struct pci_dev *, struct resource_list *); 773 int pci_enable_resources(struct pci_dev *, int mask); 774 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 775 int (*)(struct pci_dev *, u8, u8)); 776 #define HAVE_PCI_REQ_REGIONS 2 777 int __must_check pci_request_regions(struct pci_dev *, const char *); 778 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 779 void pci_release_regions(struct pci_dev *); 780 int __must_check pci_request_region(struct pci_dev *, int, const char *); 781 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 782 void pci_release_region(struct pci_dev *, int); 783 int pci_request_selected_regions(struct pci_dev *, int, const char *); 784 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 785 void pci_release_selected_regions(struct pci_dev *, int); 786 787 /* drivers/pci/bus.c */ 788 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 789 struct resource *res, resource_size_t size, 790 resource_size_t align, resource_size_t min, 791 unsigned int type_mask, 792 void (*alignf)(void *, struct resource *, 793 resource_size_t, resource_size_t), 794 void *alignf_data); 795 void pci_enable_bridges(struct pci_bus *bus); 796 797 /* Proper probing supporting hot-pluggable devices */ 798 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 799 const char *mod_name); 800 801 /* 802 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 803 */ 804 #define pci_register_driver(driver) \ 805 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 806 807 void pci_unregister_driver(struct pci_driver *dev); 808 void pci_remove_behind_bridge(struct pci_dev *dev); 809 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 810 int pci_add_dynid(struct pci_driver *drv, 811 unsigned int vendor, unsigned int device, 812 unsigned int subvendor, unsigned int subdevice, 813 unsigned int class, unsigned int class_mask, 814 unsigned long driver_data); 815 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 816 struct pci_dev *dev); 817 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 818 int pass); 819 820 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 821 void *userdata); 822 int pci_cfg_space_size_ext(struct pci_dev *dev); 823 int pci_cfg_space_size(struct pci_dev *dev); 824 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 825 826 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 827 unsigned int command_bits, bool change_bridge); 828 /* kmem_cache style wrapper around pci_alloc_consistent() */ 829 830 #include <linux/dmapool.h> 831 832 #define pci_pool dma_pool 833 #define pci_pool_create(name, pdev, size, align, allocation) \ 834 dma_pool_create(name, &pdev->dev, size, align, allocation) 835 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 836 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 837 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 838 839 enum pci_dma_burst_strategy { 840 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, 841 strategy_parameter is N/A */ 842 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter 843 byte boundaries */ 844 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of 845 strategy_parameter byte boundaries */ 846 }; 847 848 struct msix_entry { 849 u32 vector; /* kernel uses to write allocated vector */ 850 u16 entry; /* driver uses to specify entry, OS writes */ 851 }; 852 853 854 #ifndef CONFIG_PCI_MSI 855 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) 856 { 857 return -1; 858 } 859 860 static inline void pci_msi_shutdown(struct pci_dev *dev) 861 { } 862 static inline void pci_disable_msi(struct pci_dev *dev) 863 { } 864 865 static inline int pci_msix_table_size(struct pci_dev *dev) 866 { 867 return 0; 868 } 869 static inline int pci_enable_msix(struct pci_dev *dev, 870 struct msix_entry *entries, int nvec) 871 { 872 return -1; 873 } 874 875 static inline void pci_msix_shutdown(struct pci_dev *dev) 876 { } 877 static inline void pci_disable_msix(struct pci_dev *dev) 878 { } 879 880 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) 881 { } 882 883 static inline void pci_restore_msi_state(struct pci_dev *dev) 884 { } 885 static inline int pci_msi_enabled(void) 886 { 887 return 0; 888 } 889 #else 890 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); 891 extern void pci_msi_shutdown(struct pci_dev *dev); 892 extern void pci_disable_msi(struct pci_dev *dev); 893 extern int pci_msix_table_size(struct pci_dev *dev); 894 extern int pci_enable_msix(struct pci_dev *dev, 895 struct msix_entry *entries, int nvec); 896 extern void pci_msix_shutdown(struct pci_dev *dev); 897 extern void pci_disable_msix(struct pci_dev *dev); 898 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); 899 extern void pci_restore_msi_state(struct pci_dev *dev); 900 extern int pci_msi_enabled(void); 901 #endif 902 903 #ifndef CONFIG_PCIEASPM 904 static inline int pcie_aspm_enabled(void) 905 { 906 return 0; 907 } 908 #else 909 extern int pcie_aspm_enabled(void); 910 #endif 911 912 #ifndef CONFIG_PCIE_ECRC 913 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) 914 { 915 return; 916 } 917 static inline void pcie_ecrc_get_policy(char *str) {}; 918 #else 919 extern void pcie_set_ecrc_checking(struct pci_dev *dev); 920 extern void pcie_ecrc_get_policy(char *str); 921 #endif 922 923 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) 924 925 #ifdef CONFIG_HT_IRQ 926 /* The functions a driver should call */ 927 int ht_create_irq(struct pci_dev *dev, int idx); 928 void ht_destroy_irq(unsigned int irq); 929 #endif /* CONFIG_HT_IRQ */ 930 931 extern void pci_block_user_cfg_access(struct pci_dev *dev); 932 extern void pci_unblock_user_cfg_access(struct pci_dev *dev); 933 934 /* 935 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 936 * a PCI domain is defined to be a set of PCI busses which share 937 * configuration space. 938 */ 939 #ifdef CONFIG_PCI_DOMAINS 940 extern int pci_domains_supported; 941 #else 942 enum { pci_domains_supported = 0 }; 943 static inline int pci_domain_nr(struct pci_bus *bus) 944 { 945 return 0; 946 } 947 948 static inline int pci_proc_domain(struct pci_bus *bus) 949 { 950 return 0; 951 } 952 #endif /* CONFIG_PCI_DOMAINS */ 953 954 #else /* CONFIG_PCI is not enabled */ 955 956 /* 957 * If the system does not have PCI, clearly these return errors. Define 958 * these as simple inline functions to avoid hair in drivers. 959 */ 960 961 #define _PCI_NOP(o, s, t) \ 962 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 963 int where, t val) \ 964 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 965 966 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 967 _PCI_NOP(o, word, u16 x) \ 968 _PCI_NOP(o, dword, u32 x) 969 _PCI_NOP_ALL(read, *) 970 _PCI_NOP_ALL(write,) 971 972 static inline struct pci_dev *pci_find_device(unsigned int vendor, 973 unsigned int device, 974 struct pci_dev *from) 975 { 976 return NULL; 977 } 978 979 static inline struct pci_dev *pci_get_device(unsigned int vendor, 980 unsigned int device, 981 struct pci_dev *from) 982 { 983 return NULL; 984 } 985 986 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 987 unsigned int device, 988 unsigned int ss_vendor, 989 unsigned int ss_device, 990 struct pci_dev *from) 991 { 992 return NULL; 993 } 994 995 static inline struct pci_dev *pci_get_class(unsigned int class, 996 struct pci_dev *from) 997 { 998 return NULL; 999 } 1000 1001 #define pci_dev_present(ids) (0) 1002 #define no_pci_devices() (1) 1003 #define pci_dev_put(dev) do { } while (0) 1004 1005 static inline void pci_set_master(struct pci_dev *dev) 1006 { } 1007 1008 static inline int pci_enable_device(struct pci_dev *dev) 1009 { 1010 return -EIO; 1011 } 1012 1013 static inline void pci_disable_device(struct pci_dev *dev) 1014 { } 1015 1016 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1017 { 1018 return -EIO; 1019 } 1020 1021 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1022 { 1023 return -EIO; 1024 } 1025 1026 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1027 unsigned int size) 1028 { 1029 return -EIO; 1030 } 1031 1032 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1033 unsigned long mask) 1034 { 1035 return -EIO; 1036 } 1037 1038 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1039 { 1040 return -EBUSY; 1041 } 1042 1043 static inline int __pci_register_driver(struct pci_driver *drv, 1044 struct module *owner) 1045 { 1046 return 0; 1047 } 1048 1049 static inline int pci_register_driver(struct pci_driver *drv) 1050 { 1051 return 0; 1052 } 1053 1054 static inline void pci_unregister_driver(struct pci_driver *drv) 1055 { } 1056 1057 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1058 { 1059 return 0; 1060 } 1061 1062 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1063 int cap) 1064 { 1065 return 0; 1066 } 1067 1068 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1069 { 1070 return 0; 1071 } 1072 1073 /* Power management related routines */ 1074 static inline int pci_save_state(struct pci_dev *dev) 1075 { 1076 return 0; 1077 } 1078 1079 static inline int pci_restore_state(struct pci_dev *dev) 1080 { 1081 return 0; 1082 } 1083 1084 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1085 { 1086 return 0; 1087 } 1088 1089 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1090 pm_message_t state) 1091 { 1092 return PCI_D0; 1093 } 1094 1095 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1096 int enable) 1097 { 1098 return 0; 1099 } 1100 1101 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1102 { 1103 return -EIO; 1104 } 1105 1106 static inline void pci_release_regions(struct pci_dev *dev) 1107 { } 1108 1109 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 1110 1111 static inline void pci_block_user_cfg_access(struct pci_dev *dev) 1112 { } 1113 1114 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) 1115 { } 1116 1117 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1118 { return NULL; } 1119 1120 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1121 unsigned int devfn) 1122 { return NULL; } 1123 1124 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1125 unsigned int devfn) 1126 { return NULL; } 1127 1128 #endif /* CONFIG_PCI */ 1129 1130 /* Include architecture-dependent settings and functions */ 1131 1132 #include <asm/pci.h> 1133 1134 #ifndef PCIBIOS_MAX_MEM_32 1135 #define PCIBIOS_MAX_MEM_32 (-1) 1136 #endif 1137 1138 /* these helpers provide future and backwards compatibility 1139 * for accessing popular PCI BAR info */ 1140 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1141 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1142 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1143 #define pci_resource_len(dev,bar) \ 1144 ((pci_resource_start((dev), (bar)) == 0 && \ 1145 pci_resource_end((dev), (bar)) == \ 1146 pci_resource_start((dev), (bar))) ? 0 : \ 1147 \ 1148 (pci_resource_end((dev), (bar)) - \ 1149 pci_resource_start((dev), (bar)) + 1)) 1150 1151 /* Similar to the helpers above, these manipulate per-pci_dev 1152 * driver-specific data. They are really just a wrapper around 1153 * the generic device structure functions of these calls. 1154 */ 1155 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1156 { 1157 return dev_get_drvdata(&pdev->dev); 1158 } 1159 1160 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1161 { 1162 dev_set_drvdata(&pdev->dev, data); 1163 } 1164 1165 /* If you want to know what to call your pci_dev, ask this function. 1166 * Again, it's a wrapper around the generic device. 1167 */ 1168 static inline const char *pci_name(const struct pci_dev *pdev) 1169 { 1170 return dev_name(&pdev->dev); 1171 } 1172 1173 1174 /* Some archs don't want to expose struct resource to userland as-is 1175 * in sysfs and /proc 1176 */ 1177 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1178 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1179 const struct resource *rsrc, resource_size_t *start, 1180 resource_size_t *end) 1181 { 1182 *start = rsrc->start; 1183 *end = rsrc->end; 1184 } 1185 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1186 1187 1188 /* 1189 * The world is not perfect and supplies us with broken PCI devices. 1190 * For at least a part of these bugs we need a work-around, so both 1191 * generic (drivers/pci/quirks.c) and per-architecture code can define 1192 * fixup hooks to be called for particular buggy devices. 1193 */ 1194 1195 struct pci_fixup { 1196 u16 vendor, device; /* You can use PCI_ANY_ID here of course */ 1197 void (*hook)(struct pci_dev *dev); 1198 }; 1199 1200 enum pci_fixup_pass { 1201 pci_fixup_early, /* Before probing BARs */ 1202 pci_fixup_header, /* After reading configuration header */ 1203 pci_fixup_final, /* Final phase of device fixups */ 1204 pci_fixup_enable, /* pci_enable_device() time */ 1205 pci_fixup_resume, /* pci_device_resume() */ 1206 pci_fixup_suspend, /* pci_device_suspend */ 1207 pci_fixup_resume_early, /* pci_device_resume_early() */ 1208 }; 1209 1210 /* Anonymous variables would be nice... */ 1211 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ 1212 static const struct pci_fixup __pci_fixup_##name __used \ 1213 __attribute__((__section__(#section))) = { vendor, device, hook }; 1214 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1215 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1216 vendor##device##hook, vendor, device, hook) 1217 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1218 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1219 vendor##device##hook, vendor, device, hook) 1220 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1221 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1222 vendor##device##hook, vendor, device, hook) 1223 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1224 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1225 vendor##device##hook, vendor, device, hook) 1226 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1227 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1228 resume##vendor##device##hook, vendor, device, hook) 1229 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1230 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1231 resume_early##vendor##device##hook, vendor, device, hook) 1232 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1233 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1234 suspend##vendor##device##hook, vendor, device, hook) 1235 1236 1237 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1238 1239 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1240 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1241 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1242 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); 1243 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, 1244 const char *name); 1245 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); 1246 1247 extern int pci_pci_problems; 1248 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1249 #define PCIPCI_TRITON 2 1250 #define PCIPCI_NATOMA 4 1251 #define PCIPCI_VIAETBF 8 1252 #define PCIPCI_VSFX 16 1253 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1254 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1255 1256 extern unsigned long pci_cardbus_io_size; 1257 extern unsigned long pci_cardbus_mem_size; 1258 extern u8 pci_dfl_cache_line_size; 1259 extern u8 pci_cache_line_size; 1260 1261 extern unsigned long pci_hotplug_io_size; 1262 extern unsigned long pci_hotplug_mem_size; 1263 1264 int pcibios_add_platform_entries(struct pci_dev *dev); 1265 void pcibios_disable_device(struct pci_dev *dev); 1266 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1267 enum pcie_reset_state state); 1268 1269 #ifdef CONFIG_PCI_MMCONFIG 1270 extern void __init pci_mmcfg_early_init(void); 1271 extern void __init pci_mmcfg_late_init(void); 1272 #else 1273 static inline void pci_mmcfg_early_init(void) { } 1274 static inline void pci_mmcfg_late_init(void) { } 1275 #endif 1276 1277 int pci_ext_cfg_avail(struct pci_dev *dev); 1278 1279 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1280 1281 #ifdef CONFIG_PCI_IOV 1282 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1283 extern void pci_disable_sriov(struct pci_dev *dev); 1284 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev); 1285 #else 1286 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1287 { 1288 return -ENODEV; 1289 } 1290 static inline void pci_disable_sriov(struct pci_dev *dev) 1291 { 1292 } 1293 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) 1294 { 1295 return IRQ_NONE; 1296 } 1297 #endif 1298 1299 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1300 extern void pci_hp_create_module_link(struct pci_slot *pci_slot); 1301 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1302 #endif 1303 1304 /** 1305 * pci_pcie_cap - get the saved PCIe capability offset 1306 * @dev: PCI device 1307 * 1308 * PCIe capability offset is calculated at PCI device initialization 1309 * time and saved in the data structure. This function returns saved 1310 * PCIe capability offset. Using this instead of pci_find_capability() 1311 * reduces unnecessary search in the PCI configuration space. If you 1312 * need to calculate PCIe capability offset from raw device for some 1313 * reasons, please use pci_find_capability() instead. 1314 */ 1315 static inline int pci_pcie_cap(struct pci_dev *dev) 1316 { 1317 return dev->pcie_cap; 1318 } 1319 1320 /** 1321 * pci_is_pcie - check if the PCI device is PCI Express capable 1322 * @dev: PCI device 1323 * 1324 * Retrun true if the PCI device is PCI Express capable, false otherwise. 1325 */ 1326 static inline bool pci_is_pcie(struct pci_dev *dev) 1327 { 1328 return !!pci_pcie_cap(dev); 1329 } 1330 1331 void pci_request_acs(void); 1332 1333 #endif /* __KERNEL__ */ 1334 #endif /* LINUX_PCI_H */ 1335