1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 46 PCI_STATUS_SIG_SYSTEM_ERROR | \ 47 PCI_STATUS_REC_MASTER_ABORT | \ 48 PCI_STATUS_REC_TARGET_ABORT | \ 49 PCI_STATUS_SIG_TARGET_ABORT | \ 50 PCI_STATUS_PARITY) 51 52 /* 53 * The PCI interface treats multi-function devices as independent 54 * devices. The slot/function address of each device is encoded 55 * in a single byte as follows: 56 * 57 * 7:3 = slot 58 * 2:0 = function 59 * 60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 61 * In the interest of not exposing interfaces to user-space unnecessarily, 62 * the following kernel-only defines are being added here. 63 */ 64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 67 68 /* pci_slot represents a physical slot */ 69 struct pci_slot { 70 struct pci_bus *bus; /* Bus this slot is on */ 71 struct list_head list; /* Node in list of slots */ 72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 74 struct kobject kobj; 75 }; 76 77 static inline const char *pci_slot_name(const struct pci_slot *slot) 78 { 79 return kobject_name(&slot->kobj); 80 } 81 82 /* File state for mmap()s on /proc/bus/pci/X/Y */ 83 enum pci_mmap_state { 84 pci_mmap_io, 85 pci_mmap_mem 86 }; 87 88 /* For PCI devices, the region numbers are assigned this way: */ 89 enum { 90 /* #0-5: standard PCI resources */ 91 PCI_STD_RESOURCES, 92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 93 94 /* #6: expansion ROM resource */ 95 PCI_ROM_RESOURCE, 96 97 /* Device-specific resources */ 98 #ifdef CONFIG_PCI_IOV 99 PCI_IOV_RESOURCES, 100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 101 #endif 102 103 /* PCI-to-PCI (P2P) bridge windows */ 104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 107 108 /* CardBus bridge windows */ 109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 113 114 /* Total number of bridge resources for P2P and CardBus */ 115 #define PCI_BRIDGE_RESOURCE_NUM 4 116 117 /* Resources assigned to buses behind the bridge */ 118 PCI_BRIDGE_RESOURCES, 119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 120 PCI_BRIDGE_RESOURCE_NUM - 1, 121 122 /* Total resources associated with a PCI device */ 123 PCI_NUM_RESOURCES, 124 125 /* Preserve this for compatibility */ 126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 127 }; 128 129 /** 130 * enum pci_interrupt_pin - PCI INTx interrupt values 131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 132 * @PCI_INTERRUPT_INTA: PCI INTA pin 133 * @PCI_INTERRUPT_INTB: PCI INTB pin 134 * @PCI_INTERRUPT_INTC: PCI INTC pin 135 * @PCI_INTERRUPT_INTD: PCI INTD pin 136 * 137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 138 * PCI_INTERRUPT_PIN register. 139 */ 140 enum pci_interrupt_pin { 141 PCI_INTERRUPT_UNKNOWN, 142 PCI_INTERRUPT_INTA, 143 PCI_INTERRUPT_INTB, 144 PCI_INTERRUPT_INTC, 145 PCI_INTERRUPT_INTD, 146 }; 147 148 /* The number of legacy PCI INTx interrupts */ 149 #define PCI_NUM_INTX 4 150 151 /* 152 * pci_power_t values must match the bits in the Capabilities PME_Support 153 * and Control/Status PowerState fields in the Power Management capability. 154 */ 155 typedef int __bitwise pci_power_t; 156 157 #define PCI_D0 ((pci_power_t __force) 0) 158 #define PCI_D1 ((pci_power_t __force) 1) 159 #define PCI_D2 ((pci_power_t __force) 2) 160 #define PCI_D3hot ((pci_power_t __force) 3) 161 #define PCI_D3cold ((pci_power_t __force) 4) 162 #define PCI_UNKNOWN ((pci_power_t __force) 5) 163 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 164 165 /* Remember to update this when the list above changes! */ 166 extern const char *pci_power_names[]; 167 168 static inline const char *pci_power_name(pci_power_t state) 169 { 170 return pci_power_names[1 + (__force int) state]; 171 } 172 173 /** 174 * typedef pci_channel_state_t 175 * 176 * The pci_channel state describes connectivity between the CPU and 177 * the PCI device. If some PCI bus between here and the PCI device 178 * has crashed or locked up, this info is reflected here. 179 */ 180 typedef unsigned int __bitwise pci_channel_state_t; 181 182 enum { 183 /* I/O channel is in normal state */ 184 pci_channel_io_normal = (__force pci_channel_state_t) 1, 185 186 /* I/O to channel is blocked */ 187 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 188 189 /* PCI card is dead */ 190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 191 }; 192 193 typedef unsigned int __bitwise pcie_reset_state_t; 194 195 enum pcie_reset_state { 196 /* Reset is NOT asserted (Use to deassert reset) */ 197 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 198 199 /* Use #PERST to reset PCIe device */ 200 pcie_warm_reset = (__force pcie_reset_state_t) 2, 201 202 /* Use PCIe Hot Reset to reset device */ 203 pcie_hot_reset = (__force pcie_reset_state_t) 3 204 }; 205 206 typedef unsigned short __bitwise pci_dev_flags_t; 207 enum pci_dev_flags { 208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 210 /* Device configuration is irrevocably lost if disabled into D3 */ 211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 212 /* Provide indication device is assigned by a Virtual Machine Manager */ 213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 214 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 218 /* Do not use bus resets for device */ 219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 220 /* Do not use PM reset even if device advertises NoSoftRst- */ 221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 222 /* Get VPD from function 0 VPD */ 223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 224 /* A non-root bridge where translation occurs, stop alias search here */ 225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 226 /* Do not use FLR even if device advertises PCI_AF_CAP */ 227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 228 /* Don't use Relaxed Ordering for TLPs directed at this device */ 229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 230 }; 231 232 enum pci_irq_reroute_variant { 233 INTEL_IRQ_REROUTE_VARIANT = 1, 234 MAX_IRQ_REROUTE_VARIANTS = 3 235 }; 236 237 typedef unsigned short __bitwise pci_bus_flags_t; 238 enum pci_bus_flags { 239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 243 }; 244 245 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 246 enum pcie_link_width { 247 PCIE_LNK_WIDTH_RESRV = 0x00, 248 PCIE_LNK_X1 = 0x01, 249 PCIE_LNK_X2 = 0x02, 250 PCIE_LNK_X4 = 0x04, 251 PCIE_LNK_X8 = 0x08, 252 PCIE_LNK_X12 = 0x0c, 253 PCIE_LNK_X16 = 0x10, 254 PCIE_LNK_X32 = 0x20, 255 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 256 }; 257 258 /* See matching string table in pci_speed_string() */ 259 enum pci_bus_speed { 260 PCI_SPEED_33MHz = 0x00, 261 PCI_SPEED_66MHz = 0x01, 262 PCI_SPEED_66MHz_PCIX = 0x02, 263 PCI_SPEED_100MHz_PCIX = 0x03, 264 PCI_SPEED_133MHz_PCIX = 0x04, 265 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 266 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 267 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 268 PCI_SPEED_66MHz_PCIX_266 = 0x09, 269 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 270 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 271 AGP_UNKNOWN = 0x0c, 272 AGP_1X = 0x0d, 273 AGP_2X = 0x0e, 274 AGP_4X = 0x0f, 275 AGP_8X = 0x10, 276 PCI_SPEED_66MHz_PCIX_533 = 0x11, 277 PCI_SPEED_100MHz_PCIX_533 = 0x12, 278 PCI_SPEED_133MHz_PCIX_533 = 0x13, 279 PCIE_SPEED_2_5GT = 0x14, 280 PCIE_SPEED_5_0GT = 0x15, 281 PCIE_SPEED_8_0GT = 0x16, 282 PCIE_SPEED_16_0GT = 0x17, 283 PCIE_SPEED_32_0GT = 0x18, 284 PCIE_SPEED_64_0GT = 0x19, 285 PCI_SPEED_UNKNOWN = 0xff, 286 }; 287 288 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 289 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 290 291 struct pci_cap_saved_data { 292 u16 cap_nr; 293 bool cap_extended; 294 unsigned int size; 295 u32 data[]; 296 }; 297 298 struct pci_cap_saved_state { 299 struct hlist_node next; 300 struct pci_cap_saved_data cap; 301 }; 302 303 struct irq_affinity; 304 struct pcie_link_state; 305 struct pci_vpd; 306 struct pci_sriov; 307 struct pci_p2pdma; 308 struct rcec_ea; 309 310 /* The pci_dev structure describes PCI devices */ 311 struct pci_dev { 312 struct list_head bus_list; /* Node in per-bus list */ 313 struct pci_bus *bus; /* Bus this device is on */ 314 struct pci_bus *subordinate; /* Bus this device bridges to */ 315 316 void *sysdata; /* Hook for sys-specific extension */ 317 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 318 struct pci_slot *slot; /* Physical slot this device is in */ 319 320 unsigned int devfn; /* Encoded device & function index */ 321 unsigned short vendor; 322 unsigned short device; 323 unsigned short subsystem_vendor; 324 unsigned short subsystem_device; 325 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 326 u8 revision; /* PCI revision, low byte of class word */ 327 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 328 #ifdef CONFIG_PCIEAER 329 u16 aer_cap; /* AER capability offset */ 330 struct aer_stats *aer_stats; /* AER stats for this device */ 331 #endif 332 #ifdef CONFIG_PCIEPORTBUS 333 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 334 struct pci_dev *rcec; /* Associated RCEC device */ 335 #endif 336 u8 pcie_cap; /* PCIe capability offset */ 337 u8 msi_cap; /* MSI capability offset */ 338 u8 msix_cap; /* MSI-X capability offset */ 339 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 340 u8 rom_base_reg; /* Config register controlling ROM */ 341 u8 pin; /* Interrupt pin this device uses */ 342 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 343 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 344 345 struct pci_driver *driver; /* Driver bound to this device */ 346 u64 dma_mask; /* Mask of the bits of bus address this 347 device implements. Normally this is 348 0xffffffff. You only need to change 349 this if your device has broken DMA 350 or supports 64-bit transfers. */ 351 352 struct device_dma_parameters dma_parms; 353 354 pci_power_t current_state; /* Current operating state. In ACPI, 355 this is D0-D3, D0 being fully 356 functional, and D3 being off. */ 357 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 358 u8 pm_cap; /* PM capability offset */ 359 unsigned int pme_support:5; /* Bitmask of states from which PME# 360 can be generated */ 361 unsigned int pme_poll:1; /* Poll device's PME status bit */ 362 unsigned int d1_support:1; /* Low power state D1 is supported */ 363 unsigned int d2_support:1; /* Low power state D2 is supported */ 364 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 365 unsigned int no_d3cold:1; /* D3cold is forbidden */ 366 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 367 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 368 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 369 decoding during BAR sizing */ 370 unsigned int wakeup_prepared:1; 371 unsigned int runtime_d3cold:1; /* Whether go through runtime 372 D3cold, not set for devices 373 powered on/off by the 374 corresponding bridge */ 375 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 376 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 377 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 378 controlled exclusively by 379 user sysfs */ 380 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 381 bit manually */ 382 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 383 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 384 385 #ifdef CONFIG_PCIEASPM 386 struct pcie_link_state *link_state; /* ASPM link state */ 387 unsigned int ltr_path:1; /* Latency Tolerance Reporting 388 supported from root to here */ 389 u16 l1ss; /* L1SS Capability pointer */ 390 #endif 391 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 392 393 pci_channel_state_t error_state; /* Current connectivity state */ 394 struct device dev; /* Generic device interface */ 395 396 int cfg_size; /* Size of config space */ 397 398 /* 399 * Instead of touching interrupt line and base address registers 400 * directly, use the values stored here. They might be different! 401 */ 402 unsigned int irq; 403 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 404 405 bool match_driver; /* Skip attaching driver */ 406 407 unsigned int transparent:1; /* Subtractive decode bridge */ 408 unsigned int io_window:1; /* Bridge has I/O window */ 409 unsigned int pref_window:1; /* Bridge has pref mem window */ 410 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 411 unsigned int multifunction:1; /* Multi-function device */ 412 413 unsigned int is_busmaster:1; /* Is busmaster */ 414 unsigned int no_msi:1; /* May not use MSI */ 415 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 416 unsigned int block_cfg_access:1; /* Config space access blocked */ 417 unsigned int broken_parity_status:1; /* Generates false positive parity */ 418 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 419 unsigned int msi_enabled:1; 420 unsigned int msix_enabled:1; 421 unsigned int ari_enabled:1; /* ARI forwarding */ 422 unsigned int ats_enabled:1; /* Address Translation Svc */ 423 unsigned int pasid_enabled:1; /* Process Address Space ID */ 424 unsigned int pri_enabled:1; /* Page Request Interface */ 425 unsigned int is_managed:1; 426 unsigned int needs_freset:1; /* Requires fundamental reset */ 427 unsigned int state_saved:1; 428 unsigned int is_physfn:1; 429 unsigned int is_virtfn:1; 430 unsigned int reset_fn:1; 431 unsigned int is_hotplug_bridge:1; 432 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 433 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 434 /* 435 * Devices marked being untrusted are the ones that can potentially 436 * execute DMA attacks and similar. They are typically connected 437 * through external ports such as Thunderbolt but not limited to 438 * that. When an IOMMU is enabled they should be getting full 439 * mappings to make sure they cannot access arbitrary memory. 440 */ 441 unsigned int untrusted:1; 442 /* 443 * Info from the platform, e.g., ACPI or device tree, may mark a 444 * device as "external-facing". An external-facing device is 445 * itself internal but devices downstream from it are external. 446 */ 447 unsigned int external_facing:1; 448 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 449 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 450 unsigned int irq_managed:1; 451 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 452 unsigned int is_probed:1; /* Device probing in progress */ 453 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 454 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 455 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 456 pci_dev_flags_t dev_flags; 457 atomic_t enable_cnt; /* pci_enable_device has been called */ 458 459 u32 saved_config_space[16]; /* Config space saved at suspend time */ 460 struct hlist_head saved_cap_space; 461 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 462 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 463 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 464 465 #ifdef CONFIG_HOTPLUG_PCI_PCIE 466 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 467 #endif 468 #ifdef CONFIG_PCIE_PTM 469 unsigned int ptm_root:1; 470 unsigned int ptm_enabled:1; 471 u8 ptm_granularity; 472 #endif 473 #ifdef CONFIG_PCI_MSI 474 const struct attribute_group **msi_irq_groups; 475 #endif 476 struct pci_vpd *vpd; 477 #ifdef CONFIG_PCIE_DPC 478 u16 dpc_cap; 479 unsigned int dpc_rp_extensions:1; 480 u8 dpc_rp_log_size; 481 #endif 482 #ifdef CONFIG_PCI_ATS 483 union { 484 struct pci_sriov *sriov; /* PF: SR-IOV info */ 485 struct pci_dev *physfn; /* VF: related PF */ 486 }; 487 u16 ats_cap; /* ATS Capability offset */ 488 u8 ats_stu; /* ATS Smallest Translation Unit */ 489 #endif 490 #ifdef CONFIG_PCI_PRI 491 u16 pri_cap; /* PRI Capability offset */ 492 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 493 unsigned int pasid_required:1; /* PRG Response PASID Required */ 494 #endif 495 #ifdef CONFIG_PCI_PASID 496 u16 pasid_cap; /* PASID Capability offset */ 497 u16 pasid_features; 498 #endif 499 #ifdef CONFIG_PCI_P2PDMA 500 struct pci_p2pdma __rcu *p2pdma; 501 #endif 502 u16 acs_cap; /* ACS Capability offset */ 503 phys_addr_t rom; /* Physical address if not from BAR */ 504 size_t romlen; /* Length if not from BAR */ 505 char *driver_override; /* Driver name to force a match */ 506 507 unsigned long priv_flags; /* Private flags for the PCI driver */ 508 }; 509 510 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 511 { 512 #ifdef CONFIG_PCI_IOV 513 if (dev->is_virtfn) 514 dev = dev->physfn; 515 #endif 516 return dev; 517 } 518 519 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 520 521 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 522 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 523 524 static inline int pci_channel_offline(struct pci_dev *pdev) 525 { 526 return (pdev->error_state != pci_channel_io_normal); 527 } 528 529 struct pci_host_bridge { 530 struct device dev; 531 struct pci_bus *bus; /* Root bus */ 532 struct pci_ops *ops; 533 struct pci_ops *child_ops; 534 void *sysdata; 535 int busnr; 536 struct list_head windows; /* resource_entry */ 537 struct list_head dma_ranges; /* dma ranges resource list */ 538 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 539 int (*map_irq)(const struct pci_dev *, u8, u8); 540 void (*release_fn)(struct pci_host_bridge *); 541 void *release_data; 542 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 543 unsigned int no_ext_tags:1; /* No Extended Tags */ 544 unsigned int native_aer:1; /* OS may use PCIe AER */ 545 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 546 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 547 unsigned int native_pme:1; /* OS may use PCIe PME */ 548 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 549 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 550 unsigned int preserve_config:1; /* Preserve FW resource setup */ 551 unsigned int size_windows:1; /* Enable root bus sizing */ 552 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 553 554 /* Resource alignment requirements */ 555 resource_size_t (*align_resource)(struct pci_dev *dev, 556 const struct resource *res, 557 resource_size_t start, 558 resource_size_t size, 559 resource_size_t align); 560 unsigned long private[] ____cacheline_aligned; 561 }; 562 563 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 564 565 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 566 { 567 return (void *)bridge->private; 568 } 569 570 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 571 { 572 return container_of(priv, struct pci_host_bridge, private); 573 } 574 575 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 576 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 577 size_t priv); 578 void pci_free_host_bridge(struct pci_host_bridge *bridge); 579 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 580 581 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 582 void (*release_fn)(struct pci_host_bridge *), 583 void *release_data); 584 585 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 586 587 /* 588 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 589 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 590 * buses below host bridges or subtractive decode bridges) go in the list. 591 * Use pci_bus_for_each_resource() to iterate through all the resources. 592 */ 593 594 /* 595 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 596 * and there's no way to program the bridge with the details of the window. 597 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 598 * decode bit set, because they are explicit and can be programmed with _SRS. 599 */ 600 #define PCI_SUBTRACTIVE_DECODE 0x1 601 602 struct pci_bus_resource { 603 struct list_head list; 604 struct resource *res; 605 unsigned int flags; 606 }; 607 608 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 609 610 struct pci_bus { 611 struct list_head node; /* Node in list of buses */ 612 struct pci_bus *parent; /* Parent bus this bridge is on */ 613 struct list_head children; /* List of child buses */ 614 struct list_head devices; /* List of devices on this bus */ 615 struct pci_dev *self; /* Bridge device as seen by parent */ 616 struct list_head slots; /* List of slots on this bus; 617 protected by pci_slot_mutex */ 618 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 619 struct list_head resources; /* Address space routed to this bus */ 620 struct resource busn_res; /* Bus numbers routed to this bus */ 621 622 struct pci_ops *ops; /* Configuration access functions */ 623 void *sysdata; /* Hook for sys-specific extension */ 624 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 625 626 unsigned char number; /* Bus number */ 627 unsigned char primary; /* Number of primary bridge */ 628 unsigned char max_bus_speed; /* enum pci_bus_speed */ 629 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 630 #ifdef CONFIG_PCI_DOMAINS_GENERIC 631 int domain_nr; 632 #endif 633 634 char name[48]; 635 636 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 637 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 638 struct device *bridge; 639 struct device dev; 640 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 641 struct bin_attribute *legacy_mem; /* Legacy mem */ 642 unsigned int is_added:1; 643 }; 644 645 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 646 647 static inline u16 pci_dev_id(struct pci_dev *dev) 648 { 649 return PCI_DEVID(dev->bus->number, dev->devfn); 650 } 651 652 /* 653 * Returns true if the PCI bus is root (behind host-PCI bridge), 654 * false otherwise 655 * 656 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 657 * This is incorrect because "virtual" buses added for SR-IOV (via 658 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 659 */ 660 static inline bool pci_is_root_bus(struct pci_bus *pbus) 661 { 662 return !(pbus->parent); 663 } 664 665 /** 666 * pci_is_bridge - check if the PCI device is a bridge 667 * @dev: PCI device 668 * 669 * Return true if the PCI device is bridge whether it has subordinate 670 * or not. 671 */ 672 static inline bool pci_is_bridge(struct pci_dev *dev) 673 { 674 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 675 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 676 } 677 678 #define for_each_pci_bridge(dev, bus) \ 679 list_for_each_entry(dev, &bus->devices, bus_list) \ 680 if (!pci_is_bridge(dev)) {} else 681 682 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 683 { 684 dev = pci_physfn(dev); 685 if (pci_is_root_bus(dev->bus)) 686 return NULL; 687 688 return dev->bus->self; 689 } 690 691 #ifdef CONFIG_PCI_MSI 692 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 693 { 694 return pci_dev->msi_enabled || pci_dev->msix_enabled; 695 } 696 #else 697 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 698 #endif 699 700 /* Error values that may be returned by PCI functions */ 701 #define PCIBIOS_SUCCESSFUL 0x00 702 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 703 #define PCIBIOS_BAD_VENDOR_ID 0x83 704 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 705 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 706 #define PCIBIOS_SET_FAILED 0x88 707 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 708 709 /* Translate above to generic errno for passing back through non-PCI code */ 710 static inline int pcibios_err_to_errno(int err) 711 { 712 if (err <= PCIBIOS_SUCCESSFUL) 713 return err; /* Assume already errno */ 714 715 switch (err) { 716 case PCIBIOS_FUNC_NOT_SUPPORTED: 717 return -ENOENT; 718 case PCIBIOS_BAD_VENDOR_ID: 719 return -ENOTTY; 720 case PCIBIOS_DEVICE_NOT_FOUND: 721 return -ENODEV; 722 case PCIBIOS_BAD_REGISTER_NUMBER: 723 return -EFAULT; 724 case PCIBIOS_SET_FAILED: 725 return -EIO; 726 case PCIBIOS_BUFFER_TOO_SMALL: 727 return -ENOSPC; 728 } 729 730 return -ERANGE; 731 } 732 733 /* Low-level architecture-dependent routines */ 734 735 struct pci_ops { 736 int (*add_bus)(struct pci_bus *bus); 737 void (*remove_bus)(struct pci_bus *bus); 738 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 739 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 740 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 741 }; 742 743 /* 744 * ACPI needs to be able to access PCI config space before we've done a 745 * PCI bus scan and created pci_bus structures. 746 */ 747 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 748 int reg, int len, u32 *val); 749 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 750 int reg, int len, u32 val); 751 752 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 753 typedef u64 pci_bus_addr_t; 754 #else 755 typedef u32 pci_bus_addr_t; 756 #endif 757 758 struct pci_bus_region { 759 pci_bus_addr_t start; 760 pci_bus_addr_t end; 761 }; 762 763 struct pci_dynids { 764 spinlock_t lock; /* Protects list, index */ 765 struct list_head list; /* For IDs added at runtime */ 766 }; 767 768 769 /* 770 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 771 * a set of callbacks in struct pci_error_handlers, that device driver 772 * will be notified of PCI bus errors, and will be driven to recovery 773 * when an error occurs. 774 */ 775 776 typedef unsigned int __bitwise pci_ers_result_t; 777 778 enum pci_ers_result { 779 /* No result/none/not supported in device driver */ 780 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 781 782 /* Device driver can recover without slot reset */ 783 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 784 785 /* Device driver wants slot to be reset */ 786 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 787 788 /* Device has completely failed, is unrecoverable */ 789 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 790 791 /* Device driver is fully recovered and operational */ 792 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 793 794 /* No AER capabilities registered for the driver */ 795 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 796 }; 797 798 /* PCI bus error event callbacks */ 799 struct pci_error_handlers { 800 /* PCI bus error detected on this device */ 801 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 802 pci_channel_state_t error); 803 804 /* MMIO has been re-enabled, but not DMA */ 805 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 806 807 /* PCI slot has been reset */ 808 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 809 810 /* PCI function reset prepare or completed */ 811 void (*reset_prepare)(struct pci_dev *dev); 812 void (*reset_done)(struct pci_dev *dev); 813 814 /* Device driver may resume normal operations */ 815 void (*resume)(struct pci_dev *dev); 816 }; 817 818 819 struct module; 820 821 /** 822 * struct pci_driver - PCI driver structure 823 * @node: List of driver structures. 824 * @name: Driver name. 825 * @id_table: Pointer to table of device IDs the driver is 826 * interested in. Most drivers should export this 827 * table using MODULE_DEVICE_TABLE(pci,...). 828 * @probe: This probing function gets called (during execution 829 * of pci_register_driver() for already existing 830 * devices or later if a new device gets inserted) for 831 * all PCI devices which match the ID table and are not 832 * "owned" by the other drivers yet. This function gets 833 * passed a "struct pci_dev \*" for each device whose 834 * entry in the ID table matches the device. The probe 835 * function returns zero when the driver chooses to 836 * take "ownership" of the device or an error code 837 * (negative number) otherwise. 838 * The probe function always gets called from process 839 * context, so it can sleep. 840 * @remove: The remove() function gets called whenever a device 841 * being handled by this driver is removed (either during 842 * deregistration of the driver or when it's manually 843 * pulled out of a hot-pluggable slot). 844 * The remove function always gets called from process 845 * context, so it can sleep. 846 * @suspend: Put device into low power state. 847 * @resume: Wake device from low power state. 848 * (Please see Documentation/power/pci.rst for descriptions 849 * of PCI Power Management and the related functions.) 850 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 851 * Intended to stop any idling DMA operations. 852 * Useful for enabling wake-on-lan (NIC) or changing 853 * the power state of a device before reboot. 854 * e.g. drivers/net/e100.c. 855 * @sriov_configure: Optional driver callback to allow configuration of 856 * number of VFs to enable via sysfs "sriov_numvfs" file. 857 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 858 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 859 * This will change MSI-X Table Size in the VF Message Control 860 * registers. 861 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 862 * MSI-X vectors available for distribution to the VFs. 863 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 864 * @groups: Sysfs attribute groups. 865 * @dev_groups: Attributes attached to the device that will be 866 * created once it is bound to the driver. 867 * @driver: Driver model structure. 868 * @dynids: List of dynamically added device IDs. 869 */ 870 struct pci_driver { 871 struct list_head node; 872 const char *name; 873 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 874 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 875 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 876 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 877 int (*resume)(struct pci_dev *dev); /* Device woken up */ 878 void (*shutdown)(struct pci_dev *dev); 879 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 880 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 881 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 882 const struct pci_error_handlers *err_handler; 883 const struct attribute_group **groups; 884 const struct attribute_group **dev_groups; 885 struct device_driver driver; 886 struct pci_dynids dynids; 887 }; 888 889 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 890 891 /** 892 * PCI_DEVICE - macro used to describe a specific PCI device 893 * @vend: the 16 bit PCI Vendor ID 894 * @dev: the 16 bit PCI Device ID 895 * 896 * This macro is used to create a struct pci_device_id that matches a 897 * specific device. The subvendor and subdevice fields will be set to 898 * PCI_ANY_ID. 899 */ 900 #define PCI_DEVICE(vend,dev) \ 901 .vendor = (vend), .device = (dev), \ 902 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 903 904 /** 905 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 906 * override_only flags. 907 * @vend: the 16 bit PCI Vendor ID 908 * @dev: the 16 bit PCI Device ID 909 * @driver_override: the 32 bit PCI Device override_only 910 * 911 * This macro is used to create a struct pci_device_id that matches only a 912 * driver_override device. The subvendor and subdevice fields will be set to 913 * PCI_ANY_ID. 914 */ 915 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 916 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 917 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 918 919 /** 920 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 921 * "driver_override" PCI device. 922 * @vend: the 16 bit PCI Vendor ID 923 * @dev: the 16 bit PCI Device ID 924 * 925 * This macro is used to create a struct pci_device_id that matches a 926 * specific device. The subvendor and subdevice fields will be set to 927 * PCI_ANY_ID and the driver_override will be set to 928 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 929 */ 930 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 931 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 932 933 /** 934 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 935 * @vend: the 16 bit PCI Vendor ID 936 * @dev: the 16 bit PCI Device ID 937 * @subvend: the 16 bit PCI Subvendor ID 938 * @subdev: the 16 bit PCI Subdevice ID 939 * 940 * This macro is used to create a struct pci_device_id that matches a 941 * specific device with subsystem information. 942 */ 943 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 944 .vendor = (vend), .device = (dev), \ 945 .subvendor = (subvend), .subdevice = (subdev) 946 947 /** 948 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 949 * @dev_class: the class, subclass, prog-if triple for this device 950 * @dev_class_mask: the class mask for this device 951 * 952 * This macro is used to create a struct pci_device_id that matches a 953 * specific PCI class. The vendor, device, subvendor, and subdevice 954 * fields will be set to PCI_ANY_ID. 955 */ 956 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 957 .class = (dev_class), .class_mask = (dev_class_mask), \ 958 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 959 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 960 961 /** 962 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 963 * @vend: the vendor name 964 * @dev: the 16 bit PCI Device ID 965 * 966 * This macro is used to create a struct pci_device_id that matches a 967 * specific PCI device. The subvendor, and subdevice fields will be set 968 * to PCI_ANY_ID. The macro allows the next field to follow as the device 969 * private data. 970 */ 971 #define PCI_VDEVICE(vend, dev) \ 972 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 973 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 974 975 /** 976 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 977 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 978 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 979 * @data: the driver data to be filled 980 * 981 * This macro is used to create a struct pci_device_id that matches a 982 * specific PCI device. The subvendor, and subdevice fields will be set 983 * to PCI_ANY_ID. 984 */ 985 #define PCI_DEVICE_DATA(vend, dev, data) \ 986 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 987 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 988 .driver_data = (kernel_ulong_t)(data) 989 990 enum { 991 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 992 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 993 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 994 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 995 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 996 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 997 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 998 }; 999 1000 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1001 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1002 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1003 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1004 1005 /* These external functions are only available when PCI support is enabled */ 1006 #ifdef CONFIG_PCI 1007 1008 extern unsigned int pci_flags; 1009 1010 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1011 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1012 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1013 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1014 1015 void pcie_bus_configure_settings(struct pci_bus *bus); 1016 1017 enum pcie_bus_config_types { 1018 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1019 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1020 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1021 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1022 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1023 }; 1024 1025 extern enum pcie_bus_config_types pcie_bus_config; 1026 1027 extern struct bus_type pci_bus_type; 1028 1029 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1030 * code, or PCI core code. */ 1031 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1032 /* Some device drivers need know if PCI is initiated */ 1033 int no_pci_devices(void); 1034 1035 void pcibios_resource_survey_bus(struct pci_bus *bus); 1036 void pcibios_bus_add_device(struct pci_dev *pdev); 1037 void pcibios_add_bus(struct pci_bus *bus); 1038 void pcibios_remove_bus(struct pci_bus *bus); 1039 void pcibios_fixup_bus(struct pci_bus *); 1040 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1041 /* Architecture-specific versions may override this (weak) */ 1042 char *pcibios_setup(char *str); 1043 1044 /* Used only when drivers/pci/setup.c is used */ 1045 resource_size_t pcibios_align_resource(void *, const struct resource *, 1046 resource_size_t, 1047 resource_size_t); 1048 1049 /* Weak but can be overridden by arch */ 1050 void pci_fixup_cardbus(struct pci_bus *); 1051 1052 /* Generic PCI functions used internally */ 1053 1054 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1055 struct resource *res); 1056 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1057 struct pci_bus_region *region); 1058 void pcibios_scan_specific_bus(int busn); 1059 struct pci_bus *pci_find_bus(int domain, int busnr); 1060 void pci_bus_add_devices(const struct pci_bus *bus); 1061 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1062 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1063 struct pci_ops *ops, void *sysdata, 1064 struct list_head *resources); 1065 int pci_host_probe(struct pci_host_bridge *bridge); 1066 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1067 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1068 void pci_bus_release_busn_res(struct pci_bus *b); 1069 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1070 struct pci_ops *ops, void *sysdata, 1071 struct list_head *resources); 1072 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1073 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1074 int busnr); 1075 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1076 const char *name, 1077 struct hotplug_slot *hotplug); 1078 void pci_destroy_slot(struct pci_slot *slot); 1079 #ifdef CONFIG_SYSFS 1080 void pci_dev_assign_slot(struct pci_dev *dev); 1081 #else 1082 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1083 #endif 1084 int pci_scan_slot(struct pci_bus *bus, int devfn); 1085 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1086 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1087 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1088 void pci_bus_add_device(struct pci_dev *dev); 1089 void pci_read_bridge_bases(struct pci_bus *child); 1090 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1091 struct resource *res); 1092 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1093 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1094 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1095 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1096 void pci_dev_put(struct pci_dev *dev); 1097 void pci_remove_bus(struct pci_bus *b); 1098 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1099 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1100 void pci_stop_root_bus(struct pci_bus *bus); 1101 void pci_remove_root_bus(struct pci_bus *bus); 1102 void pci_setup_cardbus(struct pci_bus *bus); 1103 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1104 void pci_sort_breadthfirst(void); 1105 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1106 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1107 1108 /* Generic PCI functions exported to card drivers */ 1109 1110 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1111 u8 pci_find_capability(struct pci_dev *dev, int cap); 1112 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1113 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1114 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1115 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1116 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1117 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1118 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1119 1120 u64 pci_get_dsn(struct pci_dev *dev); 1121 1122 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1123 struct pci_dev *from); 1124 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1125 unsigned int ss_vendor, unsigned int ss_device, 1126 struct pci_dev *from); 1127 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1128 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1129 unsigned int devfn); 1130 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1131 int pci_dev_present(const struct pci_device_id *ids); 1132 1133 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1134 int where, u8 *val); 1135 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1136 int where, u16 *val); 1137 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1138 int where, u32 *val); 1139 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1140 int where, u8 val); 1141 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1142 int where, u16 val); 1143 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1144 int where, u32 val); 1145 1146 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1147 int where, int size, u32 *val); 1148 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1149 int where, int size, u32 val); 1150 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1151 int where, int size, u32 *val); 1152 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1153 int where, int size, u32 val); 1154 1155 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1156 1157 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1158 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1159 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1160 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1161 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1162 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1163 1164 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1165 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1166 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1167 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1168 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1169 u16 clear, u16 set); 1170 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1171 u32 clear, u32 set); 1172 1173 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1174 u16 set) 1175 { 1176 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1177 } 1178 1179 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1180 u32 set) 1181 { 1182 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1183 } 1184 1185 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1186 u16 clear) 1187 { 1188 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1189 } 1190 1191 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1192 u32 clear) 1193 { 1194 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1195 } 1196 1197 /* User-space driven config access */ 1198 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1199 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1200 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1201 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1202 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1203 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1204 1205 int __must_check pci_enable_device(struct pci_dev *dev); 1206 int __must_check pci_enable_device_io(struct pci_dev *dev); 1207 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1208 int __must_check pci_reenable_device(struct pci_dev *); 1209 int __must_check pcim_enable_device(struct pci_dev *pdev); 1210 void pcim_pin_device(struct pci_dev *pdev); 1211 1212 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1213 { 1214 /* 1215 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1216 * writable and no quirk has marked the feature broken. 1217 */ 1218 return !pdev->broken_intx_masking; 1219 } 1220 1221 static inline int pci_is_enabled(struct pci_dev *pdev) 1222 { 1223 return (atomic_read(&pdev->enable_cnt) > 0); 1224 } 1225 1226 static inline int pci_is_managed(struct pci_dev *pdev) 1227 { 1228 return pdev->is_managed; 1229 } 1230 1231 void pci_disable_device(struct pci_dev *dev); 1232 1233 extern unsigned int pcibios_max_latency; 1234 void pci_set_master(struct pci_dev *dev); 1235 void pci_clear_master(struct pci_dev *dev); 1236 1237 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1238 int pci_set_cacheline_size(struct pci_dev *dev); 1239 int __must_check pci_set_mwi(struct pci_dev *dev); 1240 int __must_check pcim_set_mwi(struct pci_dev *dev); 1241 int pci_try_set_mwi(struct pci_dev *dev); 1242 void pci_clear_mwi(struct pci_dev *dev); 1243 void pci_disable_parity(struct pci_dev *dev); 1244 void pci_intx(struct pci_dev *dev, int enable); 1245 bool pci_check_and_mask_intx(struct pci_dev *dev); 1246 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1247 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1248 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1249 int pcix_get_max_mmrbc(struct pci_dev *dev); 1250 int pcix_get_mmrbc(struct pci_dev *dev); 1251 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1252 int pcie_get_readrq(struct pci_dev *dev); 1253 int pcie_set_readrq(struct pci_dev *dev, int rq); 1254 int pcie_get_mps(struct pci_dev *dev); 1255 int pcie_set_mps(struct pci_dev *dev, int mps); 1256 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1257 enum pci_bus_speed *speed, 1258 enum pcie_link_width *width); 1259 void pcie_print_link_status(struct pci_dev *dev); 1260 bool pcie_has_flr(struct pci_dev *dev); 1261 int pcie_flr(struct pci_dev *dev); 1262 int __pci_reset_function_locked(struct pci_dev *dev); 1263 int pci_reset_function(struct pci_dev *dev); 1264 int pci_reset_function_locked(struct pci_dev *dev); 1265 int pci_try_reset_function(struct pci_dev *dev); 1266 int pci_probe_reset_slot(struct pci_slot *slot); 1267 int pci_probe_reset_bus(struct pci_bus *bus); 1268 int pci_reset_bus(struct pci_dev *dev); 1269 void pci_reset_secondary_bus(struct pci_dev *dev); 1270 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1271 void pci_update_resource(struct pci_dev *dev, int resno); 1272 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1273 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1274 void pci_release_resource(struct pci_dev *dev, int resno); 1275 static inline int pci_rebar_bytes_to_size(u64 bytes) 1276 { 1277 bytes = roundup_pow_of_two(bytes); 1278 1279 /* Return BAR size as defined in the resizable BAR specification */ 1280 return max(ilog2(bytes), 20) - 20; 1281 } 1282 1283 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1284 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1285 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1286 bool pci_device_is_present(struct pci_dev *pdev); 1287 void pci_ignore_hotplug(struct pci_dev *dev); 1288 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1289 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1290 1291 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1292 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1293 const char *fmt, ...); 1294 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1295 1296 /* ROM control related routines */ 1297 int pci_enable_rom(struct pci_dev *pdev); 1298 void pci_disable_rom(struct pci_dev *pdev); 1299 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1300 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1301 1302 /* Power management related routines */ 1303 int pci_save_state(struct pci_dev *dev); 1304 void pci_restore_state(struct pci_dev *dev); 1305 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1306 int pci_load_saved_state(struct pci_dev *dev, 1307 struct pci_saved_state *state); 1308 int pci_load_and_free_saved_state(struct pci_dev *dev, 1309 struct pci_saved_state **state); 1310 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1311 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1312 u16 cap); 1313 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1314 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1315 u16 cap, unsigned int size); 1316 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1317 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1318 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1319 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1320 void pci_pme_active(struct pci_dev *dev, bool enable); 1321 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1322 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1323 int pci_prepare_to_sleep(struct pci_dev *dev); 1324 int pci_back_from_sleep(struct pci_dev *dev); 1325 bool pci_dev_run_wake(struct pci_dev *dev); 1326 void pci_d3cold_enable(struct pci_dev *dev); 1327 void pci_d3cold_disable(struct pci_dev *dev); 1328 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1329 void pci_resume_bus(struct pci_bus *bus); 1330 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1331 1332 /* For use by arch with custom probe code */ 1333 void set_pcie_port_type(struct pci_dev *pdev); 1334 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1335 1336 /* Functions for PCI Hotplug drivers to use */ 1337 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1338 unsigned int pci_rescan_bus(struct pci_bus *bus); 1339 void pci_lock_rescan_remove(void); 1340 void pci_unlock_rescan_remove(void); 1341 1342 /* Vital Product Data routines */ 1343 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1344 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1345 1346 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1347 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1348 void pci_bus_assign_resources(const struct pci_bus *bus); 1349 void pci_bus_claim_resources(struct pci_bus *bus); 1350 void pci_bus_size_bridges(struct pci_bus *bus); 1351 int pci_claim_resource(struct pci_dev *, int); 1352 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1353 void pci_assign_unassigned_resources(void); 1354 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1355 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1356 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1357 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1358 void pdev_enable_device(struct pci_dev *); 1359 int pci_enable_resources(struct pci_dev *, int mask); 1360 void pci_assign_irq(struct pci_dev *dev); 1361 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1362 #define HAVE_PCI_REQ_REGIONS 2 1363 int __must_check pci_request_regions(struct pci_dev *, const char *); 1364 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1365 void pci_release_regions(struct pci_dev *); 1366 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1367 void pci_release_region(struct pci_dev *, int); 1368 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1369 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1370 void pci_release_selected_regions(struct pci_dev *, int); 1371 1372 /* drivers/pci/bus.c */ 1373 void pci_add_resource(struct list_head *resources, struct resource *res); 1374 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1375 resource_size_t offset); 1376 void pci_free_resource_list(struct list_head *resources); 1377 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1378 unsigned int flags); 1379 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1380 void pci_bus_remove_resources(struct pci_bus *bus); 1381 int devm_request_pci_bus_resources(struct device *dev, 1382 struct list_head *resources); 1383 1384 /* Temporary until new and working PCI SBR API in place */ 1385 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1386 1387 #define pci_bus_for_each_resource(bus, res, i) \ 1388 for (i = 0; \ 1389 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1390 i++) 1391 1392 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1393 struct resource *res, resource_size_t size, 1394 resource_size_t align, resource_size_t min, 1395 unsigned long type_mask, 1396 resource_size_t (*alignf)(void *, 1397 const struct resource *, 1398 resource_size_t, 1399 resource_size_t), 1400 void *alignf_data); 1401 1402 1403 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1404 resource_size_t size); 1405 unsigned long pci_address_to_pio(phys_addr_t addr); 1406 phys_addr_t pci_pio_to_address(unsigned long pio); 1407 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1408 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1409 phys_addr_t phys_addr); 1410 void pci_unmap_iospace(struct resource *res); 1411 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1412 resource_size_t offset, 1413 resource_size_t size); 1414 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1415 struct resource *res); 1416 1417 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1418 { 1419 struct pci_bus_region region; 1420 1421 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1422 return region.start; 1423 } 1424 1425 /* Proper probing supporting hot-pluggable devices */ 1426 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1427 const char *mod_name); 1428 1429 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1430 #define pci_register_driver(driver) \ 1431 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1432 1433 void pci_unregister_driver(struct pci_driver *dev); 1434 1435 /** 1436 * module_pci_driver() - Helper macro for registering a PCI driver 1437 * @__pci_driver: pci_driver struct 1438 * 1439 * Helper macro for PCI drivers which do not do anything special in module 1440 * init/exit. This eliminates a lot of boilerplate. Each module may only 1441 * use this macro once, and calling it replaces module_init() and module_exit() 1442 */ 1443 #define module_pci_driver(__pci_driver) \ 1444 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1445 1446 /** 1447 * builtin_pci_driver() - Helper macro for registering a PCI driver 1448 * @__pci_driver: pci_driver struct 1449 * 1450 * Helper macro for PCI drivers which do not do anything special in their 1451 * init code. This eliminates a lot of boilerplate. Each driver may only 1452 * use this macro once, and calling it replaces device_initcall(...) 1453 */ 1454 #define builtin_pci_driver(__pci_driver) \ 1455 builtin_driver(__pci_driver, pci_register_driver) 1456 1457 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1458 int pci_add_dynid(struct pci_driver *drv, 1459 unsigned int vendor, unsigned int device, 1460 unsigned int subvendor, unsigned int subdevice, 1461 unsigned int class, unsigned int class_mask, 1462 unsigned long driver_data); 1463 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1464 struct pci_dev *dev); 1465 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1466 int pass); 1467 1468 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1469 void *userdata); 1470 int pci_cfg_space_size(struct pci_dev *dev); 1471 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1472 void pci_setup_bridge(struct pci_bus *bus); 1473 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1474 unsigned long type); 1475 1476 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1477 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1478 1479 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1480 unsigned int command_bits, u32 flags); 1481 1482 /* 1483 * Virtual interrupts allow for more interrupts to be allocated 1484 * than the device has interrupts for. These are not programmed 1485 * into the device's MSI-X table and must be handled by some 1486 * other driver means. 1487 */ 1488 #define PCI_IRQ_VIRTUAL (1 << 4) 1489 1490 #define PCI_IRQ_ALL_TYPES \ 1491 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1492 1493 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1494 1495 #include <linux/dmapool.h> 1496 1497 #define pci_pool dma_pool 1498 #define pci_pool_create(name, pdev, size, align, allocation) \ 1499 dma_pool_create(name, &pdev->dev, size, align, allocation) 1500 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1501 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1502 #define pci_pool_zalloc(pool, flags, handle) \ 1503 dma_pool_zalloc(pool, flags, handle) 1504 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1505 1506 struct msix_entry { 1507 u32 vector; /* Kernel uses to write allocated vector */ 1508 u16 entry; /* Driver uses to specify entry, OS writes */ 1509 }; 1510 1511 #ifdef CONFIG_PCI_MSI 1512 int pci_msi_vec_count(struct pci_dev *dev); 1513 void pci_disable_msi(struct pci_dev *dev); 1514 int pci_msix_vec_count(struct pci_dev *dev); 1515 void pci_disable_msix(struct pci_dev *dev); 1516 void pci_restore_msi_state(struct pci_dev *dev); 1517 int pci_msi_enabled(void); 1518 int pci_enable_msi(struct pci_dev *dev); 1519 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1520 int minvec, int maxvec); 1521 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1522 struct msix_entry *entries, int nvec) 1523 { 1524 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1525 if (rc < 0) 1526 return rc; 1527 return 0; 1528 } 1529 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1530 unsigned int max_vecs, unsigned int flags, 1531 struct irq_affinity *affd); 1532 1533 void pci_free_irq_vectors(struct pci_dev *dev); 1534 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1535 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1536 1537 #else 1538 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1539 static inline void pci_disable_msi(struct pci_dev *dev) { } 1540 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1541 static inline void pci_disable_msix(struct pci_dev *dev) { } 1542 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1543 static inline int pci_msi_enabled(void) { return 0; } 1544 static inline int pci_enable_msi(struct pci_dev *dev) 1545 { return -ENOSYS; } 1546 static inline int pci_enable_msix_range(struct pci_dev *dev, 1547 struct msix_entry *entries, int minvec, int maxvec) 1548 { return -ENOSYS; } 1549 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1550 struct msix_entry *entries, int nvec) 1551 { return -ENOSYS; } 1552 1553 static inline int 1554 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1555 unsigned int max_vecs, unsigned int flags, 1556 struct irq_affinity *aff_desc) 1557 { 1558 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1559 return 1; 1560 return -ENOSPC; 1561 } 1562 1563 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1564 { 1565 } 1566 1567 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1568 { 1569 if (WARN_ON_ONCE(nr > 0)) 1570 return -EINVAL; 1571 return dev->irq; 1572 } 1573 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1574 int vec) 1575 { 1576 return cpu_possible_mask; 1577 } 1578 #endif 1579 1580 /** 1581 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1582 * @d: the INTx IRQ domain 1583 * @node: the DT node for the device whose interrupt we're translating 1584 * @intspec: the interrupt specifier data from the DT 1585 * @intsize: the number of entries in @intspec 1586 * @out_hwirq: pointer at which to write the hwirq number 1587 * @out_type: pointer at which to write the interrupt type 1588 * 1589 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1590 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1591 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1592 * INTx value to obtain the hwirq number. 1593 * 1594 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1595 */ 1596 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1597 struct device_node *node, 1598 const u32 *intspec, 1599 unsigned int intsize, 1600 unsigned long *out_hwirq, 1601 unsigned int *out_type) 1602 { 1603 const u32 intx = intspec[0]; 1604 1605 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1606 return -EINVAL; 1607 1608 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1609 return 0; 1610 } 1611 1612 #ifdef CONFIG_PCIEPORTBUS 1613 extern bool pcie_ports_disabled; 1614 extern bool pcie_ports_native; 1615 #else 1616 #define pcie_ports_disabled true 1617 #define pcie_ports_native false 1618 #endif 1619 1620 #define PCIE_LINK_STATE_L0S BIT(0) 1621 #define PCIE_LINK_STATE_L1 BIT(1) 1622 #define PCIE_LINK_STATE_CLKPM BIT(2) 1623 #define PCIE_LINK_STATE_L1_1 BIT(3) 1624 #define PCIE_LINK_STATE_L1_2 BIT(4) 1625 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1626 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1627 1628 #ifdef CONFIG_PCIEASPM 1629 int pci_disable_link_state(struct pci_dev *pdev, int state); 1630 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1631 void pcie_no_aspm(void); 1632 bool pcie_aspm_support_enabled(void); 1633 bool pcie_aspm_enabled(struct pci_dev *pdev); 1634 #else 1635 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1636 { return 0; } 1637 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1638 { return 0; } 1639 static inline void pcie_no_aspm(void) { } 1640 static inline bool pcie_aspm_support_enabled(void) { return false; } 1641 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1642 #endif 1643 1644 #ifdef CONFIG_PCIEAER 1645 bool pci_aer_available(void); 1646 #else 1647 static inline bool pci_aer_available(void) { return false; } 1648 #endif 1649 1650 bool pci_ats_disabled(void); 1651 1652 #ifdef CONFIG_PCIE_PTM 1653 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1654 bool pcie_ptm_enabled(struct pci_dev *dev); 1655 #else 1656 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1657 { return -EINVAL; } 1658 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1659 { return false; } 1660 #endif 1661 1662 void pci_cfg_access_lock(struct pci_dev *dev); 1663 bool pci_cfg_access_trylock(struct pci_dev *dev); 1664 void pci_cfg_access_unlock(struct pci_dev *dev); 1665 1666 int pci_dev_trylock(struct pci_dev *dev); 1667 void pci_dev_unlock(struct pci_dev *dev); 1668 1669 /* 1670 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1671 * a PCI domain is defined to be a set of PCI buses which share 1672 * configuration space. 1673 */ 1674 #ifdef CONFIG_PCI_DOMAINS 1675 extern int pci_domains_supported; 1676 #else 1677 enum { pci_domains_supported = 0 }; 1678 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1679 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1680 #endif /* CONFIG_PCI_DOMAINS */ 1681 1682 /* 1683 * Generic implementation for PCI domain support. If your 1684 * architecture does not need custom management of PCI 1685 * domains then this implementation will be used 1686 */ 1687 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1688 static inline int pci_domain_nr(struct pci_bus *bus) 1689 { 1690 return bus->domain_nr; 1691 } 1692 #ifdef CONFIG_ACPI 1693 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1694 #else 1695 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1696 { return 0; } 1697 #endif 1698 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1699 #endif 1700 1701 /* Some architectures require additional setup to direct VGA traffic */ 1702 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1703 unsigned int command_bits, u32 flags); 1704 void pci_register_set_vga_state(arch_set_vga_state_t func); 1705 1706 static inline int 1707 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1708 { 1709 return pci_request_selected_regions(pdev, 1710 pci_select_bars(pdev, IORESOURCE_IO), name); 1711 } 1712 1713 static inline void 1714 pci_release_io_regions(struct pci_dev *pdev) 1715 { 1716 return pci_release_selected_regions(pdev, 1717 pci_select_bars(pdev, IORESOURCE_IO)); 1718 } 1719 1720 static inline int 1721 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1722 { 1723 return pci_request_selected_regions(pdev, 1724 pci_select_bars(pdev, IORESOURCE_MEM), name); 1725 } 1726 1727 static inline void 1728 pci_release_mem_regions(struct pci_dev *pdev) 1729 { 1730 return pci_release_selected_regions(pdev, 1731 pci_select_bars(pdev, IORESOURCE_MEM)); 1732 } 1733 1734 #else /* CONFIG_PCI is not enabled */ 1735 1736 static inline void pci_set_flags(int flags) { } 1737 static inline void pci_add_flags(int flags) { } 1738 static inline void pci_clear_flags(int flags) { } 1739 static inline int pci_has_flag(int flag) { return 0; } 1740 1741 /* 1742 * If the system does not have PCI, clearly these return errors. Define 1743 * these as simple inline functions to avoid hair in drivers. 1744 */ 1745 #define _PCI_NOP(o, s, t) \ 1746 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1747 int where, t val) \ 1748 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1749 1750 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1751 _PCI_NOP(o, word, u16 x) \ 1752 _PCI_NOP(o, dword, u32 x) 1753 _PCI_NOP_ALL(read, *) 1754 _PCI_NOP_ALL(write,) 1755 1756 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1757 unsigned int device, 1758 struct pci_dev *from) 1759 { return NULL; } 1760 1761 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1762 unsigned int device, 1763 unsigned int ss_vendor, 1764 unsigned int ss_device, 1765 struct pci_dev *from) 1766 { return NULL; } 1767 1768 static inline struct pci_dev *pci_get_class(unsigned int class, 1769 struct pci_dev *from) 1770 { return NULL; } 1771 1772 #define pci_dev_present(ids) (0) 1773 #define no_pci_devices() (1) 1774 #define pci_dev_put(dev) do { } while (0) 1775 1776 static inline void pci_set_master(struct pci_dev *dev) { } 1777 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1778 static inline void pci_disable_device(struct pci_dev *dev) { } 1779 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1780 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1781 { return -EBUSY; } 1782 static inline int __pci_register_driver(struct pci_driver *drv, 1783 struct module *owner) 1784 { return 0; } 1785 static inline int pci_register_driver(struct pci_driver *drv) 1786 { return 0; } 1787 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1788 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1789 { return 0; } 1790 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1791 int cap) 1792 { return 0; } 1793 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1794 { return 0; } 1795 1796 static inline u64 pci_get_dsn(struct pci_dev *dev) 1797 { return 0; } 1798 1799 /* Power management related routines */ 1800 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1801 static inline void pci_restore_state(struct pci_dev *dev) { } 1802 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1803 { return 0; } 1804 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1805 { return 0; } 1806 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1807 pm_message_t state) 1808 { return PCI_D0; } 1809 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1810 int enable) 1811 { return 0; } 1812 1813 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1814 struct resource *res) 1815 { return NULL; } 1816 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1817 { return -EIO; } 1818 static inline void pci_release_regions(struct pci_dev *dev) { } 1819 1820 static inline int pci_register_io_range(struct fwnode_handle *fwnode, 1821 phys_addr_t addr, resource_size_t size) 1822 { return -EINVAL; } 1823 1824 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1825 1826 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1827 { return NULL; } 1828 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1829 unsigned int devfn) 1830 { return NULL; } 1831 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1832 unsigned int bus, unsigned int devfn) 1833 { return NULL; } 1834 1835 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1836 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1837 1838 #define dev_is_pci(d) (false) 1839 #define dev_is_pf(d) (false) 1840 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1841 { return false; } 1842 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1843 struct device_node *node, 1844 const u32 *intspec, 1845 unsigned int intsize, 1846 unsigned long *out_hwirq, 1847 unsigned int *out_type) 1848 { return -EINVAL; } 1849 1850 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1851 struct pci_dev *dev) 1852 { return NULL; } 1853 static inline bool pci_ats_disabled(void) { return true; } 1854 1855 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1856 { 1857 return -EINVAL; 1858 } 1859 1860 static inline int 1861 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1862 unsigned int max_vecs, unsigned int flags, 1863 struct irq_affinity *aff_desc) 1864 { 1865 return -ENOSPC; 1866 } 1867 #endif /* CONFIG_PCI */ 1868 1869 static inline int 1870 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1871 unsigned int max_vecs, unsigned int flags) 1872 { 1873 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1874 NULL); 1875 } 1876 1877 /* Include architecture-dependent settings and functions */ 1878 1879 #include <asm/pci.h> 1880 1881 /* These two functions provide almost identical functionality. Depending 1882 * on the architecture, one will be implemented as a wrapper around the 1883 * other (in drivers/pci/mmap.c). 1884 * 1885 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1886 * is expected to be an offset within that region. 1887 * 1888 * pci_mmap_page_range() is the legacy architecture-specific interface, 1889 * which accepts a "user visible" resource address converted by 1890 * pci_resource_to_user(), as used in the legacy mmap() interface in 1891 * /proc/bus/pci/. 1892 */ 1893 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1894 struct vm_area_struct *vma, 1895 enum pci_mmap_state mmap_state, int write_combine); 1896 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1897 struct vm_area_struct *vma, 1898 enum pci_mmap_state mmap_state, int write_combine); 1899 1900 #ifndef arch_can_pci_mmap_wc 1901 #define arch_can_pci_mmap_wc() 0 1902 #endif 1903 1904 #ifndef arch_can_pci_mmap_io 1905 #define arch_can_pci_mmap_io() 0 1906 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1907 #else 1908 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1909 #endif 1910 1911 #ifndef pci_root_bus_fwnode 1912 #define pci_root_bus_fwnode(bus) NULL 1913 #endif 1914 1915 /* 1916 * These helpers provide future and backwards compatibility 1917 * for accessing popular PCI BAR info 1918 */ 1919 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1920 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1921 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1922 #define pci_resource_len(dev,bar) \ 1923 ((pci_resource_start((dev), (bar)) == 0 && \ 1924 pci_resource_end((dev), (bar)) == \ 1925 pci_resource_start((dev), (bar))) ? 0 : \ 1926 \ 1927 (pci_resource_end((dev), (bar)) - \ 1928 pci_resource_start((dev), (bar)) + 1)) 1929 1930 /* 1931 * Similar to the helpers above, these manipulate per-pci_dev 1932 * driver-specific data. They are really just a wrapper around 1933 * the generic device structure functions of these calls. 1934 */ 1935 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1936 { 1937 return dev_get_drvdata(&pdev->dev); 1938 } 1939 1940 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1941 { 1942 dev_set_drvdata(&pdev->dev, data); 1943 } 1944 1945 static inline const char *pci_name(const struct pci_dev *pdev) 1946 { 1947 return dev_name(&pdev->dev); 1948 } 1949 1950 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1951 const struct resource *rsrc, 1952 resource_size_t *start, resource_size_t *end); 1953 1954 /* 1955 * The world is not perfect and supplies us with broken PCI devices. 1956 * For at least a part of these bugs we need a work-around, so both 1957 * generic (drivers/pci/quirks.c) and per-architecture code can define 1958 * fixup hooks to be called for particular buggy devices. 1959 */ 1960 1961 struct pci_fixup { 1962 u16 vendor; /* Or PCI_ANY_ID */ 1963 u16 device; /* Or PCI_ANY_ID */ 1964 u32 class; /* Or PCI_ANY_ID */ 1965 unsigned int class_shift; /* should be 0, 8, 16 */ 1966 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1967 int hook_offset; 1968 #else 1969 void (*hook)(struct pci_dev *dev); 1970 #endif 1971 }; 1972 1973 enum pci_fixup_pass { 1974 pci_fixup_early, /* Before probing BARs */ 1975 pci_fixup_header, /* After reading configuration header */ 1976 pci_fixup_final, /* Final phase of device fixups */ 1977 pci_fixup_enable, /* pci_enable_device() time */ 1978 pci_fixup_resume, /* pci_device_resume() */ 1979 pci_fixup_suspend, /* pci_device_suspend() */ 1980 pci_fixup_resume_early, /* pci_device_resume_early() */ 1981 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1982 }; 1983 1984 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1985 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1986 class_shift, hook) \ 1987 __ADDRESSABLE(hook) \ 1988 asm(".section " #sec ", \"a\" \n" \ 1989 ".balign 16 \n" \ 1990 ".short " #vendor ", " #device " \n" \ 1991 ".long " #class ", " #class_shift " \n" \ 1992 ".long " #hook " - . \n" \ 1993 ".previous \n"); 1994 1995 /* 1996 * Clang's LTO may rename static functions in C, but has no way to 1997 * handle such renamings when referenced from inline asm. To work 1998 * around this, create global C stubs for these cases. 1999 */ 2000 #ifdef CONFIG_LTO_CLANG 2001 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2002 class_shift, hook, stub) \ 2003 void __cficanonical stub(struct pci_dev *dev); \ 2004 void __cficanonical stub(struct pci_dev *dev) \ 2005 { \ 2006 hook(dev); \ 2007 } \ 2008 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2009 class_shift, stub) 2010 #else 2011 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2012 class_shift, hook, stub) \ 2013 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2014 class_shift, hook) 2015 #endif 2016 2017 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2018 class_shift, hook) \ 2019 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2020 class_shift, hook, __UNIQUE_ID(hook)) 2021 #else 2022 /* Anonymous variables would be nice... */ 2023 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2024 class_shift, hook) \ 2025 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2026 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2027 = { vendor, device, class, class_shift, hook }; 2028 #endif 2029 2030 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2031 class_shift, hook) \ 2032 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2033 hook, vendor, device, class, class_shift, hook) 2034 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2035 class_shift, hook) \ 2036 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2037 hook, vendor, device, class, class_shift, hook) 2038 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2039 class_shift, hook) \ 2040 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2041 hook, vendor, device, class, class_shift, hook) 2042 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2043 class_shift, hook) \ 2044 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2045 hook, vendor, device, class, class_shift, hook) 2046 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2047 class_shift, hook) \ 2048 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2049 resume##hook, vendor, device, class, class_shift, hook) 2050 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2051 class_shift, hook) \ 2052 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2053 resume_early##hook, vendor, device, class, class_shift, hook) 2054 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2055 class_shift, hook) \ 2056 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2057 suspend##hook, vendor, device, class, class_shift, hook) 2058 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2059 class_shift, hook) \ 2060 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2061 suspend_late##hook, vendor, device, class, class_shift, hook) 2062 2063 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2064 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2065 hook, vendor, device, PCI_ANY_ID, 0, hook) 2066 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2067 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2068 hook, vendor, device, PCI_ANY_ID, 0, hook) 2069 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2070 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2071 hook, vendor, device, PCI_ANY_ID, 0, hook) 2072 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2073 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2074 hook, vendor, device, PCI_ANY_ID, 0, hook) 2075 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2076 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2077 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2078 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2079 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2080 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2081 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2082 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2083 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2084 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2085 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2086 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2087 2088 #ifdef CONFIG_PCI_QUIRKS 2089 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2090 #else 2091 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2092 struct pci_dev *dev) { } 2093 #endif 2094 2095 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2096 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2097 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2098 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2099 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2100 const char *name); 2101 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2102 2103 extern int pci_pci_problems; 2104 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2105 #define PCIPCI_TRITON 2 2106 #define PCIPCI_NATOMA 4 2107 #define PCIPCI_VIAETBF 8 2108 #define PCIPCI_VSFX 16 2109 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2110 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2111 2112 extern unsigned long pci_cardbus_io_size; 2113 extern unsigned long pci_cardbus_mem_size; 2114 extern u8 pci_dfl_cache_line_size; 2115 extern u8 pci_cache_line_size; 2116 2117 /* Architecture-specific versions may override these (weak) */ 2118 void pcibios_disable_device(struct pci_dev *dev); 2119 void pcibios_set_master(struct pci_dev *dev); 2120 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2121 enum pcie_reset_state state); 2122 int pcibios_add_device(struct pci_dev *dev); 2123 void pcibios_release_device(struct pci_dev *dev); 2124 #ifdef CONFIG_PCI 2125 void pcibios_penalize_isa_irq(int irq, int active); 2126 #else 2127 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2128 #endif 2129 int pcibios_alloc_irq(struct pci_dev *dev); 2130 void pcibios_free_irq(struct pci_dev *dev); 2131 resource_size_t pcibios_default_alignment(void); 2132 2133 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2134 void __init pci_mmcfg_early_init(void); 2135 void __init pci_mmcfg_late_init(void); 2136 #else 2137 static inline void pci_mmcfg_early_init(void) { } 2138 static inline void pci_mmcfg_late_init(void) { } 2139 #endif 2140 2141 int pci_ext_cfg_avail(void); 2142 2143 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2144 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2145 2146 #ifdef CONFIG_PCI_IOV 2147 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2148 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2149 2150 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2151 void pci_disable_sriov(struct pci_dev *dev); 2152 2153 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2154 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2155 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2156 int pci_num_vf(struct pci_dev *dev); 2157 int pci_vfs_assigned(struct pci_dev *dev); 2158 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2159 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2160 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2161 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2162 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2163 2164 /* Arch may override these (weak) */ 2165 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2166 int pcibios_sriov_disable(struct pci_dev *pdev); 2167 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2168 #else 2169 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2170 { 2171 return -ENOSYS; 2172 } 2173 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2174 { 2175 return -ENOSYS; 2176 } 2177 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2178 { return -ENODEV; } 2179 2180 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2181 struct pci_dev *virtfn, int id) 2182 { 2183 return -ENODEV; 2184 } 2185 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2186 { 2187 return -ENOSYS; 2188 } 2189 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2190 int id) { } 2191 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2192 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2193 static inline int pci_vfs_assigned(struct pci_dev *dev) 2194 { return 0; } 2195 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2196 { return 0; } 2197 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2198 { return 0; } 2199 #define pci_sriov_configure_simple NULL 2200 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2201 { return 0; } 2202 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2203 #endif 2204 2205 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2206 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2207 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2208 #endif 2209 2210 /** 2211 * pci_pcie_cap - get the saved PCIe capability offset 2212 * @dev: PCI device 2213 * 2214 * PCIe capability offset is calculated at PCI device initialization 2215 * time and saved in the data structure. This function returns saved 2216 * PCIe capability offset. Using this instead of pci_find_capability() 2217 * reduces unnecessary search in the PCI configuration space. If you 2218 * need to calculate PCIe capability offset from raw device for some 2219 * reasons, please use pci_find_capability() instead. 2220 */ 2221 static inline int pci_pcie_cap(struct pci_dev *dev) 2222 { 2223 return dev->pcie_cap; 2224 } 2225 2226 /** 2227 * pci_is_pcie - check if the PCI device is PCI Express capable 2228 * @dev: PCI device 2229 * 2230 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2231 */ 2232 static inline bool pci_is_pcie(struct pci_dev *dev) 2233 { 2234 return pci_pcie_cap(dev); 2235 } 2236 2237 /** 2238 * pcie_caps_reg - get the PCIe Capabilities Register 2239 * @dev: PCI device 2240 */ 2241 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2242 { 2243 return dev->pcie_flags_reg; 2244 } 2245 2246 /** 2247 * pci_pcie_type - get the PCIe device/port type 2248 * @dev: PCI device 2249 */ 2250 static inline int pci_pcie_type(const struct pci_dev *dev) 2251 { 2252 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2253 } 2254 2255 /** 2256 * pcie_find_root_port - Get the PCIe root port device 2257 * @dev: PCI device 2258 * 2259 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2260 * for a given PCI/PCIe Device. 2261 */ 2262 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2263 { 2264 while (dev) { 2265 if (pci_is_pcie(dev) && 2266 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2267 return dev; 2268 dev = pci_upstream_bridge(dev); 2269 } 2270 2271 return NULL; 2272 } 2273 2274 void pci_request_acs(void); 2275 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2276 bool pci_acs_path_enabled(struct pci_dev *start, 2277 struct pci_dev *end, u16 acs_flags); 2278 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2279 2280 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2281 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2282 2283 /* Large Resource Data Type Tag Item Names */ 2284 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2285 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2286 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2287 2288 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2289 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2290 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2291 2292 /* Small Resource Data Type Tag Item Names */ 2293 #define PCI_VPD_STIN_END 0x0f /* End */ 2294 2295 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2296 2297 #define PCI_VPD_SRDT_TIN_MASK 0x78 2298 #define PCI_VPD_SRDT_LEN_MASK 0x07 2299 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2300 2301 #define PCI_VPD_LRDT_TAG_SIZE 3 2302 #define PCI_VPD_SRDT_TAG_SIZE 1 2303 2304 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2305 2306 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2307 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2308 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2309 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2310 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2311 2312 /** 2313 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2314 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2315 * 2316 * Returns the extracted Large Resource Data Type length. 2317 */ 2318 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2319 { 2320 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2321 } 2322 2323 /** 2324 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2325 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2326 * 2327 * Returns the extracted Large Resource Data Type Tag item. 2328 */ 2329 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2330 { 2331 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2332 } 2333 2334 /** 2335 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2336 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2337 * 2338 * Returns the extracted Small Resource Data Type length. 2339 */ 2340 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2341 { 2342 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2343 } 2344 2345 /** 2346 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2347 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2348 * 2349 * Returns the extracted Small Resource Data Type Tag Item. 2350 */ 2351 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2352 { 2353 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2354 } 2355 2356 /** 2357 * pci_vpd_info_field_size - Extracts the information field length 2358 * @info_field: Pointer to the beginning of an information field header 2359 * 2360 * Returns the extracted information field length. 2361 */ 2362 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2363 { 2364 return info_field[2]; 2365 } 2366 2367 /** 2368 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2369 * @buf: Pointer to buffered vpd data 2370 * @len: The length of the vpd buffer 2371 * @rdt: The Resource Data Type to search for 2372 * 2373 * Returns the index where the Resource Data Type was found or 2374 * -ENOENT otherwise. 2375 */ 2376 int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt); 2377 2378 /** 2379 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2380 * @buf: Pointer to buffered vpd data 2381 * @off: The offset into the buffer at which to begin the search 2382 * @len: The length of the buffer area, relative to off, in which to search 2383 * @kw: The keyword to search for 2384 * 2385 * Returns the index where the information field keyword was found or 2386 * -ENOENT otherwise. 2387 */ 2388 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2389 unsigned int len, const char *kw); 2390 2391 /* PCI <-> OF binding helpers */ 2392 #ifdef CONFIG_OF 2393 struct device_node; 2394 struct irq_domain; 2395 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2396 bool pci_host_of_has_msi_map(struct device *dev); 2397 2398 /* Arch may override this (weak) */ 2399 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2400 2401 #else /* CONFIG_OF */ 2402 static inline struct irq_domain * 2403 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2404 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2405 #endif /* CONFIG_OF */ 2406 2407 static inline struct device_node * 2408 pci_device_to_OF_node(const struct pci_dev *pdev) 2409 { 2410 return pdev ? pdev->dev.of_node : NULL; 2411 } 2412 2413 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2414 { 2415 return bus ? bus->dev.of_node : NULL; 2416 } 2417 2418 #ifdef CONFIG_ACPI 2419 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2420 2421 void 2422 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2423 bool pci_pr3_present(struct pci_dev *pdev); 2424 #else 2425 static inline struct irq_domain * 2426 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2427 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2428 #endif 2429 2430 #ifdef CONFIG_EEH 2431 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2432 { 2433 return pdev->dev.archdata.edev; 2434 } 2435 #endif 2436 2437 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2438 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2439 int pci_for_each_dma_alias(struct pci_dev *pdev, 2440 int (*fn)(struct pci_dev *pdev, 2441 u16 alias, void *data), void *data); 2442 2443 /* Helper functions for operation of device flag */ 2444 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2445 { 2446 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2447 } 2448 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2449 { 2450 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2451 } 2452 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2453 { 2454 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2455 } 2456 2457 /** 2458 * pci_ari_enabled - query ARI forwarding status 2459 * @bus: the PCI bus 2460 * 2461 * Returns true if ARI forwarding is enabled. 2462 */ 2463 static inline bool pci_ari_enabled(struct pci_bus *bus) 2464 { 2465 return bus->self && bus->self->ari_enabled; 2466 } 2467 2468 /** 2469 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2470 * @pdev: PCI device to check 2471 * 2472 * Walk upwards from @pdev and check for each encountered bridge if it's part 2473 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2474 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2475 */ 2476 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2477 { 2478 struct pci_dev *parent = pdev; 2479 2480 if (pdev->is_thunderbolt) 2481 return true; 2482 2483 while ((parent = pci_upstream_bridge(parent))) 2484 if (parent->is_thunderbolt) 2485 return true; 2486 2487 return false; 2488 } 2489 2490 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2491 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2492 #endif 2493 2494 /* Provide the legacy pci_dma_* API */ 2495 #include <linux/pci-dma-compat.h> 2496 2497 #define pci_printk(level, pdev, fmt, arg...) \ 2498 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2499 2500 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2501 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2502 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2503 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2504 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2505 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2506 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2507 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2508 2509 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2510 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2511 2512 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2513 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2514 2515 #define pci_WARN(pdev, condition, fmt, arg...) \ 2516 WARN(condition, "%s %s: " fmt, \ 2517 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2518 2519 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2520 WARN_ONCE(condition, "%s %s: " fmt, \ 2521 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2522 2523 #endif /* LINUX_PCI_H */ 2524