1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * For more information, please consult the following manuals (look at 10 * http://www.pcisig.com/ for how to get them): 11 * 12 * PCI BIOS Specification 13 * PCI Local Bus Specification 14 * PCI to PCI Bridge Specification 15 * PCI System Design Guide 16 */ 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 21 #include <linux/mod_devicetable.h> 22 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/list.h> 27 #include <linux/compiler.h> 28 #include <linux/errno.h> 29 #include <linux/kobject.h> 30 #include <linux/atomic.h> 31 #include <linux/device.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/resource_ext.h> 35 #include <uapi/linux/pci.h> 36 37 #include <linux/pci_ids.h> 38 39 /* 40 * The PCI interface treats multi-function devices as independent 41 * devices. The slot/function address of each device is encoded 42 * in a single byte as follows: 43 * 44 * 7:3 = slot 45 * 2:0 = function 46 * 47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 48 * In the interest of not exposing interfaces to user-space unnecessarily, 49 * the following kernel-only defines are being added here. 50 */ 51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 54 55 /* pci_slot represents a physical slot */ 56 struct pci_slot { 57 struct pci_bus *bus; /* Bus this slot is on */ 58 struct list_head list; /* Node in list of slots */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 61 struct kobject kobj; 62 }; 63 64 static inline const char *pci_slot_name(const struct pci_slot *slot) 65 { 66 return kobject_name(&slot->kobj); 67 } 68 69 /* File state for mmap()s on /proc/bus/pci/X/Y */ 70 enum pci_mmap_state { 71 pci_mmap_io, 72 pci_mmap_mem 73 }; 74 75 /* For PCI devices, the region numbers are assigned this way: */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* Device-specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* Resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* Total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* Preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 /** 105 * enum pci_interrupt_pin - PCI INTx interrupt values 106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 107 * @PCI_INTERRUPT_INTA: PCI INTA pin 108 * @PCI_INTERRUPT_INTB: PCI INTB pin 109 * @PCI_INTERRUPT_INTC: PCI INTC pin 110 * @PCI_INTERRUPT_INTD: PCI INTD pin 111 * 112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 113 * PCI_INTERRUPT_PIN register. 114 */ 115 enum pci_interrupt_pin { 116 PCI_INTERRUPT_UNKNOWN, 117 PCI_INTERRUPT_INTA, 118 PCI_INTERRUPT_INTB, 119 PCI_INTERRUPT_INTC, 120 PCI_INTERRUPT_INTD, 121 }; 122 123 /* The number of legacy PCI INTx interrupts */ 124 #define PCI_NUM_INTX 4 125 126 /* 127 * pci_power_t values must match the bits in the Capabilities PME_Support 128 * and Control/Status PowerState fields in the Power Management capability. 129 */ 130 typedef int __bitwise pci_power_t; 131 132 #define PCI_D0 ((pci_power_t __force) 0) 133 #define PCI_D1 ((pci_power_t __force) 1) 134 #define PCI_D2 ((pci_power_t __force) 2) 135 #define PCI_D3hot ((pci_power_t __force) 3) 136 #define PCI_D3cold ((pci_power_t __force) 4) 137 #define PCI_UNKNOWN ((pci_power_t __force) 5) 138 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 139 140 /* Remember to update this when the list above changes! */ 141 extern const char *pci_power_names[]; 142 143 static inline const char *pci_power_name(pci_power_t state) 144 { 145 return pci_power_names[1 + (__force int) state]; 146 } 147 148 #define PCI_PM_D2_DELAY 200 149 #define PCI_PM_D3_WAIT 10 150 #define PCI_PM_D3COLD_WAIT 100 151 #define PCI_PM_BUS_WAIT 50 152 153 /** 154 * The pci_channel state describes connectivity between the CPU and 155 * the PCI device. If some PCI bus between here and the PCI device 156 * has crashed or locked up, this info is reflected here. 157 */ 158 typedef unsigned int __bitwise pci_channel_state_t; 159 160 enum pci_channel_state { 161 /* I/O channel is in normal state */ 162 pci_channel_io_normal = (__force pci_channel_state_t) 1, 163 164 /* I/O to channel is blocked */ 165 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 166 167 /* PCI card is dead */ 168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 169 }; 170 171 typedef unsigned int __bitwise pcie_reset_state_t; 172 173 enum pcie_reset_state { 174 /* Reset is NOT asserted (Use to deassert reset) */ 175 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 176 177 /* Use #PERST to reset PCIe device */ 178 pcie_warm_reset = (__force pcie_reset_state_t) 2, 179 180 /* Use PCIe Hot Reset to reset device */ 181 pcie_hot_reset = (__force pcie_reset_state_t) 3 182 }; 183 184 typedef unsigned short __bitwise pci_dev_flags_t; 185 enum pci_dev_flags { 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 188 /* Device configuration is irrevocably lost if disabled into D3 */ 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 190 /* Provide indication device is assigned by a Virtual Machine Manager */ 191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 192 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 196 /* Do not use bus resets for device */ 197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 198 /* Do not use PM reset even if device advertises NoSoftRst- */ 199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 200 /* Get VPD from function 0 VPD */ 201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 202 /* A non-root bridge where translation occurs, stop alias search here */ 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 204 /* Do not use FLR even if device advertises PCI_AF_CAP */ 205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 206 /* Don't use Relaxed Ordering for TLPs directed at this device */ 207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 208 }; 209 210 enum pci_irq_reroute_variant { 211 INTEL_IRQ_REROUTE_VARIANT = 1, 212 MAX_IRQ_REROUTE_VARIANTS = 3 213 }; 214 215 typedef unsigned short __bitwise pci_bus_flags_t; 216 enum pci_bus_flags { 217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 221 }; 222 223 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 224 enum pcie_link_width { 225 PCIE_LNK_WIDTH_RESRV = 0x00, 226 PCIE_LNK_X1 = 0x01, 227 PCIE_LNK_X2 = 0x02, 228 PCIE_LNK_X4 = 0x04, 229 PCIE_LNK_X8 = 0x08, 230 PCIE_LNK_X12 = 0x0c, 231 PCIE_LNK_X16 = 0x10, 232 PCIE_LNK_X32 = 0x20, 233 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 234 }; 235 236 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 237 enum pci_bus_speed { 238 PCI_SPEED_33MHz = 0x00, 239 PCI_SPEED_66MHz = 0x01, 240 PCI_SPEED_66MHz_PCIX = 0x02, 241 PCI_SPEED_100MHz_PCIX = 0x03, 242 PCI_SPEED_133MHz_PCIX = 0x04, 243 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 244 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 245 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 246 PCI_SPEED_66MHz_PCIX_266 = 0x09, 247 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 248 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 249 AGP_UNKNOWN = 0x0c, 250 AGP_1X = 0x0d, 251 AGP_2X = 0x0e, 252 AGP_4X = 0x0f, 253 AGP_8X = 0x10, 254 PCI_SPEED_66MHz_PCIX_533 = 0x11, 255 PCI_SPEED_100MHz_PCIX_533 = 0x12, 256 PCI_SPEED_133MHz_PCIX_533 = 0x13, 257 PCIE_SPEED_2_5GT = 0x14, 258 PCIE_SPEED_5_0GT = 0x15, 259 PCIE_SPEED_8_0GT = 0x16, 260 PCIE_SPEED_16_0GT = 0x17, 261 PCI_SPEED_UNKNOWN = 0xff, 262 }; 263 264 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 265 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 266 267 struct pci_cap_saved_data { 268 u16 cap_nr; 269 bool cap_extended; 270 unsigned int size; 271 u32 data[0]; 272 }; 273 274 struct pci_cap_saved_state { 275 struct hlist_node next; 276 struct pci_cap_saved_data cap; 277 }; 278 279 struct irq_affinity; 280 struct pcie_link_state; 281 struct pci_vpd; 282 struct pci_sriov; 283 struct pci_ats; 284 struct pci_p2pdma; 285 286 /* The pci_dev structure describes PCI devices */ 287 struct pci_dev { 288 struct list_head bus_list; /* Node in per-bus list */ 289 struct pci_bus *bus; /* Bus this device is on */ 290 struct pci_bus *subordinate; /* Bus this device bridges to */ 291 292 void *sysdata; /* Hook for sys-specific extension */ 293 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 294 struct pci_slot *slot; /* Physical slot this device is in */ 295 296 unsigned int devfn; /* Encoded device & function index */ 297 unsigned short vendor; 298 unsigned short device; 299 unsigned short subsystem_vendor; 300 unsigned short subsystem_device; 301 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 302 u8 revision; /* PCI revision, low byte of class word */ 303 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 304 #ifdef CONFIG_PCIEAER 305 u16 aer_cap; /* AER capability offset */ 306 struct aer_stats *aer_stats; /* AER stats for this device */ 307 #endif 308 u8 pcie_cap; /* PCIe capability offset */ 309 u8 msi_cap; /* MSI capability offset */ 310 u8 msix_cap; /* MSI-X capability offset */ 311 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 312 u8 rom_base_reg; /* Config register controlling ROM */ 313 u8 pin; /* Interrupt pin this device uses */ 314 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 315 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 316 317 struct pci_driver *driver; /* Driver bound to this device */ 318 u64 dma_mask; /* Mask of the bits of bus address this 319 device implements. Normally this is 320 0xffffffff. You only need to change 321 this if your device has broken DMA 322 or supports 64-bit transfers. */ 323 324 struct device_dma_parameters dma_parms; 325 326 pci_power_t current_state; /* Current operating state. In ACPI, 327 this is D0-D3, D0 being fully 328 functional, and D3 being off. */ 329 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 330 u8 pm_cap; /* PM capability offset */ 331 unsigned int pme_support:5; /* Bitmask of states from which PME# 332 can be generated */ 333 unsigned int pme_poll:1; /* Poll device's PME status bit */ 334 unsigned int d1_support:1; /* Low power state D1 is supported */ 335 unsigned int d2_support:1; /* Low power state D2 is supported */ 336 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 337 unsigned int no_d3cold:1; /* D3cold is forbidden */ 338 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 339 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 340 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 341 decoding during BAR sizing */ 342 unsigned int wakeup_prepared:1; 343 unsigned int runtime_d3cold:1; /* Whether go through runtime 344 D3cold, not set for devices 345 powered on/off by the 346 corresponding bridge */ 347 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 348 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 349 controlled exclusively by 350 user sysfs */ 351 unsigned int d3_delay; /* D3->D0 transition time in ms */ 352 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 353 354 #ifdef CONFIG_PCIEASPM 355 struct pcie_link_state *link_state; /* ASPM link state */ 356 unsigned int ltr_path:1; /* Latency Tolerance Reporting 357 supported from root to here */ 358 #endif 359 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 360 361 pci_channel_state_t error_state; /* Current connectivity state */ 362 struct device dev; /* Generic device interface */ 363 364 int cfg_size; /* Size of config space */ 365 366 /* 367 * Instead of touching interrupt line and base address registers 368 * directly, use the values stored here. They might be different! 369 */ 370 unsigned int irq; 371 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 372 373 bool match_driver; /* Skip attaching driver */ 374 375 unsigned int transparent:1; /* Subtractive decode bridge */ 376 unsigned int io_window:1; /* Bridge has I/O window */ 377 unsigned int pref_window:1; /* Bridge has pref mem window */ 378 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 379 unsigned int multifunction:1; /* Multi-function device */ 380 381 unsigned int is_busmaster:1; /* Is busmaster */ 382 unsigned int no_msi:1; /* May not use MSI */ 383 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 384 unsigned int block_cfg_access:1; /* Config space access blocked */ 385 unsigned int broken_parity_status:1; /* Generates false positive parity */ 386 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 387 unsigned int msi_enabled:1; 388 unsigned int msix_enabled:1; 389 unsigned int ari_enabled:1; /* ARI forwarding */ 390 unsigned int ats_enabled:1; /* Address Translation Svc */ 391 unsigned int pasid_enabled:1; /* Process Address Space ID */ 392 unsigned int pri_enabled:1; /* Page Request Interface */ 393 unsigned int is_managed:1; 394 unsigned int needs_freset:1; /* Requires fundamental reset */ 395 unsigned int state_saved:1; 396 unsigned int is_physfn:1; 397 unsigned int is_virtfn:1; 398 unsigned int reset_fn:1; 399 unsigned int is_hotplug_bridge:1; 400 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 401 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 402 /* 403 * Devices marked being untrusted are the ones that can potentially 404 * execute DMA attacks and similar. They are typically connected 405 * through external ports such as Thunderbolt but not limited to 406 * that. When an IOMMU is enabled they should be getting full 407 * mappings to make sure they cannot access arbitrary memory. 408 */ 409 unsigned int untrusted:1; 410 unsigned int __aer_firmware_first_valid:1; 411 unsigned int __aer_firmware_first:1; 412 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 413 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 414 unsigned int irq_managed:1; 415 unsigned int has_secondary_link:1; 416 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 417 unsigned int is_probed:1; /* Device probing in progress */ 418 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 419 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 420 pci_dev_flags_t dev_flags; 421 atomic_t enable_cnt; /* pci_enable_device has been called */ 422 423 u32 saved_config_space[16]; /* Config space saved at suspend time */ 424 struct hlist_head saved_cap_space; 425 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 426 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 427 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 428 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 429 430 #ifdef CONFIG_HOTPLUG_PCI_PCIE 431 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 432 #endif 433 #ifdef CONFIG_PCIE_PTM 434 unsigned int ptm_root:1; 435 unsigned int ptm_enabled:1; 436 u8 ptm_granularity; 437 #endif 438 #ifdef CONFIG_PCI_MSI 439 const struct attribute_group **msi_irq_groups; 440 #endif 441 struct pci_vpd *vpd; 442 #ifdef CONFIG_PCI_ATS 443 union { 444 struct pci_sriov *sriov; /* PF: SR-IOV info */ 445 struct pci_dev *physfn; /* VF: related PF */ 446 }; 447 u16 ats_cap; /* ATS Capability offset */ 448 u8 ats_stu; /* ATS Smallest Translation Unit */ 449 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ 450 #endif 451 #ifdef CONFIG_PCI_PRI 452 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 453 #endif 454 #ifdef CONFIG_PCI_PASID 455 u16 pasid_features; 456 #endif 457 #ifdef CONFIG_PCI_P2PDMA 458 struct pci_p2pdma *p2pdma; 459 #endif 460 phys_addr_t rom; /* Physical address if not from BAR */ 461 size_t romlen; /* Length if not from BAR */ 462 char *driver_override; /* Driver name to force a match */ 463 464 unsigned long priv_flags; /* Private flags for the PCI driver */ 465 }; 466 467 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 468 { 469 #ifdef CONFIG_PCI_IOV 470 if (dev->is_virtfn) 471 dev = dev->physfn; 472 #endif 473 return dev; 474 } 475 476 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 477 478 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 479 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 480 481 static inline int pci_channel_offline(struct pci_dev *pdev) 482 { 483 return (pdev->error_state != pci_channel_io_normal); 484 } 485 486 struct pci_host_bridge { 487 struct device dev; 488 struct pci_bus *bus; /* Root bus */ 489 struct pci_ops *ops; 490 void *sysdata; 491 int busnr; 492 struct list_head windows; /* resource_entry */ 493 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 494 int (*map_irq)(const struct pci_dev *, u8, u8); 495 void (*release_fn)(struct pci_host_bridge *); 496 void *release_data; 497 struct msi_controller *msi; 498 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 499 unsigned int no_ext_tags:1; /* No Extended Tags */ 500 unsigned int native_aer:1; /* OS may use PCIe AER */ 501 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 502 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 503 unsigned int native_pme:1; /* OS may use PCIe PME */ 504 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 505 /* Resource alignment requirements */ 506 resource_size_t (*align_resource)(struct pci_dev *dev, 507 const struct resource *res, 508 resource_size_t start, 509 resource_size_t size, 510 resource_size_t align); 511 unsigned long private[0] ____cacheline_aligned; 512 }; 513 514 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 515 516 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 517 { 518 return (void *)bridge->private; 519 } 520 521 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 522 { 523 return container_of(priv, struct pci_host_bridge, private); 524 } 525 526 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 527 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 528 size_t priv); 529 void pci_free_host_bridge(struct pci_host_bridge *bridge); 530 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 531 532 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 533 void (*release_fn)(struct pci_host_bridge *), 534 void *release_data); 535 536 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 537 538 /* 539 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 540 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 541 * buses below host bridges or subtractive decode bridges) go in the list. 542 * Use pci_bus_for_each_resource() to iterate through all the resources. 543 */ 544 545 /* 546 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 547 * and there's no way to program the bridge with the details of the window. 548 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 549 * decode bit set, because they are explicit and can be programmed with _SRS. 550 */ 551 #define PCI_SUBTRACTIVE_DECODE 0x1 552 553 struct pci_bus_resource { 554 struct list_head list; 555 struct resource *res; 556 unsigned int flags; 557 }; 558 559 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 560 561 struct pci_bus { 562 struct list_head node; /* Node in list of buses */ 563 struct pci_bus *parent; /* Parent bus this bridge is on */ 564 struct list_head children; /* List of child buses */ 565 struct list_head devices; /* List of devices on this bus */ 566 struct pci_dev *self; /* Bridge device as seen by parent */ 567 struct list_head slots; /* List of slots on this bus; 568 protected by pci_slot_mutex */ 569 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 570 struct list_head resources; /* Address space routed to this bus */ 571 struct resource busn_res; /* Bus numbers routed to this bus */ 572 573 struct pci_ops *ops; /* Configuration access functions */ 574 struct msi_controller *msi; /* MSI controller */ 575 void *sysdata; /* Hook for sys-specific extension */ 576 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 577 578 unsigned char number; /* Bus number */ 579 unsigned char primary; /* Number of primary bridge */ 580 unsigned char max_bus_speed; /* enum pci_bus_speed */ 581 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 582 #ifdef CONFIG_PCI_DOMAINS_GENERIC 583 int domain_nr; 584 #endif 585 586 char name[48]; 587 588 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 589 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 590 struct device *bridge; 591 struct device dev; 592 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 593 struct bin_attribute *legacy_mem; /* Legacy mem */ 594 unsigned int is_added:1; 595 }; 596 597 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 598 599 /* 600 * Returns true if the PCI bus is root (behind host-PCI bridge), 601 * false otherwise 602 * 603 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 604 * This is incorrect because "virtual" buses added for SR-IOV (via 605 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 606 */ 607 static inline bool pci_is_root_bus(struct pci_bus *pbus) 608 { 609 return !(pbus->parent); 610 } 611 612 /** 613 * pci_is_bridge - check if the PCI device is a bridge 614 * @dev: PCI device 615 * 616 * Return true if the PCI device is bridge whether it has subordinate 617 * or not. 618 */ 619 static inline bool pci_is_bridge(struct pci_dev *dev) 620 { 621 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 622 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 623 } 624 625 #define for_each_pci_bridge(dev, bus) \ 626 list_for_each_entry(dev, &bus->devices, bus_list) \ 627 if (!pci_is_bridge(dev)) {} else 628 629 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 630 { 631 dev = pci_physfn(dev); 632 if (pci_is_root_bus(dev->bus)) 633 return NULL; 634 635 return dev->bus->self; 636 } 637 638 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 639 void pci_put_host_bridge_device(struct device *dev); 640 641 #ifdef CONFIG_PCI_MSI 642 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 643 { 644 return pci_dev->msi_enabled || pci_dev->msix_enabled; 645 } 646 #else 647 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 648 #endif 649 650 /* Error values that may be returned by PCI functions */ 651 #define PCIBIOS_SUCCESSFUL 0x00 652 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 653 #define PCIBIOS_BAD_VENDOR_ID 0x83 654 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 655 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 656 #define PCIBIOS_SET_FAILED 0x88 657 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 658 659 /* Translate above to generic errno for passing back through non-PCI code */ 660 static inline int pcibios_err_to_errno(int err) 661 { 662 if (err <= PCIBIOS_SUCCESSFUL) 663 return err; /* Assume already errno */ 664 665 switch (err) { 666 case PCIBIOS_FUNC_NOT_SUPPORTED: 667 return -ENOENT; 668 case PCIBIOS_BAD_VENDOR_ID: 669 return -ENOTTY; 670 case PCIBIOS_DEVICE_NOT_FOUND: 671 return -ENODEV; 672 case PCIBIOS_BAD_REGISTER_NUMBER: 673 return -EFAULT; 674 case PCIBIOS_SET_FAILED: 675 return -EIO; 676 case PCIBIOS_BUFFER_TOO_SMALL: 677 return -ENOSPC; 678 } 679 680 return -ERANGE; 681 } 682 683 /* Low-level architecture-dependent routines */ 684 685 struct pci_ops { 686 int (*add_bus)(struct pci_bus *bus); 687 void (*remove_bus)(struct pci_bus *bus); 688 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 689 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 690 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 691 }; 692 693 /* 694 * ACPI needs to be able to access PCI config space before we've done a 695 * PCI bus scan and created pci_bus structures. 696 */ 697 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 698 int reg, int len, u32 *val); 699 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 700 int reg, int len, u32 val); 701 702 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 703 typedef u64 pci_bus_addr_t; 704 #else 705 typedef u32 pci_bus_addr_t; 706 #endif 707 708 struct pci_bus_region { 709 pci_bus_addr_t start; 710 pci_bus_addr_t end; 711 }; 712 713 struct pci_dynids { 714 spinlock_t lock; /* Protects list, index */ 715 struct list_head list; /* For IDs added at runtime */ 716 }; 717 718 719 /* 720 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 721 * a set of callbacks in struct pci_error_handlers, that device driver 722 * will be notified of PCI bus errors, and will be driven to recovery 723 * when an error occurs. 724 */ 725 726 typedef unsigned int __bitwise pci_ers_result_t; 727 728 enum pci_ers_result { 729 /* No result/none/not supported in device driver */ 730 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 731 732 /* Device driver can recover without slot reset */ 733 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 734 735 /* Device driver wants slot to be reset */ 736 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 737 738 /* Device has completely failed, is unrecoverable */ 739 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 740 741 /* Device driver is fully recovered and operational */ 742 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 743 744 /* No AER capabilities registered for the driver */ 745 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 746 }; 747 748 /* PCI bus error event callbacks */ 749 struct pci_error_handlers { 750 /* PCI bus error detected on this device */ 751 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 752 enum pci_channel_state error); 753 754 /* MMIO has been re-enabled, but not DMA */ 755 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 756 757 /* PCI slot has been reset */ 758 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 759 760 /* PCI function reset prepare or completed */ 761 void (*reset_prepare)(struct pci_dev *dev); 762 void (*reset_done)(struct pci_dev *dev); 763 764 /* Device driver may resume normal operations */ 765 void (*resume)(struct pci_dev *dev); 766 }; 767 768 769 struct module; 770 struct pci_driver { 771 struct list_head node; 772 const char *name; 773 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 774 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 775 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 776 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 777 int (*suspend_late)(struct pci_dev *dev, pm_message_t state); 778 int (*resume_early)(struct pci_dev *dev); 779 int (*resume)(struct pci_dev *dev); /* Device woken up */ 780 void (*shutdown)(struct pci_dev *dev); 781 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 782 const struct pci_error_handlers *err_handler; 783 const struct attribute_group **groups; 784 struct device_driver driver; 785 struct pci_dynids dynids; 786 }; 787 788 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 789 790 /** 791 * PCI_DEVICE - macro used to describe a specific PCI device 792 * @vend: the 16 bit PCI Vendor ID 793 * @dev: the 16 bit PCI Device ID 794 * 795 * This macro is used to create a struct pci_device_id that matches a 796 * specific device. The subvendor and subdevice fields will be set to 797 * PCI_ANY_ID. 798 */ 799 #define PCI_DEVICE(vend,dev) \ 800 .vendor = (vend), .device = (dev), \ 801 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 802 803 /** 804 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 805 * @vend: the 16 bit PCI Vendor ID 806 * @dev: the 16 bit PCI Device ID 807 * @subvend: the 16 bit PCI Subvendor ID 808 * @subdev: the 16 bit PCI Subdevice ID 809 * 810 * This macro is used to create a struct pci_device_id that matches a 811 * specific device with subsystem information. 812 */ 813 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 814 .vendor = (vend), .device = (dev), \ 815 .subvendor = (subvend), .subdevice = (subdev) 816 817 /** 818 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 819 * @dev_class: the class, subclass, prog-if triple for this device 820 * @dev_class_mask: the class mask for this device 821 * 822 * This macro is used to create a struct pci_device_id that matches a 823 * specific PCI class. The vendor, device, subvendor, and subdevice 824 * fields will be set to PCI_ANY_ID. 825 */ 826 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 827 .class = (dev_class), .class_mask = (dev_class_mask), \ 828 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 829 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 830 831 /** 832 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 833 * @vend: the vendor name 834 * @dev: the 16 bit PCI Device ID 835 * 836 * This macro is used to create a struct pci_device_id that matches a 837 * specific PCI device. The subvendor, and subdevice fields will be set 838 * to PCI_ANY_ID. The macro allows the next field to follow as the device 839 * private data. 840 */ 841 #define PCI_VDEVICE(vend, dev) \ 842 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 843 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 844 845 /** 846 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 847 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 848 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 849 * @data: the driver data to be filled 850 * 851 * This macro is used to create a struct pci_device_id that matches a 852 * specific PCI device. The subvendor, and subdevice fields will be set 853 * to PCI_ANY_ID. 854 */ 855 #define PCI_DEVICE_DATA(vend, dev, data) \ 856 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 857 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 858 .driver_data = (kernel_ulong_t)(data) 859 860 enum { 861 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 862 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 863 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 864 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 865 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 866 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 867 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 868 }; 869 870 /* These external functions are only available when PCI support is enabled */ 871 #ifdef CONFIG_PCI 872 873 extern unsigned int pci_flags; 874 875 static inline void pci_set_flags(int flags) { pci_flags = flags; } 876 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 877 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 878 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 879 880 void pcie_bus_configure_settings(struct pci_bus *bus); 881 882 enum pcie_bus_config_types { 883 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 884 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 885 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 886 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 887 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 888 }; 889 890 extern enum pcie_bus_config_types pcie_bus_config; 891 892 extern struct bus_type pci_bus_type; 893 894 /* Do NOT directly access these two variables, unless you are arch-specific PCI 895 * code, or PCI core code. */ 896 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 897 /* Some device drivers need know if PCI is initiated */ 898 int no_pci_devices(void); 899 900 void pcibios_resource_survey_bus(struct pci_bus *bus); 901 void pcibios_bus_add_device(struct pci_dev *pdev); 902 void pcibios_add_bus(struct pci_bus *bus); 903 void pcibios_remove_bus(struct pci_bus *bus); 904 void pcibios_fixup_bus(struct pci_bus *); 905 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 906 /* Architecture-specific versions may override this (weak) */ 907 char *pcibios_setup(char *str); 908 909 /* Used only when drivers/pci/setup.c is used */ 910 resource_size_t pcibios_align_resource(void *, const struct resource *, 911 resource_size_t, 912 resource_size_t); 913 914 /* Weak but can be overriden by arch */ 915 void pci_fixup_cardbus(struct pci_bus *); 916 917 /* Generic PCI functions used internally */ 918 919 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 920 struct resource *res); 921 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 922 struct pci_bus_region *region); 923 void pcibios_scan_specific_bus(int busn); 924 struct pci_bus *pci_find_bus(int domain, int busnr); 925 void pci_bus_add_devices(const struct pci_bus *bus); 926 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 927 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 928 struct pci_ops *ops, void *sysdata, 929 struct list_head *resources); 930 int pci_host_probe(struct pci_host_bridge *bridge); 931 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 932 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 933 void pci_bus_release_busn_res(struct pci_bus *b); 934 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 935 struct pci_ops *ops, void *sysdata, 936 struct list_head *resources); 937 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 938 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 939 int busnr); 940 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 941 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 942 const char *name, 943 struct hotplug_slot *hotplug); 944 void pci_destroy_slot(struct pci_slot *slot); 945 #ifdef CONFIG_SYSFS 946 void pci_dev_assign_slot(struct pci_dev *dev); 947 #else 948 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 949 #endif 950 int pci_scan_slot(struct pci_bus *bus, int devfn); 951 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 952 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 953 unsigned int pci_scan_child_bus(struct pci_bus *bus); 954 void pci_bus_add_device(struct pci_dev *dev); 955 void pci_read_bridge_bases(struct pci_bus *child); 956 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 957 struct resource *res); 958 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 959 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 960 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 961 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 962 struct pci_dev *pci_dev_get(struct pci_dev *dev); 963 void pci_dev_put(struct pci_dev *dev); 964 void pci_remove_bus(struct pci_bus *b); 965 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 966 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 967 void pci_stop_root_bus(struct pci_bus *bus); 968 void pci_remove_root_bus(struct pci_bus *bus); 969 void pci_setup_cardbus(struct pci_bus *bus); 970 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 971 void pci_sort_breadthfirst(void); 972 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 973 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 974 975 /* Generic PCI functions exported to card drivers */ 976 977 enum pci_lost_interrupt_reason { 978 PCI_LOST_IRQ_NO_INFORMATION = 0, 979 PCI_LOST_IRQ_DISABLE_MSI, 980 PCI_LOST_IRQ_DISABLE_MSIX, 981 PCI_LOST_IRQ_DISABLE_ACPI, 982 }; 983 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 984 int pci_find_capability(struct pci_dev *dev, int cap); 985 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 986 int pci_find_ext_capability(struct pci_dev *dev, int cap); 987 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 988 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 989 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 990 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 991 992 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 993 struct pci_dev *from); 994 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 995 unsigned int ss_vendor, unsigned int ss_device, 996 struct pci_dev *from); 997 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 998 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 999 unsigned int devfn); 1000 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1001 int pci_dev_present(const struct pci_device_id *ids); 1002 1003 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1004 int where, u8 *val); 1005 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1006 int where, u16 *val); 1007 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1008 int where, u32 *val); 1009 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1010 int where, u8 val); 1011 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1012 int where, u16 val); 1013 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1014 int where, u32 val); 1015 1016 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1017 int where, int size, u32 *val); 1018 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1019 int where, int size, u32 val); 1020 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1021 int where, int size, u32 *val); 1022 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1023 int where, int size, u32 val); 1024 1025 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1026 1027 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1028 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1029 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1030 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1031 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1032 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1033 1034 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1035 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1036 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1037 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1038 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1039 u16 clear, u16 set); 1040 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1041 u32 clear, u32 set); 1042 1043 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1044 u16 set) 1045 { 1046 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1047 } 1048 1049 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1050 u32 set) 1051 { 1052 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1053 } 1054 1055 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1056 u16 clear) 1057 { 1058 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1059 } 1060 1061 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1062 u32 clear) 1063 { 1064 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1065 } 1066 1067 /* User-space driven config access */ 1068 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1069 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1070 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1071 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1072 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1073 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1074 1075 int __must_check pci_enable_device(struct pci_dev *dev); 1076 int __must_check pci_enable_device_io(struct pci_dev *dev); 1077 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1078 int __must_check pci_reenable_device(struct pci_dev *); 1079 int __must_check pcim_enable_device(struct pci_dev *pdev); 1080 void pcim_pin_device(struct pci_dev *pdev); 1081 1082 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1083 { 1084 /* 1085 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1086 * writable and no quirk has marked the feature broken. 1087 */ 1088 return !pdev->broken_intx_masking; 1089 } 1090 1091 static inline int pci_is_enabled(struct pci_dev *pdev) 1092 { 1093 return (atomic_read(&pdev->enable_cnt) > 0); 1094 } 1095 1096 static inline int pci_is_managed(struct pci_dev *pdev) 1097 { 1098 return pdev->is_managed; 1099 } 1100 1101 void pci_disable_device(struct pci_dev *dev); 1102 1103 extern unsigned int pcibios_max_latency; 1104 void pci_set_master(struct pci_dev *dev); 1105 void pci_clear_master(struct pci_dev *dev); 1106 1107 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1108 int pci_set_cacheline_size(struct pci_dev *dev); 1109 #define HAVE_PCI_SET_MWI 1110 int __must_check pci_set_mwi(struct pci_dev *dev); 1111 int __must_check pcim_set_mwi(struct pci_dev *dev); 1112 int pci_try_set_mwi(struct pci_dev *dev); 1113 void pci_clear_mwi(struct pci_dev *dev); 1114 void pci_intx(struct pci_dev *dev, int enable); 1115 bool pci_check_and_mask_intx(struct pci_dev *dev); 1116 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1117 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1118 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1119 int pcix_get_max_mmrbc(struct pci_dev *dev); 1120 int pcix_get_mmrbc(struct pci_dev *dev); 1121 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1122 int pcie_get_readrq(struct pci_dev *dev); 1123 int pcie_set_readrq(struct pci_dev *dev, int rq); 1124 int pcie_get_mps(struct pci_dev *dev); 1125 int pcie_set_mps(struct pci_dev *dev, int mps); 1126 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1127 enum pci_bus_speed *speed, 1128 enum pcie_link_width *width); 1129 void pcie_print_link_status(struct pci_dev *dev); 1130 bool pcie_has_flr(struct pci_dev *dev); 1131 int pcie_flr(struct pci_dev *dev); 1132 int __pci_reset_function_locked(struct pci_dev *dev); 1133 int pci_reset_function(struct pci_dev *dev); 1134 int pci_reset_function_locked(struct pci_dev *dev); 1135 int pci_try_reset_function(struct pci_dev *dev); 1136 int pci_probe_reset_slot(struct pci_slot *slot); 1137 int pci_probe_reset_bus(struct pci_bus *bus); 1138 int pci_reset_bus(struct pci_dev *dev); 1139 void pci_reset_secondary_bus(struct pci_dev *dev); 1140 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1141 void pci_update_resource(struct pci_dev *dev, int resno); 1142 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1143 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1144 void pci_release_resource(struct pci_dev *dev, int resno); 1145 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1146 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1147 bool pci_device_is_present(struct pci_dev *pdev); 1148 void pci_ignore_hotplug(struct pci_dev *dev); 1149 1150 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1151 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1152 const char *fmt, ...); 1153 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1154 1155 /* ROM control related routines */ 1156 int pci_enable_rom(struct pci_dev *pdev); 1157 void pci_disable_rom(struct pci_dev *pdev); 1158 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1159 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1160 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1161 1162 /* Power management related routines */ 1163 int pci_save_state(struct pci_dev *dev); 1164 void pci_restore_state(struct pci_dev *dev); 1165 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1166 int pci_load_saved_state(struct pci_dev *dev, 1167 struct pci_saved_state *state); 1168 int pci_load_and_free_saved_state(struct pci_dev *dev, 1169 struct pci_saved_state **state); 1170 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1171 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1172 u16 cap); 1173 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1174 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1175 u16 cap, unsigned int size); 1176 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1177 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1178 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1179 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1180 void pci_pme_active(struct pci_dev *dev, bool enable); 1181 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1182 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1183 int pci_prepare_to_sleep(struct pci_dev *dev); 1184 int pci_back_from_sleep(struct pci_dev *dev); 1185 bool pci_dev_run_wake(struct pci_dev *dev); 1186 bool pci_check_pme_status(struct pci_dev *dev); 1187 void pci_pme_wakeup_bus(struct pci_bus *bus); 1188 void pci_d3cold_enable(struct pci_dev *dev); 1189 void pci_d3cold_disable(struct pci_dev *dev); 1190 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1191 void pci_wakeup_bus(struct pci_bus *bus); 1192 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1193 1194 /* PCI Virtual Channel */ 1195 int pci_save_vc_state(struct pci_dev *dev); 1196 void pci_restore_vc_state(struct pci_dev *dev); 1197 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1198 1199 /* For use by arch with custom probe code */ 1200 void set_pcie_port_type(struct pci_dev *pdev); 1201 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1202 1203 /* Functions for PCI Hotplug drivers to use */ 1204 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1205 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1206 unsigned int pci_rescan_bus(struct pci_bus *bus); 1207 void pci_lock_rescan_remove(void); 1208 void pci_unlock_rescan_remove(void); 1209 1210 /* Vital Product Data routines */ 1211 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1212 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1213 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1214 1215 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1216 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1217 void pci_bus_assign_resources(const struct pci_bus *bus); 1218 void pci_bus_claim_resources(struct pci_bus *bus); 1219 void pci_bus_size_bridges(struct pci_bus *bus); 1220 int pci_claim_resource(struct pci_dev *, int); 1221 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1222 void pci_assign_unassigned_resources(void); 1223 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1224 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1225 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1226 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1227 void pdev_enable_device(struct pci_dev *); 1228 int pci_enable_resources(struct pci_dev *, int mask); 1229 void pci_assign_irq(struct pci_dev *dev); 1230 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1231 #define HAVE_PCI_REQ_REGIONS 2 1232 int __must_check pci_request_regions(struct pci_dev *, const char *); 1233 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1234 void pci_release_regions(struct pci_dev *); 1235 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1236 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1237 void pci_release_region(struct pci_dev *, int); 1238 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1239 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1240 void pci_release_selected_regions(struct pci_dev *, int); 1241 1242 /* drivers/pci/bus.c */ 1243 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1244 void pci_bus_put(struct pci_bus *bus); 1245 void pci_add_resource(struct list_head *resources, struct resource *res); 1246 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1247 resource_size_t offset); 1248 void pci_free_resource_list(struct list_head *resources); 1249 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1250 unsigned int flags); 1251 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1252 void pci_bus_remove_resources(struct pci_bus *bus); 1253 int devm_request_pci_bus_resources(struct device *dev, 1254 struct list_head *resources); 1255 1256 /* Temporary until new and working PCI SBR API in place */ 1257 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1258 1259 #define pci_bus_for_each_resource(bus, res, i) \ 1260 for (i = 0; \ 1261 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1262 i++) 1263 1264 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1265 struct resource *res, resource_size_t size, 1266 resource_size_t align, resource_size_t min, 1267 unsigned long type_mask, 1268 resource_size_t (*alignf)(void *, 1269 const struct resource *, 1270 resource_size_t, 1271 resource_size_t), 1272 void *alignf_data); 1273 1274 1275 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1276 resource_size_t size); 1277 unsigned long pci_address_to_pio(phys_addr_t addr); 1278 phys_addr_t pci_pio_to_address(unsigned long pio); 1279 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1280 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1281 phys_addr_t phys_addr); 1282 void pci_unmap_iospace(struct resource *res); 1283 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1284 resource_size_t offset, 1285 resource_size_t size); 1286 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1287 struct resource *res); 1288 1289 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1290 { 1291 struct pci_bus_region region; 1292 1293 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1294 return region.start; 1295 } 1296 1297 /* Proper probing supporting hot-pluggable devices */ 1298 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1299 const char *mod_name); 1300 1301 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1302 #define pci_register_driver(driver) \ 1303 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1304 1305 void pci_unregister_driver(struct pci_driver *dev); 1306 1307 /** 1308 * module_pci_driver() - Helper macro for registering a PCI driver 1309 * @__pci_driver: pci_driver struct 1310 * 1311 * Helper macro for PCI drivers which do not do anything special in module 1312 * init/exit. This eliminates a lot of boilerplate. Each module may only 1313 * use this macro once, and calling it replaces module_init() and module_exit() 1314 */ 1315 #define module_pci_driver(__pci_driver) \ 1316 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1317 1318 /** 1319 * builtin_pci_driver() - Helper macro for registering a PCI driver 1320 * @__pci_driver: pci_driver struct 1321 * 1322 * Helper macro for PCI drivers which do not do anything special in their 1323 * init code. This eliminates a lot of boilerplate. Each driver may only 1324 * use this macro once, and calling it replaces device_initcall(...) 1325 */ 1326 #define builtin_pci_driver(__pci_driver) \ 1327 builtin_driver(__pci_driver, pci_register_driver) 1328 1329 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1330 int pci_add_dynid(struct pci_driver *drv, 1331 unsigned int vendor, unsigned int device, 1332 unsigned int subvendor, unsigned int subdevice, 1333 unsigned int class, unsigned int class_mask, 1334 unsigned long driver_data); 1335 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1336 struct pci_dev *dev); 1337 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1338 int pass); 1339 1340 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1341 void *userdata); 1342 int pci_cfg_space_size(struct pci_dev *dev); 1343 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1344 void pci_setup_bridge(struct pci_bus *bus); 1345 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1346 unsigned long type); 1347 1348 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1349 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1350 1351 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1352 unsigned int command_bits, u32 flags); 1353 1354 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1355 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1356 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1357 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1358 #define PCI_IRQ_ALL_TYPES \ 1359 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1360 1361 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1362 1363 #include <linux/dmapool.h> 1364 1365 #define pci_pool dma_pool 1366 #define pci_pool_create(name, pdev, size, align, allocation) \ 1367 dma_pool_create(name, &pdev->dev, size, align, allocation) 1368 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1369 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1370 #define pci_pool_zalloc(pool, flags, handle) \ 1371 dma_pool_zalloc(pool, flags, handle) 1372 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1373 1374 struct msix_entry { 1375 u32 vector; /* Kernel uses to write allocated vector */ 1376 u16 entry; /* Driver uses to specify entry, OS writes */ 1377 }; 1378 1379 #ifdef CONFIG_PCI_MSI 1380 int pci_msi_vec_count(struct pci_dev *dev); 1381 void pci_disable_msi(struct pci_dev *dev); 1382 int pci_msix_vec_count(struct pci_dev *dev); 1383 void pci_disable_msix(struct pci_dev *dev); 1384 void pci_restore_msi_state(struct pci_dev *dev); 1385 int pci_msi_enabled(void); 1386 int pci_enable_msi(struct pci_dev *dev); 1387 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1388 int minvec, int maxvec); 1389 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1390 struct msix_entry *entries, int nvec) 1391 { 1392 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1393 if (rc < 0) 1394 return rc; 1395 return 0; 1396 } 1397 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1398 unsigned int max_vecs, unsigned int flags, 1399 struct irq_affinity *affd); 1400 1401 void pci_free_irq_vectors(struct pci_dev *dev); 1402 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1403 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1404 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1405 1406 #else 1407 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1408 static inline void pci_disable_msi(struct pci_dev *dev) { } 1409 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1410 static inline void pci_disable_msix(struct pci_dev *dev) { } 1411 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1412 static inline int pci_msi_enabled(void) { return 0; } 1413 static inline int pci_enable_msi(struct pci_dev *dev) 1414 { return -ENOSYS; } 1415 static inline int pci_enable_msix_range(struct pci_dev *dev, 1416 struct msix_entry *entries, int minvec, int maxvec) 1417 { return -ENOSYS; } 1418 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1419 struct msix_entry *entries, int nvec) 1420 { return -ENOSYS; } 1421 1422 static inline int 1423 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1424 unsigned int max_vecs, unsigned int flags, 1425 struct irq_affinity *aff_desc) 1426 { 1427 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1428 return 1; 1429 return -ENOSPC; 1430 } 1431 1432 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1433 { 1434 } 1435 1436 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1437 { 1438 if (WARN_ON_ONCE(nr > 0)) 1439 return -EINVAL; 1440 return dev->irq; 1441 } 1442 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1443 int vec) 1444 { 1445 return cpu_possible_mask; 1446 } 1447 1448 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1449 { 1450 return first_online_node; 1451 } 1452 #endif 1453 1454 static inline int 1455 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1456 unsigned int max_vecs, unsigned int flags) 1457 { 1458 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1459 NULL); 1460 } 1461 1462 /** 1463 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1464 * @d: the INTx IRQ domain 1465 * @node: the DT node for the device whose interrupt we're translating 1466 * @intspec: the interrupt specifier data from the DT 1467 * @intsize: the number of entries in @intspec 1468 * @out_hwirq: pointer at which to write the hwirq number 1469 * @out_type: pointer at which to write the interrupt type 1470 * 1471 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1472 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1473 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1474 * INTx value to obtain the hwirq number. 1475 * 1476 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1477 */ 1478 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1479 struct device_node *node, 1480 const u32 *intspec, 1481 unsigned int intsize, 1482 unsigned long *out_hwirq, 1483 unsigned int *out_type) 1484 { 1485 const u32 intx = intspec[0]; 1486 1487 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1488 return -EINVAL; 1489 1490 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1491 return 0; 1492 } 1493 1494 #ifdef CONFIG_PCIEPORTBUS 1495 extern bool pcie_ports_disabled; 1496 extern bool pcie_ports_native; 1497 #else 1498 #define pcie_ports_disabled true 1499 #define pcie_ports_native false 1500 #endif 1501 1502 #ifdef CONFIG_PCIEASPM 1503 bool pcie_aspm_support_enabled(void); 1504 #else 1505 static inline bool pcie_aspm_support_enabled(void) { return false; } 1506 #endif 1507 1508 #ifdef CONFIG_PCIEAER 1509 bool pci_aer_available(void); 1510 #else 1511 static inline bool pci_aer_available(void) { return false; } 1512 #endif 1513 1514 #ifdef CONFIG_PCIE_ECRC 1515 void pcie_set_ecrc_checking(struct pci_dev *dev); 1516 void pcie_ecrc_get_policy(char *str); 1517 #else 1518 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1519 static inline void pcie_ecrc_get_policy(char *str) { } 1520 #endif 1521 1522 bool pci_ats_disabled(void); 1523 1524 #ifdef CONFIG_PCI_ATS 1525 /* Address Translation Service */ 1526 void pci_ats_init(struct pci_dev *dev); 1527 int pci_enable_ats(struct pci_dev *dev, int ps); 1528 void pci_disable_ats(struct pci_dev *dev); 1529 int pci_ats_queue_depth(struct pci_dev *dev); 1530 int pci_ats_page_aligned(struct pci_dev *dev); 1531 #else 1532 static inline void pci_ats_init(struct pci_dev *d) { } 1533 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1534 static inline void pci_disable_ats(struct pci_dev *d) { } 1535 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1536 static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; } 1537 #endif 1538 1539 #ifdef CONFIG_PCIE_PTM 1540 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1541 #else 1542 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1543 { return -EINVAL; } 1544 #endif 1545 1546 void pci_cfg_access_lock(struct pci_dev *dev); 1547 bool pci_cfg_access_trylock(struct pci_dev *dev); 1548 void pci_cfg_access_unlock(struct pci_dev *dev); 1549 1550 /* 1551 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1552 * a PCI domain is defined to be a set of PCI buses which share 1553 * configuration space. 1554 */ 1555 #ifdef CONFIG_PCI_DOMAINS 1556 extern int pci_domains_supported; 1557 #else 1558 enum { pci_domains_supported = 0 }; 1559 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1560 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1561 #endif /* CONFIG_PCI_DOMAINS */ 1562 1563 /* 1564 * Generic implementation for PCI domain support. If your 1565 * architecture does not need custom management of PCI 1566 * domains then this implementation will be used 1567 */ 1568 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1569 static inline int pci_domain_nr(struct pci_bus *bus) 1570 { 1571 return bus->domain_nr; 1572 } 1573 #ifdef CONFIG_ACPI 1574 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1575 #else 1576 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1577 { return 0; } 1578 #endif 1579 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1580 #endif 1581 1582 /* Some architectures require additional setup to direct VGA traffic */ 1583 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1584 unsigned int command_bits, u32 flags); 1585 void pci_register_set_vga_state(arch_set_vga_state_t func); 1586 1587 static inline int 1588 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1589 { 1590 return pci_request_selected_regions(pdev, 1591 pci_select_bars(pdev, IORESOURCE_IO), name); 1592 } 1593 1594 static inline void 1595 pci_release_io_regions(struct pci_dev *pdev) 1596 { 1597 return pci_release_selected_regions(pdev, 1598 pci_select_bars(pdev, IORESOURCE_IO)); 1599 } 1600 1601 static inline int 1602 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1603 { 1604 return pci_request_selected_regions(pdev, 1605 pci_select_bars(pdev, IORESOURCE_MEM), name); 1606 } 1607 1608 static inline void 1609 pci_release_mem_regions(struct pci_dev *pdev) 1610 { 1611 return pci_release_selected_regions(pdev, 1612 pci_select_bars(pdev, IORESOURCE_MEM)); 1613 } 1614 1615 #else /* CONFIG_PCI is not enabled */ 1616 1617 static inline void pci_set_flags(int flags) { } 1618 static inline void pci_add_flags(int flags) { } 1619 static inline void pci_clear_flags(int flags) { } 1620 static inline int pci_has_flag(int flag) { return 0; } 1621 1622 /* 1623 * If the system does not have PCI, clearly these return errors. Define 1624 * these as simple inline functions to avoid hair in drivers. 1625 */ 1626 #define _PCI_NOP(o, s, t) \ 1627 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1628 int where, t val) \ 1629 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1630 1631 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1632 _PCI_NOP(o, word, u16 x) \ 1633 _PCI_NOP(o, dword, u32 x) 1634 _PCI_NOP_ALL(read, *) 1635 _PCI_NOP_ALL(write,) 1636 1637 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1638 unsigned int device, 1639 struct pci_dev *from) 1640 { return NULL; } 1641 1642 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1643 unsigned int device, 1644 unsigned int ss_vendor, 1645 unsigned int ss_device, 1646 struct pci_dev *from) 1647 { return NULL; } 1648 1649 static inline struct pci_dev *pci_get_class(unsigned int class, 1650 struct pci_dev *from) 1651 { return NULL; } 1652 1653 #define pci_dev_present(ids) (0) 1654 #define no_pci_devices() (1) 1655 #define pci_dev_put(dev) do { } while (0) 1656 1657 static inline void pci_set_master(struct pci_dev *dev) { } 1658 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1659 static inline void pci_disable_device(struct pci_dev *dev) { } 1660 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1661 { return -EBUSY; } 1662 static inline int __pci_register_driver(struct pci_driver *drv, 1663 struct module *owner) 1664 { return 0; } 1665 static inline int pci_register_driver(struct pci_driver *drv) 1666 { return 0; } 1667 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1668 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1669 { return 0; } 1670 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1671 int cap) 1672 { return 0; } 1673 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1674 { return 0; } 1675 1676 /* Power management related routines */ 1677 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1678 static inline void pci_restore_state(struct pci_dev *dev) { } 1679 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1680 { return 0; } 1681 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1682 { return 0; } 1683 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1684 pm_message_t state) 1685 { return PCI_D0; } 1686 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1687 int enable) 1688 { return 0; } 1689 1690 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1691 struct resource *res) 1692 { return NULL; } 1693 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1694 { return -EIO; } 1695 static inline void pci_release_regions(struct pci_dev *dev) { } 1696 1697 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1698 1699 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1700 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1701 { return 0; } 1702 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1703 1704 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1705 { return NULL; } 1706 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1707 unsigned int devfn) 1708 { return NULL; } 1709 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1710 unsigned int bus, unsigned int devfn) 1711 { return NULL; } 1712 1713 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1714 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1715 1716 #define dev_is_pci(d) (false) 1717 #define dev_is_pf(d) (false) 1718 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1719 { return false; } 1720 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1721 struct device_node *node, 1722 const u32 *intspec, 1723 unsigned int intsize, 1724 unsigned long *out_hwirq, 1725 unsigned int *out_type) 1726 { return -EINVAL; } 1727 1728 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1729 struct pci_dev *dev) 1730 { return NULL; } 1731 #endif /* CONFIG_PCI */ 1732 1733 /* Include architecture-dependent settings and functions */ 1734 1735 #include <asm/pci.h> 1736 1737 /* These two functions provide almost identical functionality. Depennding 1738 * on the architecture, one will be implemented as a wrapper around the 1739 * other (in drivers/pci/mmap.c). 1740 * 1741 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1742 * is expected to be an offset within that region. 1743 * 1744 * pci_mmap_page_range() is the legacy architecture-specific interface, 1745 * which accepts a "user visible" resource address converted by 1746 * pci_resource_to_user(), as used in the legacy mmap() interface in 1747 * /proc/bus/pci/. 1748 */ 1749 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1750 struct vm_area_struct *vma, 1751 enum pci_mmap_state mmap_state, int write_combine); 1752 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1753 struct vm_area_struct *vma, 1754 enum pci_mmap_state mmap_state, int write_combine); 1755 1756 #ifndef arch_can_pci_mmap_wc 1757 #define arch_can_pci_mmap_wc() 0 1758 #endif 1759 1760 #ifndef arch_can_pci_mmap_io 1761 #define arch_can_pci_mmap_io() 0 1762 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1763 #else 1764 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1765 #endif 1766 1767 #ifndef pci_root_bus_fwnode 1768 #define pci_root_bus_fwnode(bus) NULL 1769 #endif 1770 1771 /* 1772 * These helpers provide future and backwards compatibility 1773 * for accessing popular PCI BAR info 1774 */ 1775 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1776 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1777 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1778 #define pci_resource_len(dev,bar) \ 1779 ((pci_resource_start((dev), (bar)) == 0 && \ 1780 pci_resource_end((dev), (bar)) == \ 1781 pci_resource_start((dev), (bar))) ? 0 : \ 1782 \ 1783 (pci_resource_end((dev), (bar)) - \ 1784 pci_resource_start((dev), (bar)) + 1)) 1785 1786 /* 1787 * Similar to the helpers above, these manipulate per-pci_dev 1788 * driver-specific data. They are really just a wrapper around 1789 * the generic device structure functions of these calls. 1790 */ 1791 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1792 { 1793 return dev_get_drvdata(&pdev->dev); 1794 } 1795 1796 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1797 { 1798 dev_set_drvdata(&pdev->dev, data); 1799 } 1800 1801 static inline const char *pci_name(const struct pci_dev *pdev) 1802 { 1803 return dev_name(&pdev->dev); 1804 } 1805 1806 1807 /* 1808 * Some archs don't want to expose struct resource to userland as-is 1809 * in sysfs and /proc 1810 */ 1811 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1812 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1813 const struct resource *rsrc, 1814 resource_size_t *start, resource_size_t *end); 1815 #else 1816 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1817 const struct resource *rsrc, resource_size_t *start, 1818 resource_size_t *end) 1819 { 1820 *start = rsrc->start; 1821 *end = rsrc->end; 1822 } 1823 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1824 1825 1826 /* 1827 * The world is not perfect and supplies us with broken PCI devices. 1828 * For at least a part of these bugs we need a work-around, so both 1829 * generic (drivers/pci/quirks.c) and per-architecture code can define 1830 * fixup hooks to be called for particular buggy devices. 1831 */ 1832 1833 struct pci_fixup { 1834 u16 vendor; /* Or PCI_ANY_ID */ 1835 u16 device; /* Or PCI_ANY_ID */ 1836 u32 class; /* Or PCI_ANY_ID */ 1837 unsigned int class_shift; /* should be 0, 8, 16 */ 1838 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1839 int hook_offset; 1840 #else 1841 void (*hook)(struct pci_dev *dev); 1842 #endif 1843 }; 1844 1845 enum pci_fixup_pass { 1846 pci_fixup_early, /* Before probing BARs */ 1847 pci_fixup_header, /* After reading configuration header */ 1848 pci_fixup_final, /* Final phase of device fixups */ 1849 pci_fixup_enable, /* pci_enable_device() time */ 1850 pci_fixup_resume, /* pci_device_resume() */ 1851 pci_fixup_suspend, /* pci_device_suspend() */ 1852 pci_fixup_resume_early, /* pci_device_resume_early() */ 1853 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1854 }; 1855 1856 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1857 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1858 class_shift, hook) \ 1859 __ADDRESSABLE(hook) \ 1860 asm(".section " #sec ", \"a\" \n" \ 1861 ".balign 16 \n" \ 1862 ".short " #vendor ", " #device " \n" \ 1863 ".long " #class ", " #class_shift " \n" \ 1864 ".long " #hook " - . \n" \ 1865 ".previous \n"); 1866 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1867 class_shift, hook) \ 1868 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1869 class_shift, hook) 1870 #else 1871 /* Anonymous variables would be nice... */ 1872 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1873 class_shift, hook) \ 1874 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1875 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1876 = { vendor, device, class, class_shift, hook }; 1877 #endif 1878 1879 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1880 class_shift, hook) \ 1881 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1882 hook, vendor, device, class, class_shift, hook) 1883 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1884 class_shift, hook) \ 1885 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1886 hook, vendor, device, class, class_shift, hook) 1887 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1888 class_shift, hook) \ 1889 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1890 hook, vendor, device, class, class_shift, hook) 1891 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1892 class_shift, hook) \ 1893 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1894 hook, vendor, device, class, class_shift, hook) 1895 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1896 class_shift, hook) \ 1897 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1898 resume##hook, vendor, device, class, class_shift, hook) 1899 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1900 class_shift, hook) \ 1901 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1902 resume_early##hook, vendor, device, class, class_shift, hook) 1903 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1904 class_shift, hook) \ 1905 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1906 suspend##hook, vendor, device, class, class_shift, hook) 1907 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1908 class_shift, hook) \ 1909 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1910 suspend_late##hook, vendor, device, class, class_shift, hook) 1911 1912 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1913 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1914 hook, vendor, device, PCI_ANY_ID, 0, hook) 1915 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1916 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1917 hook, vendor, device, PCI_ANY_ID, 0, hook) 1918 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1919 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1920 hook, vendor, device, PCI_ANY_ID, 0, hook) 1921 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1922 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1923 hook, vendor, device, PCI_ANY_ID, 0, hook) 1924 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1925 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1926 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1927 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1928 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1929 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1930 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1931 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1932 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1933 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1934 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1935 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1936 1937 #ifdef CONFIG_PCI_QUIRKS 1938 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1939 #else 1940 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1941 struct pci_dev *dev) { } 1942 #endif 1943 1944 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1945 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1946 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1947 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1948 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1949 const char *name); 1950 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1951 1952 extern int pci_pci_problems; 1953 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1954 #define PCIPCI_TRITON 2 1955 #define PCIPCI_NATOMA 4 1956 #define PCIPCI_VIAETBF 8 1957 #define PCIPCI_VSFX 16 1958 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1959 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1960 1961 extern unsigned long pci_cardbus_io_size; 1962 extern unsigned long pci_cardbus_mem_size; 1963 extern u8 pci_dfl_cache_line_size; 1964 extern u8 pci_cache_line_size; 1965 1966 extern unsigned long pci_hotplug_io_size; 1967 extern unsigned long pci_hotplug_mem_size; 1968 extern unsigned long pci_hotplug_bus_size; 1969 1970 /* Architecture-specific versions may override these (weak) */ 1971 void pcibios_disable_device(struct pci_dev *dev); 1972 void pcibios_set_master(struct pci_dev *dev); 1973 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1974 enum pcie_reset_state state); 1975 int pcibios_add_device(struct pci_dev *dev); 1976 void pcibios_release_device(struct pci_dev *dev); 1977 #ifdef CONFIG_PCI 1978 void pcibios_penalize_isa_irq(int irq, int active); 1979 #else 1980 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 1981 #endif 1982 int pcibios_alloc_irq(struct pci_dev *dev); 1983 void pcibios_free_irq(struct pci_dev *dev); 1984 resource_size_t pcibios_default_alignment(void); 1985 1986 #ifdef CONFIG_HIBERNATE_CALLBACKS 1987 extern struct dev_pm_ops pcibios_pm_ops; 1988 #endif 1989 1990 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1991 void __init pci_mmcfg_early_init(void); 1992 void __init pci_mmcfg_late_init(void); 1993 #else 1994 static inline void pci_mmcfg_early_init(void) { } 1995 static inline void pci_mmcfg_late_init(void) { } 1996 #endif 1997 1998 int pci_ext_cfg_avail(void); 1999 2000 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2001 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2002 2003 #ifdef CONFIG_PCI_IOV 2004 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2005 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2006 2007 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2008 void pci_disable_sriov(struct pci_dev *dev); 2009 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2010 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2011 int pci_num_vf(struct pci_dev *dev); 2012 int pci_vfs_assigned(struct pci_dev *dev); 2013 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2014 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2015 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2016 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2017 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2018 2019 /* Arch may override these (weak) */ 2020 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2021 int pcibios_sriov_disable(struct pci_dev *pdev); 2022 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2023 #else 2024 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2025 { 2026 return -ENOSYS; 2027 } 2028 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2029 { 2030 return -ENOSYS; 2031 } 2032 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2033 { return -ENODEV; } 2034 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2035 { 2036 return -ENOSYS; 2037 } 2038 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2039 int id) { } 2040 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2041 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2042 static inline int pci_vfs_assigned(struct pci_dev *dev) 2043 { return 0; } 2044 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2045 { return 0; } 2046 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2047 { return 0; } 2048 #define pci_sriov_configure_simple NULL 2049 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2050 { return 0; } 2051 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2052 #endif 2053 2054 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2055 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2056 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2057 #endif 2058 2059 /** 2060 * pci_pcie_cap - get the saved PCIe capability offset 2061 * @dev: PCI device 2062 * 2063 * PCIe capability offset is calculated at PCI device initialization 2064 * time and saved in the data structure. This function returns saved 2065 * PCIe capability offset. Using this instead of pci_find_capability() 2066 * reduces unnecessary search in the PCI configuration space. If you 2067 * need to calculate PCIe capability offset from raw device for some 2068 * reasons, please use pci_find_capability() instead. 2069 */ 2070 static inline int pci_pcie_cap(struct pci_dev *dev) 2071 { 2072 return dev->pcie_cap; 2073 } 2074 2075 /** 2076 * pci_is_pcie - check if the PCI device is PCI Express capable 2077 * @dev: PCI device 2078 * 2079 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2080 */ 2081 static inline bool pci_is_pcie(struct pci_dev *dev) 2082 { 2083 return pci_pcie_cap(dev); 2084 } 2085 2086 /** 2087 * pcie_caps_reg - get the PCIe Capabilities Register 2088 * @dev: PCI device 2089 */ 2090 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2091 { 2092 return dev->pcie_flags_reg; 2093 } 2094 2095 /** 2096 * pci_pcie_type - get the PCIe device/port type 2097 * @dev: PCI device 2098 */ 2099 static inline int pci_pcie_type(const struct pci_dev *dev) 2100 { 2101 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2102 } 2103 2104 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2105 { 2106 while (1) { 2107 if (!pci_is_pcie(dev)) 2108 break; 2109 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2110 return dev; 2111 if (!dev->bus->self) 2112 break; 2113 dev = dev->bus->self; 2114 } 2115 return NULL; 2116 } 2117 2118 void pci_request_acs(void); 2119 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2120 bool pci_acs_path_enabled(struct pci_dev *start, 2121 struct pci_dev *end, u16 acs_flags); 2122 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2123 2124 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2125 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2126 2127 /* Large Resource Data Type Tag Item Names */ 2128 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2129 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2130 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2131 2132 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2133 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2134 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2135 2136 /* Small Resource Data Type Tag Item Names */ 2137 #define PCI_VPD_STIN_END 0x0f /* End */ 2138 2139 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2140 2141 #define PCI_VPD_SRDT_TIN_MASK 0x78 2142 #define PCI_VPD_SRDT_LEN_MASK 0x07 2143 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2144 2145 #define PCI_VPD_LRDT_TAG_SIZE 3 2146 #define PCI_VPD_SRDT_TAG_SIZE 1 2147 2148 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2149 2150 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2151 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2152 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2153 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2154 2155 /** 2156 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2157 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2158 * 2159 * Returns the extracted Large Resource Data Type length. 2160 */ 2161 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2162 { 2163 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2164 } 2165 2166 /** 2167 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2168 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2169 * 2170 * Returns the extracted Large Resource Data Type Tag item. 2171 */ 2172 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2173 { 2174 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2175 } 2176 2177 /** 2178 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2179 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2180 * 2181 * Returns the extracted Small Resource Data Type length. 2182 */ 2183 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2184 { 2185 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2186 } 2187 2188 /** 2189 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2190 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2191 * 2192 * Returns the extracted Small Resource Data Type Tag Item. 2193 */ 2194 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2195 { 2196 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2197 } 2198 2199 /** 2200 * pci_vpd_info_field_size - Extracts the information field length 2201 * @lrdt: Pointer to the beginning of an information field header 2202 * 2203 * Returns the extracted information field length. 2204 */ 2205 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2206 { 2207 return info_field[2]; 2208 } 2209 2210 /** 2211 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2212 * @buf: Pointer to buffered vpd data 2213 * @off: The offset into the buffer at which to begin the search 2214 * @len: The length of the vpd buffer 2215 * @rdt: The Resource Data Type to search for 2216 * 2217 * Returns the index where the Resource Data Type was found or 2218 * -ENOENT otherwise. 2219 */ 2220 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2221 2222 /** 2223 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2224 * @buf: Pointer to buffered vpd data 2225 * @off: The offset into the buffer at which to begin the search 2226 * @len: The length of the buffer area, relative to off, in which to search 2227 * @kw: The keyword to search for 2228 * 2229 * Returns the index where the information field keyword was found or 2230 * -ENOENT otherwise. 2231 */ 2232 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2233 unsigned int len, const char *kw); 2234 2235 /* PCI <-> OF binding helpers */ 2236 #ifdef CONFIG_OF 2237 struct device_node; 2238 struct irq_domain; 2239 void pci_set_of_node(struct pci_dev *dev); 2240 void pci_release_of_node(struct pci_dev *dev); 2241 void pci_set_bus_of_node(struct pci_bus *bus); 2242 void pci_release_bus_of_node(struct pci_bus *bus); 2243 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2244 int pci_parse_request_of_pci_ranges(struct device *dev, 2245 struct list_head *resources, 2246 struct resource **bus_range); 2247 2248 /* Arch may override this (weak) */ 2249 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2250 2251 #else /* CONFIG_OF */ 2252 static inline void pci_set_of_node(struct pci_dev *dev) { } 2253 static inline void pci_release_of_node(struct pci_dev *dev) { } 2254 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2255 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2256 static inline struct irq_domain * 2257 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2258 static inline int pci_parse_request_of_pci_ranges(struct device *dev, 2259 struct list_head *resources, 2260 struct resource **bus_range) 2261 { 2262 return -EINVAL; 2263 } 2264 #endif /* CONFIG_OF */ 2265 2266 static inline struct device_node * 2267 pci_device_to_OF_node(const struct pci_dev *pdev) 2268 { 2269 return pdev ? pdev->dev.of_node : NULL; 2270 } 2271 2272 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2273 { 2274 return bus ? bus->dev.of_node : NULL; 2275 } 2276 2277 #ifdef CONFIG_ACPI 2278 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2279 2280 void 2281 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2282 #else 2283 static inline struct irq_domain * 2284 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2285 #endif 2286 2287 #ifdef CONFIG_EEH 2288 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2289 { 2290 return pdev->dev.archdata.edev; 2291 } 2292 #endif 2293 2294 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2295 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2296 int pci_for_each_dma_alias(struct pci_dev *pdev, 2297 int (*fn)(struct pci_dev *pdev, 2298 u16 alias, void *data), void *data); 2299 2300 /* Helper functions for operation of device flag */ 2301 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2302 { 2303 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2304 } 2305 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2306 { 2307 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2308 } 2309 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2310 { 2311 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2312 } 2313 2314 /** 2315 * pci_ari_enabled - query ARI forwarding status 2316 * @bus: the PCI bus 2317 * 2318 * Returns true if ARI forwarding is enabled. 2319 */ 2320 static inline bool pci_ari_enabled(struct pci_bus *bus) 2321 { 2322 return bus->self && bus->self->ari_enabled; 2323 } 2324 2325 /** 2326 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2327 * @pdev: PCI device to check 2328 * 2329 * Walk upwards from @pdev and check for each encountered bridge if it's part 2330 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2331 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2332 */ 2333 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2334 { 2335 struct pci_dev *parent = pdev; 2336 2337 if (pdev->is_thunderbolt) 2338 return true; 2339 2340 while ((parent = pci_upstream_bridge(parent))) 2341 if (parent->is_thunderbolt) 2342 return true; 2343 2344 return false; 2345 } 2346 2347 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2348 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2349 #endif 2350 2351 /* Provide the legacy pci_dma_* API */ 2352 #include <linux/pci-dma-compat.h> 2353 2354 #define pci_printk(level, pdev, fmt, arg...) \ 2355 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2356 2357 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2358 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2359 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2360 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2361 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2362 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2363 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2364 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2365 2366 #endif /* LINUX_PCI_H */ 2367