1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * For more information, please consult the following manuals (look at 10 * http://www.pcisig.com/ for how to get them): 11 * 12 * PCI BIOS Specification 13 * PCI Local Bus Specification 14 * PCI to PCI Bridge Specification 15 * PCI System Design Guide 16 */ 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 21 #include <linux/mod_devicetable.h> 22 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/list.h> 27 #include <linux/compiler.h> 28 #include <linux/errno.h> 29 #include <linux/kobject.h> 30 #include <linux/atomic.h> 31 #include <linux/device.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/resource_ext.h> 35 #include <uapi/linux/pci.h> 36 37 #include <linux/pci_ids.h> 38 39 /* 40 * The PCI interface treats multi-function devices as independent 41 * devices. The slot/function address of each device is encoded 42 * in a single byte as follows: 43 * 44 * 7:3 = slot 45 * 2:0 = function 46 * 47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 48 * In the interest of not exposing interfaces to user-space unnecessarily, 49 * the following kernel-only defines are being added here. 50 */ 51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 54 55 /* pci_slot represents a physical slot */ 56 struct pci_slot { 57 struct pci_bus *bus; /* Bus this slot is on */ 58 struct list_head list; /* Node in list of slots */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 61 struct kobject kobj; 62 }; 63 64 static inline const char *pci_slot_name(const struct pci_slot *slot) 65 { 66 return kobject_name(&slot->kobj); 67 } 68 69 /* File state for mmap()s on /proc/bus/pci/X/Y */ 70 enum pci_mmap_state { 71 pci_mmap_io, 72 pci_mmap_mem 73 }; 74 75 /* For PCI devices, the region numbers are assigned this way: */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* Device-specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* Resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* Total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* Preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 /** 105 * enum pci_interrupt_pin - PCI INTx interrupt values 106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 107 * @PCI_INTERRUPT_INTA: PCI INTA pin 108 * @PCI_INTERRUPT_INTB: PCI INTB pin 109 * @PCI_INTERRUPT_INTC: PCI INTC pin 110 * @PCI_INTERRUPT_INTD: PCI INTD pin 111 * 112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 113 * PCI_INTERRUPT_PIN register. 114 */ 115 enum pci_interrupt_pin { 116 PCI_INTERRUPT_UNKNOWN, 117 PCI_INTERRUPT_INTA, 118 PCI_INTERRUPT_INTB, 119 PCI_INTERRUPT_INTC, 120 PCI_INTERRUPT_INTD, 121 }; 122 123 /* The number of legacy PCI INTx interrupts */ 124 #define PCI_NUM_INTX 4 125 126 /* 127 * pci_power_t values must match the bits in the Capabilities PME_Support 128 * and Control/Status PowerState fields in the Power Management capability. 129 */ 130 typedef int __bitwise pci_power_t; 131 132 #define PCI_D0 ((pci_power_t __force) 0) 133 #define PCI_D1 ((pci_power_t __force) 1) 134 #define PCI_D2 ((pci_power_t __force) 2) 135 #define PCI_D3hot ((pci_power_t __force) 3) 136 #define PCI_D3cold ((pci_power_t __force) 4) 137 #define PCI_UNKNOWN ((pci_power_t __force) 5) 138 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 139 140 /* Remember to update this when the list above changes! */ 141 extern const char *pci_power_names[]; 142 143 static inline const char *pci_power_name(pci_power_t state) 144 { 145 return pci_power_names[1 + (__force int) state]; 146 } 147 148 #define PCI_PM_D2_DELAY 200 149 #define PCI_PM_D3_WAIT 10 150 #define PCI_PM_D3COLD_WAIT 100 151 #define PCI_PM_BUS_WAIT 50 152 153 /** 154 * The pci_channel state describes connectivity between the CPU and 155 * the PCI device. If some PCI bus between here and the PCI device 156 * has crashed or locked up, this info is reflected here. 157 */ 158 typedef unsigned int __bitwise pci_channel_state_t; 159 160 enum pci_channel_state { 161 /* I/O channel is in normal state */ 162 pci_channel_io_normal = (__force pci_channel_state_t) 1, 163 164 /* I/O to channel is blocked */ 165 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 166 167 /* PCI card is dead */ 168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 169 }; 170 171 typedef unsigned int __bitwise pcie_reset_state_t; 172 173 enum pcie_reset_state { 174 /* Reset is NOT asserted (Use to deassert reset) */ 175 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 176 177 /* Use #PERST to reset PCIe device */ 178 pcie_warm_reset = (__force pcie_reset_state_t) 2, 179 180 /* Use PCIe Hot Reset to reset device */ 181 pcie_hot_reset = (__force pcie_reset_state_t) 3 182 }; 183 184 typedef unsigned short __bitwise pci_dev_flags_t; 185 enum pci_dev_flags { 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 188 /* Device configuration is irrevocably lost if disabled into D3 */ 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 190 /* Provide indication device is assigned by a Virtual Machine Manager */ 191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 192 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 196 /* Do not use bus resets for device */ 197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 198 /* Do not use PM reset even if device advertises NoSoftRst- */ 199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 200 /* Get VPD from function 0 VPD */ 201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 202 /* A non-root bridge where translation occurs, stop alias search here */ 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 204 /* Do not use FLR even if device advertises PCI_AF_CAP */ 205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 206 /* Don't use Relaxed Ordering for TLPs directed at this device */ 207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 208 }; 209 210 enum pci_irq_reroute_variant { 211 INTEL_IRQ_REROUTE_VARIANT = 1, 212 MAX_IRQ_REROUTE_VARIANTS = 3 213 }; 214 215 typedef unsigned short __bitwise pci_bus_flags_t; 216 enum pci_bus_flags { 217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 221 }; 222 223 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 224 enum pcie_link_width { 225 PCIE_LNK_WIDTH_RESRV = 0x00, 226 PCIE_LNK_X1 = 0x01, 227 PCIE_LNK_X2 = 0x02, 228 PCIE_LNK_X4 = 0x04, 229 PCIE_LNK_X8 = 0x08, 230 PCIE_LNK_X12 = 0x0c, 231 PCIE_LNK_X16 = 0x10, 232 PCIE_LNK_X32 = 0x20, 233 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 234 }; 235 236 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 237 enum pci_bus_speed { 238 PCI_SPEED_33MHz = 0x00, 239 PCI_SPEED_66MHz = 0x01, 240 PCI_SPEED_66MHz_PCIX = 0x02, 241 PCI_SPEED_100MHz_PCIX = 0x03, 242 PCI_SPEED_133MHz_PCIX = 0x04, 243 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 244 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 245 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 246 PCI_SPEED_66MHz_PCIX_266 = 0x09, 247 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 248 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 249 AGP_UNKNOWN = 0x0c, 250 AGP_1X = 0x0d, 251 AGP_2X = 0x0e, 252 AGP_4X = 0x0f, 253 AGP_8X = 0x10, 254 PCI_SPEED_66MHz_PCIX_533 = 0x11, 255 PCI_SPEED_100MHz_PCIX_533 = 0x12, 256 PCI_SPEED_133MHz_PCIX_533 = 0x13, 257 PCIE_SPEED_2_5GT = 0x14, 258 PCIE_SPEED_5_0GT = 0x15, 259 PCIE_SPEED_8_0GT = 0x16, 260 PCIE_SPEED_16_0GT = 0x17, 261 PCI_SPEED_UNKNOWN = 0xff, 262 }; 263 264 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 265 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 266 267 struct pci_cap_saved_data { 268 u16 cap_nr; 269 bool cap_extended; 270 unsigned int size; 271 u32 data[0]; 272 }; 273 274 struct pci_cap_saved_state { 275 struct hlist_node next; 276 struct pci_cap_saved_data cap; 277 }; 278 279 struct irq_affinity; 280 struct pcie_link_state; 281 struct pci_vpd; 282 struct pci_sriov; 283 struct pci_ats; 284 struct pci_p2pdma; 285 286 /* The pci_dev structure describes PCI devices */ 287 struct pci_dev { 288 struct list_head bus_list; /* Node in per-bus list */ 289 struct pci_bus *bus; /* Bus this device is on */ 290 struct pci_bus *subordinate; /* Bus this device bridges to */ 291 292 void *sysdata; /* Hook for sys-specific extension */ 293 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 294 struct pci_slot *slot; /* Physical slot this device is in */ 295 296 unsigned int devfn; /* Encoded device & function index */ 297 unsigned short vendor; 298 unsigned short device; 299 unsigned short subsystem_vendor; 300 unsigned short subsystem_device; 301 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 302 u8 revision; /* PCI revision, low byte of class word */ 303 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 304 #ifdef CONFIG_PCIEAER 305 u16 aer_cap; /* AER capability offset */ 306 struct aer_stats *aer_stats; /* AER stats for this device */ 307 #endif 308 u8 pcie_cap; /* PCIe capability offset */ 309 u8 msi_cap; /* MSI capability offset */ 310 u8 msix_cap; /* MSI-X capability offset */ 311 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 312 u8 rom_base_reg; /* Config register controlling ROM */ 313 u8 pin; /* Interrupt pin this device uses */ 314 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 315 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 316 317 struct pci_driver *driver; /* Driver bound to this device */ 318 u64 dma_mask; /* Mask of the bits of bus address this 319 device implements. Normally this is 320 0xffffffff. You only need to change 321 this if your device has broken DMA 322 or supports 64-bit transfers. */ 323 324 struct device_dma_parameters dma_parms; 325 326 pci_power_t current_state; /* Current operating state. In ACPI, 327 this is D0-D3, D0 being fully 328 functional, and D3 being off. */ 329 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 330 u8 pm_cap; /* PM capability offset */ 331 unsigned int pme_support:5; /* Bitmask of states from which PME# 332 can be generated */ 333 unsigned int pme_poll:1; /* Poll device's PME status bit */ 334 unsigned int d1_support:1; /* Low power state D1 is supported */ 335 unsigned int d2_support:1; /* Low power state D2 is supported */ 336 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 337 unsigned int no_d3cold:1; /* D3cold is forbidden */ 338 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 339 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 340 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 341 decoding during BAR sizing */ 342 unsigned int wakeup_prepared:1; 343 unsigned int runtime_d3cold:1; /* Whether go through runtime 344 D3cold, not set for devices 345 powered on/off by the 346 corresponding bridge */ 347 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 348 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 349 controlled exclusively by 350 user sysfs */ 351 unsigned int d3_delay; /* D3->D0 transition time in ms */ 352 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 353 354 #ifdef CONFIG_PCIEASPM 355 struct pcie_link_state *link_state; /* ASPM link state */ 356 unsigned int ltr_path:1; /* Latency Tolerance Reporting 357 supported from root to here */ 358 #endif 359 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 360 361 pci_channel_state_t error_state; /* Current connectivity state */ 362 struct device dev; /* Generic device interface */ 363 364 int cfg_size; /* Size of config space */ 365 366 /* 367 * Instead of touching interrupt line and base address registers 368 * directly, use the values stored here. They might be different! 369 */ 370 unsigned int irq; 371 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 372 373 bool match_driver; /* Skip attaching driver */ 374 375 unsigned int transparent:1; /* Subtractive decode bridge */ 376 unsigned int multifunction:1; /* Multi-function device */ 377 378 unsigned int is_busmaster:1; /* Is busmaster */ 379 unsigned int no_msi:1; /* May not use MSI */ 380 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 381 unsigned int block_cfg_access:1; /* Config space access blocked */ 382 unsigned int broken_parity_status:1; /* Generates false positive parity */ 383 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 384 unsigned int msi_enabled:1; 385 unsigned int msix_enabled:1; 386 unsigned int ari_enabled:1; /* ARI forwarding */ 387 unsigned int ats_enabled:1; /* Address Translation Svc */ 388 unsigned int pasid_enabled:1; /* Process Address Space ID */ 389 unsigned int pri_enabled:1; /* Page Request Interface */ 390 unsigned int is_managed:1; 391 unsigned int needs_freset:1; /* Requires fundamental reset */ 392 unsigned int state_saved:1; 393 unsigned int is_physfn:1; 394 unsigned int is_virtfn:1; 395 unsigned int reset_fn:1; 396 unsigned int is_hotplug_bridge:1; 397 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 398 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 399 /* 400 * Devices marked being untrusted are the ones that can potentially 401 * execute DMA attacks and similar. They are typically connected 402 * through external ports such as Thunderbolt but not limited to 403 * that. When an IOMMU is enabled they should be getting full 404 * mappings to make sure they cannot access arbitrary memory. 405 */ 406 unsigned int untrusted:1; 407 unsigned int __aer_firmware_first_valid:1; 408 unsigned int __aer_firmware_first:1; 409 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 410 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 411 unsigned int irq_managed:1; 412 unsigned int has_secondary_link:1; 413 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 414 unsigned int is_probed:1; /* Device probing in progress */ 415 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 416 pci_dev_flags_t dev_flags; 417 atomic_t enable_cnt; /* pci_enable_device has been called */ 418 419 u32 saved_config_space[16]; /* Config space saved at suspend time */ 420 struct hlist_head saved_cap_space; 421 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 422 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 423 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 424 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 425 426 #ifdef CONFIG_HOTPLUG_PCI_PCIE 427 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 428 #endif 429 #ifdef CONFIG_PCIE_PTM 430 unsigned int ptm_root:1; 431 unsigned int ptm_enabled:1; 432 u8 ptm_granularity; 433 #endif 434 #ifdef CONFIG_PCI_MSI 435 const struct attribute_group **msi_irq_groups; 436 #endif 437 struct pci_vpd *vpd; 438 #ifdef CONFIG_PCI_ATS 439 union { 440 struct pci_sriov *sriov; /* PF: SR-IOV info */ 441 struct pci_dev *physfn; /* VF: related PF */ 442 }; 443 u16 ats_cap; /* ATS Capability offset */ 444 u8 ats_stu; /* ATS Smallest Translation Unit */ 445 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ 446 #endif 447 #ifdef CONFIG_PCI_PRI 448 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 449 #endif 450 #ifdef CONFIG_PCI_PASID 451 u16 pasid_features; 452 #endif 453 #ifdef CONFIG_PCI_P2PDMA 454 struct pci_p2pdma *p2pdma; 455 #endif 456 phys_addr_t rom; /* Physical address if not from BAR */ 457 size_t romlen; /* Length if not from BAR */ 458 char *driver_override; /* Driver name to force a match */ 459 460 unsigned long priv_flags; /* Private flags for the PCI driver */ 461 }; 462 463 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 464 { 465 #ifdef CONFIG_PCI_IOV 466 if (dev->is_virtfn) 467 dev = dev->physfn; 468 #endif 469 return dev; 470 } 471 472 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 473 474 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 475 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 476 477 static inline int pci_channel_offline(struct pci_dev *pdev) 478 { 479 return (pdev->error_state != pci_channel_io_normal); 480 } 481 482 struct pci_host_bridge { 483 struct device dev; 484 struct pci_bus *bus; /* Root bus */ 485 struct pci_ops *ops; 486 void *sysdata; 487 int busnr; 488 struct list_head windows; /* resource_entry */ 489 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 490 int (*map_irq)(const struct pci_dev *, u8, u8); 491 void (*release_fn)(struct pci_host_bridge *); 492 void *release_data; 493 struct msi_controller *msi; 494 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 495 unsigned int no_ext_tags:1; /* No Extended Tags */ 496 unsigned int native_aer:1; /* OS may use PCIe AER */ 497 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 498 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 499 unsigned int native_pme:1; /* OS may use PCIe PME */ 500 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 501 /* Resource alignment requirements */ 502 resource_size_t (*align_resource)(struct pci_dev *dev, 503 const struct resource *res, 504 resource_size_t start, 505 resource_size_t size, 506 resource_size_t align); 507 unsigned long private[0] ____cacheline_aligned; 508 }; 509 510 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 511 512 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 513 { 514 return (void *)bridge->private; 515 } 516 517 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 518 { 519 return container_of(priv, struct pci_host_bridge, private); 520 } 521 522 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 523 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 524 size_t priv); 525 void pci_free_host_bridge(struct pci_host_bridge *bridge); 526 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 527 528 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 529 void (*release_fn)(struct pci_host_bridge *), 530 void *release_data); 531 532 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 533 534 /* 535 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 536 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 537 * buses below host bridges or subtractive decode bridges) go in the list. 538 * Use pci_bus_for_each_resource() to iterate through all the resources. 539 */ 540 541 /* 542 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 543 * and there's no way to program the bridge with the details of the window. 544 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 545 * decode bit set, because they are explicit and can be programmed with _SRS. 546 */ 547 #define PCI_SUBTRACTIVE_DECODE 0x1 548 549 struct pci_bus_resource { 550 struct list_head list; 551 struct resource *res; 552 unsigned int flags; 553 }; 554 555 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 556 557 struct pci_bus { 558 struct list_head node; /* Node in list of buses */ 559 struct pci_bus *parent; /* Parent bus this bridge is on */ 560 struct list_head children; /* List of child buses */ 561 struct list_head devices; /* List of devices on this bus */ 562 struct pci_dev *self; /* Bridge device as seen by parent */ 563 struct list_head slots; /* List of slots on this bus; 564 protected by pci_slot_mutex */ 565 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 566 struct list_head resources; /* Address space routed to this bus */ 567 struct resource busn_res; /* Bus numbers routed to this bus */ 568 569 struct pci_ops *ops; /* Configuration access functions */ 570 struct msi_controller *msi; /* MSI controller */ 571 void *sysdata; /* Hook for sys-specific extension */ 572 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 573 574 unsigned char number; /* Bus number */ 575 unsigned char primary; /* Number of primary bridge */ 576 unsigned char max_bus_speed; /* enum pci_bus_speed */ 577 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 578 #ifdef CONFIG_PCI_DOMAINS_GENERIC 579 int domain_nr; 580 #endif 581 582 char name[48]; 583 584 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 585 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 586 struct device *bridge; 587 struct device dev; 588 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 589 struct bin_attribute *legacy_mem; /* Legacy mem */ 590 unsigned int is_added:1; 591 }; 592 593 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 594 595 /* 596 * Returns true if the PCI bus is root (behind host-PCI bridge), 597 * false otherwise 598 * 599 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 600 * This is incorrect because "virtual" buses added for SR-IOV (via 601 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 602 */ 603 static inline bool pci_is_root_bus(struct pci_bus *pbus) 604 { 605 return !(pbus->parent); 606 } 607 608 /** 609 * pci_is_bridge - check if the PCI device is a bridge 610 * @dev: PCI device 611 * 612 * Return true if the PCI device is bridge whether it has subordinate 613 * or not. 614 */ 615 static inline bool pci_is_bridge(struct pci_dev *dev) 616 { 617 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 618 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 619 } 620 621 #define for_each_pci_bridge(dev, bus) \ 622 list_for_each_entry(dev, &bus->devices, bus_list) \ 623 if (!pci_is_bridge(dev)) {} else 624 625 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 626 { 627 dev = pci_physfn(dev); 628 if (pci_is_root_bus(dev->bus)) 629 return NULL; 630 631 return dev->bus->self; 632 } 633 634 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 635 void pci_put_host_bridge_device(struct device *dev); 636 637 #ifdef CONFIG_PCI_MSI 638 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 639 { 640 return pci_dev->msi_enabled || pci_dev->msix_enabled; 641 } 642 #else 643 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 644 #endif 645 646 /* Error values that may be returned by PCI functions */ 647 #define PCIBIOS_SUCCESSFUL 0x00 648 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 649 #define PCIBIOS_BAD_VENDOR_ID 0x83 650 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 651 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 652 #define PCIBIOS_SET_FAILED 0x88 653 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 654 655 /* Translate above to generic errno for passing back through non-PCI code */ 656 static inline int pcibios_err_to_errno(int err) 657 { 658 if (err <= PCIBIOS_SUCCESSFUL) 659 return err; /* Assume already errno */ 660 661 switch (err) { 662 case PCIBIOS_FUNC_NOT_SUPPORTED: 663 return -ENOENT; 664 case PCIBIOS_BAD_VENDOR_ID: 665 return -ENOTTY; 666 case PCIBIOS_DEVICE_NOT_FOUND: 667 return -ENODEV; 668 case PCIBIOS_BAD_REGISTER_NUMBER: 669 return -EFAULT; 670 case PCIBIOS_SET_FAILED: 671 return -EIO; 672 case PCIBIOS_BUFFER_TOO_SMALL: 673 return -ENOSPC; 674 } 675 676 return -ERANGE; 677 } 678 679 /* Low-level architecture-dependent routines */ 680 681 struct pci_ops { 682 int (*add_bus)(struct pci_bus *bus); 683 void (*remove_bus)(struct pci_bus *bus); 684 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 685 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 686 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 687 }; 688 689 /* 690 * ACPI needs to be able to access PCI config space before we've done a 691 * PCI bus scan and created pci_bus structures. 692 */ 693 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 694 int reg, int len, u32 *val); 695 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 696 int reg, int len, u32 val); 697 698 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 699 typedef u64 pci_bus_addr_t; 700 #else 701 typedef u32 pci_bus_addr_t; 702 #endif 703 704 struct pci_bus_region { 705 pci_bus_addr_t start; 706 pci_bus_addr_t end; 707 }; 708 709 struct pci_dynids { 710 spinlock_t lock; /* Protects list, index */ 711 struct list_head list; /* For IDs added at runtime */ 712 }; 713 714 715 /* 716 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 717 * a set of callbacks in struct pci_error_handlers, that device driver 718 * will be notified of PCI bus errors, and will be driven to recovery 719 * when an error occurs. 720 */ 721 722 typedef unsigned int __bitwise pci_ers_result_t; 723 724 enum pci_ers_result { 725 /* No result/none/not supported in device driver */ 726 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 727 728 /* Device driver can recover without slot reset */ 729 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 730 731 /* Device driver wants slot to be reset */ 732 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 733 734 /* Device has completely failed, is unrecoverable */ 735 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 736 737 /* Device driver is fully recovered and operational */ 738 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 739 740 /* No AER capabilities registered for the driver */ 741 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 742 }; 743 744 /* PCI bus error event callbacks */ 745 struct pci_error_handlers { 746 /* PCI bus error detected on this device */ 747 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 748 enum pci_channel_state error); 749 750 /* MMIO has been re-enabled, but not DMA */ 751 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 752 753 /* PCI slot has been reset */ 754 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 755 756 /* PCI function reset prepare or completed */ 757 void (*reset_prepare)(struct pci_dev *dev); 758 void (*reset_done)(struct pci_dev *dev); 759 760 /* Device driver may resume normal operations */ 761 void (*resume)(struct pci_dev *dev); 762 }; 763 764 765 struct module; 766 struct pci_driver { 767 struct list_head node; 768 const char *name; 769 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 770 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 771 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 772 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 773 int (*suspend_late)(struct pci_dev *dev, pm_message_t state); 774 int (*resume_early)(struct pci_dev *dev); 775 int (*resume) (struct pci_dev *dev); /* Device woken up */ 776 void (*shutdown) (struct pci_dev *dev); 777 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */ 778 const struct pci_error_handlers *err_handler; 779 const struct attribute_group **groups; 780 struct device_driver driver; 781 struct pci_dynids dynids; 782 }; 783 784 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 785 786 /** 787 * PCI_DEVICE - macro used to describe a specific PCI device 788 * @vend: the 16 bit PCI Vendor ID 789 * @dev: the 16 bit PCI Device ID 790 * 791 * This macro is used to create a struct pci_device_id that matches a 792 * specific device. The subvendor and subdevice fields will be set to 793 * PCI_ANY_ID. 794 */ 795 #define PCI_DEVICE(vend,dev) \ 796 .vendor = (vend), .device = (dev), \ 797 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 798 799 /** 800 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 801 * @vend: the 16 bit PCI Vendor ID 802 * @dev: the 16 bit PCI Device ID 803 * @subvend: the 16 bit PCI Subvendor ID 804 * @subdev: the 16 bit PCI Subdevice ID 805 * 806 * This macro is used to create a struct pci_device_id that matches a 807 * specific device with subsystem information. 808 */ 809 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 810 .vendor = (vend), .device = (dev), \ 811 .subvendor = (subvend), .subdevice = (subdev) 812 813 /** 814 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 815 * @dev_class: the class, subclass, prog-if triple for this device 816 * @dev_class_mask: the class mask for this device 817 * 818 * This macro is used to create a struct pci_device_id that matches a 819 * specific PCI class. The vendor, device, subvendor, and subdevice 820 * fields will be set to PCI_ANY_ID. 821 */ 822 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 823 .class = (dev_class), .class_mask = (dev_class_mask), \ 824 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 825 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 826 827 /** 828 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 829 * @vend: the vendor name 830 * @dev: the 16 bit PCI Device ID 831 * 832 * This macro is used to create a struct pci_device_id that matches a 833 * specific PCI device. The subvendor, and subdevice fields will be set 834 * to PCI_ANY_ID. The macro allows the next field to follow as the device 835 * private data. 836 */ 837 #define PCI_VDEVICE(vend, dev) \ 838 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 839 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 840 841 /** 842 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 843 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 844 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 845 * @data: the driver data to be filled 846 * 847 * This macro is used to create a struct pci_device_id that matches a 848 * specific PCI device. The subvendor, and subdevice fields will be set 849 * to PCI_ANY_ID. 850 */ 851 #define PCI_DEVICE_DATA(vend, dev, data) \ 852 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 853 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 854 .driver_data = (kernel_ulong_t)(data) 855 856 enum { 857 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 858 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 859 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 860 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 861 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 862 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 863 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 864 }; 865 866 /* These external functions are only available when PCI support is enabled */ 867 #ifdef CONFIG_PCI 868 869 extern unsigned int pci_flags; 870 871 static inline void pci_set_flags(int flags) { pci_flags = flags; } 872 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 873 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 874 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 875 876 void pcie_bus_configure_settings(struct pci_bus *bus); 877 878 enum pcie_bus_config_types { 879 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 880 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 881 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 882 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 883 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 884 }; 885 886 extern enum pcie_bus_config_types pcie_bus_config; 887 888 extern struct bus_type pci_bus_type; 889 890 /* Do NOT directly access these two variables, unless you are arch-specific PCI 891 * code, or PCI core code. */ 892 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 893 /* Some device drivers need know if PCI is initiated */ 894 int no_pci_devices(void); 895 896 void pcibios_resource_survey_bus(struct pci_bus *bus); 897 void pcibios_bus_add_device(struct pci_dev *pdev); 898 void pcibios_add_bus(struct pci_bus *bus); 899 void pcibios_remove_bus(struct pci_bus *bus); 900 void pcibios_fixup_bus(struct pci_bus *); 901 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 902 /* Architecture-specific versions may override this (weak) */ 903 char *pcibios_setup(char *str); 904 905 /* Used only when drivers/pci/setup.c is used */ 906 resource_size_t pcibios_align_resource(void *, const struct resource *, 907 resource_size_t, 908 resource_size_t); 909 910 /* Weak but can be overriden by arch */ 911 void pci_fixup_cardbus(struct pci_bus *); 912 913 /* Generic PCI functions used internally */ 914 915 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 916 struct resource *res); 917 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 918 struct pci_bus_region *region); 919 void pcibios_scan_specific_bus(int busn); 920 struct pci_bus *pci_find_bus(int domain, int busnr); 921 void pci_bus_add_devices(const struct pci_bus *bus); 922 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 923 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 924 struct pci_ops *ops, void *sysdata, 925 struct list_head *resources); 926 int pci_host_probe(struct pci_host_bridge *bridge); 927 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 928 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 929 void pci_bus_release_busn_res(struct pci_bus *b); 930 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 931 struct pci_ops *ops, void *sysdata, 932 struct list_head *resources); 933 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 934 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 935 int busnr); 936 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 937 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 938 const char *name, 939 struct hotplug_slot *hotplug); 940 void pci_destroy_slot(struct pci_slot *slot); 941 #ifdef CONFIG_SYSFS 942 void pci_dev_assign_slot(struct pci_dev *dev); 943 #else 944 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 945 #endif 946 int pci_scan_slot(struct pci_bus *bus, int devfn); 947 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 948 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 949 unsigned int pci_scan_child_bus(struct pci_bus *bus); 950 void pci_bus_add_device(struct pci_dev *dev); 951 void pci_read_bridge_bases(struct pci_bus *child); 952 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 953 struct resource *res); 954 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 955 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 956 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 957 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 958 struct pci_dev *pci_dev_get(struct pci_dev *dev); 959 void pci_dev_put(struct pci_dev *dev); 960 void pci_remove_bus(struct pci_bus *b); 961 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 962 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 963 void pci_stop_root_bus(struct pci_bus *bus); 964 void pci_remove_root_bus(struct pci_bus *bus); 965 void pci_setup_cardbus(struct pci_bus *bus); 966 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 967 void pci_sort_breadthfirst(void); 968 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 969 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 970 971 /* Generic PCI functions exported to card drivers */ 972 973 enum pci_lost_interrupt_reason { 974 PCI_LOST_IRQ_NO_INFORMATION = 0, 975 PCI_LOST_IRQ_DISABLE_MSI, 976 PCI_LOST_IRQ_DISABLE_MSIX, 977 PCI_LOST_IRQ_DISABLE_ACPI, 978 }; 979 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 980 int pci_find_capability(struct pci_dev *dev, int cap); 981 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 982 int pci_find_ext_capability(struct pci_dev *dev, int cap); 983 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 984 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 985 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 986 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 987 988 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 989 struct pci_dev *from); 990 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 991 unsigned int ss_vendor, unsigned int ss_device, 992 struct pci_dev *from); 993 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 994 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 995 unsigned int devfn); 996 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 997 int pci_dev_present(const struct pci_device_id *ids); 998 999 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1000 int where, u8 *val); 1001 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1002 int where, u16 *val); 1003 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1004 int where, u32 *val); 1005 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1006 int where, u8 val); 1007 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1008 int where, u16 val); 1009 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1010 int where, u32 val); 1011 1012 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1013 int where, int size, u32 *val); 1014 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1015 int where, int size, u32 val); 1016 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1017 int where, int size, u32 *val); 1018 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1019 int where, int size, u32 val); 1020 1021 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1022 1023 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1024 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1025 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1026 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1027 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1028 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1029 1030 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1031 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1032 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1033 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1034 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1035 u16 clear, u16 set); 1036 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1037 u32 clear, u32 set); 1038 1039 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1040 u16 set) 1041 { 1042 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1043 } 1044 1045 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1046 u32 set) 1047 { 1048 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1049 } 1050 1051 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1052 u16 clear) 1053 { 1054 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1055 } 1056 1057 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1058 u32 clear) 1059 { 1060 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1061 } 1062 1063 /* User-space driven config access */ 1064 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1065 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1066 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1067 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1068 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1069 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1070 1071 int __must_check pci_enable_device(struct pci_dev *dev); 1072 int __must_check pci_enable_device_io(struct pci_dev *dev); 1073 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1074 int __must_check pci_reenable_device(struct pci_dev *); 1075 int __must_check pcim_enable_device(struct pci_dev *pdev); 1076 void pcim_pin_device(struct pci_dev *pdev); 1077 1078 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1079 { 1080 /* 1081 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1082 * writable and no quirk has marked the feature broken. 1083 */ 1084 return !pdev->broken_intx_masking; 1085 } 1086 1087 static inline int pci_is_enabled(struct pci_dev *pdev) 1088 { 1089 return (atomic_read(&pdev->enable_cnt) > 0); 1090 } 1091 1092 static inline int pci_is_managed(struct pci_dev *pdev) 1093 { 1094 return pdev->is_managed; 1095 } 1096 1097 void pci_disable_device(struct pci_dev *dev); 1098 1099 extern unsigned int pcibios_max_latency; 1100 void pci_set_master(struct pci_dev *dev); 1101 void pci_clear_master(struct pci_dev *dev); 1102 1103 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1104 int pci_set_cacheline_size(struct pci_dev *dev); 1105 #define HAVE_PCI_SET_MWI 1106 int __must_check pci_set_mwi(struct pci_dev *dev); 1107 int __must_check pcim_set_mwi(struct pci_dev *dev); 1108 int pci_try_set_mwi(struct pci_dev *dev); 1109 void pci_clear_mwi(struct pci_dev *dev); 1110 void pci_intx(struct pci_dev *dev, int enable); 1111 bool pci_check_and_mask_intx(struct pci_dev *dev); 1112 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1113 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1114 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1115 int pcix_get_max_mmrbc(struct pci_dev *dev); 1116 int pcix_get_mmrbc(struct pci_dev *dev); 1117 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1118 int pcie_get_readrq(struct pci_dev *dev); 1119 int pcie_set_readrq(struct pci_dev *dev, int rq); 1120 int pcie_get_mps(struct pci_dev *dev); 1121 int pcie_set_mps(struct pci_dev *dev, int mps); 1122 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1123 enum pci_bus_speed *speed, 1124 enum pcie_link_width *width); 1125 void pcie_print_link_status(struct pci_dev *dev); 1126 bool pcie_has_flr(struct pci_dev *dev); 1127 int pcie_flr(struct pci_dev *dev); 1128 int __pci_reset_function_locked(struct pci_dev *dev); 1129 int pci_reset_function(struct pci_dev *dev); 1130 int pci_reset_function_locked(struct pci_dev *dev); 1131 int pci_try_reset_function(struct pci_dev *dev); 1132 int pci_probe_reset_slot(struct pci_slot *slot); 1133 int pci_probe_reset_bus(struct pci_bus *bus); 1134 int pci_reset_bus(struct pci_dev *dev); 1135 void pci_reset_secondary_bus(struct pci_dev *dev); 1136 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1137 void pci_update_resource(struct pci_dev *dev, int resno); 1138 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1139 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1140 void pci_release_resource(struct pci_dev *dev, int resno); 1141 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1142 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1143 bool pci_device_is_present(struct pci_dev *pdev); 1144 void pci_ignore_hotplug(struct pci_dev *dev); 1145 1146 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1147 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1148 const char *fmt, ...); 1149 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1150 1151 /* ROM control related routines */ 1152 int pci_enable_rom(struct pci_dev *pdev); 1153 void pci_disable_rom(struct pci_dev *pdev); 1154 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1155 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1156 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1157 1158 /* Power management related routines */ 1159 int pci_save_state(struct pci_dev *dev); 1160 void pci_restore_state(struct pci_dev *dev); 1161 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1162 int pci_load_saved_state(struct pci_dev *dev, 1163 struct pci_saved_state *state); 1164 int pci_load_and_free_saved_state(struct pci_dev *dev, 1165 struct pci_saved_state **state); 1166 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1167 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1168 u16 cap); 1169 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1170 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1171 u16 cap, unsigned int size); 1172 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1173 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1174 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1175 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1176 void pci_pme_active(struct pci_dev *dev, bool enable); 1177 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1178 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1179 int pci_prepare_to_sleep(struct pci_dev *dev); 1180 int pci_back_from_sleep(struct pci_dev *dev); 1181 bool pci_dev_run_wake(struct pci_dev *dev); 1182 bool pci_check_pme_status(struct pci_dev *dev); 1183 void pci_pme_wakeup_bus(struct pci_bus *bus); 1184 void pci_d3cold_enable(struct pci_dev *dev); 1185 void pci_d3cold_disable(struct pci_dev *dev); 1186 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1187 void pci_wakeup_bus(struct pci_bus *bus); 1188 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1189 1190 /* PCI Virtual Channel */ 1191 int pci_save_vc_state(struct pci_dev *dev); 1192 void pci_restore_vc_state(struct pci_dev *dev); 1193 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1194 1195 /* For use by arch with custom probe code */ 1196 void set_pcie_port_type(struct pci_dev *pdev); 1197 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1198 1199 /* Functions for PCI Hotplug drivers to use */ 1200 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1201 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1202 unsigned int pci_rescan_bus(struct pci_bus *bus); 1203 void pci_lock_rescan_remove(void); 1204 void pci_unlock_rescan_remove(void); 1205 1206 /* Vital Product Data routines */ 1207 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1208 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1209 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1210 1211 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1212 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1213 void pci_bus_assign_resources(const struct pci_bus *bus); 1214 void pci_bus_claim_resources(struct pci_bus *bus); 1215 void pci_bus_size_bridges(struct pci_bus *bus); 1216 int pci_claim_resource(struct pci_dev *, int); 1217 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1218 void pci_assign_unassigned_resources(void); 1219 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1220 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1221 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1222 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1223 void pdev_enable_device(struct pci_dev *); 1224 int pci_enable_resources(struct pci_dev *, int mask); 1225 void pci_assign_irq(struct pci_dev *dev); 1226 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1227 #define HAVE_PCI_REQ_REGIONS 2 1228 int __must_check pci_request_regions(struct pci_dev *, const char *); 1229 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1230 void pci_release_regions(struct pci_dev *); 1231 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1232 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1233 void pci_release_region(struct pci_dev *, int); 1234 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1235 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1236 void pci_release_selected_regions(struct pci_dev *, int); 1237 1238 /* drivers/pci/bus.c */ 1239 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1240 void pci_bus_put(struct pci_bus *bus); 1241 void pci_add_resource(struct list_head *resources, struct resource *res); 1242 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1243 resource_size_t offset); 1244 void pci_free_resource_list(struct list_head *resources); 1245 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1246 unsigned int flags); 1247 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1248 void pci_bus_remove_resources(struct pci_bus *bus); 1249 int devm_request_pci_bus_resources(struct device *dev, 1250 struct list_head *resources); 1251 1252 /* Temporary until new and working PCI SBR API in place */ 1253 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1254 1255 #define pci_bus_for_each_resource(bus, res, i) \ 1256 for (i = 0; \ 1257 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1258 i++) 1259 1260 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1261 struct resource *res, resource_size_t size, 1262 resource_size_t align, resource_size_t min, 1263 unsigned long type_mask, 1264 resource_size_t (*alignf)(void *, 1265 const struct resource *, 1266 resource_size_t, 1267 resource_size_t), 1268 void *alignf_data); 1269 1270 1271 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1272 resource_size_t size); 1273 unsigned long pci_address_to_pio(phys_addr_t addr); 1274 phys_addr_t pci_pio_to_address(unsigned long pio); 1275 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1276 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1277 phys_addr_t phys_addr); 1278 void pci_unmap_iospace(struct resource *res); 1279 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1280 resource_size_t offset, 1281 resource_size_t size); 1282 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1283 struct resource *res); 1284 1285 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1286 { 1287 struct pci_bus_region region; 1288 1289 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1290 return region.start; 1291 } 1292 1293 /* Proper probing supporting hot-pluggable devices */ 1294 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1295 const char *mod_name); 1296 1297 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1298 #define pci_register_driver(driver) \ 1299 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1300 1301 void pci_unregister_driver(struct pci_driver *dev); 1302 1303 /** 1304 * module_pci_driver() - Helper macro for registering a PCI driver 1305 * @__pci_driver: pci_driver struct 1306 * 1307 * Helper macro for PCI drivers which do not do anything special in module 1308 * init/exit. This eliminates a lot of boilerplate. Each module may only 1309 * use this macro once, and calling it replaces module_init() and module_exit() 1310 */ 1311 #define module_pci_driver(__pci_driver) \ 1312 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1313 1314 /** 1315 * builtin_pci_driver() - Helper macro for registering a PCI driver 1316 * @__pci_driver: pci_driver struct 1317 * 1318 * Helper macro for PCI drivers which do not do anything special in their 1319 * init code. This eliminates a lot of boilerplate. Each driver may only 1320 * use this macro once, and calling it replaces device_initcall(...) 1321 */ 1322 #define builtin_pci_driver(__pci_driver) \ 1323 builtin_driver(__pci_driver, pci_register_driver) 1324 1325 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1326 int pci_add_dynid(struct pci_driver *drv, 1327 unsigned int vendor, unsigned int device, 1328 unsigned int subvendor, unsigned int subdevice, 1329 unsigned int class, unsigned int class_mask, 1330 unsigned long driver_data); 1331 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1332 struct pci_dev *dev); 1333 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1334 int pass); 1335 1336 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1337 void *userdata); 1338 int pci_cfg_space_size(struct pci_dev *dev); 1339 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1340 void pci_setup_bridge(struct pci_bus *bus); 1341 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1342 unsigned long type); 1343 1344 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1345 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1346 1347 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1348 unsigned int command_bits, u32 flags); 1349 1350 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1351 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1352 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1353 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1354 #define PCI_IRQ_ALL_TYPES \ 1355 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1356 1357 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1358 1359 #include <linux/dmapool.h> 1360 1361 #define pci_pool dma_pool 1362 #define pci_pool_create(name, pdev, size, align, allocation) \ 1363 dma_pool_create(name, &pdev->dev, size, align, allocation) 1364 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1365 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1366 #define pci_pool_zalloc(pool, flags, handle) \ 1367 dma_pool_zalloc(pool, flags, handle) 1368 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1369 1370 struct msix_entry { 1371 u32 vector; /* Kernel uses to write allocated vector */ 1372 u16 entry; /* Driver uses to specify entry, OS writes */ 1373 }; 1374 1375 #ifdef CONFIG_PCI_MSI 1376 int pci_msi_vec_count(struct pci_dev *dev); 1377 void pci_disable_msi(struct pci_dev *dev); 1378 int pci_msix_vec_count(struct pci_dev *dev); 1379 void pci_disable_msix(struct pci_dev *dev); 1380 void pci_restore_msi_state(struct pci_dev *dev); 1381 int pci_msi_enabled(void); 1382 int pci_enable_msi(struct pci_dev *dev); 1383 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1384 int minvec, int maxvec); 1385 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1386 struct msix_entry *entries, int nvec) 1387 { 1388 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1389 if (rc < 0) 1390 return rc; 1391 return 0; 1392 } 1393 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1394 unsigned int max_vecs, unsigned int flags, 1395 const struct irq_affinity *affd); 1396 1397 void pci_free_irq_vectors(struct pci_dev *dev); 1398 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1399 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1400 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1401 1402 #else 1403 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1404 static inline void pci_disable_msi(struct pci_dev *dev) { } 1405 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1406 static inline void pci_disable_msix(struct pci_dev *dev) { } 1407 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1408 static inline int pci_msi_enabled(void) { return 0; } 1409 static inline int pci_enable_msi(struct pci_dev *dev) 1410 { return -ENOSYS; } 1411 static inline int pci_enable_msix_range(struct pci_dev *dev, 1412 struct msix_entry *entries, int minvec, int maxvec) 1413 { return -ENOSYS; } 1414 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1415 struct msix_entry *entries, int nvec) 1416 { return -ENOSYS; } 1417 1418 static inline int 1419 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1420 unsigned int max_vecs, unsigned int flags, 1421 const struct irq_affinity *aff_desc) 1422 { 1423 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1424 return 1; 1425 return -ENOSPC; 1426 } 1427 1428 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1429 { 1430 } 1431 1432 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1433 { 1434 if (WARN_ON_ONCE(nr > 0)) 1435 return -EINVAL; 1436 return dev->irq; 1437 } 1438 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1439 int vec) 1440 { 1441 return cpu_possible_mask; 1442 } 1443 1444 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1445 { 1446 return first_online_node; 1447 } 1448 #endif 1449 1450 static inline int 1451 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1452 unsigned int max_vecs, unsigned int flags) 1453 { 1454 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1455 NULL); 1456 } 1457 1458 /** 1459 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1460 * @d: the INTx IRQ domain 1461 * @node: the DT node for the device whose interrupt we're translating 1462 * @intspec: the interrupt specifier data from the DT 1463 * @intsize: the number of entries in @intspec 1464 * @out_hwirq: pointer at which to write the hwirq number 1465 * @out_type: pointer at which to write the interrupt type 1466 * 1467 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1468 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1469 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1470 * INTx value to obtain the hwirq number. 1471 * 1472 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1473 */ 1474 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1475 struct device_node *node, 1476 const u32 *intspec, 1477 unsigned int intsize, 1478 unsigned long *out_hwirq, 1479 unsigned int *out_type) 1480 { 1481 const u32 intx = intspec[0]; 1482 1483 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1484 return -EINVAL; 1485 1486 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1487 return 0; 1488 } 1489 1490 #ifdef CONFIG_PCIEPORTBUS 1491 extern bool pcie_ports_disabled; 1492 extern bool pcie_ports_native; 1493 #else 1494 #define pcie_ports_disabled true 1495 #define pcie_ports_native false 1496 #endif 1497 1498 #ifdef CONFIG_PCIEASPM 1499 bool pcie_aspm_support_enabled(void); 1500 #else 1501 static inline bool pcie_aspm_support_enabled(void) { return false; } 1502 #endif 1503 1504 #ifdef CONFIG_PCIEAER 1505 bool pci_aer_available(void); 1506 #else 1507 static inline bool pci_aer_available(void) { return false; } 1508 #endif 1509 1510 #ifdef CONFIG_PCIE_ECRC 1511 void pcie_set_ecrc_checking(struct pci_dev *dev); 1512 void pcie_ecrc_get_policy(char *str); 1513 #else 1514 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1515 static inline void pcie_ecrc_get_policy(char *str) { } 1516 #endif 1517 1518 bool pci_ats_disabled(void); 1519 1520 #ifdef CONFIG_PCI_ATS 1521 /* Address Translation Service */ 1522 void pci_ats_init(struct pci_dev *dev); 1523 int pci_enable_ats(struct pci_dev *dev, int ps); 1524 void pci_disable_ats(struct pci_dev *dev); 1525 int pci_ats_queue_depth(struct pci_dev *dev); 1526 #else 1527 static inline void pci_ats_init(struct pci_dev *d) { } 1528 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1529 static inline void pci_disable_ats(struct pci_dev *d) { } 1530 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1531 #endif 1532 1533 #ifdef CONFIG_PCIE_PTM 1534 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1535 #else 1536 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1537 { return -EINVAL; } 1538 #endif 1539 1540 void pci_cfg_access_lock(struct pci_dev *dev); 1541 bool pci_cfg_access_trylock(struct pci_dev *dev); 1542 void pci_cfg_access_unlock(struct pci_dev *dev); 1543 1544 /* 1545 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1546 * a PCI domain is defined to be a set of PCI buses which share 1547 * configuration space. 1548 */ 1549 #ifdef CONFIG_PCI_DOMAINS 1550 extern int pci_domains_supported; 1551 #else 1552 enum { pci_domains_supported = 0 }; 1553 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1554 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1555 #endif /* CONFIG_PCI_DOMAINS */ 1556 1557 /* 1558 * Generic implementation for PCI domain support. If your 1559 * architecture does not need custom management of PCI 1560 * domains then this implementation will be used 1561 */ 1562 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1563 static inline int pci_domain_nr(struct pci_bus *bus) 1564 { 1565 return bus->domain_nr; 1566 } 1567 #ifdef CONFIG_ACPI 1568 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1569 #else 1570 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1571 { return 0; } 1572 #endif 1573 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1574 #endif 1575 1576 /* Some architectures require additional setup to direct VGA traffic */ 1577 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1578 unsigned int command_bits, u32 flags); 1579 void pci_register_set_vga_state(arch_set_vga_state_t func); 1580 1581 static inline int 1582 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1583 { 1584 return pci_request_selected_regions(pdev, 1585 pci_select_bars(pdev, IORESOURCE_IO), name); 1586 } 1587 1588 static inline void 1589 pci_release_io_regions(struct pci_dev *pdev) 1590 { 1591 return pci_release_selected_regions(pdev, 1592 pci_select_bars(pdev, IORESOURCE_IO)); 1593 } 1594 1595 static inline int 1596 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1597 { 1598 return pci_request_selected_regions(pdev, 1599 pci_select_bars(pdev, IORESOURCE_MEM), name); 1600 } 1601 1602 static inline void 1603 pci_release_mem_regions(struct pci_dev *pdev) 1604 { 1605 return pci_release_selected_regions(pdev, 1606 pci_select_bars(pdev, IORESOURCE_MEM)); 1607 } 1608 1609 #else /* CONFIG_PCI is not enabled */ 1610 1611 static inline void pci_set_flags(int flags) { } 1612 static inline void pci_add_flags(int flags) { } 1613 static inline void pci_clear_flags(int flags) { } 1614 static inline int pci_has_flag(int flag) { return 0; } 1615 1616 /* 1617 * If the system does not have PCI, clearly these return errors. Define 1618 * these as simple inline functions to avoid hair in drivers. 1619 */ 1620 #define _PCI_NOP(o, s, t) \ 1621 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1622 int where, t val) \ 1623 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1624 1625 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1626 _PCI_NOP(o, word, u16 x) \ 1627 _PCI_NOP(o, dword, u32 x) 1628 _PCI_NOP_ALL(read, *) 1629 _PCI_NOP_ALL(write,) 1630 1631 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1632 unsigned int device, 1633 struct pci_dev *from) 1634 { return NULL; } 1635 1636 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1637 unsigned int device, 1638 unsigned int ss_vendor, 1639 unsigned int ss_device, 1640 struct pci_dev *from) 1641 { return NULL; } 1642 1643 static inline struct pci_dev *pci_get_class(unsigned int class, 1644 struct pci_dev *from) 1645 { return NULL; } 1646 1647 #define pci_dev_present(ids) (0) 1648 #define no_pci_devices() (1) 1649 #define pci_dev_put(dev) do { } while (0) 1650 1651 static inline void pci_set_master(struct pci_dev *dev) { } 1652 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1653 static inline void pci_disable_device(struct pci_dev *dev) { } 1654 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1655 { return -EBUSY; } 1656 static inline int __pci_register_driver(struct pci_driver *drv, 1657 struct module *owner) 1658 { return 0; } 1659 static inline int pci_register_driver(struct pci_driver *drv) 1660 { return 0; } 1661 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1662 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1663 { return 0; } 1664 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1665 int cap) 1666 { return 0; } 1667 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1668 { return 0; } 1669 1670 /* Power management related routines */ 1671 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1672 static inline void pci_restore_state(struct pci_dev *dev) { } 1673 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1674 { return 0; } 1675 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1676 { return 0; } 1677 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1678 pm_message_t state) 1679 { return PCI_D0; } 1680 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1681 int enable) 1682 { return 0; } 1683 1684 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1685 struct resource *res) 1686 { return NULL; } 1687 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1688 { return -EIO; } 1689 static inline void pci_release_regions(struct pci_dev *dev) { } 1690 1691 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1692 1693 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1694 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1695 { return 0; } 1696 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1697 1698 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1699 { return NULL; } 1700 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1701 unsigned int devfn) 1702 { return NULL; } 1703 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1704 unsigned int bus, unsigned int devfn) 1705 { return NULL; } 1706 1707 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1708 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1709 1710 #define dev_is_pci(d) (false) 1711 #define dev_is_pf(d) (false) 1712 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1713 { return false; } 1714 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1715 struct device_node *node, 1716 const u32 *intspec, 1717 unsigned int intsize, 1718 unsigned long *out_hwirq, 1719 unsigned int *out_type) 1720 { return -EINVAL; } 1721 1722 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1723 struct pci_dev *dev) 1724 { return NULL; } 1725 #endif /* CONFIG_PCI */ 1726 1727 /* Include architecture-dependent settings and functions */ 1728 1729 #include <asm/pci.h> 1730 1731 /* These two functions provide almost identical functionality. Depennding 1732 * on the architecture, one will be implemented as a wrapper around the 1733 * other (in drivers/pci/mmap.c). 1734 * 1735 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1736 * is expected to be an offset within that region. 1737 * 1738 * pci_mmap_page_range() is the legacy architecture-specific interface, 1739 * which accepts a "user visible" resource address converted by 1740 * pci_resource_to_user(), as used in the legacy mmap() interface in 1741 * /proc/bus/pci/. 1742 */ 1743 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1744 struct vm_area_struct *vma, 1745 enum pci_mmap_state mmap_state, int write_combine); 1746 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1747 struct vm_area_struct *vma, 1748 enum pci_mmap_state mmap_state, int write_combine); 1749 1750 #ifndef arch_can_pci_mmap_wc 1751 #define arch_can_pci_mmap_wc() 0 1752 #endif 1753 1754 #ifndef arch_can_pci_mmap_io 1755 #define arch_can_pci_mmap_io() 0 1756 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1757 #else 1758 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1759 #endif 1760 1761 #ifndef pci_root_bus_fwnode 1762 #define pci_root_bus_fwnode(bus) NULL 1763 #endif 1764 1765 /* 1766 * These helpers provide future and backwards compatibility 1767 * for accessing popular PCI BAR info 1768 */ 1769 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1770 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1771 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1772 #define pci_resource_len(dev,bar) \ 1773 ((pci_resource_start((dev), (bar)) == 0 && \ 1774 pci_resource_end((dev), (bar)) == \ 1775 pci_resource_start((dev), (bar))) ? 0 : \ 1776 \ 1777 (pci_resource_end((dev), (bar)) - \ 1778 pci_resource_start((dev), (bar)) + 1)) 1779 1780 /* 1781 * Similar to the helpers above, these manipulate per-pci_dev 1782 * driver-specific data. They are really just a wrapper around 1783 * the generic device structure functions of these calls. 1784 */ 1785 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1786 { 1787 return dev_get_drvdata(&pdev->dev); 1788 } 1789 1790 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1791 { 1792 dev_set_drvdata(&pdev->dev, data); 1793 } 1794 1795 static inline const char *pci_name(const struct pci_dev *pdev) 1796 { 1797 return dev_name(&pdev->dev); 1798 } 1799 1800 1801 /* 1802 * Some archs don't want to expose struct resource to userland as-is 1803 * in sysfs and /proc 1804 */ 1805 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1806 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1807 const struct resource *rsrc, 1808 resource_size_t *start, resource_size_t *end); 1809 #else 1810 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1811 const struct resource *rsrc, resource_size_t *start, 1812 resource_size_t *end) 1813 { 1814 *start = rsrc->start; 1815 *end = rsrc->end; 1816 } 1817 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1818 1819 1820 /* 1821 * The world is not perfect and supplies us with broken PCI devices. 1822 * For at least a part of these bugs we need a work-around, so both 1823 * generic (drivers/pci/quirks.c) and per-architecture code can define 1824 * fixup hooks to be called for particular buggy devices. 1825 */ 1826 1827 struct pci_fixup { 1828 u16 vendor; /* Or PCI_ANY_ID */ 1829 u16 device; /* Or PCI_ANY_ID */ 1830 u32 class; /* Or PCI_ANY_ID */ 1831 unsigned int class_shift; /* should be 0, 8, 16 */ 1832 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1833 int hook_offset; 1834 #else 1835 void (*hook)(struct pci_dev *dev); 1836 #endif 1837 }; 1838 1839 enum pci_fixup_pass { 1840 pci_fixup_early, /* Before probing BARs */ 1841 pci_fixup_header, /* After reading configuration header */ 1842 pci_fixup_final, /* Final phase of device fixups */ 1843 pci_fixup_enable, /* pci_enable_device() time */ 1844 pci_fixup_resume, /* pci_device_resume() */ 1845 pci_fixup_suspend, /* pci_device_suspend() */ 1846 pci_fixup_resume_early, /* pci_device_resume_early() */ 1847 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1848 }; 1849 1850 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1851 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1852 class_shift, hook) \ 1853 __ADDRESSABLE(hook) \ 1854 asm(".section " #sec ", \"a\" \n" \ 1855 ".balign 16 \n" \ 1856 ".short " #vendor ", " #device " \n" \ 1857 ".long " #class ", " #class_shift " \n" \ 1858 ".long " #hook " - . \n" \ 1859 ".previous \n"); 1860 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1861 class_shift, hook) \ 1862 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1863 class_shift, hook) 1864 #else 1865 /* Anonymous variables would be nice... */ 1866 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1867 class_shift, hook) \ 1868 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1869 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1870 = { vendor, device, class, class_shift, hook }; 1871 #endif 1872 1873 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1874 class_shift, hook) \ 1875 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1876 hook, vendor, device, class, class_shift, hook) 1877 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1878 class_shift, hook) \ 1879 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1880 hook, vendor, device, class, class_shift, hook) 1881 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1882 class_shift, hook) \ 1883 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1884 hook, vendor, device, class, class_shift, hook) 1885 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1886 class_shift, hook) \ 1887 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1888 hook, vendor, device, class, class_shift, hook) 1889 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1890 class_shift, hook) \ 1891 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1892 resume##hook, vendor, device, class, class_shift, hook) 1893 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1894 class_shift, hook) \ 1895 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1896 resume_early##hook, vendor, device, class, class_shift, hook) 1897 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1898 class_shift, hook) \ 1899 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1900 suspend##hook, vendor, device, class, class_shift, hook) 1901 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1902 class_shift, hook) \ 1903 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1904 suspend_late##hook, vendor, device, class, class_shift, hook) 1905 1906 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1907 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1908 hook, vendor, device, PCI_ANY_ID, 0, hook) 1909 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1910 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1911 hook, vendor, device, PCI_ANY_ID, 0, hook) 1912 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1913 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1914 hook, vendor, device, PCI_ANY_ID, 0, hook) 1915 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1916 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1917 hook, vendor, device, PCI_ANY_ID, 0, hook) 1918 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1919 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1920 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1921 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1922 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1923 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1924 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1925 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1926 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1927 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1928 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1929 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1930 1931 #ifdef CONFIG_PCI_QUIRKS 1932 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1933 #else 1934 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1935 struct pci_dev *dev) { } 1936 #endif 1937 1938 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1939 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1940 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1941 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1942 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1943 const char *name); 1944 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1945 1946 extern int pci_pci_problems; 1947 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1948 #define PCIPCI_TRITON 2 1949 #define PCIPCI_NATOMA 4 1950 #define PCIPCI_VIAETBF 8 1951 #define PCIPCI_VSFX 16 1952 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1953 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1954 1955 extern unsigned long pci_cardbus_io_size; 1956 extern unsigned long pci_cardbus_mem_size; 1957 extern u8 pci_dfl_cache_line_size; 1958 extern u8 pci_cache_line_size; 1959 1960 extern unsigned long pci_hotplug_io_size; 1961 extern unsigned long pci_hotplug_mem_size; 1962 extern unsigned long pci_hotplug_bus_size; 1963 1964 /* Architecture-specific versions may override these (weak) */ 1965 void pcibios_disable_device(struct pci_dev *dev); 1966 void pcibios_set_master(struct pci_dev *dev); 1967 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1968 enum pcie_reset_state state); 1969 int pcibios_add_device(struct pci_dev *dev); 1970 void pcibios_release_device(struct pci_dev *dev); 1971 #ifdef CONFIG_PCI 1972 void pcibios_penalize_isa_irq(int irq, int active); 1973 #else 1974 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 1975 #endif 1976 int pcibios_alloc_irq(struct pci_dev *dev); 1977 void pcibios_free_irq(struct pci_dev *dev); 1978 resource_size_t pcibios_default_alignment(void); 1979 1980 #ifdef CONFIG_HIBERNATE_CALLBACKS 1981 extern struct dev_pm_ops pcibios_pm_ops; 1982 #endif 1983 1984 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 1985 void __init pci_mmcfg_early_init(void); 1986 void __init pci_mmcfg_late_init(void); 1987 #else 1988 static inline void pci_mmcfg_early_init(void) { } 1989 static inline void pci_mmcfg_late_init(void) { } 1990 #endif 1991 1992 int pci_ext_cfg_avail(void); 1993 1994 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1995 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1996 1997 #ifdef CONFIG_PCI_IOV 1998 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1999 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2000 2001 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2002 void pci_disable_sriov(struct pci_dev *dev); 2003 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2004 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2005 int pci_num_vf(struct pci_dev *dev); 2006 int pci_vfs_assigned(struct pci_dev *dev); 2007 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2008 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2009 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2010 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2011 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2012 2013 /* Arch may override these (weak) */ 2014 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2015 int pcibios_sriov_disable(struct pci_dev *pdev); 2016 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2017 #else 2018 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2019 { 2020 return -ENOSYS; 2021 } 2022 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2023 { 2024 return -ENOSYS; 2025 } 2026 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2027 { return -ENODEV; } 2028 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2029 { 2030 return -ENOSYS; 2031 } 2032 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2033 int id) { } 2034 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2035 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2036 static inline int pci_vfs_assigned(struct pci_dev *dev) 2037 { return 0; } 2038 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2039 { return 0; } 2040 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2041 { return 0; } 2042 #define pci_sriov_configure_simple NULL 2043 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2044 { return 0; } 2045 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2046 #endif 2047 2048 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2049 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2050 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2051 #endif 2052 2053 /** 2054 * pci_pcie_cap - get the saved PCIe capability offset 2055 * @dev: PCI device 2056 * 2057 * PCIe capability offset is calculated at PCI device initialization 2058 * time and saved in the data structure. This function returns saved 2059 * PCIe capability offset. Using this instead of pci_find_capability() 2060 * reduces unnecessary search in the PCI configuration space. If you 2061 * need to calculate PCIe capability offset from raw device for some 2062 * reasons, please use pci_find_capability() instead. 2063 */ 2064 static inline int pci_pcie_cap(struct pci_dev *dev) 2065 { 2066 return dev->pcie_cap; 2067 } 2068 2069 /** 2070 * pci_is_pcie - check if the PCI device is PCI Express capable 2071 * @dev: PCI device 2072 * 2073 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2074 */ 2075 static inline bool pci_is_pcie(struct pci_dev *dev) 2076 { 2077 return pci_pcie_cap(dev); 2078 } 2079 2080 /** 2081 * pcie_caps_reg - get the PCIe Capabilities Register 2082 * @dev: PCI device 2083 */ 2084 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2085 { 2086 return dev->pcie_flags_reg; 2087 } 2088 2089 /** 2090 * pci_pcie_type - get the PCIe device/port type 2091 * @dev: PCI device 2092 */ 2093 static inline int pci_pcie_type(const struct pci_dev *dev) 2094 { 2095 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2096 } 2097 2098 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2099 { 2100 while (1) { 2101 if (!pci_is_pcie(dev)) 2102 break; 2103 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2104 return dev; 2105 if (!dev->bus->self) 2106 break; 2107 dev = dev->bus->self; 2108 } 2109 return NULL; 2110 } 2111 2112 void pci_request_acs(void); 2113 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2114 bool pci_acs_path_enabled(struct pci_dev *start, 2115 struct pci_dev *end, u16 acs_flags); 2116 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2117 2118 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2119 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2120 2121 /* Large Resource Data Type Tag Item Names */ 2122 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2123 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2124 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2125 2126 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2127 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2128 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2129 2130 /* Small Resource Data Type Tag Item Names */ 2131 #define PCI_VPD_STIN_END 0x0f /* End */ 2132 2133 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2134 2135 #define PCI_VPD_SRDT_TIN_MASK 0x78 2136 #define PCI_VPD_SRDT_LEN_MASK 0x07 2137 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2138 2139 #define PCI_VPD_LRDT_TAG_SIZE 3 2140 #define PCI_VPD_SRDT_TAG_SIZE 1 2141 2142 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2143 2144 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2145 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2146 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2147 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2148 2149 /** 2150 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2151 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2152 * 2153 * Returns the extracted Large Resource Data Type length. 2154 */ 2155 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2156 { 2157 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2158 } 2159 2160 /** 2161 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2162 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2163 * 2164 * Returns the extracted Large Resource Data Type Tag item. 2165 */ 2166 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2167 { 2168 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2169 } 2170 2171 /** 2172 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2173 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2174 * 2175 * Returns the extracted Small Resource Data Type length. 2176 */ 2177 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2178 { 2179 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2180 } 2181 2182 /** 2183 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2184 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2185 * 2186 * Returns the extracted Small Resource Data Type Tag Item. 2187 */ 2188 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2189 { 2190 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2191 } 2192 2193 /** 2194 * pci_vpd_info_field_size - Extracts the information field length 2195 * @lrdt: Pointer to the beginning of an information field header 2196 * 2197 * Returns the extracted information field length. 2198 */ 2199 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2200 { 2201 return info_field[2]; 2202 } 2203 2204 /** 2205 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2206 * @buf: Pointer to buffered vpd data 2207 * @off: The offset into the buffer at which to begin the search 2208 * @len: The length of the vpd buffer 2209 * @rdt: The Resource Data Type to search for 2210 * 2211 * Returns the index where the Resource Data Type was found or 2212 * -ENOENT otherwise. 2213 */ 2214 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2215 2216 /** 2217 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2218 * @buf: Pointer to buffered vpd data 2219 * @off: The offset into the buffer at which to begin the search 2220 * @len: The length of the buffer area, relative to off, in which to search 2221 * @kw: The keyword to search for 2222 * 2223 * Returns the index where the information field keyword was found or 2224 * -ENOENT otherwise. 2225 */ 2226 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2227 unsigned int len, const char *kw); 2228 2229 /* PCI <-> OF binding helpers */ 2230 #ifdef CONFIG_OF 2231 struct device_node; 2232 struct irq_domain; 2233 void pci_set_of_node(struct pci_dev *dev); 2234 void pci_release_of_node(struct pci_dev *dev); 2235 void pci_set_bus_of_node(struct pci_bus *bus); 2236 void pci_release_bus_of_node(struct pci_bus *bus); 2237 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2238 int pci_parse_request_of_pci_ranges(struct device *dev, 2239 struct list_head *resources, 2240 struct resource **bus_range); 2241 2242 /* Arch may override this (weak) */ 2243 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2244 2245 #else /* CONFIG_OF */ 2246 static inline void pci_set_of_node(struct pci_dev *dev) { } 2247 static inline void pci_release_of_node(struct pci_dev *dev) { } 2248 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2249 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2250 static inline struct irq_domain * 2251 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2252 static inline int pci_parse_request_of_pci_ranges(struct device *dev, 2253 struct list_head *resources, 2254 struct resource **bus_range) 2255 { 2256 return -EINVAL; 2257 } 2258 #endif /* CONFIG_OF */ 2259 2260 static inline struct device_node * 2261 pci_device_to_OF_node(const struct pci_dev *pdev) 2262 { 2263 return pdev ? pdev->dev.of_node : NULL; 2264 } 2265 2266 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2267 { 2268 return bus ? bus->dev.of_node : NULL; 2269 } 2270 2271 #ifdef CONFIG_ACPI 2272 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2273 2274 void 2275 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2276 #else 2277 static inline struct irq_domain * 2278 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2279 #endif 2280 2281 #ifdef CONFIG_EEH 2282 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2283 { 2284 return pdev->dev.archdata.edev; 2285 } 2286 #endif 2287 2288 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2289 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2290 int pci_for_each_dma_alias(struct pci_dev *pdev, 2291 int (*fn)(struct pci_dev *pdev, 2292 u16 alias, void *data), void *data); 2293 2294 /* Helper functions for operation of device flag */ 2295 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2296 { 2297 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2298 } 2299 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2300 { 2301 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2302 } 2303 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2304 { 2305 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2306 } 2307 2308 /** 2309 * pci_ari_enabled - query ARI forwarding status 2310 * @bus: the PCI bus 2311 * 2312 * Returns true if ARI forwarding is enabled. 2313 */ 2314 static inline bool pci_ari_enabled(struct pci_bus *bus) 2315 { 2316 return bus->self && bus->self->ari_enabled; 2317 } 2318 2319 /** 2320 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2321 * @pdev: PCI device to check 2322 * 2323 * Walk upwards from @pdev and check for each encountered bridge if it's part 2324 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2325 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2326 */ 2327 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2328 { 2329 struct pci_dev *parent = pdev; 2330 2331 if (pdev->is_thunderbolt) 2332 return true; 2333 2334 while ((parent = pci_upstream_bridge(parent))) 2335 if (parent->is_thunderbolt) 2336 return true; 2337 2338 return false; 2339 } 2340 2341 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2342 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2343 #endif 2344 2345 /* Provide the legacy pci_dma_* API */ 2346 #include <linux/pci-dma-compat.h> 2347 2348 #define pci_printk(level, pdev, fmt, arg...) \ 2349 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2350 2351 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2352 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2353 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2354 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2355 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2356 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2357 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2358 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2359 2360 #endif /* LINUX_PCI_H */ 2361