1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * For more information, please consult the following manuals (look at 10 * http://www.pcisig.com/ for how to get them): 11 * 12 * PCI BIOS Specification 13 * PCI Local Bus Specification 14 * PCI to PCI Bridge Specification 15 * PCI System Design Guide 16 */ 17 #ifndef LINUX_PCI_H 18 #define LINUX_PCI_H 19 20 21 #include <linux/mod_devicetable.h> 22 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/list.h> 27 #include <linux/compiler.h> 28 #include <linux/errno.h> 29 #include <linux/kobject.h> 30 #include <linux/atomic.h> 31 #include <linux/device.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/resource_ext.h> 35 #include <uapi/linux/pci.h> 36 37 #include <linux/pci_ids.h> 38 39 /* 40 * The PCI interface treats multi-function devices as independent 41 * devices. The slot/function address of each device is encoded 42 * in a single byte as follows: 43 * 44 * 7:3 = slot 45 * 2:0 = function 46 * 47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 48 * In the interest of not exposing interfaces to user-space unnecessarily, 49 * the following kernel-only defines are being added here. 50 */ 51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 54 55 /* pci_slot represents a physical slot */ 56 struct pci_slot { 57 struct pci_bus *bus; /* Bus this slot is on */ 58 struct list_head list; /* Node in list of slots */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 61 struct kobject kobj; 62 }; 63 64 static inline const char *pci_slot_name(const struct pci_slot *slot) 65 { 66 return kobject_name(&slot->kobj); 67 } 68 69 /* File state for mmap()s on /proc/bus/pci/X/Y */ 70 enum pci_mmap_state { 71 pci_mmap_io, 72 pci_mmap_mem 73 }; 74 75 /* For PCI devices, the region numbers are assigned this way: */ 76 enum { 77 /* #0-5: standard PCI resources */ 78 PCI_STD_RESOURCES, 79 PCI_STD_RESOURCE_END = 5, 80 81 /* #6: expansion ROM resource */ 82 PCI_ROM_RESOURCE, 83 84 /* Device-specific resources */ 85 #ifdef CONFIG_PCI_IOV 86 PCI_IOV_RESOURCES, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 88 #endif 89 90 /* Resources assigned to buses behind the bridge */ 91 #define PCI_BRIDGE_RESOURCE_NUM 4 92 93 PCI_BRIDGE_RESOURCES, 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 95 PCI_BRIDGE_RESOURCE_NUM - 1, 96 97 /* Total resources associated with a PCI device */ 98 PCI_NUM_RESOURCES, 99 100 /* Preserve this for compatibility */ 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 102 }; 103 104 /** 105 * enum pci_interrupt_pin - PCI INTx interrupt values 106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 107 * @PCI_INTERRUPT_INTA: PCI INTA pin 108 * @PCI_INTERRUPT_INTB: PCI INTB pin 109 * @PCI_INTERRUPT_INTC: PCI INTC pin 110 * @PCI_INTERRUPT_INTD: PCI INTD pin 111 * 112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 113 * PCI_INTERRUPT_PIN register. 114 */ 115 enum pci_interrupt_pin { 116 PCI_INTERRUPT_UNKNOWN, 117 PCI_INTERRUPT_INTA, 118 PCI_INTERRUPT_INTB, 119 PCI_INTERRUPT_INTC, 120 PCI_INTERRUPT_INTD, 121 }; 122 123 /* The number of legacy PCI INTx interrupts */ 124 #define PCI_NUM_INTX 4 125 126 /* 127 * pci_power_t values must match the bits in the Capabilities PME_Support 128 * and Control/Status PowerState fields in the Power Management capability. 129 */ 130 typedef int __bitwise pci_power_t; 131 132 #define PCI_D0 ((pci_power_t __force) 0) 133 #define PCI_D1 ((pci_power_t __force) 1) 134 #define PCI_D2 ((pci_power_t __force) 2) 135 #define PCI_D3hot ((pci_power_t __force) 3) 136 #define PCI_D3cold ((pci_power_t __force) 4) 137 #define PCI_UNKNOWN ((pci_power_t __force) 5) 138 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 139 140 /* Remember to update this when the list above changes! */ 141 extern const char *pci_power_names[]; 142 143 static inline const char *pci_power_name(pci_power_t state) 144 { 145 return pci_power_names[1 + (__force int) state]; 146 } 147 148 #define PCI_PM_D2_DELAY 200 149 #define PCI_PM_D3_WAIT 10 150 #define PCI_PM_D3COLD_WAIT 100 151 #define PCI_PM_BUS_WAIT 50 152 153 /** 154 * typedef pci_channel_state_t 155 * 156 * The pci_channel state describes connectivity between the CPU and 157 * the PCI device. If some PCI bus between here and the PCI device 158 * has crashed or locked up, this info is reflected here. 159 */ 160 typedef unsigned int __bitwise pci_channel_state_t; 161 162 enum pci_channel_state { 163 /* I/O channel is in normal state */ 164 pci_channel_io_normal = (__force pci_channel_state_t) 1, 165 166 /* I/O to channel is blocked */ 167 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 168 169 /* PCI card is dead */ 170 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 171 }; 172 173 typedef unsigned int __bitwise pcie_reset_state_t; 174 175 enum pcie_reset_state { 176 /* Reset is NOT asserted (Use to deassert reset) */ 177 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 178 179 /* Use #PERST to reset PCIe device */ 180 pcie_warm_reset = (__force pcie_reset_state_t) 2, 181 182 /* Use PCIe Hot Reset to reset device */ 183 pcie_hot_reset = (__force pcie_reset_state_t) 3 184 }; 185 186 typedef unsigned short __bitwise pci_dev_flags_t; 187 enum pci_dev_flags { 188 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 189 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 190 /* Device configuration is irrevocably lost if disabled into D3 */ 191 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 192 /* Provide indication device is assigned by a Virtual Machine Manager */ 193 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 194 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 195 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 196 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 197 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 198 /* Do not use bus resets for device */ 199 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 200 /* Do not use PM reset even if device advertises NoSoftRst- */ 201 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 202 /* Get VPD from function 0 VPD */ 203 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 204 /* A non-root bridge where translation occurs, stop alias search here */ 205 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 206 /* Do not use FLR even if device advertises PCI_AF_CAP */ 207 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 208 /* Don't use Relaxed Ordering for TLPs directed at this device */ 209 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 210 }; 211 212 enum pci_irq_reroute_variant { 213 INTEL_IRQ_REROUTE_VARIANT = 1, 214 MAX_IRQ_REROUTE_VARIANTS = 3 215 }; 216 217 typedef unsigned short __bitwise pci_bus_flags_t; 218 enum pci_bus_flags { 219 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 220 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 221 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 222 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 223 }; 224 225 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 226 enum pcie_link_width { 227 PCIE_LNK_WIDTH_RESRV = 0x00, 228 PCIE_LNK_X1 = 0x01, 229 PCIE_LNK_X2 = 0x02, 230 PCIE_LNK_X4 = 0x04, 231 PCIE_LNK_X8 = 0x08, 232 PCIE_LNK_X12 = 0x0c, 233 PCIE_LNK_X16 = 0x10, 234 PCIE_LNK_X32 = 0x20, 235 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 236 }; 237 238 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 239 enum pci_bus_speed { 240 PCI_SPEED_33MHz = 0x00, 241 PCI_SPEED_66MHz = 0x01, 242 PCI_SPEED_66MHz_PCIX = 0x02, 243 PCI_SPEED_100MHz_PCIX = 0x03, 244 PCI_SPEED_133MHz_PCIX = 0x04, 245 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 246 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 247 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 248 PCI_SPEED_66MHz_PCIX_266 = 0x09, 249 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 250 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 251 AGP_UNKNOWN = 0x0c, 252 AGP_1X = 0x0d, 253 AGP_2X = 0x0e, 254 AGP_4X = 0x0f, 255 AGP_8X = 0x10, 256 PCI_SPEED_66MHz_PCIX_533 = 0x11, 257 PCI_SPEED_100MHz_PCIX_533 = 0x12, 258 PCI_SPEED_133MHz_PCIX_533 = 0x13, 259 PCIE_SPEED_2_5GT = 0x14, 260 PCIE_SPEED_5_0GT = 0x15, 261 PCIE_SPEED_8_0GT = 0x16, 262 PCIE_SPEED_16_0GT = 0x17, 263 PCI_SPEED_UNKNOWN = 0xff, 264 }; 265 266 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 267 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 268 269 struct pci_cap_saved_data { 270 u16 cap_nr; 271 bool cap_extended; 272 unsigned int size; 273 u32 data[0]; 274 }; 275 276 struct pci_cap_saved_state { 277 struct hlist_node next; 278 struct pci_cap_saved_data cap; 279 }; 280 281 struct irq_affinity; 282 struct pcie_link_state; 283 struct pci_vpd; 284 struct pci_sriov; 285 struct pci_ats; 286 struct pci_p2pdma; 287 288 /* The pci_dev structure describes PCI devices */ 289 struct pci_dev { 290 struct list_head bus_list; /* Node in per-bus list */ 291 struct pci_bus *bus; /* Bus this device is on */ 292 struct pci_bus *subordinate; /* Bus this device bridges to */ 293 294 void *sysdata; /* Hook for sys-specific extension */ 295 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 296 struct pci_slot *slot; /* Physical slot this device is in */ 297 298 unsigned int devfn; /* Encoded device & function index */ 299 unsigned short vendor; 300 unsigned short device; 301 unsigned short subsystem_vendor; 302 unsigned short subsystem_device; 303 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 304 u8 revision; /* PCI revision, low byte of class word */ 305 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 306 #ifdef CONFIG_PCIEAER 307 u16 aer_cap; /* AER capability offset */ 308 struct aer_stats *aer_stats; /* AER stats for this device */ 309 #endif 310 u8 pcie_cap; /* PCIe capability offset */ 311 u8 msi_cap; /* MSI capability offset */ 312 u8 msix_cap; /* MSI-X capability offset */ 313 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 314 u8 rom_base_reg; /* Config register controlling ROM */ 315 u8 pin; /* Interrupt pin this device uses */ 316 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 317 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 318 319 struct pci_driver *driver; /* Driver bound to this device */ 320 u64 dma_mask; /* Mask of the bits of bus address this 321 device implements. Normally this is 322 0xffffffff. You only need to change 323 this if your device has broken DMA 324 or supports 64-bit transfers. */ 325 326 struct device_dma_parameters dma_parms; 327 328 pci_power_t current_state; /* Current operating state. In ACPI, 329 this is D0-D3, D0 being fully 330 functional, and D3 being off. */ 331 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 332 u8 pm_cap; /* PM capability offset */ 333 unsigned int pme_support:5; /* Bitmask of states from which PME# 334 can be generated */ 335 unsigned int pme_poll:1; /* Poll device's PME status bit */ 336 unsigned int d1_support:1; /* Low power state D1 is supported */ 337 unsigned int d2_support:1; /* Low power state D2 is supported */ 338 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 339 unsigned int no_d3cold:1; /* D3cold is forbidden */ 340 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 341 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 342 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 343 decoding during BAR sizing */ 344 unsigned int wakeup_prepared:1; 345 unsigned int runtime_d3cold:1; /* Whether go through runtime 346 D3cold, not set for devices 347 powered on/off by the 348 corresponding bridge */ 349 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 350 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 351 controlled exclusively by 352 user sysfs */ 353 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 354 bit manually */ 355 unsigned int d3_delay; /* D3->D0 transition time in ms */ 356 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 357 358 #ifdef CONFIG_PCIEASPM 359 struct pcie_link_state *link_state; /* ASPM link state */ 360 unsigned int ltr_path:1; /* Latency Tolerance Reporting 361 supported from root to here */ 362 #endif 363 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 364 365 pci_channel_state_t error_state; /* Current connectivity state */ 366 struct device dev; /* Generic device interface */ 367 368 int cfg_size; /* Size of config space */ 369 370 /* 371 * Instead of touching interrupt line and base address registers 372 * directly, use the values stored here. They might be different! 373 */ 374 unsigned int irq; 375 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 376 377 bool match_driver; /* Skip attaching driver */ 378 379 unsigned int transparent:1; /* Subtractive decode bridge */ 380 unsigned int io_window:1; /* Bridge has I/O window */ 381 unsigned int pref_window:1; /* Bridge has pref mem window */ 382 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 383 unsigned int multifunction:1; /* Multi-function device */ 384 385 unsigned int is_busmaster:1; /* Is busmaster */ 386 unsigned int no_msi:1; /* May not use MSI */ 387 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 388 unsigned int block_cfg_access:1; /* Config space access blocked */ 389 unsigned int broken_parity_status:1; /* Generates false positive parity */ 390 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 391 unsigned int msi_enabled:1; 392 unsigned int msix_enabled:1; 393 unsigned int ari_enabled:1; /* ARI forwarding */ 394 unsigned int ats_enabled:1; /* Address Translation Svc */ 395 unsigned int pasid_enabled:1; /* Process Address Space ID */ 396 unsigned int pri_enabled:1; /* Page Request Interface */ 397 unsigned int is_managed:1; 398 unsigned int needs_freset:1; /* Requires fundamental reset */ 399 unsigned int state_saved:1; 400 unsigned int is_physfn:1; 401 unsigned int is_virtfn:1; 402 unsigned int reset_fn:1; 403 unsigned int is_hotplug_bridge:1; 404 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 405 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 406 /* 407 * Devices marked being untrusted are the ones that can potentially 408 * execute DMA attacks and similar. They are typically connected 409 * through external ports such as Thunderbolt but not limited to 410 * that. When an IOMMU is enabled they should be getting full 411 * mappings to make sure they cannot access arbitrary memory. 412 */ 413 unsigned int untrusted:1; 414 unsigned int __aer_firmware_first_valid:1; 415 unsigned int __aer_firmware_first:1; 416 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 417 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 418 unsigned int irq_managed:1; 419 unsigned int has_secondary_link:1; 420 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 421 unsigned int is_probed:1; /* Device probing in progress */ 422 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 423 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 424 pci_dev_flags_t dev_flags; 425 atomic_t enable_cnt; /* pci_enable_device has been called */ 426 427 u32 saved_config_space[16]; /* Config space saved at suspend time */ 428 struct hlist_head saved_cap_space; 429 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ 430 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 431 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 432 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 433 434 #ifdef CONFIG_HOTPLUG_PCI_PCIE 435 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 436 #endif 437 #ifdef CONFIG_PCIE_PTM 438 unsigned int ptm_root:1; 439 unsigned int ptm_enabled:1; 440 u8 ptm_granularity; 441 #endif 442 #ifdef CONFIG_PCI_MSI 443 const struct attribute_group **msi_irq_groups; 444 #endif 445 struct pci_vpd *vpd; 446 #ifdef CONFIG_PCI_ATS 447 union { 448 struct pci_sriov *sriov; /* PF: SR-IOV info */ 449 struct pci_dev *physfn; /* VF: related PF */ 450 }; 451 u16 ats_cap; /* ATS Capability offset */ 452 u8 ats_stu; /* ATS Smallest Translation Unit */ 453 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ 454 #endif 455 #ifdef CONFIG_PCI_PRI 456 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 457 #endif 458 #ifdef CONFIG_PCI_PASID 459 u16 pasid_features; 460 #endif 461 #ifdef CONFIG_PCI_P2PDMA 462 struct pci_p2pdma *p2pdma; 463 #endif 464 phys_addr_t rom; /* Physical address if not from BAR */ 465 size_t romlen; /* Length if not from BAR */ 466 char *driver_override; /* Driver name to force a match */ 467 468 unsigned long priv_flags; /* Private flags for the PCI driver */ 469 }; 470 471 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 472 { 473 #ifdef CONFIG_PCI_IOV 474 if (dev->is_virtfn) 475 dev = dev->physfn; 476 #endif 477 return dev; 478 } 479 480 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 481 482 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 483 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 484 485 static inline int pci_channel_offline(struct pci_dev *pdev) 486 { 487 return (pdev->error_state != pci_channel_io_normal); 488 } 489 490 struct pci_host_bridge { 491 struct device dev; 492 struct pci_bus *bus; /* Root bus */ 493 struct pci_ops *ops; 494 void *sysdata; 495 int busnr; 496 struct list_head windows; /* resource_entry */ 497 struct list_head dma_ranges; /* dma ranges resource list */ 498 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 499 int (*map_irq)(const struct pci_dev *, u8, u8); 500 void (*release_fn)(struct pci_host_bridge *); 501 void *release_data; 502 struct msi_controller *msi; 503 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 504 unsigned int no_ext_tags:1; /* No Extended Tags */ 505 unsigned int native_aer:1; /* OS may use PCIe AER */ 506 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 507 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 508 unsigned int native_pme:1; /* OS may use PCIe PME */ 509 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 510 /* Resource alignment requirements */ 511 resource_size_t (*align_resource)(struct pci_dev *dev, 512 const struct resource *res, 513 resource_size_t start, 514 resource_size_t size, 515 resource_size_t align); 516 unsigned long private[0] ____cacheline_aligned; 517 }; 518 519 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 520 521 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 522 { 523 return (void *)bridge->private; 524 } 525 526 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 527 { 528 return container_of(priv, struct pci_host_bridge, private); 529 } 530 531 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 532 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 533 size_t priv); 534 void pci_free_host_bridge(struct pci_host_bridge *bridge); 535 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 536 537 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 538 void (*release_fn)(struct pci_host_bridge *), 539 void *release_data); 540 541 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 542 543 /* 544 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 545 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 546 * buses below host bridges or subtractive decode bridges) go in the list. 547 * Use pci_bus_for_each_resource() to iterate through all the resources. 548 */ 549 550 /* 551 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 552 * and there's no way to program the bridge with the details of the window. 553 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 554 * decode bit set, because they are explicit and can be programmed with _SRS. 555 */ 556 #define PCI_SUBTRACTIVE_DECODE 0x1 557 558 struct pci_bus_resource { 559 struct list_head list; 560 struct resource *res; 561 unsigned int flags; 562 }; 563 564 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 565 566 struct pci_bus { 567 struct list_head node; /* Node in list of buses */ 568 struct pci_bus *parent; /* Parent bus this bridge is on */ 569 struct list_head children; /* List of child buses */ 570 struct list_head devices; /* List of devices on this bus */ 571 struct pci_dev *self; /* Bridge device as seen by parent */ 572 struct list_head slots; /* List of slots on this bus; 573 protected by pci_slot_mutex */ 574 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 575 struct list_head resources; /* Address space routed to this bus */ 576 struct resource busn_res; /* Bus numbers routed to this bus */ 577 578 struct pci_ops *ops; /* Configuration access functions */ 579 struct msi_controller *msi; /* MSI controller */ 580 void *sysdata; /* Hook for sys-specific extension */ 581 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 582 583 unsigned char number; /* Bus number */ 584 unsigned char primary; /* Number of primary bridge */ 585 unsigned char max_bus_speed; /* enum pci_bus_speed */ 586 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 587 #ifdef CONFIG_PCI_DOMAINS_GENERIC 588 int domain_nr; 589 #endif 590 591 char name[48]; 592 593 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 594 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 595 struct device *bridge; 596 struct device dev; 597 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 598 struct bin_attribute *legacy_mem; /* Legacy mem */ 599 unsigned int is_added:1; 600 }; 601 602 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 603 604 static inline u16 pci_dev_id(struct pci_dev *dev) 605 { 606 return PCI_DEVID(dev->bus->number, dev->devfn); 607 } 608 609 /* 610 * Returns true if the PCI bus is root (behind host-PCI bridge), 611 * false otherwise 612 * 613 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 614 * This is incorrect because "virtual" buses added for SR-IOV (via 615 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 616 */ 617 static inline bool pci_is_root_bus(struct pci_bus *pbus) 618 { 619 return !(pbus->parent); 620 } 621 622 /** 623 * pci_is_bridge - check if the PCI device is a bridge 624 * @dev: PCI device 625 * 626 * Return true if the PCI device is bridge whether it has subordinate 627 * or not. 628 */ 629 static inline bool pci_is_bridge(struct pci_dev *dev) 630 { 631 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 632 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 633 } 634 635 #define for_each_pci_bridge(dev, bus) \ 636 list_for_each_entry(dev, &bus->devices, bus_list) \ 637 if (!pci_is_bridge(dev)) {} else 638 639 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 640 { 641 dev = pci_physfn(dev); 642 if (pci_is_root_bus(dev->bus)) 643 return NULL; 644 645 return dev->bus->self; 646 } 647 648 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 649 void pci_put_host_bridge_device(struct device *dev); 650 651 #ifdef CONFIG_PCI_MSI 652 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 653 { 654 return pci_dev->msi_enabled || pci_dev->msix_enabled; 655 } 656 #else 657 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 658 #endif 659 660 /* Error values that may be returned by PCI functions */ 661 #define PCIBIOS_SUCCESSFUL 0x00 662 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 663 #define PCIBIOS_BAD_VENDOR_ID 0x83 664 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 665 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 666 #define PCIBIOS_SET_FAILED 0x88 667 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 668 669 /* Translate above to generic errno for passing back through non-PCI code */ 670 static inline int pcibios_err_to_errno(int err) 671 { 672 if (err <= PCIBIOS_SUCCESSFUL) 673 return err; /* Assume already errno */ 674 675 switch (err) { 676 case PCIBIOS_FUNC_NOT_SUPPORTED: 677 return -ENOENT; 678 case PCIBIOS_BAD_VENDOR_ID: 679 return -ENOTTY; 680 case PCIBIOS_DEVICE_NOT_FOUND: 681 return -ENODEV; 682 case PCIBIOS_BAD_REGISTER_NUMBER: 683 return -EFAULT; 684 case PCIBIOS_SET_FAILED: 685 return -EIO; 686 case PCIBIOS_BUFFER_TOO_SMALL: 687 return -ENOSPC; 688 } 689 690 return -ERANGE; 691 } 692 693 /* Low-level architecture-dependent routines */ 694 695 struct pci_ops { 696 int (*add_bus)(struct pci_bus *bus); 697 void (*remove_bus)(struct pci_bus *bus); 698 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 699 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 700 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 701 }; 702 703 /* 704 * ACPI needs to be able to access PCI config space before we've done a 705 * PCI bus scan and created pci_bus structures. 706 */ 707 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 708 int reg, int len, u32 *val); 709 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 710 int reg, int len, u32 val); 711 712 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 713 typedef u64 pci_bus_addr_t; 714 #else 715 typedef u32 pci_bus_addr_t; 716 #endif 717 718 struct pci_bus_region { 719 pci_bus_addr_t start; 720 pci_bus_addr_t end; 721 }; 722 723 struct pci_dynids { 724 spinlock_t lock; /* Protects list, index */ 725 struct list_head list; /* For IDs added at runtime */ 726 }; 727 728 729 /* 730 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 731 * a set of callbacks in struct pci_error_handlers, that device driver 732 * will be notified of PCI bus errors, and will be driven to recovery 733 * when an error occurs. 734 */ 735 736 typedef unsigned int __bitwise pci_ers_result_t; 737 738 enum pci_ers_result { 739 /* No result/none/not supported in device driver */ 740 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 741 742 /* Device driver can recover without slot reset */ 743 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 744 745 /* Device driver wants slot to be reset */ 746 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 747 748 /* Device has completely failed, is unrecoverable */ 749 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 750 751 /* Device driver is fully recovered and operational */ 752 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 753 754 /* No AER capabilities registered for the driver */ 755 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 756 }; 757 758 /* PCI bus error event callbacks */ 759 struct pci_error_handlers { 760 /* PCI bus error detected on this device */ 761 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 762 enum pci_channel_state error); 763 764 /* MMIO has been re-enabled, but not DMA */ 765 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 766 767 /* PCI slot has been reset */ 768 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 769 770 /* PCI function reset prepare or completed */ 771 void (*reset_prepare)(struct pci_dev *dev); 772 void (*reset_done)(struct pci_dev *dev); 773 774 /* Device driver may resume normal operations */ 775 void (*resume)(struct pci_dev *dev); 776 }; 777 778 779 struct module; 780 781 /** 782 * struct pci_driver - PCI driver structure 783 * @node: List of driver structures. 784 * @name: Driver name. 785 * @id_table: Pointer to table of device IDs the driver is 786 * interested in. Most drivers should export this 787 * table using MODULE_DEVICE_TABLE(pci,...). 788 * @probe: This probing function gets called (during execution 789 * of pci_register_driver() for already existing 790 * devices or later if a new device gets inserted) for 791 * all PCI devices which match the ID table and are not 792 * "owned" by the other drivers yet. This function gets 793 * passed a "struct pci_dev \*" for each device whose 794 * entry in the ID table matches the device. The probe 795 * function returns zero when the driver chooses to 796 * take "ownership" of the device or an error code 797 * (negative number) otherwise. 798 * The probe function always gets called from process 799 * context, so it can sleep. 800 * @remove: The remove() function gets called whenever a device 801 * being handled by this driver is removed (either during 802 * deregistration of the driver or when it's manually 803 * pulled out of a hot-pluggable slot). 804 * The remove function always gets called from process 805 * context, so it can sleep. 806 * @suspend: Put device into low power state. 807 * @suspend_late: Put device into low power state. 808 * @resume_early: Wake device from low power state. 809 * @resume: Wake device from low power state. 810 * (Please see Documentation/power/pci.rst for descriptions 811 * of PCI Power Management and the related functions.) 812 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 813 * Intended to stop any idling DMA operations. 814 * Useful for enabling wake-on-lan (NIC) or changing 815 * the power state of a device before reboot. 816 * e.g. drivers/net/e100.c. 817 * @sriov_configure: Optional driver callback to allow configuration of 818 * number of VFs to enable via sysfs "sriov_numvfs" file. 819 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 820 * @groups: Sysfs attribute groups. 821 * @driver: Driver model structure. 822 * @dynids: List of dynamically added device IDs. 823 */ 824 struct pci_driver { 825 struct list_head node; 826 const char *name; 827 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 828 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 829 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 830 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 831 int (*suspend_late)(struct pci_dev *dev, pm_message_t state); 832 int (*resume_early)(struct pci_dev *dev); 833 int (*resume)(struct pci_dev *dev); /* Device woken up */ 834 void (*shutdown)(struct pci_dev *dev); 835 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 836 const struct pci_error_handlers *err_handler; 837 const struct attribute_group **groups; 838 struct device_driver driver; 839 struct pci_dynids dynids; 840 }; 841 842 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 843 844 /** 845 * PCI_DEVICE - macro used to describe a specific PCI device 846 * @vend: the 16 bit PCI Vendor ID 847 * @dev: the 16 bit PCI Device ID 848 * 849 * This macro is used to create a struct pci_device_id that matches a 850 * specific device. The subvendor and subdevice fields will be set to 851 * PCI_ANY_ID. 852 */ 853 #define PCI_DEVICE(vend,dev) \ 854 .vendor = (vend), .device = (dev), \ 855 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 856 857 /** 858 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 859 * @vend: the 16 bit PCI Vendor ID 860 * @dev: the 16 bit PCI Device ID 861 * @subvend: the 16 bit PCI Subvendor ID 862 * @subdev: the 16 bit PCI Subdevice ID 863 * 864 * This macro is used to create a struct pci_device_id that matches a 865 * specific device with subsystem information. 866 */ 867 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 868 .vendor = (vend), .device = (dev), \ 869 .subvendor = (subvend), .subdevice = (subdev) 870 871 /** 872 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 873 * @dev_class: the class, subclass, prog-if triple for this device 874 * @dev_class_mask: the class mask for this device 875 * 876 * This macro is used to create a struct pci_device_id that matches a 877 * specific PCI class. The vendor, device, subvendor, and subdevice 878 * fields will be set to PCI_ANY_ID. 879 */ 880 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 881 .class = (dev_class), .class_mask = (dev_class_mask), \ 882 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 883 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 884 885 /** 886 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 887 * @vend: the vendor name 888 * @dev: the 16 bit PCI Device ID 889 * 890 * This macro is used to create a struct pci_device_id that matches a 891 * specific PCI device. The subvendor, and subdevice fields will be set 892 * to PCI_ANY_ID. The macro allows the next field to follow as the device 893 * private data. 894 */ 895 #define PCI_VDEVICE(vend, dev) \ 896 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 897 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 898 899 /** 900 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 901 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 902 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 903 * @data: the driver data to be filled 904 * 905 * This macro is used to create a struct pci_device_id that matches a 906 * specific PCI device. The subvendor, and subdevice fields will be set 907 * to PCI_ANY_ID. 908 */ 909 #define PCI_DEVICE_DATA(vend, dev, data) \ 910 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 911 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 912 .driver_data = (kernel_ulong_t)(data) 913 914 enum { 915 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 916 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 917 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 918 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 919 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 920 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 921 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 922 }; 923 924 /* These external functions are only available when PCI support is enabled */ 925 #ifdef CONFIG_PCI 926 927 extern unsigned int pci_flags; 928 929 static inline void pci_set_flags(int flags) { pci_flags = flags; } 930 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 931 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 932 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 933 934 void pcie_bus_configure_settings(struct pci_bus *bus); 935 936 enum pcie_bus_config_types { 937 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 938 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 939 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 940 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 941 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 942 }; 943 944 extern enum pcie_bus_config_types pcie_bus_config; 945 946 extern struct bus_type pci_bus_type; 947 948 /* Do NOT directly access these two variables, unless you are arch-specific PCI 949 * code, or PCI core code. */ 950 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 951 /* Some device drivers need know if PCI is initiated */ 952 int no_pci_devices(void); 953 954 void pcibios_resource_survey_bus(struct pci_bus *bus); 955 void pcibios_bus_add_device(struct pci_dev *pdev); 956 void pcibios_add_bus(struct pci_bus *bus); 957 void pcibios_remove_bus(struct pci_bus *bus); 958 void pcibios_fixup_bus(struct pci_bus *); 959 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 960 /* Architecture-specific versions may override this (weak) */ 961 char *pcibios_setup(char *str); 962 963 /* Used only when drivers/pci/setup.c is used */ 964 resource_size_t pcibios_align_resource(void *, const struct resource *, 965 resource_size_t, 966 resource_size_t); 967 968 /* Weak but can be overriden by arch */ 969 void pci_fixup_cardbus(struct pci_bus *); 970 971 /* Generic PCI functions used internally */ 972 973 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 974 struct resource *res); 975 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 976 struct pci_bus_region *region); 977 void pcibios_scan_specific_bus(int busn); 978 struct pci_bus *pci_find_bus(int domain, int busnr); 979 void pci_bus_add_devices(const struct pci_bus *bus); 980 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 981 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 982 struct pci_ops *ops, void *sysdata, 983 struct list_head *resources); 984 int pci_host_probe(struct pci_host_bridge *bridge); 985 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 986 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 987 void pci_bus_release_busn_res(struct pci_bus *b); 988 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 989 struct pci_ops *ops, void *sysdata, 990 struct list_head *resources); 991 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 992 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 993 int busnr); 994 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 995 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 996 const char *name, 997 struct hotplug_slot *hotplug); 998 void pci_destroy_slot(struct pci_slot *slot); 999 #ifdef CONFIG_SYSFS 1000 void pci_dev_assign_slot(struct pci_dev *dev); 1001 #else 1002 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1003 #endif 1004 int pci_scan_slot(struct pci_bus *bus, int devfn); 1005 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1006 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1007 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1008 void pci_bus_add_device(struct pci_dev *dev); 1009 void pci_read_bridge_bases(struct pci_bus *child); 1010 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1011 struct resource *res); 1012 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 1013 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1014 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1015 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1016 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1017 void pci_dev_put(struct pci_dev *dev); 1018 void pci_remove_bus(struct pci_bus *b); 1019 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1020 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1021 void pci_stop_root_bus(struct pci_bus *bus); 1022 void pci_remove_root_bus(struct pci_bus *bus); 1023 void pci_setup_cardbus(struct pci_bus *bus); 1024 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1025 void pci_sort_breadthfirst(void); 1026 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1027 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1028 1029 /* Generic PCI functions exported to card drivers */ 1030 1031 enum pci_lost_interrupt_reason { 1032 PCI_LOST_IRQ_NO_INFORMATION = 0, 1033 PCI_LOST_IRQ_DISABLE_MSI, 1034 PCI_LOST_IRQ_DISABLE_MSIX, 1035 PCI_LOST_IRQ_DISABLE_ACPI, 1036 }; 1037 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 1038 int pci_find_capability(struct pci_dev *dev, int cap); 1039 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1040 int pci_find_ext_capability(struct pci_dev *dev, int cap); 1041 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 1042 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1043 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 1044 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1045 1046 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1047 struct pci_dev *from); 1048 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1049 unsigned int ss_vendor, unsigned int ss_device, 1050 struct pci_dev *from); 1051 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1052 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1053 unsigned int devfn); 1054 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1055 int pci_dev_present(const struct pci_device_id *ids); 1056 1057 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1058 int where, u8 *val); 1059 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1060 int where, u16 *val); 1061 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1062 int where, u32 *val); 1063 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1064 int where, u8 val); 1065 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1066 int where, u16 val); 1067 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1068 int where, u32 val); 1069 1070 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1071 int where, int size, u32 *val); 1072 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1073 int where, int size, u32 val); 1074 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1075 int where, int size, u32 *val); 1076 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1077 int where, int size, u32 val); 1078 1079 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1080 1081 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1082 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1083 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1084 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1085 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1086 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1087 1088 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1089 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1090 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1091 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1092 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1093 u16 clear, u16 set); 1094 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1095 u32 clear, u32 set); 1096 1097 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1098 u16 set) 1099 { 1100 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1101 } 1102 1103 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1104 u32 set) 1105 { 1106 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1107 } 1108 1109 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1110 u16 clear) 1111 { 1112 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1113 } 1114 1115 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1116 u32 clear) 1117 { 1118 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1119 } 1120 1121 /* User-space driven config access */ 1122 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1123 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1124 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1125 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1126 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1127 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1128 1129 int __must_check pci_enable_device(struct pci_dev *dev); 1130 int __must_check pci_enable_device_io(struct pci_dev *dev); 1131 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1132 int __must_check pci_reenable_device(struct pci_dev *); 1133 int __must_check pcim_enable_device(struct pci_dev *pdev); 1134 void pcim_pin_device(struct pci_dev *pdev); 1135 1136 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1137 { 1138 /* 1139 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1140 * writable and no quirk has marked the feature broken. 1141 */ 1142 return !pdev->broken_intx_masking; 1143 } 1144 1145 static inline int pci_is_enabled(struct pci_dev *pdev) 1146 { 1147 return (atomic_read(&pdev->enable_cnt) > 0); 1148 } 1149 1150 static inline int pci_is_managed(struct pci_dev *pdev) 1151 { 1152 return pdev->is_managed; 1153 } 1154 1155 void pci_disable_device(struct pci_dev *dev); 1156 1157 extern unsigned int pcibios_max_latency; 1158 void pci_set_master(struct pci_dev *dev); 1159 void pci_clear_master(struct pci_dev *dev); 1160 1161 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1162 int pci_set_cacheline_size(struct pci_dev *dev); 1163 #define HAVE_PCI_SET_MWI 1164 int __must_check pci_set_mwi(struct pci_dev *dev); 1165 int __must_check pcim_set_mwi(struct pci_dev *dev); 1166 int pci_try_set_mwi(struct pci_dev *dev); 1167 void pci_clear_mwi(struct pci_dev *dev); 1168 void pci_intx(struct pci_dev *dev, int enable); 1169 bool pci_check_and_mask_intx(struct pci_dev *dev); 1170 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1171 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1172 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1173 int pcix_get_max_mmrbc(struct pci_dev *dev); 1174 int pcix_get_mmrbc(struct pci_dev *dev); 1175 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1176 int pcie_get_readrq(struct pci_dev *dev); 1177 int pcie_set_readrq(struct pci_dev *dev, int rq); 1178 int pcie_get_mps(struct pci_dev *dev); 1179 int pcie_set_mps(struct pci_dev *dev, int mps); 1180 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1181 enum pci_bus_speed *speed, 1182 enum pcie_link_width *width); 1183 void pcie_print_link_status(struct pci_dev *dev); 1184 bool pcie_has_flr(struct pci_dev *dev); 1185 int pcie_flr(struct pci_dev *dev); 1186 int __pci_reset_function_locked(struct pci_dev *dev); 1187 int pci_reset_function(struct pci_dev *dev); 1188 int pci_reset_function_locked(struct pci_dev *dev); 1189 int pci_try_reset_function(struct pci_dev *dev); 1190 int pci_probe_reset_slot(struct pci_slot *slot); 1191 int pci_probe_reset_bus(struct pci_bus *bus); 1192 int pci_reset_bus(struct pci_dev *dev); 1193 void pci_reset_secondary_bus(struct pci_dev *dev); 1194 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1195 void pci_update_resource(struct pci_dev *dev, int resno); 1196 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1197 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1198 void pci_release_resource(struct pci_dev *dev, int resno); 1199 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1200 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1201 bool pci_device_is_present(struct pci_dev *pdev); 1202 void pci_ignore_hotplug(struct pci_dev *dev); 1203 1204 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1205 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1206 const char *fmt, ...); 1207 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1208 1209 /* ROM control related routines */ 1210 int pci_enable_rom(struct pci_dev *pdev); 1211 void pci_disable_rom(struct pci_dev *pdev); 1212 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1213 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1214 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1215 1216 /* Power management related routines */ 1217 int pci_save_state(struct pci_dev *dev); 1218 void pci_restore_state(struct pci_dev *dev); 1219 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1220 int pci_load_saved_state(struct pci_dev *dev, 1221 struct pci_saved_state *state); 1222 int pci_load_and_free_saved_state(struct pci_dev *dev, 1223 struct pci_saved_state **state); 1224 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1225 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1226 u16 cap); 1227 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1228 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1229 u16 cap, unsigned int size); 1230 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1231 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1232 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1233 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1234 void pci_pme_active(struct pci_dev *dev, bool enable); 1235 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1236 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1237 int pci_prepare_to_sleep(struct pci_dev *dev); 1238 int pci_back_from_sleep(struct pci_dev *dev); 1239 bool pci_dev_run_wake(struct pci_dev *dev); 1240 bool pci_check_pme_status(struct pci_dev *dev); 1241 void pci_pme_wakeup_bus(struct pci_bus *bus); 1242 void pci_d3cold_enable(struct pci_dev *dev); 1243 void pci_d3cold_disable(struct pci_dev *dev); 1244 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1245 void pci_wakeup_bus(struct pci_bus *bus); 1246 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1247 1248 /* PCI Virtual Channel */ 1249 int pci_save_vc_state(struct pci_dev *dev); 1250 void pci_restore_vc_state(struct pci_dev *dev); 1251 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1252 1253 /* For use by arch with custom probe code */ 1254 void set_pcie_port_type(struct pci_dev *pdev); 1255 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1256 1257 /* Functions for PCI Hotplug drivers to use */ 1258 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1259 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1260 unsigned int pci_rescan_bus(struct pci_bus *bus); 1261 void pci_lock_rescan_remove(void); 1262 void pci_unlock_rescan_remove(void); 1263 1264 /* Vital Product Data routines */ 1265 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1266 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1267 int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1268 1269 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1270 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1271 void pci_bus_assign_resources(const struct pci_bus *bus); 1272 void pci_bus_claim_resources(struct pci_bus *bus); 1273 void pci_bus_size_bridges(struct pci_bus *bus); 1274 int pci_claim_resource(struct pci_dev *, int); 1275 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1276 void pci_assign_unassigned_resources(void); 1277 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1278 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1279 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1280 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1281 void pdev_enable_device(struct pci_dev *); 1282 int pci_enable_resources(struct pci_dev *, int mask); 1283 void pci_assign_irq(struct pci_dev *dev); 1284 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1285 #define HAVE_PCI_REQ_REGIONS 2 1286 int __must_check pci_request_regions(struct pci_dev *, const char *); 1287 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1288 void pci_release_regions(struct pci_dev *); 1289 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1290 void pci_release_region(struct pci_dev *, int); 1291 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1292 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1293 void pci_release_selected_regions(struct pci_dev *, int); 1294 1295 /* drivers/pci/bus.c */ 1296 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1297 void pci_bus_put(struct pci_bus *bus); 1298 void pci_add_resource(struct list_head *resources, struct resource *res); 1299 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1300 resource_size_t offset); 1301 void pci_free_resource_list(struct list_head *resources); 1302 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1303 unsigned int flags); 1304 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1305 void pci_bus_remove_resources(struct pci_bus *bus); 1306 int devm_request_pci_bus_resources(struct device *dev, 1307 struct list_head *resources); 1308 1309 /* Temporary until new and working PCI SBR API in place */ 1310 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1311 1312 #define pci_bus_for_each_resource(bus, res, i) \ 1313 for (i = 0; \ 1314 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1315 i++) 1316 1317 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1318 struct resource *res, resource_size_t size, 1319 resource_size_t align, resource_size_t min, 1320 unsigned long type_mask, 1321 resource_size_t (*alignf)(void *, 1322 const struct resource *, 1323 resource_size_t, 1324 resource_size_t), 1325 void *alignf_data); 1326 1327 1328 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1329 resource_size_t size); 1330 unsigned long pci_address_to_pio(phys_addr_t addr); 1331 phys_addr_t pci_pio_to_address(unsigned long pio); 1332 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1333 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1334 phys_addr_t phys_addr); 1335 void pci_unmap_iospace(struct resource *res); 1336 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1337 resource_size_t offset, 1338 resource_size_t size); 1339 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1340 struct resource *res); 1341 1342 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1343 { 1344 struct pci_bus_region region; 1345 1346 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1347 return region.start; 1348 } 1349 1350 /* Proper probing supporting hot-pluggable devices */ 1351 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1352 const char *mod_name); 1353 1354 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1355 #define pci_register_driver(driver) \ 1356 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1357 1358 void pci_unregister_driver(struct pci_driver *dev); 1359 1360 /** 1361 * module_pci_driver() - Helper macro for registering a PCI driver 1362 * @__pci_driver: pci_driver struct 1363 * 1364 * Helper macro for PCI drivers which do not do anything special in module 1365 * init/exit. This eliminates a lot of boilerplate. Each module may only 1366 * use this macro once, and calling it replaces module_init() and module_exit() 1367 */ 1368 #define module_pci_driver(__pci_driver) \ 1369 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1370 1371 /** 1372 * builtin_pci_driver() - Helper macro for registering a PCI driver 1373 * @__pci_driver: pci_driver struct 1374 * 1375 * Helper macro for PCI drivers which do not do anything special in their 1376 * init code. This eliminates a lot of boilerplate. Each driver may only 1377 * use this macro once, and calling it replaces device_initcall(...) 1378 */ 1379 #define builtin_pci_driver(__pci_driver) \ 1380 builtin_driver(__pci_driver, pci_register_driver) 1381 1382 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1383 int pci_add_dynid(struct pci_driver *drv, 1384 unsigned int vendor, unsigned int device, 1385 unsigned int subvendor, unsigned int subdevice, 1386 unsigned int class, unsigned int class_mask, 1387 unsigned long driver_data); 1388 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1389 struct pci_dev *dev); 1390 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1391 int pass); 1392 1393 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1394 void *userdata); 1395 int pci_cfg_space_size(struct pci_dev *dev); 1396 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1397 void pci_setup_bridge(struct pci_bus *bus); 1398 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1399 unsigned long type); 1400 1401 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1402 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1403 1404 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1405 unsigned int command_bits, u32 flags); 1406 1407 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1408 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1409 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1410 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1411 #define PCI_IRQ_ALL_TYPES \ 1412 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1413 1414 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1415 1416 #include <linux/dmapool.h> 1417 1418 #define pci_pool dma_pool 1419 #define pci_pool_create(name, pdev, size, align, allocation) \ 1420 dma_pool_create(name, &pdev->dev, size, align, allocation) 1421 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1422 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1423 #define pci_pool_zalloc(pool, flags, handle) \ 1424 dma_pool_zalloc(pool, flags, handle) 1425 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1426 1427 struct msix_entry { 1428 u32 vector; /* Kernel uses to write allocated vector */ 1429 u16 entry; /* Driver uses to specify entry, OS writes */ 1430 }; 1431 1432 #ifdef CONFIG_PCI_MSI 1433 int pci_msi_vec_count(struct pci_dev *dev); 1434 void pci_disable_msi(struct pci_dev *dev); 1435 int pci_msix_vec_count(struct pci_dev *dev); 1436 void pci_disable_msix(struct pci_dev *dev); 1437 void pci_restore_msi_state(struct pci_dev *dev); 1438 int pci_msi_enabled(void); 1439 int pci_enable_msi(struct pci_dev *dev); 1440 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1441 int minvec, int maxvec); 1442 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1443 struct msix_entry *entries, int nvec) 1444 { 1445 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1446 if (rc < 0) 1447 return rc; 1448 return 0; 1449 } 1450 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1451 unsigned int max_vecs, unsigned int flags, 1452 struct irq_affinity *affd); 1453 1454 void pci_free_irq_vectors(struct pci_dev *dev); 1455 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1456 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1457 int pci_irq_get_node(struct pci_dev *pdev, int vec); 1458 1459 #else 1460 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1461 static inline void pci_disable_msi(struct pci_dev *dev) { } 1462 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1463 static inline void pci_disable_msix(struct pci_dev *dev) { } 1464 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1465 static inline int pci_msi_enabled(void) { return 0; } 1466 static inline int pci_enable_msi(struct pci_dev *dev) 1467 { return -ENOSYS; } 1468 static inline int pci_enable_msix_range(struct pci_dev *dev, 1469 struct msix_entry *entries, int minvec, int maxvec) 1470 { return -ENOSYS; } 1471 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1472 struct msix_entry *entries, int nvec) 1473 { return -ENOSYS; } 1474 1475 static inline int 1476 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1477 unsigned int max_vecs, unsigned int flags, 1478 struct irq_affinity *aff_desc) 1479 { 1480 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1481 return 1; 1482 return -ENOSPC; 1483 } 1484 1485 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1486 { 1487 } 1488 1489 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1490 { 1491 if (WARN_ON_ONCE(nr > 0)) 1492 return -EINVAL; 1493 return dev->irq; 1494 } 1495 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1496 int vec) 1497 { 1498 return cpu_possible_mask; 1499 } 1500 1501 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) 1502 { 1503 return first_online_node; 1504 } 1505 #endif 1506 1507 static inline int 1508 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1509 unsigned int max_vecs, unsigned int flags) 1510 { 1511 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1512 NULL); 1513 } 1514 1515 /** 1516 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1517 * @d: the INTx IRQ domain 1518 * @node: the DT node for the device whose interrupt we're translating 1519 * @intspec: the interrupt specifier data from the DT 1520 * @intsize: the number of entries in @intspec 1521 * @out_hwirq: pointer at which to write the hwirq number 1522 * @out_type: pointer at which to write the interrupt type 1523 * 1524 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1525 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1526 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1527 * INTx value to obtain the hwirq number. 1528 * 1529 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1530 */ 1531 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1532 struct device_node *node, 1533 const u32 *intspec, 1534 unsigned int intsize, 1535 unsigned long *out_hwirq, 1536 unsigned int *out_type) 1537 { 1538 const u32 intx = intspec[0]; 1539 1540 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1541 return -EINVAL; 1542 1543 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1544 return 0; 1545 } 1546 1547 #ifdef CONFIG_PCIEPORTBUS 1548 extern bool pcie_ports_disabled; 1549 extern bool pcie_ports_native; 1550 #else 1551 #define pcie_ports_disabled true 1552 #define pcie_ports_native false 1553 #endif 1554 1555 #ifdef CONFIG_PCIEASPM 1556 bool pcie_aspm_support_enabled(void); 1557 #else 1558 static inline bool pcie_aspm_support_enabled(void) { return false; } 1559 #endif 1560 1561 #ifdef CONFIG_PCIEAER 1562 bool pci_aer_available(void); 1563 #else 1564 static inline bool pci_aer_available(void) { return false; } 1565 #endif 1566 1567 #ifdef CONFIG_PCIE_ECRC 1568 void pcie_set_ecrc_checking(struct pci_dev *dev); 1569 void pcie_ecrc_get_policy(char *str); 1570 #else 1571 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1572 static inline void pcie_ecrc_get_policy(char *str) { } 1573 #endif 1574 1575 bool pci_ats_disabled(void); 1576 1577 #ifdef CONFIG_PCIE_PTM 1578 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1579 #else 1580 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1581 { return -EINVAL; } 1582 #endif 1583 1584 void pci_cfg_access_lock(struct pci_dev *dev); 1585 bool pci_cfg_access_trylock(struct pci_dev *dev); 1586 void pci_cfg_access_unlock(struct pci_dev *dev); 1587 1588 /* 1589 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1590 * a PCI domain is defined to be a set of PCI buses which share 1591 * configuration space. 1592 */ 1593 #ifdef CONFIG_PCI_DOMAINS 1594 extern int pci_domains_supported; 1595 #else 1596 enum { pci_domains_supported = 0 }; 1597 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1598 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1599 #endif /* CONFIG_PCI_DOMAINS */ 1600 1601 /* 1602 * Generic implementation for PCI domain support. If your 1603 * architecture does not need custom management of PCI 1604 * domains then this implementation will be used 1605 */ 1606 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1607 static inline int pci_domain_nr(struct pci_bus *bus) 1608 { 1609 return bus->domain_nr; 1610 } 1611 #ifdef CONFIG_ACPI 1612 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1613 #else 1614 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1615 { return 0; } 1616 #endif 1617 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1618 #endif 1619 1620 /* Some architectures require additional setup to direct VGA traffic */ 1621 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1622 unsigned int command_bits, u32 flags); 1623 void pci_register_set_vga_state(arch_set_vga_state_t func); 1624 1625 static inline int 1626 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1627 { 1628 return pci_request_selected_regions(pdev, 1629 pci_select_bars(pdev, IORESOURCE_IO), name); 1630 } 1631 1632 static inline void 1633 pci_release_io_regions(struct pci_dev *pdev) 1634 { 1635 return pci_release_selected_regions(pdev, 1636 pci_select_bars(pdev, IORESOURCE_IO)); 1637 } 1638 1639 static inline int 1640 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1641 { 1642 return pci_request_selected_regions(pdev, 1643 pci_select_bars(pdev, IORESOURCE_MEM), name); 1644 } 1645 1646 static inline void 1647 pci_release_mem_regions(struct pci_dev *pdev) 1648 { 1649 return pci_release_selected_regions(pdev, 1650 pci_select_bars(pdev, IORESOURCE_MEM)); 1651 } 1652 1653 #else /* CONFIG_PCI is not enabled */ 1654 1655 static inline void pci_set_flags(int flags) { } 1656 static inline void pci_add_flags(int flags) { } 1657 static inline void pci_clear_flags(int flags) { } 1658 static inline int pci_has_flag(int flag) { return 0; } 1659 1660 /* 1661 * If the system does not have PCI, clearly these return errors. Define 1662 * these as simple inline functions to avoid hair in drivers. 1663 */ 1664 #define _PCI_NOP(o, s, t) \ 1665 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1666 int where, t val) \ 1667 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1668 1669 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1670 _PCI_NOP(o, word, u16 x) \ 1671 _PCI_NOP(o, dword, u32 x) 1672 _PCI_NOP_ALL(read, *) 1673 _PCI_NOP_ALL(write,) 1674 1675 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1676 unsigned int device, 1677 struct pci_dev *from) 1678 { return NULL; } 1679 1680 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1681 unsigned int device, 1682 unsigned int ss_vendor, 1683 unsigned int ss_device, 1684 struct pci_dev *from) 1685 { return NULL; } 1686 1687 static inline struct pci_dev *pci_get_class(unsigned int class, 1688 struct pci_dev *from) 1689 { return NULL; } 1690 1691 #define pci_dev_present(ids) (0) 1692 #define no_pci_devices() (1) 1693 #define pci_dev_put(dev) do { } while (0) 1694 1695 static inline void pci_set_master(struct pci_dev *dev) { } 1696 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1697 static inline void pci_disable_device(struct pci_dev *dev) { } 1698 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1699 { return -EBUSY; } 1700 static inline int __pci_register_driver(struct pci_driver *drv, 1701 struct module *owner) 1702 { return 0; } 1703 static inline int pci_register_driver(struct pci_driver *drv) 1704 { return 0; } 1705 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1706 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1707 { return 0; } 1708 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1709 int cap) 1710 { return 0; } 1711 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1712 { return 0; } 1713 1714 /* Power management related routines */ 1715 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1716 static inline void pci_restore_state(struct pci_dev *dev) { } 1717 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1718 { return 0; } 1719 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1720 { return 0; } 1721 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1722 pm_message_t state) 1723 { return PCI_D0; } 1724 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1725 int enable) 1726 { return 0; } 1727 1728 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1729 struct resource *res) 1730 { return NULL; } 1731 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1732 { return -EIO; } 1733 static inline void pci_release_regions(struct pci_dev *dev) { } 1734 1735 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1736 1737 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1738 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1739 { return 0; } 1740 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1741 1742 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1743 { return NULL; } 1744 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1745 unsigned int devfn) 1746 { return NULL; } 1747 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1748 unsigned int bus, unsigned int devfn) 1749 { return NULL; } 1750 1751 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1752 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1753 1754 #define dev_is_pci(d) (false) 1755 #define dev_is_pf(d) (false) 1756 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1757 { return false; } 1758 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1759 struct device_node *node, 1760 const u32 *intspec, 1761 unsigned int intsize, 1762 unsigned long *out_hwirq, 1763 unsigned int *out_type) 1764 { return -EINVAL; } 1765 1766 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1767 struct pci_dev *dev) 1768 { return NULL; } 1769 static inline bool pci_ats_disabled(void) { return true; } 1770 #endif /* CONFIG_PCI */ 1771 1772 #ifdef CONFIG_PCI_ATS 1773 /* Address Translation Service */ 1774 void pci_ats_init(struct pci_dev *dev); 1775 int pci_enable_ats(struct pci_dev *dev, int ps); 1776 void pci_disable_ats(struct pci_dev *dev); 1777 int pci_ats_queue_depth(struct pci_dev *dev); 1778 int pci_ats_page_aligned(struct pci_dev *dev); 1779 #else 1780 static inline void pci_ats_init(struct pci_dev *d) { } 1781 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1782 static inline void pci_disable_ats(struct pci_dev *d) { } 1783 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1784 static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; } 1785 #endif 1786 1787 /* Include architecture-dependent settings and functions */ 1788 1789 #include <asm/pci.h> 1790 1791 /* These two functions provide almost identical functionality. Depennding 1792 * on the architecture, one will be implemented as a wrapper around the 1793 * other (in drivers/pci/mmap.c). 1794 * 1795 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1796 * is expected to be an offset within that region. 1797 * 1798 * pci_mmap_page_range() is the legacy architecture-specific interface, 1799 * which accepts a "user visible" resource address converted by 1800 * pci_resource_to_user(), as used in the legacy mmap() interface in 1801 * /proc/bus/pci/. 1802 */ 1803 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1804 struct vm_area_struct *vma, 1805 enum pci_mmap_state mmap_state, int write_combine); 1806 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1807 struct vm_area_struct *vma, 1808 enum pci_mmap_state mmap_state, int write_combine); 1809 1810 #ifndef arch_can_pci_mmap_wc 1811 #define arch_can_pci_mmap_wc() 0 1812 #endif 1813 1814 #ifndef arch_can_pci_mmap_io 1815 #define arch_can_pci_mmap_io() 0 1816 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1817 #else 1818 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1819 #endif 1820 1821 #ifndef pci_root_bus_fwnode 1822 #define pci_root_bus_fwnode(bus) NULL 1823 #endif 1824 1825 /* 1826 * These helpers provide future and backwards compatibility 1827 * for accessing popular PCI BAR info 1828 */ 1829 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1830 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1831 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1832 #define pci_resource_len(dev,bar) \ 1833 ((pci_resource_start((dev), (bar)) == 0 && \ 1834 pci_resource_end((dev), (bar)) == \ 1835 pci_resource_start((dev), (bar))) ? 0 : \ 1836 \ 1837 (pci_resource_end((dev), (bar)) - \ 1838 pci_resource_start((dev), (bar)) + 1)) 1839 1840 /* 1841 * Similar to the helpers above, these manipulate per-pci_dev 1842 * driver-specific data. They are really just a wrapper around 1843 * the generic device structure functions of these calls. 1844 */ 1845 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1846 { 1847 return dev_get_drvdata(&pdev->dev); 1848 } 1849 1850 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1851 { 1852 dev_set_drvdata(&pdev->dev, data); 1853 } 1854 1855 static inline const char *pci_name(const struct pci_dev *pdev) 1856 { 1857 return dev_name(&pdev->dev); 1858 } 1859 1860 1861 /* 1862 * Some archs don't want to expose struct resource to userland as-is 1863 * in sysfs and /proc 1864 */ 1865 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1866 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1867 const struct resource *rsrc, 1868 resource_size_t *start, resource_size_t *end); 1869 #else 1870 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1871 const struct resource *rsrc, resource_size_t *start, 1872 resource_size_t *end) 1873 { 1874 *start = rsrc->start; 1875 *end = rsrc->end; 1876 } 1877 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1878 1879 1880 /* 1881 * The world is not perfect and supplies us with broken PCI devices. 1882 * For at least a part of these bugs we need a work-around, so both 1883 * generic (drivers/pci/quirks.c) and per-architecture code can define 1884 * fixup hooks to be called for particular buggy devices. 1885 */ 1886 1887 struct pci_fixup { 1888 u16 vendor; /* Or PCI_ANY_ID */ 1889 u16 device; /* Or PCI_ANY_ID */ 1890 u32 class; /* Or PCI_ANY_ID */ 1891 unsigned int class_shift; /* should be 0, 8, 16 */ 1892 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1893 int hook_offset; 1894 #else 1895 void (*hook)(struct pci_dev *dev); 1896 #endif 1897 }; 1898 1899 enum pci_fixup_pass { 1900 pci_fixup_early, /* Before probing BARs */ 1901 pci_fixup_header, /* After reading configuration header */ 1902 pci_fixup_final, /* Final phase of device fixups */ 1903 pci_fixup_enable, /* pci_enable_device() time */ 1904 pci_fixup_resume, /* pci_device_resume() */ 1905 pci_fixup_suspend, /* pci_device_suspend() */ 1906 pci_fixup_resume_early, /* pci_device_resume_early() */ 1907 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1908 }; 1909 1910 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1911 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1912 class_shift, hook) \ 1913 __ADDRESSABLE(hook) \ 1914 asm(".section " #sec ", \"a\" \n" \ 1915 ".balign 16 \n" \ 1916 ".short " #vendor ", " #device " \n" \ 1917 ".long " #class ", " #class_shift " \n" \ 1918 ".long " #hook " - . \n" \ 1919 ".previous \n"); 1920 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1921 class_shift, hook) \ 1922 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1923 class_shift, hook) 1924 #else 1925 /* Anonymous variables would be nice... */ 1926 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1927 class_shift, hook) \ 1928 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1929 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1930 = { vendor, device, class, class_shift, hook }; 1931 #endif 1932 1933 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1934 class_shift, hook) \ 1935 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1936 hook, vendor, device, class, class_shift, hook) 1937 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1938 class_shift, hook) \ 1939 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1940 hook, vendor, device, class, class_shift, hook) 1941 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1942 class_shift, hook) \ 1943 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1944 hook, vendor, device, class, class_shift, hook) 1945 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1946 class_shift, hook) \ 1947 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1948 hook, vendor, device, class, class_shift, hook) 1949 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1950 class_shift, hook) \ 1951 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1952 resume##hook, vendor, device, class, class_shift, hook) 1953 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1954 class_shift, hook) \ 1955 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1956 resume_early##hook, vendor, device, class, class_shift, hook) 1957 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1958 class_shift, hook) \ 1959 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1960 suspend##hook, vendor, device, class, class_shift, hook) 1961 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1962 class_shift, hook) \ 1963 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1964 suspend_late##hook, vendor, device, class, class_shift, hook) 1965 1966 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1967 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1968 hook, vendor, device, PCI_ANY_ID, 0, hook) 1969 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1970 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1971 hook, vendor, device, PCI_ANY_ID, 0, hook) 1972 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1973 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1974 hook, vendor, device, PCI_ANY_ID, 0, hook) 1975 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1976 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1977 hook, vendor, device, PCI_ANY_ID, 0, hook) 1978 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1979 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1980 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 1981 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1982 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1983 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 1984 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1985 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1986 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 1987 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1988 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1989 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 1990 1991 #ifdef CONFIG_PCI_QUIRKS 1992 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1993 #else 1994 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1995 struct pci_dev *dev) { } 1996 #endif 1997 1998 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1999 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2000 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2001 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2002 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2003 const char *name); 2004 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2005 2006 extern int pci_pci_problems; 2007 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2008 #define PCIPCI_TRITON 2 2009 #define PCIPCI_NATOMA 4 2010 #define PCIPCI_VIAETBF 8 2011 #define PCIPCI_VSFX 16 2012 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2013 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2014 2015 extern unsigned long pci_cardbus_io_size; 2016 extern unsigned long pci_cardbus_mem_size; 2017 extern u8 pci_dfl_cache_line_size; 2018 extern u8 pci_cache_line_size; 2019 2020 extern unsigned long pci_hotplug_io_size; 2021 extern unsigned long pci_hotplug_mem_size; 2022 extern unsigned long pci_hotplug_bus_size; 2023 2024 /* Architecture-specific versions may override these (weak) */ 2025 void pcibios_disable_device(struct pci_dev *dev); 2026 void pcibios_set_master(struct pci_dev *dev); 2027 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2028 enum pcie_reset_state state); 2029 int pcibios_add_device(struct pci_dev *dev); 2030 void pcibios_release_device(struct pci_dev *dev); 2031 #ifdef CONFIG_PCI 2032 void pcibios_penalize_isa_irq(int irq, int active); 2033 #else 2034 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2035 #endif 2036 int pcibios_alloc_irq(struct pci_dev *dev); 2037 void pcibios_free_irq(struct pci_dev *dev); 2038 resource_size_t pcibios_default_alignment(void); 2039 2040 #ifdef CONFIG_HIBERNATE_CALLBACKS 2041 extern struct dev_pm_ops pcibios_pm_ops; 2042 #endif 2043 2044 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2045 void __init pci_mmcfg_early_init(void); 2046 void __init pci_mmcfg_late_init(void); 2047 #else 2048 static inline void pci_mmcfg_early_init(void) { } 2049 static inline void pci_mmcfg_late_init(void) { } 2050 #endif 2051 2052 int pci_ext_cfg_avail(void); 2053 2054 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2055 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2056 2057 #ifdef CONFIG_PCI_IOV 2058 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2059 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2060 2061 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2062 void pci_disable_sriov(struct pci_dev *dev); 2063 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2064 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2065 int pci_num_vf(struct pci_dev *dev); 2066 int pci_vfs_assigned(struct pci_dev *dev); 2067 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2068 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2069 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2070 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2071 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2072 2073 /* Arch may override these (weak) */ 2074 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2075 int pcibios_sriov_disable(struct pci_dev *pdev); 2076 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2077 #else 2078 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2079 { 2080 return -ENOSYS; 2081 } 2082 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2083 { 2084 return -ENOSYS; 2085 } 2086 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2087 { return -ENODEV; } 2088 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2089 { 2090 return -ENOSYS; 2091 } 2092 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2093 int id) { } 2094 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2095 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2096 static inline int pci_vfs_assigned(struct pci_dev *dev) 2097 { return 0; } 2098 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2099 { return 0; } 2100 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2101 { return 0; } 2102 #define pci_sriov_configure_simple NULL 2103 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2104 { return 0; } 2105 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2106 #endif 2107 2108 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2109 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2110 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2111 #endif 2112 2113 /** 2114 * pci_pcie_cap - get the saved PCIe capability offset 2115 * @dev: PCI device 2116 * 2117 * PCIe capability offset is calculated at PCI device initialization 2118 * time and saved in the data structure. This function returns saved 2119 * PCIe capability offset. Using this instead of pci_find_capability() 2120 * reduces unnecessary search in the PCI configuration space. If you 2121 * need to calculate PCIe capability offset from raw device for some 2122 * reasons, please use pci_find_capability() instead. 2123 */ 2124 static inline int pci_pcie_cap(struct pci_dev *dev) 2125 { 2126 return dev->pcie_cap; 2127 } 2128 2129 /** 2130 * pci_is_pcie - check if the PCI device is PCI Express capable 2131 * @dev: PCI device 2132 * 2133 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2134 */ 2135 static inline bool pci_is_pcie(struct pci_dev *dev) 2136 { 2137 return pci_pcie_cap(dev); 2138 } 2139 2140 /** 2141 * pcie_caps_reg - get the PCIe Capabilities Register 2142 * @dev: PCI device 2143 */ 2144 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2145 { 2146 return dev->pcie_flags_reg; 2147 } 2148 2149 /** 2150 * pci_pcie_type - get the PCIe device/port type 2151 * @dev: PCI device 2152 */ 2153 static inline int pci_pcie_type(const struct pci_dev *dev) 2154 { 2155 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2156 } 2157 2158 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2159 { 2160 while (1) { 2161 if (!pci_is_pcie(dev)) 2162 break; 2163 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2164 return dev; 2165 if (!dev->bus->self) 2166 break; 2167 dev = dev->bus->self; 2168 } 2169 return NULL; 2170 } 2171 2172 void pci_request_acs(void); 2173 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2174 bool pci_acs_path_enabled(struct pci_dev *start, 2175 struct pci_dev *end, u16 acs_flags); 2176 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2177 2178 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2179 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2180 2181 /* Large Resource Data Type Tag Item Names */ 2182 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2183 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2184 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2185 2186 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2187 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2188 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2189 2190 /* Small Resource Data Type Tag Item Names */ 2191 #define PCI_VPD_STIN_END 0x0f /* End */ 2192 2193 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2194 2195 #define PCI_VPD_SRDT_TIN_MASK 0x78 2196 #define PCI_VPD_SRDT_LEN_MASK 0x07 2197 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2198 2199 #define PCI_VPD_LRDT_TAG_SIZE 3 2200 #define PCI_VPD_SRDT_TAG_SIZE 1 2201 2202 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2203 2204 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2205 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2206 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2207 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2208 2209 /** 2210 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2211 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2212 * 2213 * Returns the extracted Large Resource Data Type length. 2214 */ 2215 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2216 { 2217 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2218 } 2219 2220 /** 2221 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2222 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2223 * 2224 * Returns the extracted Large Resource Data Type Tag item. 2225 */ 2226 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2227 { 2228 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2229 } 2230 2231 /** 2232 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2233 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2234 * 2235 * Returns the extracted Small Resource Data Type length. 2236 */ 2237 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2238 { 2239 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2240 } 2241 2242 /** 2243 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2244 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2245 * 2246 * Returns the extracted Small Resource Data Type Tag Item. 2247 */ 2248 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2249 { 2250 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2251 } 2252 2253 /** 2254 * pci_vpd_info_field_size - Extracts the information field length 2255 * @info_field: Pointer to the beginning of an information field header 2256 * 2257 * Returns the extracted information field length. 2258 */ 2259 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2260 { 2261 return info_field[2]; 2262 } 2263 2264 /** 2265 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2266 * @buf: Pointer to buffered vpd data 2267 * @off: The offset into the buffer at which to begin the search 2268 * @len: The length of the vpd buffer 2269 * @rdt: The Resource Data Type to search for 2270 * 2271 * Returns the index where the Resource Data Type was found or 2272 * -ENOENT otherwise. 2273 */ 2274 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 2275 2276 /** 2277 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2278 * @buf: Pointer to buffered vpd data 2279 * @off: The offset into the buffer at which to begin the search 2280 * @len: The length of the buffer area, relative to off, in which to search 2281 * @kw: The keyword to search for 2282 * 2283 * Returns the index where the information field keyword was found or 2284 * -ENOENT otherwise. 2285 */ 2286 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2287 unsigned int len, const char *kw); 2288 2289 /* PCI <-> OF binding helpers */ 2290 #ifdef CONFIG_OF 2291 struct device_node; 2292 struct irq_domain; 2293 void pci_set_of_node(struct pci_dev *dev); 2294 void pci_release_of_node(struct pci_dev *dev); 2295 void pci_set_bus_of_node(struct pci_bus *bus); 2296 void pci_release_bus_of_node(struct pci_bus *bus); 2297 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2298 int pci_parse_request_of_pci_ranges(struct device *dev, 2299 struct list_head *resources, 2300 struct resource **bus_range); 2301 2302 /* Arch may override this (weak) */ 2303 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2304 2305 #else /* CONFIG_OF */ 2306 static inline void pci_set_of_node(struct pci_dev *dev) { } 2307 static inline void pci_release_of_node(struct pci_dev *dev) { } 2308 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2309 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 2310 static inline struct irq_domain * 2311 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2312 static inline int pci_parse_request_of_pci_ranges(struct device *dev, 2313 struct list_head *resources, 2314 struct resource **bus_range) 2315 { 2316 return -EINVAL; 2317 } 2318 #endif /* CONFIG_OF */ 2319 2320 static inline struct device_node * 2321 pci_device_to_OF_node(const struct pci_dev *pdev) 2322 { 2323 return pdev ? pdev->dev.of_node : NULL; 2324 } 2325 2326 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2327 { 2328 return bus ? bus->dev.of_node : NULL; 2329 } 2330 2331 #ifdef CONFIG_ACPI 2332 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2333 2334 void 2335 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2336 #else 2337 static inline struct irq_domain * 2338 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2339 #endif 2340 2341 #ifdef CONFIG_EEH 2342 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2343 { 2344 return pdev->dev.archdata.edev; 2345 } 2346 #endif 2347 2348 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); 2349 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2350 int pci_for_each_dma_alias(struct pci_dev *pdev, 2351 int (*fn)(struct pci_dev *pdev, 2352 u16 alias, void *data), void *data); 2353 2354 /* Helper functions for operation of device flag */ 2355 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2356 { 2357 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2358 } 2359 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2360 { 2361 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2362 } 2363 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2364 { 2365 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2366 } 2367 2368 /** 2369 * pci_ari_enabled - query ARI forwarding status 2370 * @bus: the PCI bus 2371 * 2372 * Returns true if ARI forwarding is enabled. 2373 */ 2374 static inline bool pci_ari_enabled(struct pci_bus *bus) 2375 { 2376 return bus->self && bus->self->ari_enabled; 2377 } 2378 2379 /** 2380 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2381 * @pdev: PCI device to check 2382 * 2383 * Walk upwards from @pdev and check for each encountered bridge if it's part 2384 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2385 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2386 */ 2387 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2388 { 2389 struct pci_dev *parent = pdev; 2390 2391 if (pdev->is_thunderbolt) 2392 return true; 2393 2394 while ((parent = pci_upstream_bridge(parent))) 2395 if (parent->is_thunderbolt) 2396 return true; 2397 2398 return false; 2399 } 2400 2401 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2402 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2403 #endif 2404 2405 /* Provide the legacy pci_dma_* API */ 2406 #include <linux/pci-dma-compat.h> 2407 2408 #define pci_printk(level, pdev, fmt, arg...) \ 2409 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2410 2411 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2412 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2413 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2414 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2415 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2416 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2417 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2418 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2419 2420 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2421 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2422 2423 #endif /* LINUX_PCI_H */ 2424