1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <linux/irqreturn.h> 33 #include <uapi/linux/pci.h> 34 35 #include <linux/pci_ids.h> 36 37 /* 38 * The PCI interface treats multi-function devices as independent 39 * devices. The slot/function address of each device is encoded 40 * in a single byte as follows: 41 * 42 * 7:3 = slot 43 * 2:0 = function 44 * 45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 46 * In the interest of not exposing interfaces to user-space unnecessarily, 47 * the following kernel-only defines are being added here. 48 */ 49 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn) 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 52 53 /* pci_slot represents a physical slot */ 54 struct pci_slot { 55 struct pci_bus *bus; /* The bus this slot is on */ 56 struct list_head list; /* node in list of slots on this bus */ 57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 59 struct kobject kobj; 60 }; 61 62 static inline const char *pci_slot_name(const struct pci_slot *slot) 63 { 64 return kobject_name(&slot->kobj); 65 } 66 67 /* File state for mmap()s on /proc/bus/pci/X/Y */ 68 enum pci_mmap_state { 69 pci_mmap_io, 70 pci_mmap_mem 71 }; 72 73 /* This defines the direction arg to the DMA mapping routines. */ 74 #define PCI_DMA_BIDIRECTIONAL 0 75 #define PCI_DMA_TODEVICE 1 76 #define PCI_DMA_FROMDEVICE 2 77 #define PCI_DMA_NONE 3 78 79 /* 80 * For PCI devices, the region numbers are assigned this way: 81 */ 82 enum { 83 /* #0-5: standard PCI resources */ 84 PCI_STD_RESOURCES, 85 PCI_STD_RESOURCE_END = 5, 86 87 /* #6: expansion ROM resource */ 88 PCI_ROM_RESOURCE, 89 90 /* device specific resources */ 91 #ifdef CONFIG_PCI_IOV 92 PCI_IOV_RESOURCES, 93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 94 #endif 95 96 /* resources assigned to buses behind the bridge */ 97 #define PCI_BRIDGE_RESOURCE_NUM 4 98 99 PCI_BRIDGE_RESOURCES, 100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 101 PCI_BRIDGE_RESOURCE_NUM - 1, 102 103 /* total resources associated with a PCI device */ 104 PCI_NUM_RESOURCES, 105 106 /* preserve this for compatibility */ 107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 108 }; 109 110 typedef int __bitwise pci_power_t; 111 112 #define PCI_D0 ((pci_power_t __force) 0) 113 #define PCI_D1 ((pci_power_t __force) 1) 114 #define PCI_D2 ((pci_power_t __force) 2) 115 #define PCI_D3hot ((pci_power_t __force) 3) 116 #define PCI_D3cold ((pci_power_t __force) 4) 117 #define PCI_UNKNOWN ((pci_power_t __force) 5) 118 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 119 120 /* Remember to update this when the list above changes! */ 121 extern const char *pci_power_names[]; 122 123 static inline const char *pci_power_name(pci_power_t state) 124 { 125 return pci_power_names[1 + (int) state]; 126 } 127 128 #define PCI_PM_D2_DELAY 200 129 #define PCI_PM_D3_WAIT 10 130 #define PCI_PM_D3COLD_WAIT 100 131 #define PCI_PM_BUS_WAIT 50 132 133 /** The pci_channel state describes connectivity between the CPU and 134 * the pci device. If some PCI bus between here and the pci device 135 * has crashed or locked up, this info is reflected here. 136 */ 137 typedef unsigned int __bitwise pci_channel_state_t; 138 139 enum pci_channel_state { 140 /* I/O channel is in normal state */ 141 pci_channel_io_normal = (__force pci_channel_state_t) 1, 142 143 /* I/O to channel is blocked */ 144 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 145 146 /* PCI card is dead */ 147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 148 }; 149 150 typedef unsigned int __bitwise pcie_reset_state_t; 151 152 enum pcie_reset_state { 153 /* Reset is NOT asserted (Use to deassert reset) */ 154 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 155 156 /* Use #PERST to reset PCIe device */ 157 pcie_warm_reset = (__force pcie_reset_state_t) 2, 158 159 /* Use PCIe Hot Reset to reset device */ 160 pcie_hot_reset = (__force pcie_reset_state_t) 3 161 }; 162 163 typedef unsigned short __bitwise pci_dev_flags_t; 164 enum pci_dev_flags { 165 /* INTX_DISABLE in PCI_COMMAND register disables MSI 166 * generation too. 167 */ 168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, 169 /* Device configuration is irrevocably lost if disabled into D3 */ 170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, 171 /* Provide indication device is assigned by a Virtual Machine Manager */ 172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4, 173 }; 174 175 enum pci_irq_reroute_variant { 176 INTEL_IRQ_REROUTE_VARIANT = 1, 177 MAX_IRQ_REROUTE_VARIANTS = 3 178 }; 179 180 typedef unsigned short __bitwise pci_bus_flags_t; 181 enum pci_bus_flags { 182 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 183 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 184 }; 185 186 /* These values come from the PCI Express Spec */ 187 enum pcie_link_width { 188 PCIE_LNK_WIDTH_RESRV = 0x00, 189 PCIE_LNK_X1 = 0x01, 190 PCIE_LNK_X2 = 0x02, 191 PCIE_LNK_X4 = 0x04, 192 PCIE_LNK_X8 = 0x08, 193 PCIE_LNK_X12 = 0x0C, 194 PCIE_LNK_X16 = 0x10, 195 PCIE_LNK_X32 = 0x20, 196 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 197 }; 198 199 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 200 enum pci_bus_speed { 201 PCI_SPEED_33MHz = 0x00, 202 PCI_SPEED_66MHz = 0x01, 203 PCI_SPEED_66MHz_PCIX = 0x02, 204 PCI_SPEED_100MHz_PCIX = 0x03, 205 PCI_SPEED_133MHz_PCIX = 0x04, 206 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 207 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 208 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 209 PCI_SPEED_66MHz_PCIX_266 = 0x09, 210 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 211 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 212 AGP_UNKNOWN = 0x0c, 213 AGP_1X = 0x0d, 214 AGP_2X = 0x0e, 215 AGP_4X = 0x0f, 216 AGP_8X = 0x10, 217 PCI_SPEED_66MHz_PCIX_533 = 0x11, 218 PCI_SPEED_100MHz_PCIX_533 = 0x12, 219 PCI_SPEED_133MHz_PCIX_533 = 0x13, 220 PCIE_SPEED_2_5GT = 0x14, 221 PCIE_SPEED_5_0GT = 0x15, 222 PCIE_SPEED_8_0GT = 0x16, 223 PCI_SPEED_UNKNOWN = 0xff, 224 }; 225 226 struct pci_cap_saved_data { 227 char cap_nr; 228 unsigned int size; 229 u32 data[0]; 230 }; 231 232 struct pci_cap_saved_state { 233 struct hlist_node next; 234 struct pci_cap_saved_data cap; 235 }; 236 237 struct pcie_link_state; 238 struct pci_vpd; 239 struct pci_sriov; 240 struct pci_ats; 241 242 /* 243 * The pci_dev structure is used to describe PCI devices. 244 */ 245 struct pci_dev { 246 struct list_head bus_list; /* node in per-bus list */ 247 struct pci_bus *bus; /* bus this device is on */ 248 struct pci_bus *subordinate; /* bus this device bridges to */ 249 250 void *sysdata; /* hook for sys-specific extension */ 251 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 252 struct pci_slot *slot; /* Physical slot this device is in */ 253 254 unsigned int devfn; /* encoded device & function index */ 255 unsigned short vendor; 256 unsigned short device; 257 unsigned short subsystem_vendor; 258 unsigned short subsystem_device; 259 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 260 u8 revision; /* PCI revision, low byte of class word */ 261 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 262 u8 pcie_cap; /* PCIe capability offset */ 263 u8 msi_cap; /* MSI capability offset */ 264 u8 msix_cap; /* MSI-X capability offset */ 265 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 266 u8 rom_base_reg; /* which config register controls the ROM */ 267 u8 pin; /* which interrupt pin this device uses */ 268 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 269 270 struct pci_driver *driver; /* which driver has allocated this device */ 271 u64 dma_mask; /* Mask of the bits of bus address this 272 device implements. Normally this is 273 0xffffffff. You only need to change 274 this if your device has broken DMA 275 or supports 64-bit transfers. */ 276 277 struct device_dma_parameters dma_parms; 278 279 pci_power_t current_state; /* Current operating state. In ACPI-speak, 280 this is D0-D3, D0 being fully functional, 281 and D3 being off. */ 282 u8 pm_cap; /* PM capability offset */ 283 unsigned int pme_support:5; /* Bitmask of states from which PME# 284 can be generated */ 285 unsigned int pme_interrupt:1; 286 unsigned int pme_poll:1; /* Poll device's PME status bit */ 287 unsigned int d1_support:1; /* Low power state D1 is supported */ 288 unsigned int d2_support:1; /* Low power state D2 is supported */ 289 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 290 unsigned int no_d3cold:1; /* D3cold is forbidden */ 291 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 292 unsigned int mmio_always_on:1; /* disallow turning off io/mem 293 decoding during bar sizing */ 294 unsigned int wakeup_prepared:1; 295 unsigned int runtime_d3cold:1; /* whether go through runtime 296 D3cold, not set for devices 297 powered on/off by the 298 corresponding bridge */ 299 unsigned int d3_delay; /* D3->D0 transition time in ms */ 300 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 301 302 #ifdef CONFIG_PCIEASPM 303 struct pcie_link_state *link_state; /* ASPM link state */ 304 #endif 305 306 pci_channel_state_t error_state; /* current connectivity state */ 307 struct device dev; /* Generic device interface */ 308 309 int cfg_size; /* Size of configuration space */ 310 311 /* 312 * Instead of touching interrupt line and base address registers 313 * directly, use the values stored here. They might be different! 314 */ 315 unsigned int irq; 316 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 317 318 bool match_driver; /* Skip attaching driver */ 319 /* These fields are used by common fixups */ 320 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 321 unsigned int multifunction:1;/* Part of multi-function device */ 322 /* keep track of device state */ 323 unsigned int is_added:1; 324 unsigned int is_busmaster:1; /* device is busmaster */ 325 unsigned int no_msi:1; /* device may not use msi */ 326 unsigned int block_cfg_access:1; /* config space access is blocked */ 327 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 328 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 329 unsigned int msi_enabled:1; 330 unsigned int msix_enabled:1; 331 unsigned int ari_enabled:1; /* ARI forwarding */ 332 unsigned int is_managed:1; 333 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 334 unsigned int state_saved:1; 335 unsigned int is_physfn:1; 336 unsigned int is_virtfn:1; 337 unsigned int reset_fn:1; 338 unsigned int is_hotplug_bridge:1; 339 unsigned int __aer_firmware_first_valid:1; 340 unsigned int __aer_firmware_first:1; 341 unsigned int broken_intx_masking:1; 342 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 343 pci_dev_flags_t dev_flags; 344 atomic_t enable_cnt; /* pci_enable_device has been called */ 345 346 u32 saved_config_space[16]; /* config space saved at suspend time */ 347 struct hlist_head saved_cap_space; 348 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 349 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 350 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 351 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 352 #ifdef CONFIG_PCI_MSI 353 struct list_head msi_list; 354 struct kset *msi_kset; 355 #endif 356 struct pci_vpd *vpd; 357 #ifdef CONFIG_PCI_ATS 358 union { 359 struct pci_sriov *sriov; /* SR-IOV capability related */ 360 struct pci_dev *physfn; /* the PF this VF is associated with */ 361 }; 362 struct pci_ats *ats; /* Address Translation Service */ 363 #endif 364 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 365 size_t romlen; /* Length of ROM if it's not from the BAR */ 366 }; 367 368 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 369 { 370 #ifdef CONFIG_PCI_IOV 371 if (dev->is_virtfn) 372 dev = dev->physfn; 373 #endif 374 return dev; 375 } 376 377 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 378 struct pci_dev * __deprecated alloc_pci_dev(void); 379 380 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 381 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 382 383 static inline int pci_channel_offline(struct pci_dev *pdev) 384 { 385 return (pdev->error_state != pci_channel_io_normal); 386 } 387 388 extern struct resource busn_resource; 389 390 struct pci_host_bridge_window { 391 struct list_head list; 392 struct resource *res; /* host bridge aperture (CPU address) */ 393 resource_size_t offset; /* bus address + offset = CPU address */ 394 }; 395 396 struct pci_host_bridge { 397 struct device dev; 398 struct pci_bus *bus; /* root bus */ 399 struct list_head windows; /* pci_host_bridge_windows */ 400 void (*release_fn)(struct pci_host_bridge *); 401 void *release_data; 402 }; 403 404 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 405 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 406 void (*release_fn)(struct pci_host_bridge *), 407 void *release_data); 408 409 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 410 411 /* 412 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 413 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 414 * buses below host bridges or subtractive decode bridges) go in the list. 415 * Use pci_bus_for_each_resource() to iterate through all the resources. 416 */ 417 418 /* 419 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 420 * and there's no way to program the bridge with the details of the window. 421 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 422 * decode bit set, because they are explicit and can be programmed with _SRS. 423 */ 424 #define PCI_SUBTRACTIVE_DECODE 0x1 425 426 struct pci_bus_resource { 427 struct list_head list; 428 struct resource *res; 429 unsigned int flags; 430 }; 431 432 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 433 434 struct pci_bus { 435 struct list_head node; /* node in list of buses */ 436 struct pci_bus *parent; /* parent bus this bridge is on */ 437 struct list_head children; /* list of child buses */ 438 struct list_head devices; /* list of devices on this bus */ 439 struct pci_dev *self; /* bridge device as seen by parent */ 440 struct list_head slots; /* list of slots on this bus */ 441 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 442 struct list_head resources; /* address space routed to this bus */ 443 struct resource busn_res; /* bus numbers routed to this bus */ 444 445 struct pci_ops *ops; /* configuration access functions */ 446 struct msi_chip *msi; /* MSI controller */ 447 void *sysdata; /* hook for sys-specific extension */ 448 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 449 450 unsigned char number; /* bus number */ 451 unsigned char primary; /* number of primary bridge */ 452 unsigned char max_bus_speed; /* enum pci_bus_speed */ 453 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 454 455 char name[48]; 456 457 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 458 pci_bus_flags_t bus_flags; /* inherited by child buses */ 459 struct device *bridge; 460 struct device dev; 461 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 462 struct bin_attribute *legacy_mem; /* legacy mem */ 463 unsigned int is_added:1; 464 }; 465 466 #define pci_bus_b(n) list_entry(n, struct pci_bus, node) 467 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 468 469 /* 470 * Returns true if the PCI bus is root (behind host-PCI bridge), 471 * false otherwise 472 * 473 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 474 * This is incorrect because "virtual" buses added for SR-IOV (via 475 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 476 */ 477 static inline bool pci_is_root_bus(struct pci_bus *pbus) 478 { 479 return !(pbus->parent); 480 } 481 482 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 483 { 484 dev = pci_physfn(dev); 485 if (pci_is_root_bus(dev->bus)) 486 return NULL; 487 488 return dev->bus->self; 489 } 490 491 #ifdef CONFIG_PCI_MSI 492 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 493 { 494 return pci_dev->msi_enabled || pci_dev->msix_enabled; 495 } 496 #else 497 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 498 #endif 499 500 /* 501 * Error values that may be returned by PCI functions. 502 */ 503 #define PCIBIOS_SUCCESSFUL 0x00 504 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 505 #define PCIBIOS_BAD_VENDOR_ID 0x83 506 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 507 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 508 #define PCIBIOS_SET_FAILED 0x88 509 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 510 511 /* 512 * Translate above to generic errno for passing back through non-PCI code. 513 */ 514 static inline int pcibios_err_to_errno(int err) 515 { 516 if (err <= PCIBIOS_SUCCESSFUL) 517 return err; /* Assume already errno */ 518 519 switch (err) { 520 case PCIBIOS_FUNC_NOT_SUPPORTED: 521 return -ENOENT; 522 case PCIBIOS_BAD_VENDOR_ID: 523 return -EINVAL; 524 case PCIBIOS_DEVICE_NOT_FOUND: 525 return -ENODEV; 526 case PCIBIOS_BAD_REGISTER_NUMBER: 527 return -EFAULT; 528 case PCIBIOS_SET_FAILED: 529 return -EIO; 530 case PCIBIOS_BUFFER_TOO_SMALL: 531 return -ENOSPC; 532 } 533 534 return -ENOTTY; 535 } 536 537 /* Low-level architecture-dependent routines */ 538 539 struct pci_ops { 540 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 541 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 542 }; 543 544 /* 545 * ACPI needs to be able to access PCI config space before we've done a 546 * PCI bus scan and created pci_bus structures. 547 */ 548 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 549 int reg, int len, u32 *val); 550 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 551 int reg, int len, u32 val); 552 553 struct pci_bus_region { 554 resource_size_t start; 555 resource_size_t end; 556 }; 557 558 struct pci_dynids { 559 spinlock_t lock; /* protects list, index */ 560 struct list_head list; /* for IDs added at runtime */ 561 }; 562 563 564 /* 565 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 566 * a set of callbacks in struct pci_error_handlers, that device driver 567 * will be notified of PCI bus errors, and will be driven to recovery 568 * when an error occurs. 569 */ 570 571 typedef unsigned int __bitwise pci_ers_result_t; 572 573 enum pci_ers_result { 574 /* no result/none/not supported in device driver */ 575 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 576 577 /* Device driver can recover without slot reset */ 578 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 579 580 /* Device driver wants slot to be reset. */ 581 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 582 583 /* Device has completely failed, is unrecoverable */ 584 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 585 586 /* Device driver is fully recovered and operational */ 587 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 588 589 /* No AER capabilities registered for the driver */ 590 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 591 }; 592 593 /* PCI bus error event callbacks */ 594 struct pci_error_handlers { 595 /* PCI bus error detected on this device */ 596 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 597 enum pci_channel_state error); 598 599 /* MMIO has been re-enabled, but not DMA */ 600 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 601 602 /* PCI Express link has been reset */ 603 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 604 605 /* PCI slot has been reset */ 606 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 607 608 /* Device driver may resume normal operations */ 609 void (*resume)(struct pci_dev *dev); 610 }; 611 612 613 struct module; 614 struct pci_driver { 615 struct list_head node; 616 const char *name; 617 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 618 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 619 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 620 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 621 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 622 int (*resume_early) (struct pci_dev *dev); 623 int (*resume) (struct pci_dev *dev); /* Device woken up */ 624 void (*shutdown) (struct pci_dev *dev); 625 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 626 const struct pci_error_handlers *err_handler; 627 struct device_driver driver; 628 struct pci_dynids dynids; 629 }; 630 631 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 632 633 /** 634 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 635 * @_table: device table name 636 * 637 * This macro is used to create a struct pci_device_id array (a device table) 638 * in a generic manner. 639 */ 640 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 641 const struct pci_device_id _table[] 642 643 /** 644 * PCI_DEVICE - macro used to describe a specific pci device 645 * @vend: the 16 bit PCI Vendor ID 646 * @dev: the 16 bit PCI Device ID 647 * 648 * This macro is used to create a struct pci_device_id that matches a 649 * specific device. The subvendor and subdevice fields will be set to 650 * PCI_ANY_ID. 651 */ 652 #define PCI_DEVICE(vend,dev) \ 653 .vendor = (vend), .device = (dev), \ 654 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 655 656 /** 657 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 658 * @vend: the 16 bit PCI Vendor ID 659 * @dev: the 16 bit PCI Device ID 660 * @subvend: the 16 bit PCI Subvendor ID 661 * @subdev: the 16 bit PCI Subdevice ID 662 * 663 * This macro is used to create a struct pci_device_id that matches a 664 * specific device with subsystem information. 665 */ 666 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 667 .vendor = (vend), .device = (dev), \ 668 .subvendor = (subvend), .subdevice = (subdev) 669 670 /** 671 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 672 * @dev_class: the class, subclass, prog-if triple for this device 673 * @dev_class_mask: the class mask for this device 674 * 675 * This macro is used to create a struct pci_device_id that matches a 676 * specific PCI class. The vendor, device, subvendor, and subdevice 677 * fields will be set to PCI_ANY_ID. 678 */ 679 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 680 .class = (dev_class), .class_mask = (dev_class_mask), \ 681 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 682 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 683 684 /** 685 * PCI_VDEVICE - macro used to describe a specific pci device in short form 686 * @vendor: the vendor name 687 * @device: the 16 bit PCI Device ID 688 * 689 * This macro is used to create a struct pci_device_id that matches a 690 * specific PCI device. The subvendor, and subdevice fields will be set 691 * to PCI_ANY_ID. The macro allows the next field to follow as the device 692 * private data. 693 */ 694 695 #define PCI_VDEVICE(vendor, device) \ 696 PCI_VENDOR_ID_##vendor, (device), \ 697 PCI_ANY_ID, PCI_ANY_ID, 0, 0 698 699 /* these external functions are only available when PCI support is enabled */ 700 #ifdef CONFIG_PCI 701 702 void pcie_bus_configure_settings(struct pci_bus *bus); 703 704 enum pcie_bus_config_types { 705 PCIE_BUS_TUNE_OFF, 706 PCIE_BUS_SAFE, 707 PCIE_BUS_PERFORMANCE, 708 PCIE_BUS_PEER2PEER, 709 }; 710 711 extern enum pcie_bus_config_types pcie_bus_config; 712 713 extern struct bus_type pci_bus_type; 714 715 /* Do NOT directly access these two variables, unless you are arch-specific PCI 716 * code, or PCI core code. */ 717 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 718 /* Some device drivers need know if PCI is initiated */ 719 int no_pci_devices(void); 720 721 void pcibios_resource_survey_bus(struct pci_bus *bus); 722 void pcibios_add_bus(struct pci_bus *bus); 723 void pcibios_remove_bus(struct pci_bus *bus); 724 void pcibios_fixup_bus(struct pci_bus *); 725 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 726 /* Architecture-specific versions may override this (weak) */ 727 char *pcibios_setup(char *str); 728 729 /* Used only when drivers/pci/setup.c is used */ 730 resource_size_t pcibios_align_resource(void *, const struct resource *, 731 resource_size_t, 732 resource_size_t); 733 void pcibios_update_irq(struct pci_dev *, int irq); 734 735 /* Weak but can be overriden by arch */ 736 void pci_fixup_cardbus(struct pci_bus *); 737 738 /* Generic PCI functions used internally */ 739 740 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 741 struct resource *res); 742 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 743 struct pci_bus_region *region); 744 void pcibios_scan_specific_bus(int busn); 745 struct pci_bus *pci_find_bus(int domain, int busnr); 746 void pci_bus_add_devices(const struct pci_bus *bus); 747 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, 748 struct pci_ops *ops, void *sysdata); 749 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 750 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 751 struct pci_ops *ops, void *sysdata, 752 struct list_head *resources); 753 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 754 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 755 void pci_bus_release_busn_res(struct pci_bus *b); 756 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 757 struct pci_ops *ops, void *sysdata, 758 struct list_head *resources); 759 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 760 int busnr); 761 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 762 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 763 const char *name, 764 struct hotplug_slot *hotplug); 765 void pci_destroy_slot(struct pci_slot *slot); 766 void pci_renumber_slot(struct pci_slot *slot, int slot_nr); 767 int pci_scan_slot(struct pci_bus *bus, int devfn); 768 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 769 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 770 unsigned int pci_scan_child_bus(struct pci_bus *bus); 771 int __must_check pci_bus_add_device(struct pci_dev *dev); 772 void pci_read_bridge_bases(struct pci_bus *child); 773 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 774 struct resource *res); 775 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 776 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 777 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 778 struct pci_dev *pci_dev_get(struct pci_dev *dev); 779 void pci_dev_put(struct pci_dev *dev); 780 void pci_remove_bus(struct pci_bus *b); 781 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 782 void pci_stop_root_bus(struct pci_bus *bus); 783 void pci_remove_root_bus(struct pci_bus *bus); 784 void pci_setup_cardbus(struct pci_bus *bus); 785 void pci_sort_breadthfirst(void); 786 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 787 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 788 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 789 790 /* Generic PCI functions exported to card drivers */ 791 792 enum pci_lost_interrupt_reason { 793 PCI_LOST_IRQ_NO_INFORMATION = 0, 794 PCI_LOST_IRQ_DISABLE_MSI, 795 PCI_LOST_IRQ_DISABLE_MSIX, 796 PCI_LOST_IRQ_DISABLE_ACPI, 797 }; 798 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 799 int pci_find_capability(struct pci_dev *dev, int cap); 800 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 801 int pci_find_ext_capability(struct pci_dev *dev, int cap); 802 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 803 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 804 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 805 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 806 807 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 808 struct pci_dev *from); 809 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 810 unsigned int ss_vendor, unsigned int ss_device, 811 struct pci_dev *from); 812 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 813 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 814 unsigned int devfn); 815 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 816 unsigned int devfn) 817 { 818 return pci_get_domain_bus_and_slot(0, bus, devfn); 819 } 820 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 821 int pci_dev_present(const struct pci_device_id *ids); 822 823 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 824 int where, u8 *val); 825 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 826 int where, u16 *val); 827 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 828 int where, u32 *val); 829 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 830 int where, u8 val); 831 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 832 int where, u16 val); 833 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 834 int where, u32 val); 835 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 836 837 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 838 { 839 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 840 } 841 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 842 { 843 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 844 } 845 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 846 u32 *val) 847 { 848 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 849 } 850 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 851 { 852 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 853 } 854 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 855 { 856 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 857 } 858 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 859 u32 val) 860 { 861 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 862 } 863 864 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 865 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 866 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 867 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 868 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 869 u16 clear, u16 set); 870 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 871 u32 clear, u32 set); 872 873 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 874 u16 set) 875 { 876 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 877 } 878 879 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 880 u32 set) 881 { 882 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 883 } 884 885 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 886 u16 clear) 887 { 888 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 889 } 890 891 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 892 u32 clear) 893 { 894 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 895 } 896 897 /* user-space driven config access */ 898 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 899 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 900 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 901 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 902 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 903 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 904 905 int __must_check pci_enable_device(struct pci_dev *dev); 906 int __must_check pci_enable_device_io(struct pci_dev *dev); 907 int __must_check pci_enable_device_mem(struct pci_dev *dev); 908 int __must_check pci_reenable_device(struct pci_dev *); 909 int __must_check pcim_enable_device(struct pci_dev *pdev); 910 void pcim_pin_device(struct pci_dev *pdev); 911 912 static inline int pci_is_enabled(struct pci_dev *pdev) 913 { 914 return (atomic_read(&pdev->enable_cnt) > 0); 915 } 916 917 static inline int pci_is_managed(struct pci_dev *pdev) 918 { 919 return pdev->is_managed; 920 } 921 922 void pci_disable_device(struct pci_dev *dev); 923 924 extern unsigned int pcibios_max_latency; 925 void pci_set_master(struct pci_dev *dev); 926 void pci_clear_master(struct pci_dev *dev); 927 928 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 929 int pci_set_cacheline_size(struct pci_dev *dev); 930 #define HAVE_PCI_SET_MWI 931 int __must_check pci_set_mwi(struct pci_dev *dev); 932 int pci_try_set_mwi(struct pci_dev *dev); 933 void pci_clear_mwi(struct pci_dev *dev); 934 void pci_intx(struct pci_dev *dev, int enable); 935 bool pci_intx_mask_supported(struct pci_dev *dev); 936 bool pci_check_and_mask_intx(struct pci_dev *dev); 937 bool pci_check_and_unmask_intx(struct pci_dev *dev); 938 void pci_msi_off(struct pci_dev *dev); 939 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 940 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 941 int pci_wait_for_pending_transaction(struct pci_dev *dev); 942 int pcix_get_max_mmrbc(struct pci_dev *dev); 943 int pcix_get_mmrbc(struct pci_dev *dev); 944 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 945 int pcie_get_readrq(struct pci_dev *dev); 946 int pcie_set_readrq(struct pci_dev *dev, int rq); 947 int pcie_get_mps(struct pci_dev *dev); 948 int pcie_set_mps(struct pci_dev *dev, int mps); 949 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 950 enum pcie_link_width *width); 951 int __pci_reset_function(struct pci_dev *dev); 952 int __pci_reset_function_locked(struct pci_dev *dev); 953 int pci_reset_function(struct pci_dev *dev); 954 int pci_probe_reset_slot(struct pci_slot *slot); 955 int pci_reset_slot(struct pci_slot *slot); 956 int pci_probe_reset_bus(struct pci_bus *bus); 957 int pci_reset_bus(struct pci_bus *bus); 958 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 959 void pci_update_resource(struct pci_dev *dev, int resno); 960 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 961 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 962 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 963 bool pci_device_is_present(struct pci_dev *pdev); 964 965 /* ROM control related routines */ 966 int pci_enable_rom(struct pci_dev *pdev); 967 void pci_disable_rom(struct pci_dev *pdev); 968 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 969 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 970 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 971 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 972 973 /* Power management related routines */ 974 int pci_save_state(struct pci_dev *dev); 975 void pci_restore_state(struct pci_dev *dev); 976 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 977 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state); 978 int pci_load_and_free_saved_state(struct pci_dev *dev, 979 struct pci_saved_state **state); 980 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 981 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 982 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 983 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 984 void pci_pme_active(struct pci_dev *dev, bool enable); 985 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 986 bool runtime, bool enable); 987 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 988 pci_power_t pci_target_state(struct pci_dev *dev); 989 int pci_prepare_to_sleep(struct pci_dev *dev); 990 int pci_back_from_sleep(struct pci_dev *dev); 991 bool pci_dev_run_wake(struct pci_dev *dev); 992 bool pci_check_pme_status(struct pci_dev *dev); 993 void pci_pme_wakeup_bus(struct pci_bus *bus); 994 995 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 996 bool enable) 997 { 998 return __pci_enable_wake(dev, state, false, enable); 999 } 1000 1001 #define PCI_EXP_IDO_REQUEST (1<<0) 1002 #define PCI_EXP_IDO_COMPLETION (1<<1) 1003 void pci_enable_ido(struct pci_dev *dev, unsigned long type); 1004 void pci_disable_ido(struct pci_dev *dev, unsigned long type); 1005 1006 enum pci_obff_signal_type { 1007 PCI_EXP_OBFF_SIGNAL_L0 = 0, 1008 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1, 1009 }; 1010 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type); 1011 void pci_disable_obff(struct pci_dev *dev); 1012 1013 int pci_enable_ltr(struct pci_dev *dev); 1014 void pci_disable_ltr(struct pci_dev *dev); 1015 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns); 1016 1017 /* For use by arch with custom probe code */ 1018 void set_pcie_port_type(struct pci_dev *pdev); 1019 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1020 1021 /* Functions for PCI Hotplug drivers to use */ 1022 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1023 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1024 unsigned int pci_rescan_bus(struct pci_bus *bus); 1025 1026 /* Vital product data routines */ 1027 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1028 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1029 int pci_vpd_truncate(struct pci_dev *dev, size_t size); 1030 1031 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1032 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1033 void pci_bus_assign_resources(const struct pci_bus *bus); 1034 void pci_bus_size_bridges(struct pci_bus *bus); 1035 int pci_claim_resource(struct pci_dev *, int); 1036 void pci_assign_unassigned_resources(void); 1037 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1038 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1039 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1040 void pdev_enable_device(struct pci_dev *); 1041 int pci_enable_resources(struct pci_dev *, int mask); 1042 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1043 int (*)(const struct pci_dev *, u8, u8)); 1044 #define HAVE_PCI_REQ_REGIONS 2 1045 int __must_check pci_request_regions(struct pci_dev *, const char *); 1046 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1047 void pci_release_regions(struct pci_dev *); 1048 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1049 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1050 void pci_release_region(struct pci_dev *, int); 1051 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1052 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1053 void pci_release_selected_regions(struct pci_dev *, int); 1054 1055 /* drivers/pci/bus.c */ 1056 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1057 void pci_bus_put(struct pci_bus *bus); 1058 void pci_add_resource(struct list_head *resources, struct resource *res); 1059 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1060 resource_size_t offset); 1061 void pci_free_resource_list(struct list_head *resources); 1062 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1063 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1064 void pci_bus_remove_resources(struct pci_bus *bus); 1065 1066 #define pci_bus_for_each_resource(bus, res, i) \ 1067 for (i = 0; \ 1068 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1069 i++) 1070 1071 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1072 struct resource *res, resource_size_t size, 1073 resource_size_t align, resource_size_t min, 1074 unsigned int type_mask, 1075 resource_size_t (*alignf)(void *, 1076 const struct resource *, 1077 resource_size_t, 1078 resource_size_t), 1079 void *alignf_data); 1080 1081 /* Proper probing supporting hot-pluggable devices */ 1082 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1083 const char *mod_name); 1084 1085 /* 1086 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1087 */ 1088 #define pci_register_driver(driver) \ 1089 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1090 1091 void pci_unregister_driver(struct pci_driver *dev); 1092 1093 /** 1094 * module_pci_driver() - Helper macro for registering a PCI driver 1095 * @__pci_driver: pci_driver struct 1096 * 1097 * Helper macro for PCI drivers which do not do anything special in module 1098 * init/exit. This eliminates a lot of boilerplate. Each module may only 1099 * use this macro once, and calling it replaces module_init() and module_exit() 1100 */ 1101 #define module_pci_driver(__pci_driver) \ 1102 module_driver(__pci_driver, pci_register_driver, \ 1103 pci_unregister_driver) 1104 1105 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1106 int pci_add_dynid(struct pci_driver *drv, 1107 unsigned int vendor, unsigned int device, 1108 unsigned int subvendor, unsigned int subdevice, 1109 unsigned int class, unsigned int class_mask, 1110 unsigned long driver_data); 1111 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1112 struct pci_dev *dev); 1113 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1114 int pass); 1115 1116 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1117 void *userdata); 1118 int pci_cfg_space_size_ext(struct pci_dev *dev); 1119 int pci_cfg_space_size(struct pci_dev *dev); 1120 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1121 void pci_setup_bridge(struct pci_bus *bus); 1122 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1123 unsigned long type); 1124 1125 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1126 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1127 1128 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1129 unsigned int command_bits, u32 flags); 1130 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1131 1132 #include <linux/pci-dma.h> 1133 #include <linux/dmapool.h> 1134 1135 #define pci_pool dma_pool 1136 #define pci_pool_create(name, pdev, size, align, allocation) \ 1137 dma_pool_create(name, &pdev->dev, size, align, allocation) 1138 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1139 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1140 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1141 1142 enum pci_dma_burst_strategy { 1143 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, 1144 strategy_parameter is N/A */ 1145 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter 1146 byte boundaries */ 1147 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of 1148 strategy_parameter byte boundaries */ 1149 }; 1150 1151 struct msix_entry { 1152 u32 vector; /* kernel uses to write allocated vector */ 1153 u16 entry; /* driver uses to specify entry, OS writes */ 1154 }; 1155 1156 1157 #ifndef CONFIG_PCI_MSI 1158 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) 1159 { 1160 return -1; 1161 } 1162 1163 static inline int 1164 pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) 1165 { 1166 return -1; 1167 } 1168 1169 static inline void pci_msi_shutdown(struct pci_dev *dev) 1170 { } 1171 static inline void pci_disable_msi(struct pci_dev *dev) 1172 { } 1173 1174 static inline int pci_msix_table_size(struct pci_dev *dev) 1175 { 1176 return 0; 1177 } 1178 static inline int pci_enable_msix(struct pci_dev *dev, 1179 struct msix_entry *entries, int nvec) 1180 { 1181 return -1; 1182 } 1183 1184 static inline void pci_msix_shutdown(struct pci_dev *dev) 1185 { } 1186 static inline void pci_disable_msix(struct pci_dev *dev) 1187 { } 1188 1189 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) 1190 { } 1191 1192 static inline void pci_restore_msi_state(struct pci_dev *dev) 1193 { } 1194 static inline int pci_msi_enabled(void) 1195 { 1196 return 0; 1197 } 1198 #else 1199 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); 1200 int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec); 1201 void pci_msi_shutdown(struct pci_dev *dev); 1202 void pci_disable_msi(struct pci_dev *dev); 1203 int pci_msix_table_size(struct pci_dev *dev); 1204 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1205 void pci_msix_shutdown(struct pci_dev *dev); 1206 void pci_disable_msix(struct pci_dev *dev); 1207 void msi_remove_pci_irq_vectors(struct pci_dev *dev); 1208 void pci_restore_msi_state(struct pci_dev *dev); 1209 int pci_msi_enabled(void); 1210 #endif 1211 1212 #ifdef CONFIG_PCIEPORTBUS 1213 extern bool pcie_ports_disabled; 1214 extern bool pcie_ports_auto; 1215 #else 1216 #define pcie_ports_disabled true 1217 #define pcie_ports_auto false 1218 #endif 1219 1220 #ifndef CONFIG_PCIEASPM 1221 static inline int pcie_aspm_enabled(void) { return 0; } 1222 static inline bool pcie_aspm_support_enabled(void) { return false; } 1223 #else 1224 int pcie_aspm_enabled(void); 1225 bool pcie_aspm_support_enabled(void); 1226 #endif 1227 1228 #ifdef CONFIG_PCIEAER 1229 void pci_no_aer(void); 1230 bool pci_aer_available(void); 1231 #else 1232 static inline void pci_no_aer(void) { } 1233 static inline bool pci_aer_available(void) { return false; } 1234 #endif 1235 1236 #ifndef CONFIG_PCIE_ECRC 1237 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) 1238 { 1239 return; 1240 } 1241 static inline void pcie_ecrc_get_policy(char *str) {}; 1242 #else 1243 void pcie_set_ecrc_checking(struct pci_dev *dev); 1244 void pcie_ecrc_get_policy(char *str); 1245 #endif 1246 1247 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) 1248 1249 #ifdef CONFIG_HT_IRQ 1250 /* The functions a driver should call */ 1251 int ht_create_irq(struct pci_dev *dev, int idx); 1252 void ht_destroy_irq(unsigned int irq); 1253 #endif /* CONFIG_HT_IRQ */ 1254 1255 void pci_cfg_access_lock(struct pci_dev *dev); 1256 bool pci_cfg_access_trylock(struct pci_dev *dev); 1257 void pci_cfg_access_unlock(struct pci_dev *dev); 1258 1259 /* 1260 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1261 * a PCI domain is defined to be a set of PCI buses which share 1262 * configuration space. 1263 */ 1264 #ifdef CONFIG_PCI_DOMAINS 1265 extern int pci_domains_supported; 1266 #else 1267 enum { pci_domains_supported = 0 }; 1268 static inline int pci_domain_nr(struct pci_bus *bus) 1269 { 1270 return 0; 1271 } 1272 1273 static inline int pci_proc_domain(struct pci_bus *bus) 1274 { 1275 return 0; 1276 } 1277 #endif /* CONFIG_PCI_DOMAINS */ 1278 1279 /* some architectures require additional setup to direct VGA traffic */ 1280 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1281 unsigned int command_bits, u32 flags); 1282 void pci_register_set_vga_state(arch_set_vga_state_t func); 1283 1284 #else /* CONFIG_PCI is not enabled */ 1285 1286 /* 1287 * If the system does not have PCI, clearly these return errors. Define 1288 * these as simple inline functions to avoid hair in drivers. 1289 */ 1290 1291 #define _PCI_NOP(o, s, t) \ 1292 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1293 int where, t val) \ 1294 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1295 1296 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1297 _PCI_NOP(o, word, u16 x) \ 1298 _PCI_NOP(o, dword, u32 x) 1299 _PCI_NOP_ALL(read, *) 1300 _PCI_NOP_ALL(write,) 1301 1302 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1303 unsigned int device, 1304 struct pci_dev *from) 1305 { 1306 return NULL; 1307 } 1308 1309 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1310 unsigned int device, 1311 unsigned int ss_vendor, 1312 unsigned int ss_device, 1313 struct pci_dev *from) 1314 { 1315 return NULL; 1316 } 1317 1318 static inline struct pci_dev *pci_get_class(unsigned int class, 1319 struct pci_dev *from) 1320 { 1321 return NULL; 1322 } 1323 1324 #define pci_dev_present(ids) (0) 1325 #define no_pci_devices() (1) 1326 #define pci_dev_put(dev) do { } while (0) 1327 1328 static inline void pci_set_master(struct pci_dev *dev) 1329 { } 1330 1331 static inline int pci_enable_device(struct pci_dev *dev) 1332 { 1333 return -EIO; 1334 } 1335 1336 static inline void pci_disable_device(struct pci_dev *dev) 1337 { } 1338 1339 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1340 { 1341 return -EIO; 1342 } 1343 1344 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1345 { 1346 return -EIO; 1347 } 1348 1349 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1350 unsigned int size) 1351 { 1352 return -EIO; 1353 } 1354 1355 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1356 unsigned long mask) 1357 { 1358 return -EIO; 1359 } 1360 1361 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1362 { 1363 return -EBUSY; 1364 } 1365 1366 static inline int __pci_register_driver(struct pci_driver *drv, 1367 struct module *owner) 1368 { 1369 return 0; 1370 } 1371 1372 static inline int pci_register_driver(struct pci_driver *drv) 1373 { 1374 return 0; 1375 } 1376 1377 static inline void pci_unregister_driver(struct pci_driver *drv) 1378 { } 1379 1380 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1381 { 1382 return 0; 1383 } 1384 1385 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1386 int cap) 1387 { 1388 return 0; 1389 } 1390 1391 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1392 { 1393 return 0; 1394 } 1395 1396 /* Power management related routines */ 1397 static inline int pci_save_state(struct pci_dev *dev) 1398 { 1399 return 0; 1400 } 1401 1402 static inline void pci_restore_state(struct pci_dev *dev) 1403 { } 1404 1405 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1406 { 1407 return 0; 1408 } 1409 1410 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1411 { 1412 return 0; 1413 } 1414 1415 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1416 pm_message_t state) 1417 { 1418 return PCI_D0; 1419 } 1420 1421 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1422 int enable) 1423 { 1424 return 0; 1425 } 1426 1427 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type) 1428 { 1429 } 1430 1431 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type) 1432 { 1433 } 1434 1435 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type) 1436 { 1437 return 0; 1438 } 1439 1440 static inline void pci_disable_obff(struct pci_dev *dev) 1441 { 1442 } 1443 1444 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1445 { 1446 return -EIO; 1447 } 1448 1449 static inline void pci_release_regions(struct pci_dev *dev) 1450 { } 1451 1452 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 1453 1454 static inline void pci_block_cfg_access(struct pci_dev *dev) 1455 { } 1456 1457 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1458 { return 0; } 1459 1460 static inline void pci_unblock_cfg_access(struct pci_dev *dev) 1461 { } 1462 1463 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1464 { return NULL; } 1465 1466 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1467 unsigned int devfn) 1468 { return NULL; } 1469 1470 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1471 unsigned int devfn) 1472 { return NULL; } 1473 1474 static inline int pci_domain_nr(struct pci_bus *bus) 1475 { return 0; } 1476 1477 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) 1478 { return NULL; } 1479 1480 #define dev_is_pci(d) (false) 1481 #define dev_is_pf(d) (false) 1482 #define dev_num_vf(d) (0) 1483 #endif /* CONFIG_PCI */ 1484 1485 /* Include architecture-dependent settings and functions */ 1486 1487 #include <asm/pci.h> 1488 1489 #ifndef PCIBIOS_MAX_MEM_32 1490 #define PCIBIOS_MAX_MEM_32 (-1) 1491 #endif 1492 1493 /* these helpers provide future and backwards compatibility 1494 * for accessing popular PCI BAR info */ 1495 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1496 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1497 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1498 #define pci_resource_len(dev,bar) \ 1499 ((pci_resource_start((dev), (bar)) == 0 && \ 1500 pci_resource_end((dev), (bar)) == \ 1501 pci_resource_start((dev), (bar))) ? 0 : \ 1502 \ 1503 (pci_resource_end((dev), (bar)) - \ 1504 pci_resource_start((dev), (bar)) + 1)) 1505 1506 /* Similar to the helpers above, these manipulate per-pci_dev 1507 * driver-specific data. They are really just a wrapper around 1508 * the generic device structure functions of these calls. 1509 */ 1510 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1511 { 1512 return dev_get_drvdata(&pdev->dev); 1513 } 1514 1515 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1516 { 1517 dev_set_drvdata(&pdev->dev, data); 1518 } 1519 1520 /* If you want to know what to call your pci_dev, ask this function. 1521 * Again, it's a wrapper around the generic device. 1522 */ 1523 static inline const char *pci_name(const struct pci_dev *pdev) 1524 { 1525 return dev_name(&pdev->dev); 1526 } 1527 1528 1529 /* Some archs don't want to expose struct resource to userland as-is 1530 * in sysfs and /proc 1531 */ 1532 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1533 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1534 const struct resource *rsrc, resource_size_t *start, 1535 resource_size_t *end) 1536 { 1537 *start = rsrc->start; 1538 *end = rsrc->end; 1539 } 1540 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1541 1542 1543 /* 1544 * The world is not perfect and supplies us with broken PCI devices. 1545 * For at least a part of these bugs we need a work-around, so both 1546 * generic (drivers/pci/quirks.c) and per-architecture code can define 1547 * fixup hooks to be called for particular buggy devices. 1548 */ 1549 1550 struct pci_fixup { 1551 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1552 u16 device; /* You can use PCI_ANY_ID here of course */ 1553 u32 class; /* You can use PCI_ANY_ID here too */ 1554 unsigned int class_shift; /* should be 0, 8, 16 */ 1555 void (*hook)(struct pci_dev *dev); 1556 }; 1557 1558 enum pci_fixup_pass { 1559 pci_fixup_early, /* Before probing BARs */ 1560 pci_fixup_header, /* After reading configuration header */ 1561 pci_fixup_final, /* Final phase of device fixups */ 1562 pci_fixup_enable, /* pci_enable_device() time */ 1563 pci_fixup_resume, /* pci_device_resume() */ 1564 pci_fixup_suspend, /* pci_device_suspend */ 1565 pci_fixup_resume_early, /* pci_device_resume_early() */ 1566 }; 1567 1568 /* Anonymous variables would be nice... */ 1569 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1570 class_shift, hook) \ 1571 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1572 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1573 = { vendor, device, class, class_shift, hook }; 1574 1575 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1576 class_shift, hook) \ 1577 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1578 hook, vendor, device, class, class_shift, hook) 1579 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1580 class_shift, hook) \ 1581 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1582 hook, vendor, device, class, class_shift, hook) 1583 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1584 class_shift, hook) \ 1585 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1586 hook, vendor, device, class, class_shift, hook) 1587 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1588 class_shift, hook) \ 1589 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1590 hook, vendor, device, class, class_shift, hook) 1591 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1592 class_shift, hook) \ 1593 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1594 resume##hook, vendor, device, class, \ 1595 class_shift, hook) 1596 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1597 class_shift, hook) \ 1598 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1599 resume_early##hook, vendor, device, \ 1600 class, class_shift, hook) 1601 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1602 class_shift, hook) \ 1603 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1604 suspend##hook, vendor, device, class, \ 1605 class_shift, hook) 1606 1607 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1608 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1609 hook, vendor, device, PCI_ANY_ID, 0, hook) 1610 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1611 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1612 hook, vendor, device, PCI_ANY_ID, 0, hook) 1613 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1614 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1615 hook, vendor, device, PCI_ANY_ID, 0, hook) 1616 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1617 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1618 hook, vendor, device, PCI_ANY_ID, 0, hook) 1619 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1620 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1621 resume##hook, vendor, device, \ 1622 PCI_ANY_ID, 0, hook) 1623 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1624 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1625 resume_early##hook, vendor, device, \ 1626 PCI_ANY_ID, 0, hook) 1627 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1628 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1629 suspend##hook, vendor, device, \ 1630 PCI_ANY_ID, 0, hook) 1631 1632 #ifdef CONFIG_PCI_QUIRKS 1633 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1634 struct pci_dev *pci_get_dma_source(struct pci_dev *dev); 1635 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1636 #else 1637 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1638 struct pci_dev *dev) {} 1639 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev) 1640 { 1641 return pci_dev_get(dev); 1642 } 1643 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1644 u16 acs_flags) 1645 { 1646 return -ENOTTY; 1647 } 1648 #endif 1649 1650 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1651 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1652 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1653 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1654 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1655 const char *name); 1656 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1657 1658 extern int pci_pci_problems; 1659 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1660 #define PCIPCI_TRITON 2 1661 #define PCIPCI_NATOMA 4 1662 #define PCIPCI_VIAETBF 8 1663 #define PCIPCI_VSFX 16 1664 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1665 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1666 1667 extern unsigned long pci_cardbus_io_size; 1668 extern unsigned long pci_cardbus_mem_size; 1669 extern u8 pci_dfl_cache_line_size; 1670 extern u8 pci_cache_line_size; 1671 1672 extern unsigned long pci_hotplug_io_size; 1673 extern unsigned long pci_hotplug_mem_size; 1674 1675 /* Architecture-specific versions may override these (weak) */ 1676 int pcibios_add_platform_entries(struct pci_dev *dev); 1677 void pcibios_disable_device(struct pci_dev *dev); 1678 void pcibios_set_master(struct pci_dev *dev); 1679 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1680 enum pcie_reset_state state); 1681 int pcibios_add_device(struct pci_dev *dev); 1682 void pcibios_release_device(struct pci_dev *dev); 1683 1684 #ifdef CONFIG_HIBERNATE_CALLBACKS 1685 extern struct dev_pm_ops pcibios_pm_ops; 1686 #endif 1687 1688 #ifdef CONFIG_PCI_MMCONFIG 1689 void __init pci_mmcfg_early_init(void); 1690 void __init pci_mmcfg_late_init(void); 1691 #else 1692 static inline void pci_mmcfg_early_init(void) { } 1693 static inline void pci_mmcfg_late_init(void) { } 1694 #endif 1695 1696 int pci_ext_cfg_avail(void); 1697 1698 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1699 1700 #ifdef CONFIG_PCI_IOV 1701 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1702 void pci_disable_sriov(struct pci_dev *dev); 1703 irqreturn_t pci_sriov_migration(struct pci_dev *dev); 1704 int pci_num_vf(struct pci_dev *dev); 1705 int pci_vfs_assigned(struct pci_dev *dev); 1706 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1707 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1708 #else 1709 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1710 { 1711 return -ENODEV; 1712 } 1713 static inline void pci_disable_sriov(struct pci_dev *dev) 1714 { 1715 } 1716 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) 1717 { 1718 return IRQ_NONE; 1719 } 1720 static inline int pci_num_vf(struct pci_dev *dev) 1721 { 1722 return 0; 1723 } 1724 static inline int pci_vfs_assigned(struct pci_dev *dev) 1725 { 1726 return 0; 1727 } 1728 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1729 { 1730 return 0; 1731 } 1732 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1733 { 1734 return 0; 1735 } 1736 #endif 1737 1738 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1739 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1740 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1741 #endif 1742 1743 /** 1744 * pci_pcie_cap - get the saved PCIe capability offset 1745 * @dev: PCI device 1746 * 1747 * PCIe capability offset is calculated at PCI device initialization 1748 * time and saved in the data structure. This function returns saved 1749 * PCIe capability offset. Using this instead of pci_find_capability() 1750 * reduces unnecessary search in the PCI configuration space. If you 1751 * need to calculate PCIe capability offset from raw device for some 1752 * reasons, please use pci_find_capability() instead. 1753 */ 1754 static inline int pci_pcie_cap(struct pci_dev *dev) 1755 { 1756 return dev->pcie_cap; 1757 } 1758 1759 /** 1760 * pci_is_pcie - check if the PCI device is PCI Express capable 1761 * @dev: PCI device 1762 * 1763 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1764 */ 1765 static inline bool pci_is_pcie(struct pci_dev *dev) 1766 { 1767 return pci_pcie_cap(dev); 1768 } 1769 1770 /** 1771 * pcie_caps_reg - get the PCIe Capabilities Register 1772 * @dev: PCI device 1773 */ 1774 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1775 { 1776 return dev->pcie_flags_reg; 1777 } 1778 1779 /** 1780 * pci_pcie_type - get the PCIe device/port type 1781 * @dev: PCI device 1782 */ 1783 static inline int pci_pcie_type(const struct pci_dev *dev) 1784 { 1785 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1786 } 1787 1788 void pci_request_acs(void); 1789 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1790 bool pci_acs_path_enabled(struct pci_dev *start, 1791 struct pci_dev *end, u16 acs_flags); 1792 1793 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1794 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) 1795 1796 /* Large Resource Data Type Tag Item Names */ 1797 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1798 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1799 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1800 1801 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1802 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1803 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1804 1805 /* Small Resource Data Type Tag Item Names */ 1806 #define PCI_VPD_STIN_END 0x78 /* End */ 1807 1808 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1809 1810 #define PCI_VPD_SRDT_TIN_MASK 0x78 1811 #define PCI_VPD_SRDT_LEN_MASK 0x07 1812 1813 #define PCI_VPD_LRDT_TAG_SIZE 3 1814 #define PCI_VPD_SRDT_TAG_SIZE 1 1815 1816 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1817 1818 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1819 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1820 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1821 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1822 1823 /** 1824 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1825 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1826 * 1827 * Returns the extracted Large Resource Data Type length. 1828 */ 1829 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1830 { 1831 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1832 } 1833 1834 /** 1835 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1836 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1837 * 1838 * Returns the extracted Small Resource Data Type length. 1839 */ 1840 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1841 { 1842 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1843 } 1844 1845 /** 1846 * pci_vpd_info_field_size - Extracts the information field length 1847 * @lrdt: Pointer to the beginning of an information field header 1848 * 1849 * Returns the extracted information field length. 1850 */ 1851 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1852 { 1853 return info_field[2]; 1854 } 1855 1856 /** 1857 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1858 * @buf: Pointer to buffered vpd data 1859 * @off: The offset into the buffer at which to begin the search 1860 * @len: The length of the vpd buffer 1861 * @rdt: The Resource Data Type to search for 1862 * 1863 * Returns the index where the Resource Data Type was found or 1864 * -ENOENT otherwise. 1865 */ 1866 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1867 1868 /** 1869 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1870 * @buf: Pointer to buffered vpd data 1871 * @off: The offset into the buffer at which to begin the search 1872 * @len: The length of the buffer area, relative to off, in which to search 1873 * @kw: The keyword to search for 1874 * 1875 * Returns the index where the information field keyword was found or 1876 * -ENOENT otherwise. 1877 */ 1878 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1879 unsigned int len, const char *kw); 1880 1881 /* PCI <-> OF binding helpers */ 1882 #ifdef CONFIG_OF 1883 struct device_node; 1884 void pci_set_of_node(struct pci_dev *dev); 1885 void pci_release_of_node(struct pci_dev *dev); 1886 void pci_set_bus_of_node(struct pci_bus *bus); 1887 void pci_release_bus_of_node(struct pci_bus *bus); 1888 1889 /* Arch may override this (weak) */ 1890 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1891 1892 static inline struct device_node * 1893 pci_device_to_OF_node(const struct pci_dev *pdev) 1894 { 1895 return pdev ? pdev->dev.of_node : NULL; 1896 } 1897 1898 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1899 { 1900 return bus ? bus->dev.of_node : NULL; 1901 } 1902 1903 #else /* CONFIG_OF */ 1904 static inline void pci_set_of_node(struct pci_dev *dev) { } 1905 static inline void pci_release_of_node(struct pci_dev *dev) { } 1906 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1907 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1908 #endif /* CONFIG_OF */ 1909 1910 #ifdef CONFIG_EEH 1911 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1912 { 1913 return pdev->dev.archdata.edev; 1914 } 1915 #endif 1916 1917 /** 1918 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device 1919 * @pdev: the PCI device 1920 * 1921 * if the device is PCIE, return NULL 1922 * if the device isn't connected to a PCIe bridge (that is its parent is a 1923 * legacy PCI bridge and the bridge is directly connected to bus 0), return its 1924 * parent 1925 */ 1926 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); 1927 1928 #endif /* LINUX_PCI_H */ 1929