1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <linux/resource_ext.h> 33 #include <uapi/linux/pci.h> 34 35 #include <linux/pci_ids.h> 36 37 /* 38 * The PCI interface treats multi-function devices as independent 39 * devices. The slot/function address of each device is encoded 40 * in a single byte as follows: 41 * 42 * 7:3 = slot 43 * 2:0 = function 44 * 45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 46 * In the interest of not exposing interfaces to user-space unnecessarily, 47 * the following kernel-only defines are being added here. 48 */ 49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 52 53 /* pci_slot represents a physical slot */ 54 struct pci_slot { 55 struct pci_bus *bus; /* The bus this slot is on */ 56 struct list_head list; /* node in list of slots on this bus */ 57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 59 struct kobject kobj; 60 }; 61 62 static inline const char *pci_slot_name(const struct pci_slot *slot) 63 { 64 return kobject_name(&slot->kobj); 65 } 66 67 /* File state for mmap()s on /proc/bus/pci/X/Y */ 68 enum pci_mmap_state { 69 pci_mmap_io, 70 pci_mmap_mem 71 }; 72 73 /* This defines the direction arg to the DMA mapping routines. */ 74 #define PCI_DMA_BIDIRECTIONAL 0 75 #define PCI_DMA_TODEVICE 1 76 #define PCI_DMA_FROMDEVICE 2 77 #define PCI_DMA_NONE 3 78 79 /* 80 * For PCI devices, the region numbers are assigned this way: 81 */ 82 enum { 83 /* #0-5: standard PCI resources */ 84 PCI_STD_RESOURCES, 85 PCI_STD_RESOURCE_END = 5, 86 87 /* #6: expansion ROM resource */ 88 PCI_ROM_RESOURCE, 89 90 /* device specific resources */ 91 #ifdef CONFIG_PCI_IOV 92 PCI_IOV_RESOURCES, 93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 94 #endif 95 96 /* resources assigned to buses behind the bridge */ 97 #define PCI_BRIDGE_RESOURCE_NUM 4 98 99 PCI_BRIDGE_RESOURCES, 100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 101 PCI_BRIDGE_RESOURCE_NUM - 1, 102 103 /* total resources associated with a PCI device */ 104 PCI_NUM_RESOURCES, 105 106 /* preserve this for compatibility */ 107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 108 }; 109 110 typedef int __bitwise pci_power_t; 111 112 #define PCI_D0 ((pci_power_t __force) 0) 113 #define PCI_D1 ((pci_power_t __force) 1) 114 #define PCI_D2 ((pci_power_t __force) 2) 115 #define PCI_D3hot ((pci_power_t __force) 3) 116 #define PCI_D3cold ((pci_power_t __force) 4) 117 #define PCI_UNKNOWN ((pci_power_t __force) 5) 118 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 119 120 /* Remember to update this when the list above changes! */ 121 extern const char *pci_power_names[]; 122 123 static inline const char *pci_power_name(pci_power_t state) 124 { 125 return pci_power_names[1 + (int) state]; 126 } 127 128 #define PCI_PM_D2_DELAY 200 129 #define PCI_PM_D3_WAIT 10 130 #define PCI_PM_D3COLD_WAIT 100 131 #define PCI_PM_BUS_WAIT 50 132 133 /** The pci_channel state describes connectivity between the CPU and 134 * the pci device. If some PCI bus between here and the pci device 135 * has crashed or locked up, this info is reflected here. 136 */ 137 typedef unsigned int __bitwise pci_channel_state_t; 138 139 enum pci_channel_state { 140 /* I/O channel is in normal state */ 141 pci_channel_io_normal = (__force pci_channel_state_t) 1, 142 143 /* I/O to channel is blocked */ 144 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 145 146 /* PCI card is dead */ 147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 148 }; 149 150 typedef unsigned int __bitwise pcie_reset_state_t; 151 152 enum pcie_reset_state { 153 /* Reset is NOT asserted (Use to deassert reset) */ 154 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 155 156 /* Use #PERST to reset PCIe device */ 157 pcie_warm_reset = (__force pcie_reset_state_t) 2, 158 159 /* Use PCIe Hot Reset to reset device */ 160 pcie_hot_reset = (__force pcie_reset_state_t) 3 161 }; 162 163 typedef unsigned short __bitwise pci_dev_flags_t; 164 enum pci_dev_flags { 165 /* INTX_DISABLE in PCI_COMMAND register disables MSI 166 * generation too. 167 */ 168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 169 /* Device configuration is irrevocably lost if disabled into D3 */ 170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 171 /* Provide indication device is assigned by a Virtual Machine Manager */ 172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 173 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 175 /* Flag to indicate the device uses dma_alias_devfn */ 176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), 177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 179 /* Do not use bus resets for device */ 180 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 181 /* Do not use PM reset even if device advertises NoSoftRst- */ 182 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 183 }; 184 185 enum pci_irq_reroute_variant { 186 INTEL_IRQ_REROUTE_VARIANT = 1, 187 MAX_IRQ_REROUTE_VARIANTS = 3 188 }; 189 190 typedef unsigned short __bitwise pci_bus_flags_t; 191 enum pci_bus_flags { 192 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 193 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 194 }; 195 196 /* These values come from the PCI Express Spec */ 197 enum pcie_link_width { 198 PCIE_LNK_WIDTH_RESRV = 0x00, 199 PCIE_LNK_X1 = 0x01, 200 PCIE_LNK_X2 = 0x02, 201 PCIE_LNK_X4 = 0x04, 202 PCIE_LNK_X8 = 0x08, 203 PCIE_LNK_X12 = 0x0C, 204 PCIE_LNK_X16 = 0x10, 205 PCIE_LNK_X32 = 0x20, 206 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 207 }; 208 209 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 210 enum pci_bus_speed { 211 PCI_SPEED_33MHz = 0x00, 212 PCI_SPEED_66MHz = 0x01, 213 PCI_SPEED_66MHz_PCIX = 0x02, 214 PCI_SPEED_100MHz_PCIX = 0x03, 215 PCI_SPEED_133MHz_PCIX = 0x04, 216 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 217 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 218 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 219 PCI_SPEED_66MHz_PCIX_266 = 0x09, 220 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 221 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 222 AGP_UNKNOWN = 0x0c, 223 AGP_1X = 0x0d, 224 AGP_2X = 0x0e, 225 AGP_4X = 0x0f, 226 AGP_8X = 0x10, 227 PCI_SPEED_66MHz_PCIX_533 = 0x11, 228 PCI_SPEED_100MHz_PCIX_533 = 0x12, 229 PCI_SPEED_133MHz_PCIX_533 = 0x13, 230 PCIE_SPEED_2_5GT = 0x14, 231 PCIE_SPEED_5_0GT = 0x15, 232 PCIE_SPEED_8_0GT = 0x16, 233 PCI_SPEED_UNKNOWN = 0xff, 234 }; 235 236 struct pci_cap_saved_data { 237 u16 cap_nr; 238 bool cap_extended; 239 unsigned int size; 240 u32 data[0]; 241 }; 242 243 struct pci_cap_saved_state { 244 struct hlist_node next; 245 struct pci_cap_saved_data cap; 246 }; 247 248 struct pcie_link_state; 249 struct pci_vpd; 250 struct pci_sriov; 251 struct pci_ats; 252 253 /* 254 * The pci_dev structure is used to describe PCI devices. 255 */ 256 struct pci_dev { 257 struct list_head bus_list; /* node in per-bus list */ 258 struct pci_bus *bus; /* bus this device is on */ 259 struct pci_bus *subordinate; /* bus this device bridges to */ 260 261 void *sysdata; /* hook for sys-specific extension */ 262 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 263 struct pci_slot *slot; /* Physical slot this device is in */ 264 265 unsigned int devfn; /* encoded device & function index */ 266 unsigned short vendor; 267 unsigned short device; 268 unsigned short subsystem_vendor; 269 unsigned short subsystem_device; 270 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 271 u8 revision; /* PCI revision, low byte of class word */ 272 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 273 u8 pcie_cap; /* PCIe capability offset */ 274 u8 msi_cap; /* MSI capability offset */ 275 u8 msix_cap; /* MSI-X capability offset */ 276 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 277 u8 rom_base_reg; /* which config register controls the ROM */ 278 u8 pin; /* which interrupt pin this device uses */ 279 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 280 u8 dma_alias_devfn;/* devfn of DMA alias, if any */ 281 282 struct pci_driver *driver; /* which driver has allocated this device */ 283 u64 dma_mask; /* Mask of the bits of bus address this 284 device implements. Normally this is 285 0xffffffff. You only need to change 286 this if your device has broken DMA 287 or supports 64-bit transfers. */ 288 289 struct device_dma_parameters dma_parms; 290 291 pci_power_t current_state; /* Current operating state. In ACPI-speak, 292 this is D0-D3, D0 being fully functional, 293 and D3 being off. */ 294 u8 pm_cap; /* PM capability offset */ 295 unsigned int pme_support:5; /* Bitmask of states from which PME# 296 can be generated */ 297 unsigned int pme_interrupt:1; 298 unsigned int pme_poll:1; /* Poll device's PME status bit */ 299 unsigned int d1_support:1; /* Low power state D1 is supported */ 300 unsigned int d2_support:1; /* Low power state D2 is supported */ 301 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 302 unsigned int no_d3cold:1; /* D3cold is forbidden */ 303 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 304 unsigned int mmio_always_on:1; /* disallow turning off io/mem 305 decoding during bar sizing */ 306 unsigned int wakeup_prepared:1; 307 unsigned int runtime_d3cold:1; /* whether go through runtime 308 D3cold, not set for devices 309 powered on/off by the 310 corresponding bridge */ 311 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 312 unsigned int d3_delay; /* D3->D0 transition time in ms */ 313 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 314 315 #ifdef CONFIG_PCIEASPM 316 struct pcie_link_state *link_state; /* ASPM link state */ 317 #endif 318 319 pci_channel_state_t error_state; /* current connectivity state */ 320 struct device dev; /* Generic device interface */ 321 322 int cfg_size; /* Size of configuration space */ 323 324 /* 325 * Instead of touching interrupt line and base address registers 326 * directly, use the values stored here. They might be different! 327 */ 328 unsigned int irq; 329 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 330 331 bool match_driver; /* Skip attaching driver */ 332 /* These fields are used by common fixups */ 333 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 334 unsigned int multifunction:1;/* Part of multi-function device */ 335 /* keep track of device state */ 336 unsigned int is_added:1; 337 unsigned int is_busmaster:1; /* device is busmaster */ 338 unsigned int no_msi:1; /* device may not use msi */ 339 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 340 unsigned int block_cfg_access:1; /* config space access is blocked */ 341 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 342 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 343 unsigned int msi_enabled:1; 344 unsigned int msix_enabled:1; 345 unsigned int ari_enabled:1; /* ARI forwarding */ 346 unsigned int is_managed:1; 347 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 348 unsigned int state_saved:1; 349 unsigned int is_physfn:1; 350 unsigned int is_virtfn:1; 351 unsigned int reset_fn:1; 352 unsigned int is_hotplug_bridge:1; 353 unsigned int __aer_firmware_first_valid:1; 354 unsigned int __aer_firmware_first:1; 355 unsigned int broken_intx_masking:1; 356 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 357 unsigned int irq_managed:1; 358 unsigned int has_secondary_link:1; 359 pci_dev_flags_t dev_flags; 360 atomic_t enable_cnt; /* pci_enable_device has been called */ 361 362 u32 saved_config_space[16]; /* config space saved at suspend time */ 363 struct hlist_head saved_cap_space; 364 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 365 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 366 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 367 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 368 #ifdef CONFIG_PCI_MSI 369 struct list_head msi_list; 370 const struct attribute_group **msi_irq_groups; 371 #endif 372 struct pci_vpd *vpd; 373 #ifdef CONFIG_PCI_ATS 374 union { 375 struct pci_sriov *sriov; /* SR-IOV capability related */ 376 struct pci_dev *physfn; /* the PF this VF is associated with */ 377 }; 378 struct pci_ats *ats; /* Address Translation Service */ 379 #endif 380 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 381 size_t romlen; /* Length of ROM if it's not from the BAR */ 382 char *driver_override; /* Driver name to force a match */ 383 }; 384 385 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 386 { 387 #ifdef CONFIG_PCI_IOV 388 if (dev->is_virtfn) 389 dev = dev->physfn; 390 #endif 391 return dev; 392 } 393 394 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 395 396 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 397 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 398 399 static inline int pci_channel_offline(struct pci_dev *pdev) 400 { 401 return (pdev->error_state != pci_channel_io_normal); 402 } 403 404 struct pci_host_bridge { 405 struct device dev; 406 struct pci_bus *bus; /* root bus */ 407 struct list_head windows; /* resource_entry */ 408 void (*release_fn)(struct pci_host_bridge *); 409 void *release_data; 410 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 411 }; 412 413 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 414 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 415 void (*release_fn)(struct pci_host_bridge *), 416 void *release_data); 417 418 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 419 420 /* 421 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 422 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 423 * buses below host bridges or subtractive decode bridges) go in the list. 424 * Use pci_bus_for_each_resource() to iterate through all the resources. 425 */ 426 427 /* 428 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 429 * and there's no way to program the bridge with the details of the window. 430 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 431 * decode bit set, because they are explicit and can be programmed with _SRS. 432 */ 433 #define PCI_SUBTRACTIVE_DECODE 0x1 434 435 struct pci_bus_resource { 436 struct list_head list; 437 struct resource *res; 438 unsigned int flags; 439 }; 440 441 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 442 443 struct pci_bus { 444 struct list_head node; /* node in list of buses */ 445 struct pci_bus *parent; /* parent bus this bridge is on */ 446 struct list_head children; /* list of child buses */ 447 struct list_head devices; /* list of devices on this bus */ 448 struct pci_dev *self; /* bridge device as seen by parent */ 449 struct list_head slots; /* list of slots on this bus */ 450 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 451 struct list_head resources; /* address space routed to this bus */ 452 struct resource busn_res; /* bus numbers routed to this bus */ 453 454 struct pci_ops *ops; /* configuration access functions */ 455 struct msi_controller *msi; /* MSI controller */ 456 void *sysdata; /* hook for sys-specific extension */ 457 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 458 459 unsigned char number; /* bus number */ 460 unsigned char primary; /* number of primary bridge */ 461 unsigned char max_bus_speed; /* enum pci_bus_speed */ 462 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 463 #ifdef CONFIG_PCI_DOMAINS_GENERIC 464 int domain_nr; 465 #endif 466 467 char name[48]; 468 469 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 470 pci_bus_flags_t bus_flags; /* inherited by child buses */ 471 struct device *bridge; 472 struct device dev; 473 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 474 struct bin_attribute *legacy_mem; /* legacy mem */ 475 unsigned int is_added:1; 476 }; 477 478 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 479 480 /* 481 * Returns true if the PCI bus is root (behind host-PCI bridge), 482 * false otherwise 483 * 484 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 485 * This is incorrect because "virtual" buses added for SR-IOV (via 486 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 487 */ 488 static inline bool pci_is_root_bus(struct pci_bus *pbus) 489 { 490 return !(pbus->parent); 491 } 492 493 /** 494 * pci_is_bridge - check if the PCI device is a bridge 495 * @dev: PCI device 496 * 497 * Return true if the PCI device is bridge whether it has subordinate 498 * or not. 499 */ 500 static inline bool pci_is_bridge(struct pci_dev *dev) 501 { 502 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 503 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 504 } 505 506 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 507 { 508 dev = pci_physfn(dev); 509 if (pci_is_root_bus(dev->bus)) 510 return NULL; 511 512 return dev->bus->self; 513 } 514 515 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 516 void pci_put_host_bridge_device(struct device *dev); 517 518 #ifdef CONFIG_PCI_MSI 519 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 520 { 521 return pci_dev->msi_enabled || pci_dev->msix_enabled; 522 } 523 #else 524 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 525 #endif 526 527 /* 528 * Error values that may be returned by PCI functions. 529 */ 530 #define PCIBIOS_SUCCESSFUL 0x00 531 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 532 #define PCIBIOS_BAD_VENDOR_ID 0x83 533 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 534 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 535 #define PCIBIOS_SET_FAILED 0x88 536 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 537 538 /* 539 * Translate above to generic errno for passing back through non-PCI code. 540 */ 541 static inline int pcibios_err_to_errno(int err) 542 { 543 if (err <= PCIBIOS_SUCCESSFUL) 544 return err; /* Assume already errno */ 545 546 switch (err) { 547 case PCIBIOS_FUNC_NOT_SUPPORTED: 548 return -ENOENT; 549 case PCIBIOS_BAD_VENDOR_ID: 550 return -ENOTTY; 551 case PCIBIOS_DEVICE_NOT_FOUND: 552 return -ENODEV; 553 case PCIBIOS_BAD_REGISTER_NUMBER: 554 return -EFAULT; 555 case PCIBIOS_SET_FAILED: 556 return -EIO; 557 case PCIBIOS_BUFFER_TOO_SMALL: 558 return -ENOSPC; 559 } 560 561 return -ERANGE; 562 } 563 564 /* Low-level architecture-dependent routines */ 565 566 struct pci_ops { 567 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 568 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 569 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 570 }; 571 572 /* 573 * ACPI needs to be able to access PCI config space before we've done a 574 * PCI bus scan and created pci_bus structures. 575 */ 576 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 577 int reg, int len, u32 *val); 578 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 579 int reg, int len, u32 val); 580 581 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 582 typedef u64 pci_bus_addr_t; 583 #else 584 typedef u32 pci_bus_addr_t; 585 #endif 586 587 struct pci_bus_region { 588 pci_bus_addr_t start; 589 pci_bus_addr_t end; 590 }; 591 592 struct pci_dynids { 593 spinlock_t lock; /* protects list, index */ 594 struct list_head list; /* for IDs added at runtime */ 595 }; 596 597 598 /* 599 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 600 * a set of callbacks in struct pci_error_handlers, that device driver 601 * will be notified of PCI bus errors, and will be driven to recovery 602 * when an error occurs. 603 */ 604 605 typedef unsigned int __bitwise pci_ers_result_t; 606 607 enum pci_ers_result { 608 /* no result/none/not supported in device driver */ 609 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 610 611 /* Device driver can recover without slot reset */ 612 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 613 614 /* Device driver wants slot to be reset. */ 615 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 616 617 /* Device has completely failed, is unrecoverable */ 618 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 619 620 /* Device driver is fully recovered and operational */ 621 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 622 623 /* No AER capabilities registered for the driver */ 624 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 625 }; 626 627 /* PCI bus error event callbacks */ 628 struct pci_error_handlers { 629 /* PCI bus error detected on this device */ 630 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 631 enum pci_channel_state error); 632 633 /* MMIO has been re-enabled, but not DMA */ 634 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 635 636 /* PCI Express link has been reset */ 637 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 638 639 /* PCI slot has been reset */ 640 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 641 642 /* PCI function reset prepare or completed */ 643 void (*reset_notify)(struct pci_dev *dev, bool prepare); 644 645 /* Device driver may resume normal operations */ 646 void (*resume)(struct pci_dev *dev); 647 }; 648 649 650 struct module; 651 struct pci_driver { 652 struct list_head node; 653 const char *name; 654 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 655 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 656 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 657 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 658 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 659 int (*resume_early) (struct pci_dev *dev); 660 int (*resume) (struct pci_dev *dev); /* Device woken up */ 661 void (*shutdown) (struct pci_dev *dev); 662 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 663 const struct pci_error_handlers *err_handler; 664 struct device_driver driver; 665 struct pci_dynids dynids; 666 }; 667 668 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 669 670 /** 671 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 672 * @_table: device table name 673 * 674 * This macro is deprecated and should not be used in new code. 675 */ 676 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 677 const struct pci_device_id _table[] 678 679 /** 680 * PCI_DEVICE - macro used to describe a specific pci device 681 * @vend: the 16 bit PCI Vendor ID 682 * @dev: the 16 bit PCI Device ID 683 * 684 * This macro is used to create a struct pci_device_id that matches a 685 * specific device. The subvendor and subdevice fields will be set to 686 * PCI_ANY_ID. 687 */ 688 #define PCI_DEVICE(vend,dev) \ 689 .vendor = (vend), .device = (dev), \ 690 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 691 692 /** 693 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 694 * @vend: the 16 bit PCI Vendor ID 695 * @dev: the 16 bit PCI Device ID 696 * @subvend: the 16 bit PCI Subvendor ID 697 * @subdev: the 16 bit PCI Subdevice ID 698 * 699 * This macro is used to create a struct pci_device_id that matches a 700 * specific device with subsystem information. 701 */ 702 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 703 .vendor = (vend), .device = (dev), \ 704 .subvendor = (subvend), .subdevice = (subdev) 705 706 /** 707 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 708 * @dev_class: the class, subclass, prog-if triple for this device 709 * @dev_class_mask: the class mask for this device 710 * 711 * This macro is used to create a struct pci_device_id that matches a 712 * specific PCI class. The vendor, device, subvendor, and subdevice 713 * fields will be set to PCI_ANY_ID. 714 */ 715 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 716 .class = (dev_class), .class_mask = (dev_class_mask), \ 717 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 718 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 719 720 /** 721 * PCI_VDEVICE - macro used to describe a specific pci device in short form 722 * @vend: the vendor name 723 * @dev: the 16 bit PCI Device ID 724 * 725 * This macro is used to create a struct pci_device_id that matches a 726 * specific PCI device. The subvendor, and subdevice fields will be set 727 * to PCI_ANY_ID. The macro allows the next field to follow as the device 728 * private data. 729 */ 730 731 #define PCI_VDEVICE(vend, dev) \ 732 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 733 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 734 735 /* these external functions are only available when PCI support is enabled */ 736 #ifdef CONFIG_PCI 737 738 void pcie_bus_configure_settings(struct pci_bus *bus); 739 740 enum pcie_bus_config_types { 741 PCIE_BUS_TUNE_OFF, 742 PCIE_BUS_SAFE, 743 PCIE_BUS_PERFORMANCE, 744 PCIE_BUS_PEER2PEER, 745 }; 746 747 extern enum pcie_bus_config_types pcie_bus_config; 748 749 extern struct bus_type pci_bus_type; 750 751 /* Do NOT directly access these two variables, unless you are arch-specific PCI 752 * code, or PCI core code. */ 753 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 754 /* Some device drivers need know if PCI is initiated */ 755 int no_pci_devices(void); 756 757 void pcibios_resource_survey_bus(struct pci_bus *bus); 758 void pcibios_add_bus(struct pci_bus *bus); 759 void pcibios_remove_bus(struct pci_bus *bus); 760 void pcibios_fixup_bus(struct pci_bus *); 761 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 762 /* Architecture-specific versions may override this (weak) */ 763 char *pcibios_setup(char *str); 764 765 /* Used only when drivers/pci/setup.c is used */ 766 resource_size_t pcibios_align_resource(void *, const struct resource *, 767 resource_size_t, 768 resource_size_t); 769 void pcibios_update_irq(struct pci_dev *, int irq); 770 771 /* Weak but can be overriden by arch */ 772 void pci_fixup_cardbus(struct pci_bus *); 773 774 /* Generic PCI functions used internally */ 775 776 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 777 struct resource *res); 778 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 779 struct pci_bus_region *region); 780 void pcibios_scan_specific_bus(int busn); 781 struct pci_bus *pci_find_bus(int domain, int busnr); 782 void pci_bus_add_devices(const struct pci_bus *bus); 783 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 784 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 785 struct pci_ops *ops, void *sysdata, 786 struct list_head *resources); 787 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 788 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 789 void pci_bus_release_busn_res(struct pci_bus *b); 790 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 791 struct pci_ops *ops, void *sysdata, 792 struct list_head *resources); 793 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 794 int busnr); 795 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 796 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 797 const char *name, 798 struct hotplug_slot *hotplug); 799 void pci_destroy_slot(struct pci_slot *slot); 800 int pci_scan_slot(struct pci_bus *bus, int devfn); 801 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 802 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 803 unsigned int pci_scan_child_bus(struct pci_bus *bus); 804 void pci_bus_add_device(struct pci_dev *dev); 805 void pci_read_bridge_bases(struct pci_bus *child); 806 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 807 struct resource *res); 808 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 809 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 810 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 811 struct pci_dev *pci_dev_get(struct pci_dev *dev); 812 void pci_dev_put(struct pci_dev *dev); 813 void pci_remove_bus(struct pci_bus *b); 814 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 815 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 816 void pci_stop_root_bus(struct pci_bus *bus); 817 void pci_remove_root_bus(struct pci_bus *bus); 818 void pci_setup_cardbus(struct pci_bus *bus); 819 void pci_sort_breadthfirst(void); 820 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 821 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 822 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 823 824 /* Generic PCI functions exported to card drivers */ 825 826 enum pci_lost_interrupt_reason { 827 PCI_LOST_IRQ_NO_INFORMATION = 0, 828 PCI_LOST_IRQ_DISABLE_MSI, 829 PCI_LOST_IRQ_DISABLE_MSIX, 830 PCI_LOST_IRQ_DISABLE_ACPI, 831 }; 832 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 833 int pci_find_capability(struct pci_dev *dev, int cap); 834 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 835 int pci_find_ext_capability(struct pci_dev *dev, int cap); 836 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 837 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 838 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 839 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 840 841 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 842 struct pci_dev *from); 843 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 844 unsigned int ss_vendor, unsigned int ss_device, 845 struct pci_dev *from); 846 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 847 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 848 unsigned int devfn); 849 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 850 unsigned int devfn) 851 { 852 return pci_get_domain_bus_and_slot(0, bus, devfn); 853 } 854 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 855 int pci_dev_present(const struct pci_device_id *ids); 856 857 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 858 int where, u8 *val); 859 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 860 int where, u16 *val); 861 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 862 int where, u32 *val); 863 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 864 int where, u8 val); 865 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 866 int where, u16 val); 867 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 868 int where, u32 val); 869 870 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 871 int where, int size, u32 *val); 872 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 873 int where, int size, u32 val); 874 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 875 int where, int size, u32 *val); 876 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 877 int where, int size, u32 val); 878 879 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 880 881 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 882 { 883 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 884 } 885 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 886 { 887 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 888 } 889 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 890 u32 *val) 891 { 892 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 893 } 894 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 895 { 896 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 897 } 898 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 899 { 900 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 901 } 902 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 903 u32 val) 904 { 905 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 906 } 907 908 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 909 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 910 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 911 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 912 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 913 u16 clear, u16 set); 914 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 915 u32 clear, u32 set); 916 917 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 918 u16 set) 919 { 920 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 921 } 922 923 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 924 u32 set) 925 { 926 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 927 } 928 929 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 930 u16 clear) 931 { 932 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 933 } 934 935 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 936 u32 clear) 937 { 938 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 939 } 940 941 /* user-space driven config access */ 942 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 943 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 944 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 945 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 946 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 947 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 948 949 int __must_check pci_enable_device(struct pci_dev *dev); 950 int __must_check pci_enable_device_io(struct pci_dev *dev); 951 int __must_check pci_enable_device_mem(struct pci_dev *dev); 952 int __must_check pci_reenable_device(struct pci_dev *); 953 int __must_check pcim_enable_device(struct pci_dev *pdev); 954 void pcim_pin_device(struct pci_dev *pdev); 955 956 static inline int pci_is_enabled(struct pci_dev *pdev) 957 { 958 return (atomic_read(&pdev->enable_cnt) > 0); 959 } 960 961 static inline int pci_is_managed(struct pci_dev *pdev) 962 { 963 return pdev->is_managed; 964 } 965 966 void pci_disable_device(struct pci_dev *dev); 967 968 extern unsigned int pcibios_max_latency; 969 void pci_set_master(struct pci_dev *dev); 970 void pci_clear_master(struct pci_dev *dev); 971 972 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 973 int pci_set_cacheline_size(struct pci_dev *dev); 974 #define HAVE_PCI_SET_MWI 975 int __must_check pci_set_mwi(struct pci_dev *dev); 976 int pci_try_set_mwi(struct pci_dev *dev); 977 void pci_clear_mwi(struct pci_dev *dev); 978 void pci_intx(struct pci_dev *dev, int enable); 979 bool pci_intx_mask_supported(struct pci_dev *dev); 980 bool pci_check_and_mask_intx(struct pci_dev *dev); 981 bool pci_check_and_unmask_intx(struct pci_dev *dev); 982 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 983 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 984 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 985 int pci_wait_for_pending_transaction(struct pci_dev *dev); 986 int pcix_get_max_mmrbc(struct pci_dev *dev); 987 int pcix_get_mmrbc(struct pci_dev *dev); 988 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 989 int pcie_get_readrq(struct pci_dev *dev); 990 int pcie_set_readrq(struct pci_dev *dev, int rq); 991 int pcie_get_mps(struct pci_dev *dev); 992 int pcie_set_mps(struct pci_dev *dev, int mps); 993 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 994 enum pcie_link_width *width); 995 int __pci_reset_function(struct pci_dev *dev); 996 int __pci_reset_function_locked(struct pci_dev *dev); 997 int pci_reset_function(struct pci_dev *dev); 998 int pci_try_reset_function(struct pci_dev *dev); 999 int pci_probe_reset_slot(struct pci_slot *slot); 1000 int pci_reset_slot(struct pci_slot *slot); 1001 int pci_try_reset_slot(struct pci_slot *slot); 1002 int pci_probe_reset_bus(struct pci_bus *bus); 1003 int pci_reset_bus(struct pci_bus *bus); 1004 int pci_try_reset_bus(struct pci_bus *bus); 1005 void pci_reset_secondary_bus(struct pci_dev *dev); 1006 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1007 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1008 void pci_update_resource(struct pci_dev *dev, int resno); 1009 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1010 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1011 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1012 bool pci_device_is_present(struct pci_dev *pdev); 1013 void pci_ignore_hotplug(struct pci_dev *dev); 1014 1015 /* ROM control related routines */ 1016 int pci_enable_rom(struct pci_dev *pdev); 1017 void pci_disable_rom(struct pci_dev *pdev); 1018 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1019 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1020 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1021 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1022 1023 /* Power management related routines */ 1024 int pci_save_state(struct pci_dev *dev); 1025 void pci_restore_state(struct pci_dev *dev); 1026 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1027 int pci_load_saved_state(struct pci_dev *dev, 1028 struct pci_saved_state *state); 1029 int pci_load_and_free_saved_state(struct pci_dev *dev, 1030 struct pci_saved_state **state); 1031 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1032 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1033 u16 cap); 1034 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1035 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1036 u16 cap, unsigned int size); 1037 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1038 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1039 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1040 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1041 void pci_pme_active(struct pci_dev *dev, bool enable); 1042 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1043 bool runtime, bool enable); 1044 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1045 int pci_prepare_to_sleep(struct pci_dev *dev); 1046 int pci_back_from_sleep(struct pci_dev *dev); 1047 bool pci_dev_run_wake(struct pci_dev *dev); 1048 bool pci_check_pme_status(struct pci_dev *dev); 1049 void pci_pme_wakeup_bus(struct pci_bus *bus); 1050 1051 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1052 bool enable) 1053 { 1054 return __pci_enable_wake(dev, state, false, enable); 1055 } 1056 1057 /* PCI Virtual Channel */ 1058 int pci_save_vc_state(struct pci_dev *dev); 1059 void pci_restore_vc_state(struct pci_dev *dev); 1060 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1061 1062 /* For use by arch with custom probe code */ 1063 void set_pcie_port_type(struct pci_dev *pdev); 1064 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1065 1066 /* Functions for PCI Hotplug drivers to use */ 1067 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1068 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1069 unsigned int pci_rescan_bus(struct pci_bus *bus); 1070 void pci_lock_rescan_remove(void); 1071 void pci_unlock_rescan_remove(void); 1072 1073 /* Vital product data routines */ 1074 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1075 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1076 1077 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1078 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1079 void pci_bus_assign_resources(const struct pci_bus *bus); 1080 void pci_bus_size_bridges(struct pci_bus *bus); 1081 int pci_claim_resource(struct pci_dev *, int); 1082 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1083 void pci_assign_unassigned_resources(void); 1084 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1085 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1086 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1087 void pdev_enable_device(struct pci_dev *); 1088 int pci_enable_resources(struct pci_dev *, int mask); 1089 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1090 int (*)(const struct pci_dev *, u8, u8)); 1091 #define HAVE_PCI_REQ_REGIONS 2 1092 int __must_check pci_request_regions(struct pci_dev *, const char *); 1093 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1094 void pci_release_regions(struct pci_dev *); 1095 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1096 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1097 void pci_release_region(struct pci_dev *, int); 1098 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1099 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1100 void pci_release_selected_regions(struct pci_dev *, int); 1101 1102 /* drivers/pci/bus.c */ 1103 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1104 void pci_bus_put(struct pci_bus *bus); 1105 void pci_add_resource(struct list_head *resources, struct resource *res); 1106 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1107 resource_size_t offset); 1108 void pci_free_resource_list(struct list_head *resources); 1109 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1110 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1111 void pci_bus_remove_resources(struct pci_bus *bus); 1112 1113 #define pci_bus_for_each_resource(bus, res, i) \ 1114 for (i = 0; \ 1115 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1116 i++) 1117 1118 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1119 struct resource *res, resource_size_t size, 1120 resource_size_t align, resource_size_t min, 1121 unsigned long type_mask, 1122 resource_size_t (*alignf)(void *, 1123 const struct resource *, 1124 resource_size_t, 1125 resource_size_t), 1126 void *alignf_data); 1127 1128 1129 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1130 1131 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1132 { 1133 struct pci_bus_region region; 1134 1135 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1136 return region.start; 1137 } 1138 1139 /* Proper probing supporting hot-pluggable devices */ 1140 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1141 const char *mod_name); 1142 1143 /* 1144 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1145 */ 1146 #define pci_register_driver(driver) \ 1147 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1148 1149 void pci_unregister_driver(struct pci_driver *dev); 1150 1151 /** 1152 * module_pci_driver() - Helper macro for registering a PCI driver 1153 * @__pci_driver: pci_driver struct 1154 * 1155 * Helper macro for PCI drivers which do not do anything special in module 1156 * init/exit. This eliminates a lot of boilerplate. Each module may only 1157 * use this macro once, and calling it replaces module_init() and module_exit() 1158 */ 1159 #define module_pci_driver(__pci_driver) \ 1160 module_driver(__pci_driver, pci_register_driver, \ 1161 pci_unregister_driver) 1162 1163 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1164 int pci_add_dynid(struct pci_driver *drv, 1165 unsigned int vendor, unsigned int device, 1166 unsigned int subvendor, unsigned int subdevice, 1167 unsigned int class, unsigned int class_mask, 1168 unsigned long driver_data); 1169 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1170 struct pci_dev *dev); 1171 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1172 int pass); 1173 1174 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1175 void *userdata); 1176 int pci_cfg_space_size(struct pci_dev *dev); 1177 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1178 void pci_setup_bridge(struct pci_bus *bus); 1179 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1180 unsigned long type); 1181 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1182 1183 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1184 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1185 1186 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1187 unsigned int command_bits, u32 flags); 1188 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1189 1190 #include <linux/pci-dma.h> 1191 #include <linux/dmapool.h> 1192 1193 #define pci_pool dma_pool 1194 #define pci_pool_create(name, pdev, size, align, allocation) \ 1195 dma_pool_create(name, &pdev->dev, size, align, allocation) 1196 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1197 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1198 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1199 1200 struct msix_entry { 1201 u32 vector; /* kernel uses to write allocated vector */ 1202 u16 entry; /* driver uses to specify entry, OS writes */ 1203 }; 1204 1205 1206 #ifdef CONFIG_PCI_MSI 1207 int pci_msi_vec_count(struct pci_dev *dev); 1208 void pci_msi_shutdown(struct pci_dev *dev); 1209 void pci_disable_msi(struct pci_dev *dev); 1210 int pci_msix_vec_count(struct pci_dev *dev); 1211 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1212 void pci_msix_shutdown(struct pci_dev *dev); 1213 void pci_disable_msix(struct pci_dev *dev); 1214 void pci_restore_msi_state(struct pci_dev *dev); 1215 int pci_msi_enabled(void); 1216 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1217 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1218 { 1219 int rc = pci_enable_msi_range(dev, nvec, nvec); 1220 if (rc < 0) 1221 return rc; 1222 return 0; 1223 } 1224 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1225 int minvec, int maxvec); 1226 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1227 struct msix_entry *entries, int nvec) 1228 { 1229 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1230 if (rc < 0) 1231 return rc; 1232 return 0; 1233 } 1234 #else 1235 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1236 static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1237 static inline void pci_disable_msi(struct pci_dev *dev) { } 1238 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1239 static inline int pci_enable_msix(struct pci_dev *dev, 1240 struct msix_entry *entries, int nvec) 1241 { return -ENOSYS; } 1242 static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1243 static inline void pci_disable_msix(struct pci_dev *dev) { } 1244 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1245 static inline int pci_msi_enabled(void) { return 0; } 1246 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1247 int maxvec) 1248 { return -ENOSYS; } 1249 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1250 { return -ENOSYS; } 1251 static inline int pci_enable_msix_range(struct pci_dev *dev, 1252 struct msix_entry *entries, int minvec, int maxvec) 1253 { return -ENOSYS; } 1254 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1255 struct msix_entry *entries, int nvec) 1256 { return -ENOSYS; } 1257 #endif 1258 1259 #ifdef CONFIG_PCIEPORTBUS 1260 extern bool pcie_ports_disabled; 1261 extern bool pcie_ports_auto; 1262 #else 1263 #define pcie_ports_disabled true 1264 #define pcie_ports_auto false 1265 #endif 1266 1267 #ifdef CONFIG_PCIEASPM 1268 bool pcie_aspm_support_enabled(void); 1269 #else 1270 static inline bool pcie_aspm_support_enabled(void) { return false; } 1271 #endif 1272 1273 #ifdef CONFIG_PCIEAER 1274 void pci_no_aer(void); 1275 bool pci_aer_available(void); 1276 #else 1277 static inline void pci_no_aer(void) { } 1278 static inline bool pci_aer_available(void) { return false; } 1279 #endif 1280 1281 #ifdef CONFIG_PCIE_ECRC 1282 void pcie_set_ecrc_checking(struct pci_dev *dev); 1283 void pcie_ecrc_get_policy(char *str); 1284 #else 1285 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1286 static inline void pcie_ecrc_get_policy(char *str) { } 1287 #endif 1288 1289 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) 1290 1291 #ifdef CONFIG_HT_IRQ 1292 /* The functions a driver should call */ 1293 int ht_create_irq(struct pci_dev *dev, int idx); 1294 void ht_destroy_irq(unsigned int irq); 1295 #endif /* CONFIG_HT_IRQ */ 1296 1297 void pci_cfg_access_lock(struct pci_dev *dev); 1298 bool pci_cfg_access_trylock(struct pci_dev *dev); 1299 void pci_cfg_access_unlock(struct pci_dev *dev); 1300 1301 /* 1302 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1303 * a PCI domain is defined to be a set of PCI buses which share 1304 * configuration space. 1305 */ 1306 #ifdef CONFIG_PCI_DOMAINS 1307 extern int pci_domains_supported; 1308 int pci_get_new_domain_nr(void); 1309 #else 1310 enum { pci_domains_supported = 0 }; 1311 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1312 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1313 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1314 #endif /* CONFIG_PCI_DOMAINS */ 1315 1316 /* 1317 * Generic implementation for PCI domain support. If your 1318 * architecture does not need custom management of PCI 1319 * domains then this implementation will be used 1320 */ 1321 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1322 static inline int pci_domain_nr(struct pci_bus *bus) 1323 { 1324 return bus->domain_nr; 1325 } 1326 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); 1327 #else 1328 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, 1329 struct device *parent) 1330 { 1331 } 1332 #endif 1333 1334 /* some architectures require additional setup to direct VGA traffic */ 1335 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1336 unsigned int command_bits, u32 flags); 1337 void pci_register_set_vga_state(arch_set_vga_state_t func); 1338 1339 #else /* CONFIG_PCI is not enabled */ 1340 1341 /* 1342 * If the system does not have PCI, clearly these return errors. Define 1343 * these as simple inline functions to avoid hair in drivers. 1344 */ 1345 1346 #define _PCI_NOP(o, s, t) \ 1347 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1348 int where, t val) \ 1349 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1350 1351 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1352 _PCI_NOP(o, word, u16 x) \ 1353 _PCI_NOP(o, dword, u32 x) 1354 _PCI_NOP_ALL(read, *) 1355 _PCI_NOP_ALL(write,) 1356 1357 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1358 unsigned int device, 1359 struct pci_dev *from) 1360 { return NULL; } 1361 1362 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1363 unsigned int device, 1364 unsigned int ss_vendor, 1365 unsigned int ss_device, 1366 struct pci_dev *from) 1367 { return NULL; } 1368 1369 static inline struct pci_dev *pci_get_class(unsigned int class, 1370 struct pci_dev *from) 1371 { return NULL; } 1372 1373 #define pci_dev_present(ids) (0) 1374 #define no_pci_devices() (1) 1375 #define pci_dev_put(dev) do { } while (0) 1376 1377 static inline void pci_set_master(struct pci_dev *dev) { } 1378 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1379 static inline void pci_disable_device(struct pci_dev *dev) { } 1380 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1381 { return -EIO; } 1382 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1383 { return -EIO; } 1384 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1385 unsigned int size) 1386 { return -EIO; } 1387 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1388 unsigned long mask) 1389 { return -EIO; } 1390 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1391 { return -EBUSY; } 1392 static inline int __pci_register_driver(struct pci_driver *drv, 1393 struct module *owner) 1394 { return 0; } 1395 static inline int pci_register_driver(struct pci_driver *drv) 1396 { return 0; } 1397 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1398 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1399 { return 0; } 1400 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1401 int cap) 1402 { return 0; } 1403 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1404 { return 0; } 1405 1406 /* Power management related routines */ 1407 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1408 static inline void pci_restore_state(struct pci_dev *dev) { } 1409 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1410 { return 0; } 1411 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1412 { return 0; } 1413 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1414 pm_message_t state) 1415 { return PCI_D0; } 1416 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1417 int enable) 1418 { return 0; } 1419 1420 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1421 { return -EIO; } 1422 static inline void pci_release_regions(struct pci_dev *dev) { } 1423 1424 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1425 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1426 { return 0; } 1427 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1428 1429 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1430 { return NULL; } 1431 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1432 unsigned int devfn) 1433 { return NULL; } 1434 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1435 unsigned int devfn) 1436 { return NULL; } 1437 1438 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1439 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1440 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1441 1442 #define dev_is_pci(d) (false) 1443 #define dev_is_pf(d) (false) 1444 #define dev_num_vf(d) (0) 1445 #endif /* CONFIG_PCI */ 1446 1447 /* Include architecture-dependent settings and functions */ 1448 1449 #include <asm/pci.h> 1450 1451 /* these helpers provide future and backwards compatibility 1452 * for accessing popular PCI BAR info */ 1453 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1454 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1455 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1456 #define pci_resource_len(dev,bar) \ 1457 ((pci_resource_start((dev), (bar)) == 0 && \ 1458 pci_resource_end((dev), (bar)) == \ 1459 pci_resource_start((dev), (bar))) ? 0 : \ 1460 \ 1461 (pci_resource_end((dev), (bar)) - \ 1462 pci_resource_start((dev), (bar)) + 1)) 1463 1464 /* Similar to the helpers above, these manipulate per-pci_dev 1465 * driver-specific data. They are really just a wrapper around 1466 * the generic device structure functions of these calls. 1467 */ 1468 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1469 { 1470 return dev_get_drvdata(&pdev->dev); 1471 } 1472 1473 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1474 { 1475 dev_set_drvdata(&pdev->dev, data); 1476 } 1477 1478 /* If you want to know what to call your pci_dev, ask this function. 1479 * Again, it's a wrapper around the generic device. 1480 */ 1481 static inline const char *pci_name(const struct pci_dev *pdev) 1482 { 1483 return dev_name(&pdev->dev); 1484 } 1485 1486 1487 /* Some archs don't want to expose struct resource to userland as-is 1488 * in sysfs and /proc 1489 */ 1490 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1491 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1492 const struct resource *rsrc, resource_size_t *start, 1493 resource_size_t *end) 1494 { 1495 *start = rsrc->start; 1496 *end = rsrc->end; 1497 } 1498 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1499 1500 1501 /* 1502 * The world is not perfect and supplies us with broken PCI devices. 1503 * For at least a part of these bugs we need a work-around, so both 1504 * generic (drivers/pci/quirks.c) and per-architecture code can define 1505 * fixup hooks to be called for particular buggy devices. 1506 */ 1507 1508 struct pci_fixup { 1509 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1510 u16 device; /* You can use PCI_ANY_ID here of course */ 1511 u32 class; /* You can use PCI_ANY_ID here too */ 1512 unsigned int class_shift; /* should be 0, 8, 16 */ 1513 void (*hook)(struct pci_dev *dev); 1514 }; 1515 1516 enum pci_fixup_pass { 1517 pci_fixup_early, /* Before probing BARs */ 1518 pci_fixup_header, /* After reading configuration header */ 1519 pci_fixup_final, /* Final phase of device fixups */ 1520 pci_fixup_enable, /* pci_enable_device() time */ 1521 pci_fixup_resume, /* pci_device_resume() */ 1522 pci_fixup_suspend, /* pci_device_suspend() */ 1523 pci_fixup_resume_early, /* pci_device_resume_early() */ 1524 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1525 }; 1526 1527 /* Anonymous variables would be nice... */ 1528 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1529 class_shift, hook) \ 1530 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1531 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1532 = { vendor, device, class, class_shift, hook }; 1533 1534 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1535 class_shift, hook) \ 1536 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1537 hook, vendor, device, class, class_shift, hook) 1538 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1539 class_shift, hook) \ 1540 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1541 hook, vendor, device, class, class_shift, hook) 1542 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1543 class_shift, hook) \ 1544 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1545 hook, vendor, device, class, class_shift, hook) 1546 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1547 class_shift, hook) \ 1548 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1549 hook, vendor, device, class, class_shift, hook) 1550 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1551 class_shift, hook) \ 1552 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1553 resume##hook, vendor, device, class, \ 1554 class_shift, hook) 1555 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1556 class_shift, hook) \ 1557 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1558 resume_early##hook, vendor, device, \ 1559 class, class_shift, hook) 1560 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1561 class_shift, hook) \ 1562 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1563 suspend##hook, vendor, device, class, \ 1564 class_shift, hook) 1565 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1566 class_shift, hook) \ 1567 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1568 suspend_late##hook, vendor, device, \ 1569 class, class_shift, hook) 1570 1571 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1572 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1573 hook, vendor, device, PCI_ANY_ID, 0, hook) 1574 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1575 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1576 hook, vendor, device, PCI_ANY_ID, 0, hook) 1577 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1578 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1579 hook, vendor, device, PCI_ANY_ID, 0, hook) 1580 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1581 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1582 hook, vendor, device, PCI_ANY_ID, 0, hook) 1583 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1584 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1585 resume##hook, vendor, device, \ 1586 PCI_ANY_ID, 0, hook) 1587 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1588 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1589 resume_early##hook, vendor, device, \ 1590 PCI_ANY_ID, 0, hook) 1591 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1592 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1593 suspend##hook, vendor, device, \ 1594 PCI_ANY_ID, 0, hook) 1595 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1596 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1597 suspend_late##hook, vendor, device, \ 1598 PCI_ANY_ID, 0, hook) 1599 1600 #ifdef CONFIG_PCI_QUIRKS 1601 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1602 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1603 void pci_dev_specific_enable_acs(struct pci_dev *dev); 1604 #else 1605 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1606 struct pci_dev *dev) { } 1607 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1608 u16 acs_flags) 1609 { 1610 return -ENOTTY; 1611 } 1612 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } 1613 #endif 1614 1615 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1616 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1617 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1618 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1619 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1620 const char *name); 1621 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1622 1623 extern int pci_pci_problems; 1624 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1625 #define PCIPCI_TRITON 2 1626 #define PCIPCI_NATOMA 4 1627 #define PCIPCI_VIAETBF 8 1628 #define PCIPCI_VSFX 16 1629 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1630 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1631 1632 extern unsigned long pci_cardbus_io_size; 1633 extern unsigned long pci_cardbus_mem_size; 1634 extern u8 pci_dfl_cache_line_size; 1635 extern u8 pci_cache_line_size; 1636 1637 extern unsigned long pci_hotplug_io_size; 1638 extern unsigned long pci_hotplug_mem_size; 1639 1640 /* Architecture-specific versions may override these (weak) */ 1641 void pcibios_disable_device(struct pci_dev *dev); 1642 void pcibios_set_master(struct pci_dev *dev); 1643 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1644 enum pcie_reset_state state); 1645 int pcibios_add_device(struct pci_dev *dev); 1646 void pcibios_release_device(struct pci_dev *dev); 1647 void pcibios_penalize_isa_irq(int irq, int active); 1648 1649 #ifdef CONFIG_HIBERNATE_CALLBACKS 1650 extern struct dev_pm_ops pcibios_pm_ops; 1651 #endif 1652 1653 #ifdef CONFIG_PCI_MMCONFIG 1654 void __init pci_mmcfg_early_init(void); 1655 void __init pci_mmcfg_late_init(void); 1656 #else 1657 static inline void pci_mmcfg_early_init(void) { } 1658 static inline void pci_mmcfg_late_init(void) { } 1659 #endif 1660 1661 int pci_ext_cfg_avail(void); 1662 1663 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1664 1665 #ifdef CONFIG_PCI_IOV 1666 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1667 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1668 1669 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1670 void pci_disable_sriov(struct pci_dev *dev); 1671 int pci_num_vf(struct pci_dev *dev); 1672 int pci_vfs_assigned(struct pci_dev *dev); 1673 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1674 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1675 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1676 #else 1677 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1678 { 1679 return -ENOSYS; 1680 } 1681 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1682 { 1683 return -ENOSYS; 1684 } 1685 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1686 { return -ENODEV; } 1687 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1688 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1689 static inline int pci_vfs_assigned(struct pci_dev *dev) 1690 { return 0; } 1691 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1692 { return 0; } 1693 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1694 { return 0; } 1695 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1696 { return 0; } 1697 #endif 1698 1699 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1700 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1701 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1702 #endif 1703 1704 /** 1705 * pci_pcie_cap - get the saved PCIe capability offset 1706 * @dev: PCI device 1707 * 1708 * PCIe capability offset is calculated at PCI device initialization 1709 * time and saved in the data structure. This function returns saved 1710 * PCIe capability offset. Using this instead of pci_find_capability() 1711 * reduces unnecessary search in the PCI configuration space. If you 1712 * need to calculate PCIe capability offset from raw device for some 1713 * reasons, please use pci_find_capability() instead. 1714 */ 1715 static inline int pci_pcie_cap(struct pci_dev *dev) 1716 { 1717 return dev->pcie_cap; 1718 } 1719 1720 /** 1721 * pci_is_pcie - check if the PCI device is PCI Express capable 1722 * @dev: PCI device 1723 * 1724 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1725 */ 1726 static inline bool pci_is_pcie(struct pci_dev *dev) 1727 { 1728 return pci_pcie_cap(dev); 1729 } 1730 1731 /** 1732 * pcie_caps_reg - get the PCIe Capabilities Register 1733 * @dev: PCI device 1734 */ 1735 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1736 { 1737 return dev->pcie_flags_reg; 1738 } 1739 1740 /** 1741 * pci_pcie_type - get the PCIe device/port type 1742 * @dev: PCI device 1743 */ 1744 static inline int pci_pcie_type(const struct pci_dev *dev) 1745 { 1746 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1747 } 1748 1749 void pci_request_acs(void); 1750 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1751 bool pci_acs_path_enabled(struct pci_dev *start, 1752 struct pci_dev *end, u16 acs_flags); 1753 1754 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1755 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1756 1757 /* Large Resource Data Type Tag Item Names */ 1758 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1759 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1760 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1761 1762 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1763 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1764 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1765 1766 /* Small Resource Data Type Tag Item Names */ 1767 #define PCI_VPD_STIN_END 0x78 /* End */ 1768 1769 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1770 1771 #define PCI_VPD_SRDT_TIN_MASK 0x78 1772 #define PCI_VPD_SRDT_LEN_MASK 0x07 1773 1774 #define PCI_VPD_LRDT_TAG_SIZE 3 1775 #define PCI_VPD_SRDT_TAG_SIZE 1 1776 1777 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1778 1779 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1780 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1781 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1782 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1783 1784 /** 1785 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1786 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1787 * 1788 * Returns the extracted Large Resource Data Type length. 1789 */ 1790 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1791 { 1792 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1793 } 1794 1795 /** 1796 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1797 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1798 * 1799 * Returns the extracted Small Resource Data Type length. 1800 */ 1801 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1802 { 1803 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1804 } 1805 1806 /** 1807 * pci_vpd_info_field_size - Extracts the information field length 1808 * @lrdt: Pointer to the beginning of an information field header 1809 * 1810 * Returns the extracted information field length. 1811 */ 1812 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1813 { 1814 return info_field[2]; 1815 } 1816 1817 /** 1818 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1819 * @buf: Pointer to buffered vpd data 1820 * @off: The offset into the buffer at which to begin the search 1821 * @len: The length of the vpd buffer 1822 * @rdt: The Resource Data Type to search for 1823 * 1824 * Returns the index where the Resource Data Type was found or 1825 * -ENOENT otherwise. 1826 */ 1827 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1828 1829 /** 1830 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1831 * @buf: Pointer to buffered vpd data 1832 * @off: The offset into the buffer at which to begin the search 1833 * @len: The length of the buffer area, relative to off, in which to search 1834 * @kw: The keyword to search for 1835 * 1836 * Returns the index where the information field keyword was found or 1837 * -ENOENT otherwise. 1838 */ 1839 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1840 unsigned int len, const char *kw); 1841 1842 /* PCI <-> OF binding helpers */ 1843 #ifdef CONFIG_OF 1844 struct device_node; 1845 void pci_set_of_node(struct pci_dev *dev); 1846 void pci_release_of_node(struct pci_dev *dev); 1847 void pci_set_bus_of_node(struct pci_bus *bus); 1848 void pci_release_bus_of_node(struct pci_bus *bus); 1849 1850 /* Arch may override this (weak) */ 1851 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1852 1853 static inline struct device_node * 1854 pci_device_to_OF_node(const struct pci_dev *pdev) 1855 { 1856 return pdev ? pdev->dev.of_node : NULL; 1857 } 1858 1859 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1860 { 1861 return bus ? bus->dev.of_node : NULL; 1862 } 1863 1864 #else /* CONFIG_OF */ 1865 static inline void pci_set_of_node(struct pci_dev *dev) { } 1866 static inline void pci_release_of_node(struct pci_dev *dev) { } 1867 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1868 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1869 static inline struct device_node * 1870 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 1871 #endif /* CONFIG_OF */ 1872 1873 #ifdef CONFIG_EEH 1874 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1875 { 1876 return pdev->dev.archdata.edev; 1877 } 1878 #endif 1879 1880 int pci_for_each_dma_alias(struct pci_dev *pdev, 1881 int (*fn)(struct pci_dev *pdev, 1882 u16 alias, void *data), void *data); 1883 1884 /* helper functions for operation of device flag */ 1885 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 1886 { 1887 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 1888 } 1889 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 1890 { 1891 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 1892 } 1893 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 1894 { 1895 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 1896 } 1897 1898 /** 1899 * pci_ari_enabled - query ARI forwarding status 1900 * @bus: the PCI bus 1901 * 1902 * Returns true if ARI forwarding is enabled. 1903 */ 1904 static inline bool pci_ari_enabled(struct pci_bus *bus) 1905 { 1906 return bus->self && bus->self->ari_enabled; 1907 } 1908 #endif /* LINUX_PCI_H */ 1909