1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 46 PCI_STATUS_SIG_SYSTEM_ERROR | \ 47 PCI_STATUS_REC_MASTER_ABORT | \ 48 PCI_STATUS_REC_TARGET_ABORT | \ 49 PCI_STATUS_SIG_TARGET_ABORT | \ 50 PCI_STATUS_PARITY) 51 52 /* 53 * The PCI interface treats multi-function devices as independent 54 * devices. The slot/function address of each device is encoded 55 * in a single byte as follows: 56 * 57 * 7:3 = slot 58 * 2:0 = function 59 * 60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 61 * In the interest of not exposing interfaces to user-space unnecessarily, 62 * the following kernel-only defines are being added here. 63 */ 64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 67 68 /* pci_slot represents a physical slot */ 69 struct pci_slot { 70 struct pci_bus *bus; /* Bus this slot is on */ 71 struct list_head list; /* Node in list of slots */ 72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 74 struct kobject kobj; 75 }; 76 77 static inline const char *pci_slot_name(const struct pci_slot *slot) 78 { 79 return kobject_name(&slot->kobj); 80 } 81 82 /* File state for mmap()s on /proc/bus/pci/X/Y */ 83 enum pci_mmap_state { 84 pci_mmap_io, 85 pci_mmap_mem 86 }; 87 88 /* For PCI devices, the region numbers are assigned this way: */ 89 enum { 90 /* #0-5: standard PCI resources */ 91 PCI_STD_RESOURCES, 92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 93 94 /* #6: expansion ROM resource */ 95 PCI_ROM_RESOURCE, 96 97 /* Device-specific resources */ 98 #ifdef CONFIG_PCI_IOV 99 PCI_IOV_RESOURCES, 100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 101 #endif 102 103 /* PCI-to-PCI (P2P) bridge windows */ 104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 107 108 /* CardBus bridge windows */ 109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 113 114 /* Total number of bridge resources for P2P and CardBus */ 115 #define PCI_BRIDGE_RESOURCE_NUM 4 116 117 /* Resources assigned to buses behind the bridge */ 118 PCI_BRIDGE_RESOURCES, 119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 120 PCI_BRIDGE_RESOURCE_NUM - 1, 121 122 /* Total resources associated with a PCI device */ 123 PCI_NUM_RESOURCES, 124 125 /* Preserve this for compatibility */ 126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 127 }; 128 129 /** 130 * enum pci_interrupt_pin - PCI INTx interrupt values 131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 132 * @PCI_INTERRUPT_INTA: PCI INTA pin 133 * @PCI_INTERRUPT_INTB: PCI INTB pin 134 * @PCI_INTERRUPT_INTC: PCI INTC pin 135 * @PCI_INTERRUPT_INTD: PCI INTD pin 136 * 137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 138 * PCI_INTERRUPT_PIN register. 139 */ 140 enum pci_interrupt_pin { 141 PCI_INTERRUPT_UNKNOWN, 142 PCI_INTERRUPT_INTA, 143 PCI_INTERRUPT_INTB, 144 PCI_INTERRUPT_INTC, 145 PCI_INTERRUPT_INTD, 146 }; 147 148 /* The number of legacy PCI INTx interrupts */ 149 #define PCI_NUM_INTX 4 150 151 /* 152 * pci_power_t values must match the bits in the Capabilities PME_Support 153 * and Control/Status PowerState fields in the Power Management capability. 154 */ 155 typedef int __bitwise pci_power_t; 156 157 #define PCI_D0 ((pci_power_t __force) 0) 158 #define PCI_D1 ((pci_power_t __force) 1) 159 #define PCI_D2 ((pci_power_t __force) 2) 160 #define PCI_D3hot ((pci_power_t __force) 3) 161 #define PCI_D3cold ((pci_power_t __force) 4) 162 #define PCI_UNKNOWN ((pci_power_t __force) 5) 163 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 164 165 /* Remember to update this when the list above changes! */ 166 extern const char *pci_power_names[]; 167 168 static inline const char *pci_power_name(pci_power_t state) 169 { 170 return pci_power_names[1 + (__force int) state]; 171 } 172 173 /** 174 * typedef pci_channel_state_t 175 * 176 * The pci_channel state describes connectivity between the CPU and 177 * the PCI device. If some PCI bus between here and the PCI device 178 * has crashed or locked up, this info is reflected here. 179 */ 180 typedef unsigned int __bitwise pci_channel_state_t; 181 182 enum { 183 /* I/O channel is in normal state */ 184 pci_channel_io_normal = (__force pci_channel_state_t) 1, 185 186 /* I/O to channel is blocked */ 187 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 188 189 /* PCI card is dead */ 190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 191 }; 192 193 typedef unsigned int __bitwise pcie_reset_state_t; 194 195 enum pcie_reset_state { 196 /* Reset is NOT asserted (Use to deassert reset) */ 197 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 198 199 /* Use #PERST to reset PCIe device */ 200 pcie_warm_reset = (__force pcie_reset_state_t) 2, 201 202 /* Use PCIe Hot Reset to reset device */ 203 pcie_hot_reset = (__force pcie_reset_state_t) 3 204 }; 205 206 typedef unsigned short __bitwise pci_dev_flags_t; 207 enum pci_dev_flags { 208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 210 /* Device configuration is irrevocably lost if disabled into D3 */ 211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 212 /* Provide indication device is assigned by a Virtual Machine Manager */ 213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 214 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 218 /* Do not use bus resets for device */ 219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 220 /* Do not use PM reset even if device advertises NoSoftRst- */ 221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 222 /* Get VPD from function 0 VPD */ 223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 224 /* A non-root bridge where translation occurs, stop alias search here */ 225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 226 /* Do not use FLR even if device advertises PCI_AF_CAP */ 227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 228 /* Don't use Relaxed Ordering for TLPs directed at this device */ 229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 230 }; 231 232 enum pci_irq_reroute_variant { 233 INTEL_IRQ_REROUTE_VARIANT = 1, 234 MAX_IRQ_REROUTE_VARIANTS = 3 235 }; 236 237 typedef unsigned short __bitwise pci_bus_flags_t; 238 enum pci_bus_flags { 239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 243 }; 244 245 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 246 enum pcie_link_width { 247 PCIE_LNK_WIDTH_RESRV = 0x00, 248 PCIE_LNK_X1 = 0x01, 249 PCIE_LNK_X2 = 0x02, 250 PCIE_LNK_X4 = 0x04, 251 PCIE_LNK_X8 = 0x08, 252 PCIE_LNK_X12 = 0x0c, 253 PCIE_LNK_X16 = 0x10, 254 PCIE_LNK_X32 = 0x20, 255 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 256 }; 257 258 /* See matching string table in pci_speed_string() */ 259 enum pci_bus_speed { 260 PCI_SPEED_33MHz = 0x00, 261 PCI_SPEED_66MHz = 0x01, 262 PCI_SPEED_66MHz_PCIX = 0x02, 263 PCI_SPEED_100MHz_PCIX = 0x03, 264 PCI_SPEED_133MHz_PCIX = 0x04, 265 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 266 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 267 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 268 PCI_SPEED_66MHz_PCIX_266 = 0x09, 269 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 270 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 271 AGP_UNKNOWN = 0x0c, 272 AGP_1X = 0x0d, 273 AGP_2X = 0x0e, 274 AGP_4X = 0x0f, 275 AGP_8X = 0x10, 276 PCI_SPEED_66MHz_PCIX_533 = 0x11, 277 PCI_SPEED_100MHz_PCIX_533 = 0x12, 278 PCI_SPEED_133MHz_PCIX_533 = 0x13, 279 PCIE_SPEED_2_5GT = 0x14, 280 PCIE_SPEED_5_0GT = 0x15, 281 PCIE_SPEED_8_0GT = 0x16, 282 PCIE_SPEED_16_0GT = 0x17, 283 PCIE_SPEED_32_0GT = 0x18, 284 PCIE_SPEED_64_0GT = 0x19, 285 PCI_SPEED_UNKNOWN = 0xff, 286 }; 287 288 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 289 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 290 291 struct pci_cap_saved_data { 292 u16 cap_nr; 293 bool cap_extended; 294 unsigned int size; 295 u32 data[]; 296 }; 297 298 struct pci_cap_saved_state { 299 struct hlist_node next; 300 struct pci_cap_saved_data cap; 301 }; 302 303 struct irq_affinity; 304 struct pcie_link_state; 305 struct pci_vpd; 306 struct pci_sriov; 307 struct pci_p2pdma; 308 struct rcec_ea; 309 310 /* The pci_dev structure describes PCI devices */ 311 struct pci_dev { 312 struct list_head bus_list; /* Node in per-bus list */ 313 struct pci_bus *bus; /* Bus this device is on */ 314 struct pci_bus *subordinate; /* Bus this device bridges to */ 315 316 void *sysdata; /* Hook for sys-specific extension */ 317 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 318 struct pci_slot *slot; /* Physical slot this device is in */ 319 320 unsigned int devfn; /* Encoded device & function index */ 321 unsigned short vendor; 322 unsigned short device; 323 unsigned short subsystem_vendor; 324 unsigned short subsystem_device; 325 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 326 u8 revision; /* PCI revision, low byte of class word */ 327 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 328 #ifdef CONFIG_PCIEAER 329 u16 aer_cap; /* AER capability offset */ 330 struct aer_stats *aer_stats; /* AER stats for this device */ 331 #endif 332 #ifdef CONFIG_PCIEPORTBUS 333 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 334 struct pci_dev *rcec; /* Associated RCEC device */ 335 #endif 336 u8 pcie_cap; /* PCIe capability offset */ 337 u8 msi_cap; /* MSI capability offset */ 338 u8 msix_cap; /* MSI-X capability offset */ 339 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 340 u8 rom_base_reg; /* Config register controlling ROM */ 341 u8 pin; /* Interrupt pin this device uses */ 342 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 343 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 344 345 struct pci_driver *driver; /* Driver bound to this device */ 346 u64 dma_mask; /* Mask of the bits of bus address this 347 device implements. Normally this is 348 0xffffffff. You only need to change 349 this if your device has broken DMA 350 or supports 64-bit transfers. */ 351 352 struct device_dma_parameters dma_parms; 353 354 pci_power_t current_state; /* Current operating state. In ACPI, 355 this is D0-D3, D0 being fully 356 functional, and D3 being off. */ 357 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 358 u8 pm_cap; /* PM capability offset */ 359 unsigned int pme_support:5; /* Bitmask of states from which PME# 360 can be generated */ 361 unsigned int pme_poll:1; /* Poll device's PME status bit */ 362 unsigned int d1_support:1; /* Low power state D1 is supported */ 363 unsigned int d2_support:1; /* Low power state D2 is supported */ 364 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 365 unsigned int no_d3cold:1; /* D3cold is forbidden */ 366 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 367 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 368 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 369 decoding during BAR sizing */ 370 unsigned int wakeup_prepared:1; 371 unsigned int runtime_d3cold:1; /* Whether go through runtime 372 D3cold, not set for devices 373 powered on/off by the 374 corresponding bridge */ 375 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 376 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 377 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 378 controlled exclusively by 379 user sysfs */ 380 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 381 bit manually */ 382 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 383 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 384 385 #ifdef CONFIG_PCIEASPM 386 struct pcie_link_state *link_state; /* ASPM link state */ 387 unsigned int ltr_path:1; /* Latency Tolerance Reporting 388 supported from root to here */ 389 u16 l1ss; /* L1SS Capability pointer */ 390 #endif 391 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 392 393 pci_channel_state_t error_state; /* Current connectivity state */ 394 struct device dev; /* Generic device interface */ 395 396 int cfg_size; /* Size of config space */ 397 398 /* 399 * Instead of touching interrupt line and base address registers 400 * directly, use the values stored here. They might be different! 401 */ 402 unsigned int irq; 403 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 404 405 bool match_driver; /* Skip attaching driver */ 406 407 unsigned int transparent:1; /* Subtractive decode bridge */ 408 unsigned int io_window:1; /* Bridge has I/O window */ 409 unsigned int pref_window:1; /* Bridge has pref mem window */ 410 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 411 unsigned int multifunction:1; /* Multi-function device */ 412 413 unsigned int is_busmaster:1; /* Is busmaster */ 414 unsigned int no_msi:1; /* May not use MSI */ 415 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 416 unsigned int block_cfg_access:1; /* Config space access blocked */ 417 unsigned int broken_parity_status:1; /* Generates false positive parity */ 418 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 419 unsigned int msi_enabled:1; 420 unsigned int msix_enabled:1; 421 unsigned int ari_enabled:1; /* ARI forwarding */ 422 unsigned int ats_enabled:1; /* Address Translation Svc */ 423 unsigned int pasid_enabled:1; /* Process Address Space ID */ 424 unsigned int pri_enabled:1; /* Page Request Interface */ 425 unsigned int is_managed:1; 426 unsigned int needs_freset:1; /* Requires fundamental reset */ 427 unsigned int state_saved:1; 428 unsigned int is_physfn:1; 429 unsigned int is_virtfn:1; 430 unsigned int reset_fn:1; 431 unsigned int is_hotplug_bridge:1; 432 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 433 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 434 /* 435 * Devices marked being untrusted are the ones that can potentially 436 * execute DMA attacks and similar. They are typically connected 437 * through external ports such as Thunderbolt but not limited to 438 * that. When an IOMMU is enabled they should be getting full 439 * mappings to make sure they cannot access arbitrary memory. 440 */ 441 unsigned int untrusted:1; 442 /* 443 * Info from the platform, e.g., ACPI or device tree, may mark a 444 * device as "external-facing". An external-facing device is 445 * itself internal but devices downstream from it are external. 446 */ 447 unsigned int external_facing:1; 448 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 449 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 450 unsigned int irq_managed:1; 451 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 452 unsigned int is_probed:1; /* Device probing in progress */ 453 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 454 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 455 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 456 pci_dev_flags_t dev_flags; 457 atomic_t enable_cnt; /* pci_enable_device has been called */ 458 459 u32 saved_config_space[16]; /* Config space saved at suspend time */ 460 struct hlist_head saved_cap_space; 461 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 462 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 463 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 464 465 #ifdef CONFIG_HOTPLUG_PCI_PCIE 466 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 467 #endif 468 #ifdef CONFIG_PCIE_PTM 469 unsigned int ptm_root:1; 470 unsigned int ptm_enabled:1; 471 u8 ptm_granularity; 472 #endif 473 #ifdef CONFIG_PCI_MSI 474 const struct attribute_group **msi_irq_groups; 475 #endif 476 struct pci_vpd *vpd; 477 #ifdef CONFIG_PCIE_DPC 478 u16 dpc_cap; 479 unsigned int dpc_rp_extensions:1; 480 u8 dpc_rp_log_size; 481 #endif 482 #ifdef CONFIG_PCI_ATS 483 union { 484 struct pci_sriov *sriov; /* PF: SR-IOV info */ 485 struct pci_dev *physfn; /* VF: related PF */ 486 }; 487 u16 ats_cap; /* ATS Capability offset */ 488 u8 ats_stu; /* ATS Smallest Translation Unit */ 489 #endif 490 #ifdef CONFIG_PCI_PRI 491 u16 pri_cap; /* PRI Capability offset */ 492 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 493 unsigned int pasid_required:1; /* PRG Response PASID Required */ 494 #endif 495 #ifdef CONFIG_PCI_PASID 496 u16 pasid_cap; /* PASID Capability offset */ 497 u16 pasid_features; 498 #endif 499 #ifdef CONFIG_PCI_P2PDMA 500 struct pci_p2pdma *p2pdma; 501 #endif 502 u16 acs_cap; /* ACS Capability offset */ 503 phys_addr_t rom; /* Physical address if not from BAR */ 504 size_t romlen; /* Length if not from BAR */ 505 char *driver_override; /* Driver name to force a match */ 506 507 unsigned long priv_flags; /* Private flags for the PCI driver */ 508 }; 509 510 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 511 { 512 #ifdef CONFIG_PCI_IOV 513 if (dev->is_virtfn) 514 dev = dev->physfn; 515 #endif 516 return dev; 517 } 518 519 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 520 521 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 522 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 523 524 static inline int pci_channel_offline(struct pci_dev *pdev) 525 { 526 return (pdev->error_state != pci_channel_io_normal); 527 } 528 529 struct pci_host_bridge { 530 struct device dev; 531 struct pci_bus *bus; /* Root bus */ 532 struct pci_ops *ops; 533 struct pci_ops *child_ops; 534 void *sysdata; 535 int busnr; 536 struct list_head windows; /* resource_entry */ 537 struct list_head dma_ranges; /* dma ranges resource list */ 538 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 539 int (*map_irq)(const struct pci_dev *, u8, u8); 540 void (*release_fn)(struct pci_host_bridge *); 541 void *release_data; 542 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 543 unsigned int no_ext_tags:1; /* No Extended Tags */ 544 unsigned int native_aer:1; /* OS may use PCIe AER */ 545 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 546 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 547 unsigned int native_pme:1; /* OS may use PCIe PME */ 548 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 549 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 550 unsigned int preserve_config:1; /* Preserve FW resource setup */ 551 unsigned int size_windows:1; /* Enable root bus sizing */ 552 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 553 554 /* Resource alignment requirements */ 555 resource_size_t (*align_resource)(struct pci_dev *dev, 556 const struct resource *res, 557 resource_size_t start, 558 resource_size_t size, 559 resource_size_t align); 560 unsigned long private[] ____cacheline_aligned; 561 }; 562 563 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 564 565 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 566 { 567 return (void *)bridge->private; 568 } 569 570 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 571 { 572 return container_of(priv, struct pci_host_bridge, private); 573 } 574 575 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 576 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 577 size_t priv); 578 void pci_free_host_bridge(struct pci_host_bridge *bridge); 579 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 580 581 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 582 void (*release_fn)(struct pci_host_bridge *), 583 void *release_data); 584 585 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 586 587 /* 588 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 589 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 590 * buses below host bridges or subtractive decode bridges) go in the list. 591 * Use pci_bus_for_each_resource() to iterate through all the resources. 592 */ 593 594 /* 595 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 596 * and there's no way to program the bridge with the details of the window. 597 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 598 * decode bit set, because they are explicit and can be programmed with _SRS. 599 */ 600 #define PCI_SUBTRACTIVE_DECODE 0x1 601 602 struct pci_bus_resource { 603 struct list_head list; 604 struct resource *res; 605 unsigned int flags; 606 }; 607 608 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 609 610 struct pci_bus { 611 struct list_head node; /* Node in list of buses */ 612 struct pci_bus *parent; /* Parent bus this bridge is on */ 613 struct list_head children; /* List of child buses */ 614 struct list_head devices; /* List of devices on this bus */ 615 struct pci_dev *self; /* Bridge device as seen by parent */ 616 struct list_head slots; /* List of slots on this bus; 617 protected by pci_slot_mutex */ 618 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 619 struct list_head resources; /* Address space routed to this bus */ 620 struct resource busn_res; /* Bus numbers routed to this bus */ 621 622 struct pci_ops *ops; /* Configuration access functions */ 623 void *sysdata; /* Hook for sys-specific extension */ 624 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 625 626 unsigned char number; /* Bus number */ 627 unsigned char primary; /* Number of primary bridge */ 628 unsigned char max_bus_speed; /* enum pci_bus_speed */ 629 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 630 #ifdef CONFIG_PCI_DOMAINS_GENERIC 631 int domain_nr; 632 #endif 633 634 char name[48]; 635 636 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 637 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 638 struct device *bridge; 639 struct device dev; 640 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 641 struct bin_attribute *legacy_mem; /* Legacy mem */ 642 unsigned int is_added:1; 643 }; 644 645 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 646 647 static inline u16 pci_dev_id(struct pci_dev *dev) 648 { 649 return PCI_DEVID(dev->bus->number, dev->devfn); 650 } 651 652 /* 653 * Returns true if the PCI bus is root (behind host-PCI bridge), 654 * false otherwise 655 * 656 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 657 * This is incorrect because "virtual" buses added for SR-IOV (via 658 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 659 */ 660 static inline bool pci_is_root_bus(struct pci_bus *pbus) 661 { 662 return !(pbus->parent); 663 } 664 665 /** 666 * pci_is_bridge - check if the PCI device is a bridge 667 * @dev: PCI device 668 * 669 * Return true if the PCI device is bridge whether it has subordinate 670 * or not. 671 */ 672 static inline bool pci_is_bridge(struct pci_dev *dev) 673 { 674 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 675 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 676 } 677 678 #define for_each_pci_bridge(dev, bus) \ 679 list_for_each_entry(dev, &bus->devices, bus_list) \ 680 if (!pci_is_bridge(dev)) {} else 681 682 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 683 { 684 dev = pci_physfn(dev); 685 if (pci_is_root_bus(dev->bus)) 686 return NULL; 687 688 return dev->bus->self; 689 } 690 691 #ifdef CONFIG_PCI_MSI 692 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 693 { 694 return pci_dev->msi_enabled || pci_dev->msix_enabled; 695 } 696 #else 697 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 698 #endif 699 700 /* Error values that may be returned by PCI functions */ 701 #define PCIBIOS_SUCCESSFUL 0x00 702 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 703 #define PCIBIOS_BAD_VENDOR_ID 0x83 704 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 705 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 706 #define PCIBIOS_SET_FAILED 0x88 707 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 708 709 /* Translate above to generic errno for passing back through non-PCI code */ 710 static inline int pcibios_err_to_errno(int err) 711 { 712 if (err <= PCIBIOS_SUCCESSFUL) 713 return err; /* Assume already errno */ 714 715 switch (err) { 716 case PCIBIOS_FUNC_NOT_SUPPORTED: 717 return -ENOENT; 718 case PCIBIOS_BAD_VENDOR_ID: 719 return -ENOTTY; 720 case PCIBIOS_DEVICE_NOT_FOUND: 721 return -ENODEV; 722 case PCIBIOS_BAD_REGISTER_NUMBER: 723 return -EFAULT; 724 case PCIBIOS_SET_FAILED: 725 return -EIO; 726 case PCIBIOS_BUFFER_TOO_SMALL: 727 return -ENOSPC; 728 } 729 730 return -ERANGE; 731 } 732 733 /* Low-level architecture-dependent routines */ 734 735 struct pci_ops { 736 int (*add_bus)(struct pci_bus *bus); 737 void (*remove_bus)(struct pci_bus *bus); 738 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 739 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 740 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 741 }; 742 743 /* 744 * ACPI needs to be able to access PCI config space before we've done a 745 * PCI bus scan and created pci_bus structures. 746 */ 747 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 748 int reg, int len, u32 *val); 749 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 750 int reg, int len, u32 val); 751 752 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 753 typedef u64 pci_bus_addr_t; 754 #else 755 typedef u32 pci_bus_addr_t; 756 #endif 757 758 struct pci_bus_region { 759 pci_bus_addr_t start; 760 pci_bus_addr_t end; 761 }; 762 763 struct pci_dynids { 764 spinlock_t lock; /* Protects list, index */ 765 struct list_head list; /* For IDs added at runtime */ 766 }; 767 768 769 /* 770 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 771 * a set of callbacks in struct pci_error_handlers, that device driver 772 * will be notified of PCI bus errors, and will be driven to recovery 773 * when an error occurs. 774 */ 775 776 typedef unsigned int __bitwise pci_ers_result_t; 777 778 enum pci_ers_result { 779 /* No result/none/not supported in device driver */ 780 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 781 782 /* Device driver can recover without slot reset */ 783 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 784 785 /* Device driver wants slot to be reset */ 786 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 787 788 /* Device has completely failed, is unrecoverable */ 789 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 790 791 /* Device driver is fully recovered and operational */ 792 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 793 794 /* No AER capabilities registered for the driver */ 795 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 796 }; 797 798 /* PCI bus error event callbacks */ 799 struct pci_error_handlers { 800 /* PCI bus error detected on this device */ 801 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 802 pci_channel_state_t error); 803 804 /* MMIO has been re-enabled, but not DMA */ 805 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 806 807 /* PCI slot has been reset */ 808 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 809 810 /* PCI function reset prepare or completed */ 811 void (*reset_prepare)(struct pci_dev *dev); 812 void (*reset_done)(struct pci_dev *dev); 813 814 /* Device driver may resume normal operations */ 815 void (*resume)(struct pci_dev *dev); 816 }; 817 818 819 struct module; 820 821 /** 822 * struct pci_driver - PCI driver structure 823 * @node: List of driver structures. 824 * @name: Driver name. 825 * @id_table: Pointer to table of device IDs the driver is 826 * interested in. Most drivers should export this 827 * table using MODULE_DEVICE_TABLE(pci,...). 828 * @probe: This probing function gets called (during execution 829 * of pci_register_driver() for already existing 830 * devices or later if a new device gets inserted) for 831 * all PCI devices which match the ID table and are not 832 * "owned" by the other drivers yet. This function gets 833 * passed a "struct pci_dev \*" for each device whose 834 * entry in the ID table matches the device. The probe 835 * function returns zero when the driver chooses to 836 * take "ownership" of the device or an error code 837 * (negative number) otherwise. 838 * The probe function always gets called from process 839 * context, so it can sleep. 840 * @remove: The remove() function gets called whenever a device 841 * being handled by this driver is removed (either during 842 * deregistration of the driver or when it's manually 843 * pulled out of a hot-pluggable slot). 844 * The remove function always gets called from process 845 * context, so it can sleep. 846 * @suspend: Put device into low power state. 847 * @resume: Wake device from low power state. 848 * (Please see Documentation/power/pci.rst for descriptions 849 * of PCI Power Management and the related functions.) 850 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 851 * Intended to stop any idling DMA operations. 852 * Useful for enabling wake-on-lan (NIC) or changing 853 * the power state of a device before reboot. 854 * e.g. drivers/net/e100.c. 855 * @sriov_configure: Optional driver callback to allow configuration of 856 * number of VFs to enable via sysfs "sriov_numvfs" file. 857 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 858 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 859 * This will change MSI-X Table Size in the VF Message Control 860 * registers. 861 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 862 * MSI-X vectors available for distribution to the VFs. 863 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 864 * @groups: Sysfs attribute groups. 865 * @driver: Driver model structure. 866 * @dynids: List of dynamically added device IDs. 867 */ 868 struct pci_driver { 869 struct list_head node; 870 const char *name; 871 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 872 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 873 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 874 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 875 int (*resume)(struct pci_dev *dev); /* Device woken up */ 876 void (*shutdown)(struct pci_dev *dev); 877 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 878 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 879 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 880 const struct pci_error_handlers *err_handler; 881 const struct attribute_group **groups; 882 struct device_driver driver; 883 struct pci_dynids dynids; 884 }; 885 886 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 887 888 /** 889 * PCI_DEVICE - macro used to describe a specific PCI device 890 * @vend: the 16 bit PCI Vendor ID 891 * @dev: the 16 bit PCI Device ID 892 * 893 * This macro is used to create a struct pci_device_id that matches a 894 * specific device. The subvendor and subdevice fields will be set to 895 * PCI_ANY_ID. 896 */ 897 #define PCI_DEVICE(vend,dev) \ 898 .vendor = (vend), .device = (dev), \ 899 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 900 901 /** 902 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 903 * @vend: the 16 bit PCI Vendor ID 904 * @dev: the 16 bit PCI Device ID 905 * @subvend: the 16 bit PCI Subvendor ID 906 * @subdev: the 16 bit PCI Subdevice ID 907 * 908 * This macro is used to create a struct pci_device_id that matches a 909 * specific device with subsystem information. 910 */ 911 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 912 .vendor = (vend), .device = (dev), \ 913 .subvendor = (subvend), .subdevice = (subdev) 914 915 /** 916 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 917 * @dev_class: the class, subclass, prog-if triple for this device 918 * @dev_class_mask: the class mask for this device 919 * 920 * This macro is used to create a struct pci_device_id that matches a 921 * specific PCI class. The vendor, device, subvendor, and subdevice 922 * fields will be set to PCI_ANY_ID. 923 */ 924 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 925 .class = (dev_class), .class_mask = (dev_class_mask), \ 926 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 927 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 928 929 /** 930 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 931 * @vend: the vendor name 932 * @dev: the 16 bit PCI Device ID 933 * 934 * This macro is used to create a struct pci_device_id that matches a 935 * specific PCI device. The subvendor, and subdevice fields will be set 936 * to PCI_ANY_ID. The macro allows the next field to follow as the device 937 * private data. 938 */ 939 #define PCI_VDEVICE(vend, dev) \ 940 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 941 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 942 943 /** 944 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 945 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 946 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 947 * @data: the driver data to be filled 948 * 949 * This macro is used to create a struct pci_device_id that matches a 950 * specific PCI device. The subvendor, and subdevice fields will be set 951 * to PCI_ANY_ID. 952 */ 953 #define PCI_DEVICE_DATA(vend, dev, data) \ 954 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 955 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 956 .driver_data = (kernel_ulong_t)(data) 957 958 enum { 959 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 960 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 961 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 962 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 963 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 964 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 965 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 966 }; 967 968 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 969 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 970 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 971 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 972 973 /* These external functions are only available when PCI support is enabled */ 974 #ifdef CONFIG_PCI 975 976 extern unsigned int pci_flags; 977 978 static inline void pci_set_flags(int flags) { pci_flags = flags; } 979 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 980 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 981 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 982 983 void pcie_bus_configure_settings(struct pci_bus *bus); 984 985 enum pcie_bus_config_types { 986 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 987 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 988 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 989 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 990 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 991 }; 992 993 extern enum pcie_bus_config_types pcie_bus_config; 994 995 extern struct bus_type pci_bus_type; 996 997 /* Do NOT directly access these two variables, unless you are arch-specific PCI 998 * code, or PCI core code. */ 999 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1000 /* Some device drivers need know if PCI is initiated */ 1001 int no_pci_devices(void); 1002 1003 void pcibios_resource_survey_bus(struct pci_bus *bus); 1004 void pcibios_bus_add_device(struct pci_dev *pdev); 1005 void pcibios_add_bus(struct pci_bus *bus); 1006 void pcibios_remove_bus(struct pci_bus *bus); 1007 void pcibios_fixup_bus(struct pci_bus *); 1008 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1009 /* Architecture-specific versions may override this (weak) */ 1010 char *pcibios_setup(char *str); 1011 1012 /* Used only when drivers/pci/setup.c is used */ 1013 resource_size_t pcibios_align_resource(void *, const struct resource *, 1014 resource_size_t, 1015 resource_size_t); 1016 1017 /* Weak but can be overridden by arch */ 1018 void pci_fixup_cardbus(struct pci_bus *); 1019 1020 /* Generic PCI functions used internally */ 1021 1022 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1023 struct resource *res); 1024 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1025 struct pci_bus_region *region); 1026 void pcibios_scan_specific_bus(int busn); 1027 struct pci_bus *pci_find_bus(int domain, int busnr); 1028 void pci_bus_add_devices(const struct pci_bus *bus); 1029 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1030 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1031 struct pci_ops *ops, void *sysdata, 1032 struct list_head *resources); 1033 int pci_host_probe(struct pci_host_bridge *bridge); 1034 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1035 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1036 void pci_bus_release_busn_res(struct pci_bus *b); 1037 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1038 struct pci_ops *ops, void *sysdata, 1039 struct list_head *resources); 1040 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1041 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1042 int busnr); 1043 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1044 const char *name, 1045 struct hotplug_slot *hotplug); 1046 void pci_destroy_slot(struct pci_slot *slot); 1047 #ifdef CONFIG_SYSFS 1048 void pci_dev_assign_slot(struct pci_dev *dev); 1049 #else 1050 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1051 #endif 1052 int pci_scan_slot(struct pci_bus *bus, int devfn); 1053 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1054 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1055 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1056 void pci_bus_add_device(struct pci_dev *dev); 1057 void pci_read_bridge_bases(struct pci_bus *child); 1058 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1059 struct resource *res); 1060 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1061 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1062 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1063 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1064 void pci_dev_put(struct pci_dev *dev); 1065 void pci_remove_bus(struct pci_bus *b); 1066 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1067 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1068 void pci_stop_root_bus(struct pci_bus *bus); 1069 void pci_remove_root_bus(struct pci_bus *bus); 1070 void pci_setup_cardbus(struct pci_bus *bus); 1071 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1072 void pci_sort_breadthfirst(void); 1073 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1074 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1075 1076 /* Generic PCI functions exported to card drivers */ 1077 1078 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1079 u8 pci_find_capability(struct pci_dev *dev, int cap); 1080 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1081 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1082 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1083 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1084 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1085 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1086 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1087 1088 u64 pci_get_dsn(struct pci_dev *dev); 1089 1090 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1091 struct pci_dev *from); 1092 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1093 unsigned int ss_vendor, unsigned int ss_device, 1094 struct pci_dev *from); 1095 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1096 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1097 unsigned int devfn); 1098 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1099 int pci_dev_present(const struct pci_device_id *ids); 1100 1101 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1102 int where, u8 *val); 1103 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1104 int where, u16 *val); 1105 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1106 int where, u32 *val); 1107 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1108 int where, u8 val); 1109 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1110 int where, u16 val); 1111 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1112 int where, u32 val); 1113 1114 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1115 int where, int size, u32 *val); 1116 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1117 int where, int size, u32 val); 1118 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1119 int where, int size, u32 *val); 1120 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1121 int where, int size, u32 val); 1122 1123 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1124 1125 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1126 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1127 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1128 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1129 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1130 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1131 1132 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1133 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1134 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1135 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1136 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1137 u16 clear, u16 set); 1138 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1139 u32 clear, u32 set); 1140 1141 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1142 u16 set) 1143 { 1144 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1145 } 1146 1147 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1148 u32 set) 1149 { 1150 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1151 } 1152 1153 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1154 u16 clear) 1155 { 1156 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1157 } 1158 1159 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1160 u32 clear) 1161 { 1162 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1163 } 1164 1165 /* User-space driven config access */ 1166 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1167 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1168 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1169 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1170 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1171 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1172 1173 int __must_check pci_enable_device(struct pci_dev *dev); 1174 int __must_check pci_enable_device_io(struct pci_dev *dev); 1175 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1176 int __must_check pci_reenable_device(struct pci_dev *); 1177 int __must_check pcim_enable_device(struct pci_dev *pdev); 1178 void pcim_pin_device(struct pci_dev *pdev); 1179 1180 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1181 { 1182 /* 1183 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1184 * writable and no quirk has marked the feature broken. 1185 */ 1186 return !pdev->broken_intx_masking; 1187 } 1188 1189 static inline int pci_is_enabled(struct pci_dev *pdev) 1190 { 1191 return (atomic_read(&pdev->enable_cnt) > 0); 1192 } 1193 1194 static inline int pci_is_managed(struct pci_dev *pdev) 1195 { 1196 return pdev->is_managed; 1197 } 1198 1199 void pci_disable_device(struct pci_dev *dev); 1200 1201 extern unsigned int pcibios_max_latency; 1202 void pci_set_master(struct pci_dev *dev); 1203 void pci_clear_master(struct pci_dev *dev); 1204 1205 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1206 int pci_set_cacheline_size(struct pci_dev *dev); 1207 int __must_check pci_set_mwi(struct pci_dev *dev); 1208 int __must_check pcim_set_mwi(struct pci_dev *dev); 1209 int pci_try_set_mwi(struct pci_dev *dev); 1210 void pci_clear_mwi(struct pci_dev *dev); 1211 void pci_disable_parity(struct pci_dev *dev); 1212 void pci_intx(struct pci_dev *dev, int enable); 1213 bool pci_check_and_mask_intx(struct pci_dev *dev); 1214 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1215 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1216 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1217 int pcix_get_max_mmrbc(struct pci_dev *dev); 1218 int pcix_get_mmrbc(struct pci_dev *dev); 1219 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1220 int pcie_get_readrq(struct pci_dev *dev); 1221 int pcie_set_readrq(struct pci_dev *dev, int rq); 1222 int pcie_get_mps(struct pci_dev *dev); 1223 int pcie_set_mps(struct pci_dev *dev, int mps); 1224 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1225 enum pci_bus_speed *speed, 1226 enum pcie_link_width *width); 1227 void pcie_print_link_status(struct pci_dev *dev); 1228 bool pcie_has_flr(struct pci_dev *dev); 1229 int pcie_flr(struct pci_dev *dev); 1230 int __pci_reset_function_locked(struct pci_dev *dev); 1231 int pci_reset_function(struct pci_dev *dev); 1232 int pci_reset_function_locked(struct pci_dev *dev); 1233 int pci_try_reset_function(struct pci_dev *dev); 1234 int pci_probe_reset_slot(struct pci_slot *slot); 1235 int pci_probe_reset_bus(struct pci_bus *bus); 1236 int pci_reset_bus(struct pci_dev *dev); 1237 void pci_reset_secondary_bus(struct pci_dev *dev); 1238 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1239 void pci_update_resource(struct pci_dev *dev, int resno); 1240 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1241 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1242 void pci_release_resource(struct pci_dev *dev, int resno); 1243 static inline int pci_rebar_bytes_to_size(u64 bytes) 1244 { 1245 bytes = roundup_pow_of_two(bytes); 1246 1247 /* Return BAR size as defined in the resizable BAR specification */ 1248 return max(ilog2(bytes), 20) - 20; 1249 } 1250 1251 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1252 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1253 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1254 bool pci_device_is_present(struct pci_dev *pdev); 1255 void pci_ignore_hotplug(struct pci_dev *dev); 1256 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1257 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1258 1259 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1260 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1261 const char *fmt, ...); 1262 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1263 1264 /* ROM control related routines */ 1265 int pci_enable_rom(struct pci_dev *pdev); 1266 void pci_disable_rom(struct pci_dev *pdev); 1267 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1268 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1269 1270 /* Power management related routines */ 1271 int pci_save_state(struct pci_dev *dev); 1272 void pci_restore_state(struct pci_dev *dev); 1273 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1274 int pci_load_saved_state(struct pci_dev *dev, 1275 struct pci_saved_state *state); 1276 int pci_load_and_free_saved_state(struct pci_dev *dev, 1277 struct pci_saved_state **state); 1278 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1279 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1280 u16 cap); 1281 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1282 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1283 u16 cap, unsigned int size); 1284 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1285 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1286 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1287 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1288 void pci_pme_active(struct pci_dev *dev, bool enable); 1289 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1290 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1291 int pci_prepare_to_sleep(struct pci_dev *dev); 1292 int pci_back_from_sleep(struct pci_dev *dev); 1293 bool pci_dev_run_wake(struct pci_dev *dev); 1294 void pci_d3cold_enable(struct pci_dev *dev); 1295 void pci_d3cold_disable(struct pci_dev *dev); 1296 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1297 void pci_resume_bus(struct pci_bus *bus); 1298 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1299 1300 /* For use by arch with custom probe code */ 1301 void set_pcie_port_type(struct pci_dev *pdev); 1302 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1303 1304 /* Functions for PCI Hotplug drivers to use */ 1305 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1306 unsigned int pci_rescan_bus(struct pci_bus *bus); 1307 void pci_lock_rescan_remove(void); 1308 void pci_unlock_rescan_remove(void); 1309 1310 /* Vital Product Data routines */ 1311 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1312 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1313 1314 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1315 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1316 void pci_bus_assign_resources(const struct pci_bus *bus); 1317 void pci_bus_claim_resources(struct pci_bus *bus); 1318 void pci_bus_size_bridges(struct pci_bus *bus); 1319 int pci_claim_resource(struct pci_dev *, int); 1320 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1321 void pci_assign_unassigned_resources(void); 1322 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1323 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1324 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1325 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1326 void pdev_enable_device(struct pci_dev *); 1327 int pci_enable_resources(struct pci_dev *, int mask); 1328 void pci_assign_irq(struct pci_dev *dev); 1329 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1330 #define HAVE_PCI_REQ_REGIONS 2 1331 int __must_check pci_request_regions(struct pci_dev *, const char *); 1332 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1333 void pci_release_regions(struct pci_dev *); 1334 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1335 void pci_release_region(struct pci_dev *, int); 1336 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1337 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1338 void pci_release_selected_regions(struct pci_dev *, int); 1339 1340 /* drivers/pci/bus.c */ 1341 void pci_add_resource(struct list_head *resources, struct resource *res); 1342 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1343 resource_size_t offset); 1344 void pci_free_resource_list(struct list_head *resources); 1345 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1346 unsigned int flags); 1347 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1348 void pci_bus_remove_resources(struct pci_bus *bus); 1349 int devm_request_pci_bus_resources(struct device *dev, 1350 struct list_head *resources); 1351 1352 /* Temporary until new and working PCI SBR API in place */ 1353 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1354 1355 #define pci_bus_for_each_resource(bus, res, i) \ 1356 for (i = 0; \ 1357 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1358 i++) 1359 1360 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1361 struct resource *res, resource_size_t size, 1362 resource_size_t align, resource_size_t min, 1363 unsigned long type_mask, 1364 resource_size_t (*alignf)(void *, 1365 const struct resource *, 1366 resource_size_t, 1367 resource_size_t), 1368 void *alignf_data); 1369 1370 1371 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1372 resource_size_t size); 1373 unsigned long pci_address_to_pio(phys_addr_t addr); 1374 phys_addr_t pci_pio_to_address(unsigned long pio); 1375 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1376 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1377 phys_addr_t phys_addr); 1378 void pci_unmap_iospace(struct resource *res); 1379 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1380 resource_size_t offset, 1381 resource_size_t size); 1382 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1383 struct resource *res); 1384 1385 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1386 { 1387 struct pci_bus_region region; 1388 1389 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1390 return region.start; 1391 } 1392 1393 /* Proper probing supporting hot-pluggable devices */ 1394 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1395 const char *mod_name); 1396 1397 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1398 #define pci_register_driver(driver) \ 1399 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1400 1401 void pci_unregister_driver(struct pci_driver *dev); 1402 1403 /** 1404 * module_pci_driver() - Helper macro for registering a PCI driver 1405 * @__pci_driver: pci_driver struct 1406 * 1407 * Helper macro for PCI drivers which do not do anything special in module 1408 * init/exit. This eliminates a lot of boilerplate. Each module may only 1409 * use this macro once, and calling it replaces module_init() and module_exit() 1410 */ 1411 #define module_pci_driver(__pci_driver) \ 1412 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1413 1414 /** 1415 * builtin_pci_driver() - Helper macro for registering a PCI driver 1416 * @__pci_driver: pci_driver struct 1417 * 1418 * Helper macro for PCI drivers which do not do anything special in their 1419 * init code. This eliminates a lot of boilerplate. Each driver may only 1420 * use this macro once, and calling it replaces device_initcall(...) 1421 */ 1422 #define builtin_pci_driver(__pci_driver) \ 1423 builtin_driver(__pci_driver, pci_register_driver) 1424 1425 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1426 int pci_add_dynid(struct pci_driver *drv, 1427 unsigned int vendor, unsigned int device, 1428 unsigned int subvendor, unsigned int subdevice, 1429 unsigned int class, unsigned int class_mask, 1430 unsigned long driver_data); 1431 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1432 struct pci_dev *dev); 1433 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1434 int pass); 1435 1436 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1437 void *userdata); 1438 int pci_cfg_space_size(struct pci_dev *dev); 1439 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1440 void pci_setup_bridge(struct pci_bus *bus); 1441 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1442 unsigned long type); 1443 1444 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1445 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1446 1447 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1448 unsigned int command_bits, u32 flags); 1449 1450 /* 1451 * Virtual interrupts allow for more interrupts to be allocated 1452 * than the device has interrupts for. These are not programmed 1453 * into the device's MSI-X table and must be handled by some 1454 * other driver means. 1455 */ 1456 #define PCI_IRQ_VIRTUAL (1 << 4) 1457 1458 #define PCI_IRQ_ALL_TYPES \ 1459 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1460 1461 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1462 1463 #include <linux/dmapool.h> 1464 1465 #define pci_pool dma_pool 1466 #define pci_pool_create(name, pdev, size, align, allocation) \ 1467 dma_pool_create(name, &pdev->dev, size, align, allocation) 1468 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1469 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1470 #define pci_pool_zalloc(pool, flags, handle) \ 1471 dma_pool_zalloc(pool, flags, handle) 1472 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1473 1474 struct msix_entry { 1475 u32 vector; /* Kernel uses to write allocated vector */ 1476 u16 entry; /* Driver uses to specify entry, OS writes */ 1477 }; 1478 1479 #ifdef CONFIG_PCI_MSI 1480 int pci_msi_vec_count(struct pci_dev *dev); 1481 void pci_disable_msi(struct pci_dev *dev); 1482 int pci_msix_vec_count(struct pci_dev *dev); 1483 void pci_disable_msix(struct pci_dev *dev); 1484 void pci_restore_msi_state(struct pci_dev *dev); 1485 int pci_msi_enabled(void); 1486 int pci_enable_msi(struct pci_dev *dev); 1487 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1488 int minvec, int maxvec); 1489 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1490 struct msix_entry *entries, int nvec) 1491 { 1492 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1493 if (rc < 0) 1494 return rc; 1495 return 0; 1496 } 1497 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1498 unsigned int max_vecs, unsigned int flags, 1499 struct irq_affinity *affd); 1500 1501 void pci_free_irq_vectors(struct pci_dev *dev); 1502 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1503 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1504 1505 #else 1506 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1507 static inline void pci_disable_msi(struct pci_dev *dev) { } 1508 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1509 static inline void pci_disable_msix(struct pci_dev *dev) { } 1510 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1511 static inline int pci_msi_enabled(void) { return 0; } 1512 static inline int pci_enable_msi(struct pci_dev *dev) 1513 { return -ENOSYS; } 1514 static inline int pci_enable_msix_range(struct pci_dev *dev, 1515 struct msix_entry *entries, int minvec, int maxvec) 1516 { return -ENOSYS; } 1517 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1518 struct msix_entry *entries, int nvec) 1519 { return -ENOSYS; } 1520 1521 static inline int 1522 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1523 unsigned int max_vecs, unsigned int flags, 1524 struct irq_affinity *aff_desc) 1525 { 1526 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1527 return 1; 1528 return -ENOSPC; 1529 } 1530 1531 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1532 { 1533 } 1534 1535 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1536 { 1537 if (WARN_ON_ONCE(nr > 0)) 1538 return -EINVAL; 1539 return dev->irq; 1540 } 1541 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1542 int vec) 1543 { 1544 return cpu_possible_mask; 1545 } 1546 #endif 1547 1548 /** 1549 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1550 * @d: the INTx IRQ domain 1551 * @node: the DT node for the device whose interrupt we're translating 1552 * @intspec: the interrupt specifier data from the DT 1553 * @intsize: the number of entries in @intspec 1554 * @out_hwirq: pointer at which to write the hwirq number 1555 * @out_type: pointer at which to write the interrupt type 1556 * 1557 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1558 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1559 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1560 * INTx value to obtain the hwirq number. 1561 * 1562 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1563 */ 1564 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1565 struct device_node *node, 1566 const u32 *intspec, 1567 unsigned int intsize, 1568 unsigned long *out_hwirq, 1569 unsigned int *out_type) 1570 { 1571 const u32 intx = intspec[0]; 1572 1573 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1574 return -EINVAL; 1575 1576 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1577 return 0; 1578 } 1579 1580 #ifdef CONFIG_PCIEPORTBUS 1581 extern bool pcie_ports_disabled; 1582 extern bool pcie_ports_native; 1583 #else 1584 #define pcie_ports_disabled true 1585 #define pcie_ports_native false 1586 #endif 1587 1588 #define PCIE_LINK_STATE_L0S BIT(0) 1589 #define PCIE_LINK_STATE_L1 BIT(1) 1590 #define PCIE_LINK_STATE_CLKPM BIT(2) 1591 #define PCIE_LINK_STATE_L1_1 BIT(3) 1592 #define PCIE_LINK_STATE_L1_2 BIT(4) 1593 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1594 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1595 1596 #ifdef CONFIG_PCIEASPM 1597 int pci_disable_link_state(struct pci_dev *pdev, int state); 1598 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1599 void pcie_no_aspm(void); 1600 bool pcie_aspm_support_enabled(void); 1601 bool pcie_aspm_enabled(struct pci_dev *pdev); 1602 #else 1603 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1604 { return 0; } 1605 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1606 { return 0; } 1607 static inline void pcie_no_aspm(void) { } 1608 static inline bool pcie_aspm_support_enabled(void) { return false; } 1609 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1610 #endif 1611 1612 #ifdef CONFIG_PCIEAER 1613 bool pci_aer_available(void); 1614 #else 1615 static inline bool pci_aer_available(void) { return false; } 1616 #endif 1617 1618 bool pci_ats_disabled(void); 1619 1620 void pci_cfg_access_lock(struct pci_dev *dev); 1621 bool pci_cfg_access_trylock(struct pci_dev *dev); 1622 void pci_cfg_access_unlock(struct pci_dev *dev); 1623 1624 /* 1625 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1626 * a PCI domain is defined to be a set of PCI buses which share 1627 * configuration space. 1628 */ 1629 #ifdef CONFIG_PCI_DOMAINS 1630 extern int pci_domains_supported; 1631 #else 1632 enum { pci_domains_supported = 0 }; 1633 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1634 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1635 #endif /* CONFIG_PCI_DOMAINS */ 1636 1637 /* 1638 * Generic implementation for PCI domain support. If your 1639 * architecture does not need custom management of PCI 1640 * domains then this implementation will be used 1641 */ 1642 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1643 static inline int pci_domain_nr(struct pci_bus *bus) 1644 { 1645 return bus->domain_nr; 1646 } 1647 #ifdef CONFIG_ACPI 1648 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1649 #else 1650 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1651 { return 0; } 1652 #endif 1653 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1654 #endif 1655 1656 /* Some architectures require additional setup to direct VGA traffic */ 1657 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1658 unsigned int command_bits, u32 flags); 1659 void pci_register_set_vga_state(arch_set_vga_state_t func); 1660 1661 static inline int 1662 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1663 { 1664 return pci_request_selected_regions(pdev, 1665 pci_select_bars(pdev, IORESOURCE_IO), name); 1666 } 1667 1668 static inline void 1669 pci_release_io_regions(struct pci_dev *pdev) 1670 { 1671 return pci_release_selected_regions(pdev, 1672 pci_select_bars(pdev, IORESOURCE_IO)); 1673 } 1674 1675 static inline int 1676 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1677 { 1678 return pci_request_selected_regions(pdev, 1679 pci_select_bars(pdev, IORESOURCE_MEM), name); 1680 } 1681 1682 static inline void 1683 pci_release_mem_regions(struct pci_dev *pdev) 1684 { 1685 return pci_release_selected_regions(pdev, 1686 pci_select_bars(pdev, IORESOURCE_MEM)); 1687 } 1688 1689 #else /* CONFIG_PCI is not enabled */ 1690 1691 static inline void pci_set_flags(int flags) { } 1692 static inline void pci_add_flags(int flags) { } 1693 static inline void pci_clear_flags(int flags) { } 1694 static inline int pci_has_flag(int flag) { return 0; } 1695 1696 /* 1697 * If the system does not have PCI, clearly these return errors. Define 1698 * these as simple inline functions to avoid hair in drivers. 1699 */ 1700 #define _PCI_NOP(o, s, t) \ 1701 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1702 int where, t val) \ 1703 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1704 1705 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1706 _PCI_NOP(o, word, u16 x) \ 1707 _PCI_NOP(o, dword, u32 x) 1708 _PCI_NOP_ALL(read, *) 1709 _PCI_NOP_ALL(write,) 1710 1711 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1712 unsigned int device, 1713 struct pci_dev *from) 1714 { return NULL; } 1715 1716 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1717 unsigned int device, 1718 unsigned int ss_vendor, 1719 unsigned int ss_device, 1720 struct pci_dev *from) 1721 { return NULL; } 1722 1723 static inline struct pci_dev *pci_get_class(unsigned int class, 1724 struct pci_dev *from) 1725 { return NULL; } 1726 1727 #define pci_dev_present(ids) (0) 1728 #define no_pci_devices() (1) 1729 #define pci_dev_put(dev) do { } while (0) 1730 1731 static inline void pci_set_master(struct pci_dev *dev) { } 1732 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1733 static inline void pci_disable_device(struct pci_dev *dev) { } 1734 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1735 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1736 { return -EBUSY; } 1737 static inline int __pci_register_driver(struct pci_driver *drv, 1738 struct module *owner) 1739 { return 0; } 1740 static inline int pci_register_driver(struct pci_driver *drv) 1741 { return 0; } 1742 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1743 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1744 { return 0; } 1745 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1746 int cap) 1747 { return 0; } 1748 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1749 { return 0; } 1750 1751 static inline u64 pci_get_dsn(struct pci_dev *dev) 1752 { return 0; } 1753 1754 /* Power management related routines */ 1755 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1756 static inline void pci_restore_state(struct pci_dev *dev) { } 1757 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1758 { return 0; } 1759 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1760 { return 0; } 1761 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1762 pm_message_t state) 1763 { return PCI_D0; } 1764 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1765 int enable) 1766 { return 0; } 1767 1768 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1769 struct resource *res) 1770 { return NULL; } 1771 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1772 { return -EIO; } 1773 static inline void pci_release_regions(struct pci_dev *dev) { } 1774 1775 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1776 1777 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1778 { return NULL; } 1779 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1780 unsigned int devfn) 1781 { return NULL; } 1782 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1783 unsigned int bus, unsigned int devfn) 1784 { return NULL; } 1785 1786 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1787 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1788 1789 #define dev_is_pci(d) (false) 1790 #define dev_is_pf(d) (false) 1791 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1792 { return false; } 1793 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1794 struct device_node *node, 1795 const u32 *intspec, 1796 unsigned int intsize, 1797 unsigned long *out_hwirq, 1798 unsigned int *out_type) 1799 { return -EINVAL; } 1800 1801 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1802 struct pci_dev *dev) 1803 { return NULL; } 1804 static inline bool pci_ats_disabled(void) { return true; } 1805 1806 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1807 { 1808 return -EINVAL; 1809 } 1810 1811 static inline int 1812 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1813 unsigned int max_vecs, unsigned int flags, 1814 struct irq_affinity *aff_desc) 1815 { 1816 return -ENOSPC; 1817 } 1818 #endif /* CONFIG_PCI */ 1819 1820 static inline int 1821 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1822 unsigned int max_vecs, unsigned int flags) 1823 { 1824 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1825 NULL); 1826 } 1827 1828 /* Include architecture-dependent settings and functions */ 1829 1830 #include <asm/pci.h> 1831 1832 /* These two functions provide almost identical functionality. Depending 1833 * on the architecture, one will be implemented as a wrapper around the 1834 * other (in drivers/pci/mmap.c). 1835 * 1836 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1837 * is expected to be an offset within that region. 1838 * 1839 * pci_mmap_page_range() is the legacy architecture-specific interface, 1840 * which accepts a "user visible" resource address converted by 1841 * pci_resource_to_user(), as used in the legacy mmap() interface in 1842 * /proc/bus/pci/. 1843 */ 1844 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1845 struct vm_area_struct *vma, 1846 enum pci_mmap_state mmap_state, int write_combine); 1847 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1848 struct vm_area_struct *vma, 1849 enum pci_mmap_state mmap_state, int write_combine); 1850 1851 #ifndef arch_can_pci_mmap_wc 1852 #define arch_can_pci_mmap_wc() 0 1853 #endif 1854 1855 #ifndef arch_can_pci_mmap_io 1856 #define arch_can_pci_mmap_io() 0 1857 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1858 #else 1859 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1860 #endif 1861 1862 #ifndef pci_root_bus_fwnode 1863 #define pci_root_bus_fwnode(bus) NULL 1864 #endif 1865 1866 /* 1867 * These helpers provide future and backwards compatibility 1868 * for accessing popular PCI BAR info 1869 */ 1870 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1871 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1872 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1873 #define pci_resource_len(dev,bar) \ 1874 ((pci_resource_start((dev), (bar)) == 0 && \ 1875 pci_resource_end((dev), (bar)) == \ 1876 pci_resource_start((dev), (bar))) ? 0 : \ 1877 \ 1878 (pci_resource_end((dev), (bar)) - \ 1879 pci_resource_start((dev), (bar)) + 1)) 1880 1881 /* 1882 * Similar to the helpers above, these manipulate per-pci_dev 1883 * driver-specific data. They are really just a wrapper around 1884 * the generic device structure functions of these calls. 1885 */ 1886 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1887 { 1888 return dev_get_drvdata(&pdev->dev); 1889 } 1890 1891 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1892 { 1893 dev_set_drvdata(&pdev->dev, data); 1894 } 1895 1896 static inline const char *pci_name(const struct pci_dev *pdev) 1897 { 1898 return dev_name(&pdev->dev); 1899 } 1900 1901 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1902 const struct resource *rsrc, 1903 resource_size_t *start, resource_size_t *end); 1904 1905 /* 1906 * The world is not perfect and supplies us with broken PCI devices. 1907 * For at least a part of these bugs we need a work-around, so both 1908 * generic (drivers/pci/quirks.c) and per-architecture code can define 1909 * fixup hooks to be called for particular buggy devices. 1910 */ 1911 1912 struct pci_fixup { 1913 u16 vendor; /* Or PCI_ANY_ID */ 1914 u16 device; /* Or PCI_ANY_ID */ 1915 u32 class; /* Or PCI_ANY_ID */ 1916 unsigned int class_shift; /* should be 0, 8, 16 */ 1917 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1918 int hook_offset; 1919 #else 1920 void (*hook)(struct pci_dev *dev); 1921 #endif 1922 }; 1923 1924 enum pci_fixup_pass { 1925 pci_fixup_early, /* Before probing BARs */ 1926 pci_fixup_header, /* After reading configuration header */ 1927 pci_fixup_final, /* Final phase of device fixups */ 1928 pci_fixup_enable, /* pci_enable_device() time */ 1929 pci_fixup_resume, /* pci_device_resume() */ 1930 pci_fixup_suspend, /* pci_device_suspend() */ 1931 pci_fixup_resume_early, /* pci_device_resume_early() */ 1932 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1933 }; 1934 1935 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1936 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1937 class_shift, hook) \ 1938 __ADDRESSABLE(hook) \ 1939 asm(".section " #sec ", \"a\" \n" \ 1940 ".balign 16 \n" \ 1941 ".short " #vendor ", " #device " \n" \ 1942 ".long " #class ", " #class_shift " \n" \ 1943 ".long " #hook " - . \n" \ 1944 ".previous \n"); 1945 1946 /* 1947 * Clang's LTO may rename static functions in C, but has no way to 1948 * handle such renamings when referenced from inline asm. To work 1949 * around this, create global C stubs for these cases. 1950 */ 1951 #ifdef CONFIG_LTO_CLANG 1952 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1953 class_shift, hook, stub) \ 1954 void __cficanonical stub(struct pci_dev *dev); \ 1955 void __cficanonical stub(struct pci_dev *dev) \ 1956 { \ 1957 hook(dev); \ 1958 } \ 1959 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1960 class_shift, stub) 1961 #else 1962 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1963 class_shift, hook, stub) \ 1964 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1965 class_shift, hook) 1966 #endif 1967 1968 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1969 class_shift, hook) \ 1970 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 1971 class_shift, hook, __UNIQUE_ID(hook)) 1972 #else 1973 /* Anonymous variables would be nice... */ 1974 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1975 class_shift, hook) \ 1976 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1977 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1978 = { vendor, device, class, class_shift, hook }; 1979 #endif 1980 1981 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1982 class_shift, hook) \ 1983 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1984 hook, vendor, device, class, class_shift, hook) 1985 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1986 class_shift, hook) \ 1987 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1988 hook, vendor, device, class, class_shift, hook) 1989 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1990 class_shift, hook) \ 1991 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1992 hook, vendor, device, class, class_shift, hook) 1993 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1994 class_shift, hook) \ 1995 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1996 hook, vendor, device, class, class_shift, hook) 1997 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1998 class_shift, hook) \ 1999 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2000 resume##hook, vendor, device, class, class_shift, hook) 2001 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2002 class_shift, hook) \ 2003 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2004 resume_early##hook, vendor, device, class, class_shift, hook) 2005 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2006 class_shift, hook) \ 2007 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2008 suspend##hook, vendor, device, class, class_shift, hook) 2009 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2010 class_shift, hook) \ 2011 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2012 suspend_late##hook, vendor, device, class, class_shift, hook) 2013 2014 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2015 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2016 hook, vendor, device, PCI_ANY_ID, 0, hook) 2017 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2018 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2019 hook, vendor, device, PCI_ANY_ID, 0, hook) 2020 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2021 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2022 hook, vendor, device, PCI_ANY_ID, 0, hook) 2023 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2024 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2025 hook, vendor, device, PCI_ANY_ID, 0, hook) 2026 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2027 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2028 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2029 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2030 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2031 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2032 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2033 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2034 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2035 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2036 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2037 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2038 2039 #ifdef CONFIG_PCI_QUIRKS 2040 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2041 #else 2042 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2043 struct pci_dev *dev) { } 2044 #endif 2045 2046 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2047 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2048 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2049 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2050 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2051 const char *name); 2052 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2053 2054 extern int pci_pci_problems; 2055 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2056 #define PCIPCI_TRITON 2 2057 #define PCIPCI_NATOMA 4 2058 #define PCIPCI_VIAETBF 8 2059 #define PCIPCI_VSFX 16 2060 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2061 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2062 2063 extern unsigned long pci_cardbus_io_size; 2064 extern unsigned long pci_cardbus_mem_size; 2065 extern u8 pci_dfl_cache_line_size; 2066 extern u8 pci_cache_line_size; 2067 2068 /* Architecture-specific versions may override these (weak) */ 2069 void pcibios_disable_device(struct pci_dev *dev); 2070 void pcibios_set_master(struct pci_dev *dev); 2071 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2072 enum pcie_reset_state state); 2073 int pcibios_add_device(struct pci_dev *dev); 2074 void pcibios_release_device(struct pci_dev *dev); 2075 #ifdef CONFIG_PCI 2076 void pcibios_penalize_isa_irq(int irq, int active); 2077 #else 2078 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2079 #endif 2080 int pcibios_alloc_irq(struct pci_dev *dev); 2081 void pcibios_free_irq(struct pci_dev *dev); 2082 resource_size_t pcibios_default_alignment(void); 2083 2084 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2085 void __init pci_mmcfg_early_init(void); 2086 void __init pci_mmcfg_late_init(void); 2087 #else 2088 static inline void pci_mmcfg_early_init(void) { } 2089 static inline void pci_mmcfg_late_init(void) { } 2090 #endif 2091 2092 int pci_ext_cfg_avail(void); 2093 2094 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2095 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2096 2097 #ifdef CONFIG_PCI_IOV 2098 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2099 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2100 2101 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2102 void pci_disable_sriov(struct pci_dev *dev); 2103 2104 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2105 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2106 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2107 int pci_num_vf(struct pci_dev *dev); 2108 int pci_vfs_assigned(struct pci_dev *dev); 2109 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2110 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2111 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2112 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2113 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2114 2115 /* Arch may override these (weak) */ 2116 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2117 int pcibios_sriov_disable(struct pci_dev *pdev); 2118 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2119 #else 2120 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2121 { 2122 return -ENOSYS; 2123 } 2124 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2125 { 2126 return -ENOSYS; 2127 } 2128 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2129 { return -ENODEV; } 2130 2131 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2132 struct pci_dev *virtfn, int id) 2133 { 2134 return -ENODEV; 2135 } 2136 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2137 { 2138 return -ENOSYS; 2139 } 2140 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2141 int id) { } 2142 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2143 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2144 static inline int pci_vfs_assigned(struct pci_dev *dev) 2145 { return 0; } 2146 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2147 { return 0; } 2148 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2149 { return 0; } 2150 #define pci_sriov_configure_simple NULL 2151 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2152 { return 0; } 2153 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2154 #endif 2155 2156 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2157 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2158 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2159 #endif 2160 2161 /** 2162 * pci_pcie_cap - get the saved PCIe capability offset 2163 * @dev: PCI device 2164 * 2165 * PCIe capability offset is calculated at PCI device initialization 2166 * time and saved in the data structure. This function returns saved 2167 * PCIe capability offset. Using this instead of pci_find_capability() 2168 * reduces unnecessary search in the PCI configuration space. If you 2169 * need to calculate PCIe capability offset from raw device for some 2170 * reasons, please use pci_find_capability() instead. 2171 */ 2172 static inline int pci_pcie_cap(struct pci_dev *dev) 2173 { 2174 return dev->pcie_cap; 2175 } 2176 2177 /** 2178 * pci_is_pcie - check if the PCI device is PCI Express capable 2179 * @dev: PCI device 2180 * 2181 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2182 */ 2183 static inline bool pci_is_pcie(struct pci_dev *dev) 2184 { 2185 return pci_pcie_cap(dev); 2186 } 2187 2188 /** 2189 * pcie_caps_reg - get the PCIe Capabilities Register 2190 * @dev: PCI device 2191 */ 2192 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2193 { 2194 return dev->pcie_flags_reg; 2195 } 2196 2197 /** 2198 * pci_pcie_type - get the PCIe device/port type 2199 * @dev: PCI device 2200 */ 2201 static inline int pci_pcie_type(const struct pci_dev *dev) 2202 { 2203 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2204 } 2205 2206 /** 2207 * pcie_find_root_port - Get the PCIe root port device 2208 * @dev: PCI device 2209 * 2210 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2211 * for a given PCI/PCIe Device. 2212 */ 2213 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2214 { 2215 while (dev) { 2216 if (pci_is_pcie(dev) && 2217 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2218 return dev; 2219 dev = pci_upstream_bridge(dev); 2220 } 2221 2222 return NULL; 2223 } 2224 2225 void pci_request_acs(void); 2226 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2227 bool pci_acs_path_enabled(struct pci_dev *start, 2228 struct pci_dev *end, u16 acs_flags); 2229 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2230 2231 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2232 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2233 2234 /* Large Resource Data Type Tag Item Names */ 2235 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2236 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2237 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2238 2239 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2240 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2241 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2242 2243 /* Small Resource Data Type Tag Item Names */ 2244 #define PCI_VPD_STIN_END 0x0f /* End */ 2245 2246 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) 2247 2248 #define PCI_VPD_SRDT_TIN_MASK 0x78 2249 #define PCI_VPD_SRDT_LEN_MASK 0x07 2250 #define PCI_VPD_LRDT_TIN_MASK 0x7f 2251 2252 #define PCI_VPD_LRDT_TAG_SIZE 3 2253 #define PCI_VPD_SRDT_TAG_SIZE 1 2254 2255 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 2256 2257 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2258 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2259 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2260 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2261 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2262 2263 /** 2264 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 2265 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2266 * 2267 * Returns the extracted Large Resource Data Type length. 2268 */ 2269 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 2270 { 2271 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 2272 } 2273 2274 /** 2275 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item 2276 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 2277 * 2278 * Returns the extracted Large Resource Data Type Tag item. 2279 */ 2280 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2281 { 2282 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2283 } 2284 2285 /** 2286 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 2287 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2288 * 2289 * Returns the extracted Small Resource Data Type length. 2290 */ 2291 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 2292 { 2293 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 2294 } 2295 2296 /** 2297 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item 2298 * @srdt: Pointer to the beginning of the Small Resource Data Type tag 2299 * 2300 * Returns the extracted Small Resource Data Type Tag Item. 2301 */ 2302 static inline u8 pci_vpd_srdt_tag(const u8 *srdt) 2303 { 2304 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; 2305 } 2306 2307 /** 2308 * pci_vpd_info_field_size - Extracts the information field length 2309 * @info_field: Pointer to the beginning of an information field header 2310 * 2311 * Returns the extracted information field length. 2312 */ 2313 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 2314 { 2315 return info_field[2]; 2316 } 2317 2318 /** 2319 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 2320 * @buf: Pointer to buffered vpd data 2321 * @len: The length of the vpd buffer 2322 * @rdt: The Resource Data Type to search for 2323 * 2324 * Returns the index where the Resource Data Type was found or 2325 * -ENOENT otherwise. 2326 */ 2327 int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt); 2328 2329 /** 2330 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 2331 * @buf: Pointer to buffered vpd data 2332 * @off: The offset into the buffer at which to begin the search 2333 * @len: The length of the buffer area, relative to off, in which to search 2334 * @kw: The keyword to search for 2335 * 2336 * Returns the index where the information field keyword was found or 2337 * -ENOENT otherwise. 2338 */ 2339 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 2340 unsigned int len, const char *kw); 2341 2342 /* PCI <-> OF binding helpers */ 2343 #ifdef CONFIG_OF 2344 struct device_node; 2345 struct irq_domain; 2346 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2347 2348 /* Arch may override this (weak) */ 2349 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2350 2351 #else /* CONFIG_OF */ 2352 static inline struct irq_domain * 2353 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2354 #endif /* CONFIG_OF */ 2355 2356 static inline struct device_node * 2357 pci_device_to_OF_node(const struct pci_dev *pdev) 2358 { 2359 return pdev ? pdev->dev.of_node : NULL; 2360 } 2361 2362 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2363 { 2364 return bus ? bus->dev.of_node : NULL; 2365 } 2366 2367 #ifdef CONFIG_ACPI 2368 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2369 2370 void 2371 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2372 bool pci_pr3_present(struct pci_dev *pdev); 2373 #else 2374 static inline struct irq_domain * 2375 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2376 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2377 #endif 2378 2379 #ifdef CONFIG_EEH 2380 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2381 { 2382 return pdev->dev.archdata.edev; 2383 } 2384 #endif 2385 2386 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2387 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2388 int pci_for_each_dma_alias(struct pci_dev *pdev, 2389 int (*fn)(struct pci_dev *pdev, 2390 u16 alias, void *data), void *data); 2391 2392 /* Helper functions for operation of device flag */ 2393 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2394 { 2395 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2396 } 2397 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2398 { 2399 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2400 } 2401 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2402 { 2403 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2404 } 2405 2406 /** 2407 * pci_ari_enabled - query ARI forwarding status 2408 * @bus: the PCI bus 2409 * 2410 * Returns true if ARI forwarding is enabled. 2411 */ 2412 static inline bool pci_ari_enabled(struct pci_bus *bus) 2413 { 2414 return bus->self && bus->self->ari_enabled; 2415 } 2416 2417 /** 2418 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2419 * @pdev: PCI device to check 2420 * 2421 * Walk upwards from @pdev and check for each encountered bridge if it's part 2422 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2423 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2424 */ 2425 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2426 { 2427 struct pci_dev *parent = pdev; 2428 2429 if (pdev->is_thunderbolt) 2430 return true; 2431 2432 while ((parent = pci_upstream_bridge(parent))) 2433 if (parent->is_thunderbolt) 2434 return true; 2435 2436 return false; 2437 } 2438 2439 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2440 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2441 #endif 2442 2443 /* Provide the legacy pci_dma_* API */ 2444 #include <linux/pci-dma-compat.h> 2445 2446 #define pci_printk(level, pdev, fmt, arg...) \ 2447 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2448 2449 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2450 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2451 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2452 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2453 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2454 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2455 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2456 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2457 2458 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2459 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2460 2461 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2462 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2463 2464 #define pci_WARN(pdev, condition, fmt, arg...) \ 2465 WARN(condition, "%s %s: " fmt, \ 2466 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2467 2468 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2469 WARN_ONCE(condition, "%s %s: " fmt, \ 2470 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2471 2472 #endif /* LINUX_PCI_H */ 2473