1 /* 2 * pci.h 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <[email protected]> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 #ifndef LINUX_PCI_H 17 #define LINUX_PCI_H 18 19 20 #include <linux/mod_devicetable.h> 21 22 #include <linux/types.h> 23 #include <linux/init.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/compiler.h> 27 #include <linux/errno.h> 28 #include <linux/kobject.h> 29 #include <linux/atomic.h> 30 #include <linux/device.h> 31 #include <linux/io.h> 32 #include <linux/resource_ext.h> 33 #include <uapi/linux/pci.h> 34 35 #include <linux/pci_ids.h> 36 37 /* 38 * The PCI interface treats multi-function devices as independent 39 * devices. The slot/function address of each device is encoded 40 * in a single byte as follows: 41 * 42 * 7:3 = slot 43 * 2:0 = function 44 * 45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 46 * In the interest of not exposing interfaces to user-space unnecessarily, 47 * the following kernel-only defines are being added here. 48 */ 49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 52 53 /* pci_slot represents a physical slot */ 54 struct pci_slot { 55 struct pci_bus *bus; /* The bus this slot is on */ 56 struct list_head list; /* node in list of slots on this bus */ 57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 59 struct kobject kobj; 60 }; 61 62 static inline const char *pci_slot_name(const struct pci_slot *slot) 63 { 64 return kobject_name(&slot->kobj); 65 } 66 67 /* File state for mmap()s on /proc/bus/pci/X/Y */ 68 enum pci_mmap_state { 69 pci_mmap_io, 70 pci_mmap_mem 71 }; 72 73 /* This defines the direction arg to the DMA mapping routines. */ 74 #define PCI_DMA_BIDIRECTIONAL 0 75 #define PCI_DMA_TODEVICE 1 76 #define PCI_DMA_FROMDEVICE 2 77 #define PCI_DMA_NONE 3 78 79 /* 80 * For PCI devices, the region numbers are assigned this way: 81 */ 82 enum { 83 /* #0-5: standard PCI resources */ 84 PCI_STD_RESOURCES, 85 PCI_STD_RESOURCE_END = 5, 86 87 /* #6: expansion ROM resource */ 88 PCI_ROM_RESOURCE, 89 90 /* device specific resources */ 91 #ifdef CONFIG_PCI_IOV 92 PCI_IOV_RESOURCES, 93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 94 #endif 95 96 /* resources assigned to buses behind the bridge */ 97 #define PCI_BRIDGE_RESOURCE_NUM 4 98 99 PCI_BRIDGE_RESOURCES, 100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 101 PCI_BRIDGE_RESOURCE_NUM - 1, 102 103 /* total resources associated with a PCI device */ 104 PCI_NUM_RESOURCES, 105 106 /* preserve this for compatibility */ 107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 108 }; 109 110 typedef int __bitwise pci_power_t; 111 112 #define PCI_D0 ((pci_power_t __force) 0) 113 #define PCI_D1 ((pci_power_t __force) 1) 114 #define PCI_D2 ((pci_power_t __force) 2) 115 #define PCI_D3hot ((pci_power_t __force) 3) 116 #define PCI_D3cold ((pci_power_t __force) 4) 117 #define PCI_UNKNOWN ((pci_power_t __force) 5) 118 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 119 120 /* Remember to update this when the list above changes! */ 121 extern const char *pci_power_names[]; 122 123 static inline const char *pci_power_name(pci_power_t state) 124 { 125 return pci_power_names[1 + (int) state]; 126 } 127 128 #define PCI_PM_D2_DELAY 200 129 #define PCI_PM_D3_WAIT 10 130 #define PCI_PM_D3COLD_WAIT 100 131 #define PCI_PM_BUS_WAIT 50 132 133 /** The pci_channel state describes connectivity between the CPU and 134 * the pci device. If some PCI bus between here and the pci device 135 * has crashed or locked up, this info is reflected here. 136 */ 137 typedef unsigned int __bitwise pci_channel_state_t; 138 139 enum pci_channel_state { 140 /* I/O channel is in normal state */ 141 pci_channel_io_normal = (__force pci_channel_state_t) 1, 142 143 /* I/O to channel is blocked */ 144 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 145 146 /* PCI card is dead */ 147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 148 }; 149 150 typedef unsigned int __bitwise pcie_reset_state_t; 151 152 enum pcie_reset_state { 153 /* Reset is NOT asserted (Use to deassert reset) */ 154 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 155 156 /* Use #PERST to reset PCIe device */ 157 pcie_warm_reset = (__force pcie_reset_state_t) 2, 158 159 /* Use PCIe Hot Reset to reset device */ 160 pcie_hot_reset = (__force pcie_reset_state_t) 3 161 }; 162 163 typedef unsigned short __bitwise pci_dev_flags_t; 164 enum pci_dev_flags { 165 /* INTX_DISABLE in PCI_COMMAND register disables MSI 166 * generation too. 167 */ 168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 169 /* Device configuration is irrevocably lost if disabled into D3 */ 170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 171 /* Provide indication device is assigned by a Virtual Machine Manager */ 172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 173 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 174 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 175 /* Flag to indicate the device uses dma_alias_devfn */ 176 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), 177 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 178 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 179 /* Do not use bus resets for device */ 180 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 181 /* Do not use PM reset even if device advertises NoSoftRst- */ 182 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 183 /* Get VPD from function 0 VPD */ 184 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 185 }; 186 187 enum pci_irq_reroute_variant { 188 INTEL_IRQ_REROUTE_VARIANT = 1, 189 MAX_IRQ_REROUTE_VARIANTS = 3 190 }; 191 192 typedef unsigned short __bitwise pci_bus_flags_t; 193 enum pci_bus_flags { 194 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 195 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 196 }; 197 198 /* These values come from the PCI Express Spec */ 199 enum pcie_link_width { 200 PCIE_LNK_WIDTH_RESRV = 0x00, 201 PCIE_LNK_X1 = 0x01, 202 PCIE_LNK_X2 = 0x02, 203 PCIE_LNK_X4 = 0x04, 204 PCIE_LNK_X8 = 0x08, 205 PCIE_LNK_X12 = 0x0C, 206 PCIE_LNK_X16 = 0x10, 207 PCIE_LNK_X32 = 0x20, 208 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 209 }; 210 211 /* Based on the PCI Hotplug Spec, but some values are made up by us */ 212 enum pci_bus_speed { 213 PCI_SPEED_33MHz = 0x00, 214 PCI_SPEED_66MHz = 0x01, 215 PCI_SPEED_66MHz_PCIX = 0x02, 216 PCI_SPEED_100MHz_PCIX = 0x03, 217 PCI_SPEED_133MHz_PCIX = 0x04, 218 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 219 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 220 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 221 PCI_SPEED_66MHz_PCIX_266 = 0x09, 222 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 223 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 224 AGP_UNKNOWN = 0x0c, 225 AGP_1X = 0x0d, 226 AGP_2X = 0x0e, 227 AGP_4X = 0x0f, 228 AGP_8X = 0x10, 229 PCI_SPEED_66MHz_PCIX_533 = 0x11, 230 PCI_SPEED_100MHz_PCIX_533 = 0x12, 231 PCI_SPEED_133MHz_PCIX_533 = 0x13, 232 PCIE_SPEED_2_5GT = 0x14, 233 PCIE_SPEED_5_0GT = 0x15, 234 PCIE_SPEED_8_0GT = 0x16, 235 PCI_SPEED_UNKNOWN = 0xff, 236 }; 237 238 struct pci_cap_saved_data { 239 u16 cap_nr; 240 bool cap_extended; 241 unsigned int size; 242 u32 data[0]; 243 }; 244 245 struct pci_cap_saved_state { 246 struct hlist_node next; 247 struct pci_cap_saved_data cap; 248 }; 249 250 struct pcie_link_state; 251 struct pci_vpd; 252 struct pci_sriov; 253 struct pci_ats; 254 255 /* 256 * The pci_dev structure is used to describe PCI devices. 257 */ 258 struct pci_dev { 259 struct list_head bus_list; /* node in per-bus list */ 260 struct pci_bus *bus; /* bus this device is on */ 261 struct pci_bus *subordinate; /* bus this device bridges to */ 262 263 void *sysdata; /* hook for sys-specific extension */ 264 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 265 struct pci_slot *slot; /* Physical slot this device is in */ 266 267 unsigned int devfn; /* encoded device & function index */ 268 unsigned short vendor; 269 unsigned short device; 270 unsigned short subsystem_vendor; 271 unsigned short subsystem_device; 272 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 273 u8 revision; /* PCI revision, low byte of class word */ 274 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 275 u8 pcie_cap; /* PCIe capability offset */ 276 u8 msi_cap; /* MSI capability offset */ 277 u8 msix_cap; /* MSI-X capability offset */ 278 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 279 u8 rom_base_reg; /* which config register controls the ROM */ 280 u8 pin; /* which interrupt pin this device uses */ 281 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 282 u8 dma_alias_devfn;/* devfn of DMA alias, if any */ 283 284 struct pci_driver *driver; /* which driver has allocated this device */ 285 u64 dma_mask; /* Mask of the bits of bus address this 286 device implements. Normally this is 287 0xffffffff. You only need to change 288 this if your device has broken DMA 289 or supports 64-bit transfers. */ 290 291 struct device_dma_parameters dma_parms; 292 293 pci_power_t current_state; /* Current operating state. In ACPI-speak, 294 this is D0-D3, D0 being fully functional, 295 and D3 being off. */ 296 u8 pm_cap; /* PM capability offset */ 297 unsigned int pme_support:5; /* Bitmask of states from which PME# 298 can be generated */ 299 unsigned int pme_interrupt:1; 300 unsigned int pme_poll:1; /* Poll device's PME status bit */ 301 unsigned int d1_support:1; /* Low power state D1 is supported */ 302 unsigned int d2_support:1; /* Low power state D2 is supported */ 303 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 304 unsigned int no_d3cold:1; /* D3cold is forbidden */ 305 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 306 unsigned int mmio_always_on:1; /* disallow turning off io/mem 307 decoding during bar sizing */ 308 unsigned int wakeup_prepared:1; 309 unsigned int runtime_d3cold:1; /* whether go through runtime 310 D3cold, not set for devices 311 powered on/off by the 312 corresponding bridge */ 313 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 314 unsigned int d3_delay; /* D3->D0 transition time in ms */ 315 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 316 317 #ifdef CONFIG_PCIEASPM 318 struct pcie_link_state *link_state; /* ASPM link state */ 319 #endif 320 321 pci_channel_state_t error_state; /* current connectivity state */ 322 struct device dev; /* Generic device interface */ 323 324 int cfg_size; /* Size of configuration space */ 325 326 /* 327 * Instead of touching interrupt line and base address registers 328 * directly, use the values stored here. They might be different! 329 */ 330 unsigned int irq; 331 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 332 333 bool match_driver; /* Skip attaching driver */ 334 /* These fields are used by common fixups */ 335 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 336 unsigned int multifunction:1;/* Part of multi-function device */ 337 /* keep track of device state */ 338 unsigned int is_added:1; 339 unsigned int is_busmaster:1; /* device is busmaster */ 340 unsigned int no_msi:1; /* device may not use msi */ 341 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 342 unsigned int block_cfg_access:1; /* config space access is blocked */ 343 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 344 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 345 unsigned int msi_enabled:1; 346 unsigned int msix_enabled:1; 347 unsigned int ari_enabled:1; /* ARI forwarding */ 348 unsigned int ats_enabled:1; /* Address Translation Service */ 349 unsigned int is_managed:1; 350 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 351 unsigned int state_saved:1; 352 unsigned int is_physfn:1; 353 unsigned int is_virtfn:1; 354 unsigned int reset_fn:1; 355 unsigned int is_hotplug_bridge:1; 356 unsigned int __aer_firmware_first_valid:1; 357 unsigned int __aer_firmware_first:1; 358 unsigned int broken_intx_masking:1; 359 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 360 unsigned int irq_managed:1; 361 unsigned int has_secondary_link:1; 362 pci_dev_flags_t dev_flags; 363 atomic_t enable_cnt; /* pci_enable_device has been called */ 364 365 u32 saved_config_space[16]; /* config space saved at suspend time */ 366 struct hlist_head saved_cap_space; 367 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 368 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 369 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 370 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 371 #ifdef CONFIG_PCI_MSI 372 const struct attribute_group **msi_irq_groups; 373 #endif 374 struct pci_vpd *vpd; 375 #ifdef CONFIG_PCI_ATS 376 union { 377 struct pci_sriov *sriov; /* SR-IOV capability related */ 378 struct pci_dev *physfn; /* the PF this VF is associated with */ 379 }; 380 u16 ats_cap; /* ATS Capability offset */ 381 u8 ats_stu; /* ATS Smallest Translation Unit */ 382 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 383 #endif 384 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 385 size_t romlen; /* Length of ROM if it's not from the BAR */ 386 char *driver_override; /* Driver name to force a match */ 387 }; 388 389 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 390 { 391 #ifdef CONFIG_PCI_IOV 392 if (dev->is_virtfn) 393 dev = dev->physfn; 394 #endif 395 return dev; 396 } 397 398 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 399 400 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 401 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 402 403 static inline int pci_channel_offline(struct pci_dev *pdev) 404 { 405 return (pdev->error_state != pci_channel_io_normal); 406 } 407 408 struct pci_host_bridge { 409 struct device dev; 410 struct pci_bus *bus; /* root bus */ 411 struct list_head windows; /* resource_entry */ 412 void (*release_fn)(struct pci_host_bridge *); 413 void *release_data; 414 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 415 /* Resource alignment requirements */ 416 resource_size_t (*align_resource)(struct pci_dev *dev, 417 const struct resource *res, 418 resource_size_t start, 419 resource_size_t size, 420 resource_size_t align); 421 }; 422 423 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 424 425 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 426 427 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 428 void (*release_fn)(struct pci_host_bridge *), 429 void *release_data); 430 431 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 432 433 /* 434 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 435 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 436 * buses below host bridges or subtractive decode bridges) go in the list. 437 * Use pci_bus_for_each_resource() to iterate through all the resources. 438 */ 439 440 /* 441 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 442 * and there's no way to program the bridge with the details of the window. 443 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 444 * decode bit set, because they are explicit and can be programmed with _SRS. 445 */ 446 #define PCI_SUBTRACTIVE_DECODE 0x1 447 448 struct pci_bus_resource { 449 struct list_head list; 450 struct resource *res; 451 unsigned int flags; 452 }; 453 454 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 455 456 struct pci_bus { 457 struct list_head node; /* node in list of buses */ 458 struct pci_bus *parent; /* parent bus this bridge is on */ 459 struct list_head children; /* list of child buses */ 460 struct list_head devices; /* list of devices on this bus */ 461 struct pci_dev *self; /* bridge device as seen by parent */ 462 struct list_head slots; /* list of slots on this bus; 463 protected by pci_slot_mutex */ 464 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 465 struct list_head resources; /* address space routed to this bus */ 466 struct resource busn_res; /* bus numbers routed to this bus */ 467 468 struct pci_ops *ops; /* configuration access functions */ 469 struct msi_controller *msi; /* MSI controller */ 470 void *sysdata; /* hook for sys-specific extension */ 471 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 472 473 unsigned char number; /* bus number */ 474 unsigned char primary; /* number of primary bridge */ 475 unsigned char max_bus_speed; /* enum pci_bus_speed */ 476 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 477 #ifdef CONFIG_PCI_DOMAINS_GENERIC 478 int domain_nr; 479 #endif 480 481 char name[48]; 482 483 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 484 pci_bus_flags_t bus_flags; /* inherited by child buses */ 485 struct device *bridge; 486 struct device dev; 487 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 488 struct bin_attribute *legacy_mem; /* legacy mem */ 489 unsigned int is_added:1; 490 }; 491 492 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 493 494 /* 495 * Returns true if the PCI bus is root (behind host-PCI bridge), 496 * false otherwise 497 * 498 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 499 * This is incorrect because "virtual" buses added for SR-IOV (via 500 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 501 */ 502 static inline bool pci_is_root_bus(struct pci_bus *pbus) 503 { 504 return !(pbus->parent); 505 } 506 507 /** 508 * pci_is_bridge - check if the PCI device is a bridge 509 * @dev: PCI device 510 * 511 * Return true if the PCI device is bridge whether it has subordinate 512 * or not. 513 */ 514 static inline bool pci_is_bridge(struct pci_dev *dev) 515 { 516 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 517 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 518 } 519 520 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 521 { 522 dev = pci_physfn(dev); 523 if (pci_is_root_bus(dev->bus)) 524 return NULL; 525 526 return dev->bus->self; 527 } 528 529 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 530 void pci_put_host_bridge_device(struct device *dev); 531 532 #ifdef CONFIG_PCI_MSI 533 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 534 { 535 return pci_dev->msi_enabled || pci_dev->msix_enabled; 536 } 537 #else 538 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 539 #endif 540 541 /* 542 * Error values that may be returned by PCI functions. 543 */ 544 #define PCIBIOS_SUCCESSFUL 0x00 545 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 546 #define PCIBIOS_BAD_VENDOR_ID 0x83 547 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 548 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 549 #define PCIBIOS_SET_FAILED 0x88 550 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 551 552 /* 553 * Translate above to generic errno for passing back through non-PCI code. 554 */ 555 static inline int pcibios_err_to_errno(int err) 556 { 557 if (err <= PCIBIOS_SUCCESSFUL) 558 return err; /* Assume already errno */ 559 560 switch (err) { 561 case PCIBIOS_FUNC_NOT_SUPPORTED: 562 return -ENOENT; 563 case PCIBIOS_BAD_VENDOR_ID: 564 return -ENOTTY; 565 case PCIBIOS_DEVICE_NOT_FOUND: 566 return -ENODEV; 567 case PCIBIOS_BAD_REGISTER_NUMBER: 568 return -EFAULT; 569 case PCIBIOS_SET_FAILED: 570 return -EIO; 571 case PCIBIOS_BUFFER_TOO_SMALL: 572 return -ENOSPC; 573 } 574 575 return -ERANGE; 576 } 577 578 /* Low-level architecture-dependent routines */ 579 580 struct pci_ops { 581 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 582 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 583 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 584 }; 585 586 /* 587 * ACPI needs to be able to access PCI config space before we've done a 588 * PCI bus scan and created pci_bus structures. 589 */ 590 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 591 int reg, int len, u32 *val); 592 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 593 int reg, int len, u32 val); 594 595 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT 596 typedef u64 pci_bus_addr_t; 597 #else 598 typedef u32 pci_bus_addr_t; 599 #endif 600 601 struct pci_bus_region { 602 pci_bus_addr_t start; 603 pci_bus_addr_t end; 604 }; 605 606 struct pci_dynids { 607 spinlock_t lock; /* protects list, index */ 608 struct list_head list; /* for IDs added at runtime */ 609 }; 610 611 612 /* 613 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 614 * a set of callbacks in struct pci_error_handlers, that device driver 615 * will be notified of PCI bus errors, and will be driven to recovery 616 * when an error occurs. 617 */ 618 619 typedef unsigned int __bitwise pci_ers_result_t; 620 621 enum pci_ers_result { 622 /* no result/none/not supported in device driver */ 623 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 624 625 /* Device driver can recover without slot reset */ 626 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 627 628 /* Device driver wants slot to be reset. */ 629 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 630 631 /* Device has completely failed, is unrecoverable */ 632 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 633 634 /* Device driver is fully recovered and operational */ 635 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 636 637 /* No AER capabilities registered for the driver */ 638 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 639 }; 640 641 /* PCI bus error event callbacks */ 642 struct pci_error_handlers { 643 /* PCI bus error detected on this device */ 644 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 645 enum pci_channel_state error); 646 647 /* MMIO has been re-enabled, but not DMA */ 648 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 649 650 /* PCI Express link has been reset */ 651 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 652 653 /* PCI slot has been reset */ 654 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 655 656 /* PCI function reset prepare or completed */ 657 void (*reset_notify)(struct pci_dev *dev, bool prepare); 658 659 /* Device driver may resume normal operations */ 660 void (*resume)(struct pci_dev *dev); 661 }; 662 663 664 struct module; 665 struct pci_driver { 666 struct list_head node; 667 const char *name; 668 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 669 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 670 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 671 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 672 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 673 int (*resume_early) (struct pci_dev *dev); 674 int (*resume) (struct pci_dev *dev); /* Device woken up */ 675 void (*shutdown) (struct pci_dev *dev); 676 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 677 const struct pci_error_handlers *err_handler; 678 struct device_driver driver; 679 struct pci_dynids dynids; 680 }; 681 682 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 683 684 /** 685 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table 686 * @_table: device table name 687 * 688 * This macro is deprecated and should not be used in new code. 689 */ 690 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 691 const struct pci_device_id _table[] 692 693 /** 694 * PCI_DEVICE - macro used to describe a specific pci device 695 * @vend: the 16 bit PCI Vendor ID 696 * @dev: the 16 bit PCI Device ID 697 * 698 * This macro is used to create a struct pci_device_id that matches a 699 * specific device. The subvendor and subdevice fields will be set to 700 * PCI_ANY_ID. 701 */ 702 #define PCI_DEVICE(vend,dev) \ 703 .vendor = (vend), .device = (dev), \ 704 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 705 706 /** 707 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 708 * @vend: the 16 bit PCI Vendor ID 709 * @dev: the 16 bit PCI Device ID 710 * @subvend: the 16 bit PCI Subvendor ID 711 * @subdev: the 16 bit PCI Subdevice ID 712 * 713 * This macro is used to create a struct pci_device_id that matches a 714 * specific device with subsystem information. 715 */ 716 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 717 .vendor = (vend), .device = (dev), \ 718 .subvendor = (subvend), .subdevice = (subdev) 719 720 /** 721 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 722 * @dev_class: the class, subclass, prog-if triple for this device 723 * @dev_class_mask: the class mask for this device 724 * 725 * This macro is used to create a struct pci_device_id that matches a 726 * specific PCI class. The vendor, device, subvendor, and subdevice 727 * fields will be set to PCI_ANY_ID. 728 */ 729 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 730 .class = (dev_class), .class_mask = (dev_class_mask), \ 731 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 732 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 733 734 /** 735 * PCI_VDEVICE - macro used to describe a specific pci device in short form 736 * @vend: the vendor name 737 * @dev: the 16 bit PCI Device ID 738 * 739 * This macro is used to create a struct pci_device_id that matches a 740 * specific PCI device. The subvendor, and subdevice fields will be set 741 * to PCI_ANY_ID. The macro allows the next field to follow as the device 742 * private data. 743 */ 744 745 #define PCI_VDEVICE(vend, dev) \ 746 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 747 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 748 749 /* these external functions are only available when PCI support is enabled */ 750 #ifdef CONFIG_PCI 751 752 void pcie_bus_configure_settings(struct pci_bus *bus); 753 754 enum pcie_bus_config_types { 755 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 756 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 757 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 758 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 759 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 760 }; 761 762 extern enum pcie_bus_config_types pcie_bus_config; 763 764 extern struct bus_type pci_bus_type; 765 766 /* Do NOT directly access these two variables, unless you are arch-specific PCI 767 * code, or PCI core code. */ 768 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 769 /* Some device drivers need know if PCI is initiated */ 770 int no_pci_devices(void); 771 772 void pcibios_resource_survey_bus(struct pci_bus *bus); 773 void pcibios_add_bus(struct pci_bus *bus); 774 void pcibios_remove_bus(struct pci_bus *bus); 775 void pcibios_fixup_bus(struct pci_bus *); 776 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 777 /* Architecture-specific versions may override this (weak) */ 778 char *pcibios_setup(char *str); 779 780 /* Used only when drivers/pci/setup.c is used */ 781 resource_size_t pcibios_align_resource(void *, const struct resource *, 782 resource_size_t, 783 resource_size_t); 784 void pcibios_update_irq(struct pci_dev *, int irq); 785 786 /* Weak but can be overriden by arch */ 787 void pci_fixup_cardbus(struct pci_bus *); 788 789 /* Generic PCI functions used internally */ 790 791 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 792 struct resource *res); 793 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 794 struct pci_bus_region *region); 795 void pcibios_scan_specific_bus(int busn); 796 struct pci_bus *pci_find_bus(int domain, int busnr); 797 void pci_bus_add_devices(const struct pci_bus *bus); 798 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 799 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 800 struct pci_ops *ops, void *sysdata, 801 struct list_head *resources); 802 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 803 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 804 void pci_bus_release_busn_res(struct pci_bus *b); 805 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, 806 struct pci_ops *ops, void *sysdata, 807 struct list_head *resources, 808 struct msi_controller *msi); 809 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 810 struct pci_ops *ops, void *sysdata, 811 struct list_head *resources); 812 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 813 int busnr); 814 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 815 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 816 const char *name, 817 struct hotplug_slot *hotplug); 818 void pci_destroy_slot(struct pci_slot *slot); 819 #ifdef CONFIG_SYSFS 820 void pci_dev_assign_slot(struct pci_dev *dev); 821 #else 822 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 823 #endif 824 int pci_scan_slot(struct pci_bus *bus, int devfn); 825 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 826 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 827 unsigned int pci_scan_child_bus(struct pci_bus *bus); 828 void pci_bus_add_device(struct pci_dev *dev); 829 void pci_read_bridge_bases(struct pci_bus *child); 830 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 831 struct resource *res); 832 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); 833 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 834 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 835 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 836 struct pci_dev *pci_dev_get(struct pci_dev *dev); 837 void pci_dev_put(struct pci_dev *dev); 838 void pci_remove_bus(struct pci_bus *b); 839 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 840 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 841 void pci_stop_root_bus(struct pci_bus *bus); 842 void pci_remove_root_bus(struct pci_bus *bus); 843 void pci_setup_cardbus(struct pci_bus *bus); 844 void pci_sort_breadthfirst(void); 845 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 846 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 847 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) 848 849 /* Generic PCI functions exported to card drivers */ 850 851 enum pci_lost_interrupt_reason { 852 PCI_LOST_IRQ_NO_INFORMATION = 0, 853 PCI_LOST_IRQ_DISABLE_MSI, 854 PCI_LOST_IRQ_DISABLE_MSIX, 855 PCI_LOST_IRQ_DISABLE_ACPI, 856 }; 857 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); 858 int pci_find_capability(struct pci_dev *dev, int cap); 859 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 860 int pci_find_ext_capability(struct pci_dev *dev, int cap); 861 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); 862 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 863 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 864 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 865 866 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 867 struct pci_dev *from); 868 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 869 unsigned int ss_vendor, unsigned int ss_device, 870 struct pci_dev *from); 871 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 872 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 873 unsigned int devfn); 874 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 875 unsigned int devfn) 876 { 877 return pci_get_domain_bus_and_slot(0, bus, devfn); 878 } 879 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 880 int pci_dev_present(const struct pci_device_id *ids); 881 882 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 883 int where, u8 *val); 884 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 885 int where, u16 *val); 886 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 887 int where, u32 *val); 888 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 889 int where, u8 val); 890 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 891 int where, u16 val); 892 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 893 int where, u32 val); 894 895 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 896 int where, int size, u32 *val); 897 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 898 int where, int size, u32 val); 899 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 900 int where, int size, u32 *val); 901 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 902 int where, int size, u32 val); 903 904 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 905 906 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) 907 { 908 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); 909 } 910 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) 911 { 912 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); 913 } 914 static inline int pci_read_config_dword(const struct pci_dev *dev, int where, 915 u32 *val) 916 { 917 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); 918 } 919 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) 920 { 921 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); 922 } 923 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) 924 { 925 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); 926 } 927 static inline int pci_write_config_dword(const struct pci_dev *dev, int where, 928 u32 val) 929 { 930 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 931 } 932 933 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 934 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 935 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 936 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 937 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 938 u16 clear, u16 set); 939 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 940 u32 clear, u32 set); 941 942 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 943 u16 set) 944 { 945 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 946 } 947 948 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 949 u32 set) 950 { 951 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 952 } 953 954 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 955 u16 clear) 956 { 957 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 958 } 959 960 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 961 u32 clear) 962 { 963 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 964 } 965 966 /* user-space driven config access */ 967 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 968 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 969 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 970 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 971 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 972 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 973 974 int __must_check pci_enable_device(struct pci_dev *dev); 975 int __must_check pci_enable_device_io(struct pci_dev *dev); 976 int __must_check pci_enable_device_mem(struct pci_dev *dev); 977 int __must_check pci_reenable_device(struct pci_dev *); 978 int __must_check pcim_enable_device(struct pci_dev *pdev); 979 void pcim_pin_device(struct pci_dev *pdev); 980 981 static inline int pci_is_enabled(struct pci_dev *pdev) 982 { 983 return (atomic_read(&pdev->enable_cnt) > 0); 984 } 985 986 static inline int pci_is_managed(struct pci_dev *pdev) 987 { 988 return pdev->is_managed; 989 } 990 991 void pci_disable_device(struct pci_dev *dev); 992 993 extern unsigned int pcibios_max_latency; 994 void pci_set_master(struct pci_dev *dev); 995 void pci_clear_master(struct pci_dev *dev); 996 997 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 998 int pci_set_cacheline_size(struct pci_dev *dev); 999 #define HAVE_PCI_SET_MWI 1000 int __must_check pci_set_mwi(struct pci_dev *dev); 1001 int pci_try_set_mwi(struct pci_dev *dev); 1002 void pci_clear_mwi(struct pci_dev *dev); 1003 void pci_intx(struct pci_dev *dev, int enable); 1004 bool pci_intx_mask_supported(struct pci_dev *dev); 1005 bool pci_check_and_mask_intx(struct pci_dev *dev); 1006 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1007 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); 1008 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); 1009 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1010 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1011 int pcix_get_max_mmrbc(struct pci_dev *dev); 1012 int pcix_get_mmrbc(struct pci_dev *dev); 1013 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1014 int pcie_get_readrq(struct pci_dev *dev); 1015 int pcie_set_readrq(struct pci_dev *dev, int rq); 1016 int pcie_get_mps(struct pci_dev *dev); 1017 int pcie_set_mps(struct pci_dev *dev, int mps); 1018 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 1019 enum pcie_link_width *width); 1020 int __pci_reset_function(struct pci_dev *dev); 1021 int __pci_reset_function_locked(struct pci_dev *dev); 1022 int pci_reset_function(struct pci_dev *dev); 1023 int pci_try_reset_function(struct pci_dev *dev); 1024 int pci_probe_reset_slot(struct pci_slot *slot); 1025 int pci_reset_slot(struct pci_slot *slot); 1026 int pci_try_reset_slot(struct pci_slot *slot); 1027 int pci_probe_reset_bus(struct pci_bus *bus); 1028 int pci_reset_bus(struct pci_bus *bus); 1029 int pci_try_reset_bus(struct pci_bus *bus); 1030 void pci_reset_secondary_bus(struct pci_dev *dev); 1031 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1032 void pci_reset_bridge_secondary_bus(struct pci_dev *dev); 1033 void pci_update_resource(struct pci_dev *dev, int resno); 1034 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1035 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1036 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1037 bool pci_device_is_present(struct pci_dev *pdev); 1038 void pci_ignore_hotplug(struct pci_dev *dev); 1039 1040 /* ROM control related routines */ 1041 int pci_enable_rom(struct pci_dev *pdev); 1042 void pci_disable_rom(struct pci_dev *pdev); 1043 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1044 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1045 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); 1046 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); 1047 1048 /* Power management related routines */ 1049 int pci_save_state(struct pci_dev *dev); 1050 void pci_restore_state(struct pci_dev *dev); 1051 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1052 int pci_load_saved_state(struct pci_dev *dev, 1053 struct pci_saved_state *state); 1054 int pci_load_and_free_saved_state(struct pci_dev *dev, 1055 struct pci_saved_state **state); 1056 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 1057 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 1058 u16 cap); 1059 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 1060 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 1061 u16 cap, unsigned int size); 1062 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); 1063 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1064 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1065 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1066 void pci_pme_active(struct pci_dev *dev, bool enable); 1067 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1068 bool runtime, bool enable); 1069 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1070 int pci_prepare_to_sleep(struct pci_dev *dev); 1071 int pci_back_from_sleep(struct pci_dev *dev); 1072 bool pci_dev_run_wake(struct pci_dev *dev); 1073 bool pci_check_pme_status(struct pci_dev *dev); 1074 void pci_pme_wakeup_bus(struct pci_bus *bus); 1075 1076 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1077 bool enable) 1078 { 1079 return __pci_enable_wake(dev, state, false, enable); 1080 } 1081 1082 /* PCI Virtual Channel */ 1083 int pci_save_vc_state(struct pci_dev *dev); 1084 void pci_restore_vc_state(struct pci_dev *dev); 1085 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 1086 1087 /* For use by arch with custom probe code */ 1088 void set_pcie_port_type(struct pci_dev *pdev); 1089 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1090 1091 /* Functions for PCI Hotplug drivers to use */ 1092 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1093 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1094 unsigned int pci_rescan_bus(struct pci_bus *bus); 1095 void pci_lock_rescan_remove(void); 1096 void pci_unlock_rescan_remove(void); 1097 1098 /* Vital product data routines */ 1099 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1100 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1101 1102 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1103 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1104 void pci_bus_assign_resources(const struct pci_bus *bus); 1105 void pci_bus_size_bridges(struct pci_bus *bus); 1106 int pci_claim_resource(struct pci_dev *, int); 1107 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1108 void pci_assign_unassigned_resources(void); 1109 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1110 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1111 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1112 void pdev_enable_device(struct pci_dev *); 1113 int pci_enable_resources(struct pci_dev *, int mask); 1114 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 1115 int (*)(const struct pci_dev *, u8, u8)); 1116 #define HAVE_PCI_REQ_REGIONS 2 1117 int __must_check pci_request_regions(struct pci_dev *, const char *); 1118 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1119 void pci_release_regions(struct pci_dev *); 1120 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1121 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); 1122 void pci_release_region(struct pci_dev *, int); 1123 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1124 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1125 void pci_release_selected_regions(struct pci_dev *, int); 1126 1127 /* drivers/pci/bus.c */ 1128 struct pci_bus *pci_bus_get(struct pci_bus *bus); 1129 void pci_bus_put(struct pci_bus *bus); 1130 void pci_add_resource(struct list_head *resources, struct resource *res); 1131 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1132 resource_size_t offset); 1133 void pci_free_resource_list(struct list_head *resources); 1134 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); 1135 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1136 void pci_bus_remove_resources(struct pci_bus *bus); 1137 1138 #define pci_bus_for_each_resource(bus, res, i) \ 1139 for (i = 0; \ 1140 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1141 i++) 1142 1143 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1144 struct resource *res, resource_size_t size, 1145 resource_size_t align, resource_size_t min, 1146 unsigned long type_mask, 1147 resource_size_t (*alignf)(void *, 1148 const struct resource *, 1149 resource_size_t, 1150 resource_size_t), 1151 void *alignf_data); 1152 1153 1154 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1155 1156 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1157 { 1158 struct pci_bus_region region; 1159 1160 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1161 return region.start; 1162 } 1163 1164 /* Proper probing supporting hot-pluggable devices */ 1165 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1166 const char *mod_name); 1167 1168 /* 1169 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded 1170 */ 1171 #define pci_register_driver(driver) \ 1172 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1173 1174 void pci_unregister_driver(struct pci_driver *dev); 1175 1176 /** 1177 * module_pci_driver() - Helper macro for registering a PCI driver 1178 * @__pci_driver: pci_driver struct 1179 * 1180 * Helper macro for PCI drivers which do not do anything special in module 1181 * init/exit. This eliminates a lot of boilerplate. Each module may only 1182 * use this macro once, and calling it replaces module_init() and module_exit() 1183 */ 1184 #define module_pci_driver(__pci_driver) \ 1185 module_driver(__pci_driver, pci_register_driver, \ 1186 pci_unregister_driver) 1187 1188 /** 1189 * builtin_pci_driver() - Helper macro for registering a PCI driver 1190 * @__pci_driver: pci_driver struct 1191 * 1192 * Helper macro for PCI drivers which do not do anything special in their 1193 * init code. This eliminates a lot of boilerplate. Each driver may only 1194 * use this macro once, and calling it replaces device_initcall(...) 1195 */ 1196 #define builtin_pci_driver(__pci_driver) \ 1197 builtin_driver(__pci_driver, pci_register_driver) 1198 1199 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1200 int pci_add_dynid(struct pci_driver *drv, 1201 unsigned int vendor, unsigned int device, 1202 unsigned int subvendor, unsigned int subdevice, 1203 unsigned int class, unsigned int class_mask, 1204 unsigned long driver_data); 1205 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1206 struct pci_dev *dev); 1207 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1208 int pass); 1209 1210 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1211 void *userdata); 1212 int pci_cfg_space_size(struct pci_dev *dev); 1213 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1214 void pci_setup_bridge(struct pci_bus *bus); 1215 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1216 unsigned long type); 1217 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 1218 1219 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1220 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1221 1222 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1223 unsigned int command_bits, u32 flags); 1224 /* kmem_cache style wrapper around pci_alloc_consistent() */ 1225 1226 #include <linux/pci-dma.h> 1227 #include <linux/dmapool.h> 1228 1229 #define pci_pool dma_pool 1230 #define pci_pool_create(name, pdev, size, align, allocation) \ 1231 dma_pool_create(name, &pdev->dev, size, align, allocation) 1232 #define pci_pool_destroy(pool) dma_pool_destroy(pool) 1233 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) 1234 #define pci_pool_zalloc(pool, flags, handle) \ 1235 dma_pool_zalloc(pool, flags, handle) 1236 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1237 1238 struct msix_entry { 1239 u32 vector; /* kernel uses to write allocated vector */ 1240 u16 entry; /* driver uses to specify entry, OS writes */ 1241 }; 1242 1243 #ifdef CONFIG_PCI_MSI 1244 int pci_msi_vec_count(struct pci_dev *dev); 1245 void pci_msi_shutdown(struct pci_dev *dev); 1246 void pci_disable_msi(struct pci_dev *dev); 1247 int pci_msix_vec_count(struct pci_dev *dev); 1248 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); 1249 void pci_msix_shutdown(struct pci_dev *dev); 1250 void pci_disable_msix(struct pci_dev *dev); 1251 void pci_restore_msi_state(struct pci_dev *dev); 1252 int pci_msi_enabled(void); 1253 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); 1254 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1255 { 1256 int rc = pci_enable_msi_range(dev, nvec, nvec); 1257 if (rc < 0) 1258 return rc; 1259 return 0; 1260 } 1261 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1262 int minvec, int maxvec); 1263 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1264 struct msix_entry *entries, int nvec) 1265 { 1266 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1267 if (rc < 0) 1268 return rc; 1269 return 0; 1270 } 1271 #else 1272 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1273 static inline void pci_msi_shutdown(struct pci_dev *dev) { } 1274 static inline void pci_disable_msi(struct pci_dev *dev) { } 1275 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1276 static inline int pci_enable_msix(struct pci_dev *dev, 1277 struct msix_entry *entries, int nvec) 1278 { return -ENOSYS; } 1279 static inline void pci_msix_shutdown(struct pci_dev *dev) { } 1280 static inline void pci_disable_msix(struct pci_dev *dev) { } 1281 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1282 static inline int pci_msi_enabled(void) { return 0; } 1283 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, 1284 int maxvec) 1285 { return -ENOSYS; } 1286 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) 1287 { return -ENOSYS; } 1288 static inline int pci_enable_msix_range(struct pci_dev *dev, 1289 struct msix_entry *entries, int minvec, int maxvec) 1290 { return -ENOSYS; } 1291 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1292 struct msix_entry *entries, int nvec) 1293 { return -ENOSYS; } 1294 #endif 1295 1296 #ifdef CONFIG_PCIEPORTBUS 1297 extern bool pcie_ports_disabled; 1298 extern bool pcie_ports_auto; 1299 #else 1300 #define pcie_ports_disabled true 1301 #define pcie_ports_auto false 1302 #endif 1303 1304 #ifdef CONFIG_PCIEASPM 1305 bool pcie_aspm_support_enabled(void); 1306 #else 1307 static inline bool pcie_aspm_support_enabled(void) { return false; } 1308 #endif 1309 1310 #ifdef CONFIG_PCIEAER 1311 void pci_no_aer(void); 1312 bool pci_aer_available(void); 1313 #else 1314 static inline void pci_no_aer(void) { } 1315 static inline bool pci_aer_available(void) { return false; } 1316 #endif 1317 1318 #ifdef CONFIG_PCIE_ECRC 1319 void pcie_set_ecrc_checking(struct pci_dev *dev); 1320 void pcie_ecrc_get_policy(char *str); 1321 #else 1322 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1323 static inline void pcie_ecrc_get_policy(char *str) { } 1324 #endif 1325 1326 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) 1327 1328 #ifdef CONFIG_HT_IRQ 1329 /* The functions a driver should call */ 1330 int ht_create_irq(struct pci_dev *dev, int idx); 1331 void ht_destroy_irq(unsigned int irq); 1332 #endif /* CONFIG_HT_IRQ */ 1333 1334 #ifdef CONFIG_PCI_ATS 1335 /* Address Translation Service */ 1336 void pci_ats_init(struct pci_dev *dev); 1337 int pci_enable_ats(struct pci_dev *dev, int ps); 1338 void pci_disable_ats(struct pci_dev *dev); 1339 int pci_ats_queue_depth(struct pci_dev *dev); 1340 #else 1341 static inline void pci_ats_init(struct pci_dev *d) { } 1342 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } 1343 static inline void pci_disable_ats(struct pci_dev *d) { } 1344 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } 1345 #endif 1346 1347 void pci_cfg_access_lock(struct pci_dev *dev); 1348 bool pci_cfg_access_trylock(struct pci_dev *dev); 1349 void pci_cfg_access_unlock(struct pci_dev *dev); 1350 1351 /* 1352 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1353 * a PCI domain is defined to be a set of PCI buses which share 1354 * configuration space. 1355 */ 1356 #ifdef CONFIG_PCI_DOMAINS 1357 extern int pci_domains_supported; 1358 int pci_get_new_domain_nr(void); 1359 #else 1360 enum { pci_domains_supported = 0 }; 1361 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1362 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1363 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1364 #endif /* CONFIG_PCI_DOMAINS */ 1365 1366 /* 1367 * Generic implementation for PCI domain support. If your 1368 * architecture does not need custom management of PCI 1369 * domains then this implementation will be used 1370 */ 1371 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1372 static inline int pci_domain_nr(struct pci_bus *bus) 1373 { 1374 return bus->domain_nr; 1375 } 1376 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); 1377 #else 1378 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, 1379 struct device *parent) 1380 { 1381 } 1382 #endif 1383 1384 /* some architectures require additional setup to direct VGA traffic */ 1385 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1386 unsigned int command_bits, u32 flags); 1387 void pci_register_set_vga_state(arch_set_vga_state_t func); 1388 1389 #else /* CONFIG_PCI is not enabled */ 1390 1391 /* 1392 * If the system does not have PCI, clearly these return errors. Define 1393 * these as simple inline functions to avoid hair in drivers. 1394 */ 1395 1396 #define _PCI_NOP(o, s, t) \ 1397 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1398 int where, t val) \ 1399 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1400 1401 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1402 _PCI_NOP(o, word, u16 x) \ 1403 _PCI_NOP(o, dword, u32 x) 1404 _PCI_NOP_ALL(read, *) 1405 _PCI_NOP_ALL(write,) 1406 1407 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1408 unsigned int device, 1409 struct pci_dev *from) 1410 { return NULL; } 1411 1412 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1413 unsigned int device, 1414 unsigned int ss_vendor, 1415 unsigned int ss_device, 1416 struct pci_dev *from) 1417 { return NULL; } 1418 1419 static inline struct pci_dev *pci_get_class(unsigned int class, 1420 struct pci_dev *from) 1421 { return NULL; } 1422 1423 #define pci_dev_present(ids) (0) 1424 #define no_pci_devices() (1) 1425 #define pci_dev_put(dev) do { } while (0) 1426 1427 static inline void pci_set_master(struct pci_dev *dev) { } 1428 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1429 static inline void pci_disable_device(struct pci_dev *dev) { } 1430 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) 1431 { return -EIO; } 1432 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 1433 { return -EIO; } 1434 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, 1435 unsigned int size) 1436 { return -EIO; } 1437 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, 1438 unsigned long mask) 1439 { return -EIO; } 1440 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1441 { return -EBUSY; } 1442 static inline int __pci_register_driver(struct pci_driver *drv, 1443 struct module *owner) 1444 { return 0; } 1445 static inline int pci_register_driver(struct pci_driver *drv) 1446 { return 0; } 1447 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1448 static inline int pci_find_capability(struct pci_dev *dev, int cap) 1449 { return 0; } 1450 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1451 int cap) 1452 { return 0; } 1453 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1454 { return 0; } 1455 1456 /* Power management related routines */ 1457 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1458 static inline void pci_restore_state(struct pci_dev *dev) { } 1459 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1460 { return 0; } 1461 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1462 { return 0; } 1463 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1464 pm_message_t state) 1465 { return PCI_D0; } 1466 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1467 int enable) 1468 { return 0; } 1469 1470 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1471 { return -EIO; } 1472 static inline void pci_release_regions(struct pci_dev *dev) { } 1473 1474 static inline void pci_block_cfg_access(struct pci_dev *dev) { } 1475 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) 1476 { return 0; } 1477 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } 1478 1479 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1480 { return NULL; } 1481 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1482 unsigned int devfn) 1483 { return NULL; } 1484 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, 1485 unsigned int devfn) 1486 { return NULL; } 1487 1488 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1489 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1490 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } 1491 1492 #define dev_is_pci(d) (false) 1493 #define dev_is_pf(d) (false) 1494 #define dev_num_vf(d) (0) 1495 #endif /* CONFIG_PCI */ 1496 1497 /* Include architecture-dependent settings and functions */ 1498 1499 #include <asm/pci.h> 1500 1501 /* these helpers provide future and backwards compatibility 1502 * for accessing popular PCI BAR info */ 1503 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1504 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1505 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1506 #define pci_resource_len(dev,bar) \ 1507 ((pci_resource_start((dev), (bar)) == 0 && \ 1508 pci_resource_end((dev), (bar)) == \ 1509 pci_resource_start((dev), (bar))) ? 0 : \ 1510 \ 1511 (pci_resource_end((dev), (bar)) - \ 1512 pci_resource_start((dev), (bar)) + 1)) 1513 1514 /* Similar to the helpers above, these manipulate per-pci_dev 1515 * driver-specific data. They are really just a wrapper around 1516 * the generic device structure functions of these calls. 1517 */ 1518 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1519 { 1520 return dev_get_drvdata(&pdev->dev); 1521 } 1522 1523 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1524 { 1525 dev_set_drvdata(&pdev->dev, data); 1526 } 1527 1528 /* If you want to know what to call your pci_dev, ask this function. 1529 * Again, it's a wrapper around the generic device. 1530 */ 1531 static inline const char *pci_name(const struct pci_dev *pdev) 1532 { 1533 return dev_name(&pdev->dev); 1534 } 1535 1536 1537 /* Some archs don't want to expose struct resource to userland as-is 1538 * in sysfs and /proc 1539 */ 1540 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER 1541 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 1542 const struct resource *rsrc, resource_size_t *start, 1543 resource_size_t *end) 1544 { 1545 *start = rsrc->start; 1546 *end = rsrc->end; 1547 } 1548 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ 1549 1550 1551 /* 1552 * The world is not perfect and supplies us with broken PCI devices. 1553 * For at least a part of these bugs we need a work-around, so both 1554 * generic (drivers/pci/quirks.c) and per-architecture code can define 1555 * fixup hooks to be called for particular buggy devices. 1556 */ 1557 1558 struct pci_fixup { 1559 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1560 u16 device; /* You can use PCI_ANY_ID here of course */ 1561 u32 class; /* You can use PCI_ANY_ID here too */ 1562 unsigned int class_shift; /* should be 0, 8, 16 */ 1563 void (*hook)(struct pci_dev *dev); 1564 }; 1565 1566 enum pci_fixup_pass { 1567 pci_fixup_early, /* Before probing BARs */ 1568 pci_fixup_header, /* After reading configuration header */ 1569 pci_fixup_final, /* Final phase of device fixups */ 1570 pci_fixup_enable, /* pci_enable_device() time */ 1571 pci_fixup_resume, /* pci_device_resume() */ 1572 pci_fixup_suspend, /* pci_device_suspend() */ 1573 pci_fixup_resume_early, /* pci_device_resume_early() */ 1574 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 1575 }; 1576 1577 /* Anonymous variables would be nice... */ 1578 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 1579 class_shift, hook) \ 1580 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 1581 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 1582 = { vendor, device, class, class_shift, hook }; 1583 1584 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 1585 class_shift, hook) \ 1586 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1587 hook, vendor, device, class, class_shift, hook) 1588 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 1589 class_shift, hook) \ 1590 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1591 hook, vendor, device, class, class_shift, hook) 1592 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 1593 class_shift, hook) \ 1594 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1595 hook, vendor, device, class, class_shift, hook) 1596 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 1597 class_shift, hook) \ 1598 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1599 hook, vendor, device, class, class_shift, hook) 1600 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1601 class_shift, hook) \ 1602 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1603 resume##hook, vendor, device, class, \ 1604 class_shift, hook) 1605 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1606 class_shift, hook) \ 1607 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1608 resume_early##hook, vendor, device, \ 1609 class, class_shift, hook) 1610 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1611 class_shift, hook) \ 1612 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1613 suspend##hook, vendor, device, class, \ 1614 class_shift, hook) 1615 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1616 class_shift, hook) \ 1617 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1618 suspend_late##hook, vendor, device, \ 1619 class, class_shift, hook) 1620 1621 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1622 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1623 hook, vendor, device, PCI_ANY_ID, 0, hook) 1624 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 1625 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 1626 hook, vendor, device, PCI_ANY_ID, 0, hook) 1627 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 1628 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 1629 hook, vendor, device, PCI_ANY_ID, 0, hook) 1630 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 1631 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 1632 hook, vendor, device, PCI_ANY_ID, 0, hook) 1633 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1634 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1635 resume##hook, vendor, device, \ 1636 PCI_ANY_ID, 0, hook) 1637 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1638 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1639 resume_early##hook, vendor, device, \ 1640 PCI_ANY_ID, 0, hook) 1641 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1642 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1643 suspend##hook, vendor, device, \ 1644 PCI_ANY_ID, 0, hook) 1645 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1646 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1647 suspend_late##hook, vendor, device, \ 1648 PCI_ANY_ID, 0, hook) 1649 1650 #ifdef CONFIG_PCI_QUIRKS 1651 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1652 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1653 void pci_dev_specific_enable_acs(struct pci_dev *dev); 1654 #else 1655 static inline void pci_fixup_device(enum pci_fixup_pass pass, 1656 struct pci_dev *dev) { } 1657 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1658 u16 acs_flags) 1659 { 1660 return -ENOTTY; 1661 } 1662 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } 1663 #endif 1664 1665 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1666 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 1667 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 1668 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 1669 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 1670 const char *name); 1671 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 1672 1673 extern int pci_pci_problems; 1674 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 1675 #define PCIPCI_TRITON 2 1676 #define PCIPCI_NATOMA 4 1677 #define PCIPCI_VIAETBF 8 1678 #define PCIPCI_VSFX 16 1679 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 1680 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 1681 1682 extern unsigned long pci_cardbus_io_size; 1683 extern unsigned long pci_cardbus_mem_size; 1684 extern u8 pci_dfl_cache_line_size; 1685 extern u8 pci_cache_line_size; 1686 1687 extern unsigned long pci_hotplug_io_size; 1688 extern unsigned long pci_hotplug_mem_size; 1689 1690 /* Architecture-specific versions may override these (weak) */ 1691 void pcibios_disable_device(struct pci_dev *dev); 1692 void pcibios_set_master(struct pci_dev *dev); 1693 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 1694 enum pcie_reset_state state); 1695 int pcibios_add_device(struct pci_dev *dev); 1696 void pcibios_release_device(struct pci_dev *dev); 1697 void pcibios_penalize_isa_irq(int irq, int active); 1698 int pcibios_alloc_irq(struct pci_dev *dev); 1699 void pcibios_free_irq(struct pci_dev *dev); 1700 1701 #ifdef CONFIG_HIBERNATE_CALLBACKS 1702 extern struct dev_pm_ops pcibios_pm_ops; 1703 #endif 1704 1705 #ifdef CONFIG_PCI_MMCONFIG 1706 void __init pci_mmcfg_early_init(void); 1707 void __init pci_mmcfg_late_init(void); 1708 #else 1709 static inline void pci_mmcfg_early_init(void) { } 1710 static inline void pci_mmcfg_late_init(void) { } 1711 #endif 1712 1713 int pci_ext_cfg_avail(void); 1714 1715 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 1716 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 1717 1718 #ifdef CONFIG_PCI_IOV 1719 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 1720 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 1721 1722 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 1723 void pci_disable_sriov(struct pci_dev *dev); 1724 int pci_num_vf(struct pci_dev *dev); 1725 int pci_vfs_assigned(struct pci_dev *dev); 1726 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 1727 int pci_sriov_get_totalvfs(struct pci_dev *dev); 1728 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 1729 #else 1730 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 1731 { 1732 return -ENOSYS; 1733 } 1734 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 1735 { 1736 return -ENOSYS; 1737 } 1738 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 1739 { return -ENODEV; } 1740 static inline void pci_disable_sriov(struct pci_dev *dev) { } 1741 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 1742 static inline int pci_vfs_assigned(struct pci_dev *dev) 1743 { return 0; } 1744 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 1745 { return 0; } 1746 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 1747 { return 0; } 1748 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 1749 { return 0; } 1750 #endif 1751 1752 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 1753 void pci_hp_create_module_link(struct pci_slot *pci_slot); 1754 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 1755 #endif 1756 1757 /** 1758 * pci_pcie_cap - get the saved PCIe capability offset 1759 * @dev: PCI device 1760 * 1761 * PCIe capability offset is calculated at PCI device initialization 1762 * time and saved in the data structure. This function returns saved 1763 * PCIe capability offset. Using this instead of pci_find_capability() 1764 * reduces unnecessary search in the PCI configuration space. If you 1765 * need to calculate PCIe capability offset from raw device for some 1766 * reasons, please use pci_find_capability() instead. 1767 */ 1768 static inline int pci_pcie_cap(struct pci_dev *dev) 1769 { 1770 return dev->pcie_cap; 1771 } 1772 1773 /** 1774 * pci_is_pcie - check if the PCI device is PCI Express capable 1775 * @dev: PCI device 1776 * 1777 * Returns: true if the PCI device is PCI Express capable, false otherwise. 1778 */ 1779 static inline bool pci_is_pcie(struct pci_dev *dev) 1780 { 1781 return pci_pcie_cap(dev); 1782 } 1783 1784 /** 1785 * pcie_caps_reg - get the PCIe Capabilities Register 1786 * @dev: PCI device 1787 */ 1788 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 1789 { 1790 return dev->pcie_flags_reg; 1791 } 1792 1793 /** 1794 * pci_pcie_type - get the PCIe device/port type 1795 * @dev: PCI device 1796 */ 1797 static inline int pci_pcie_type(const struct pci_dev *dev) 1798 { 1799 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1800 } 1801 1802 void pci_request_acs(void); 1803 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 1804 bool pci_acs_path_enabled(struct pci_dev *start, 1805 struct pci_dev *end, u16 acs_flags); 1806 1807 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1808 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 1809 1810 /* Large Resource Data Type Tag Item Names */ 1811 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 1812 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 1813 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 1814 1815 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 1816 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 1817 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 1818 1819 /* Small Resource Data Type Tag Item Names */ 1820 #define PCI_VPD_STIN_END 0x78 /* End */ 1821 1822 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END 1823 1824 #define PCI_VPD_SRDT_TIN_MASK 0x78 1825 #define PCI_VPD_SRDT_LEN_MASK 0x07 1826 1827 #define PCI_VPD_LRDT_TAG_SIZE 3 1828 #define PCI_VPD_SRDT_TAG_SIZE 1 1829 1830 #define PCI_VPD_INFO_FLD_HDR_SIZE 3 1831 1832 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 1833 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 1834 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 1835 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 1836 1837 /** 1838 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length 1839 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag 1840 * 1841 * Returns the extracted Large Resource Data Type length. 1842 */ 1843 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) 1844 { 1845 return (u16)lrdt[1] + ((u16)lrdt[2] << 8); 1846 } 1847 1848 /** 1849 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length 1850 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag 1851 * 1852 * Returns the extracted Small Resource Data Type length. 1853 */ 1854 static inline u8 pci_vpd_srdt_size(const u8 *srdt) 1855 { 1856 return (*srdt) & PCI_VPD_SRDT_LEN_MASK; 1857 } 1858 1859 /** 1860 * pci_vpd_info_field_size - Extracts the information field length 1861 * @lrdt: Pointer to the beginning of an information field header 1862 * 1863 * Returns the extracted information field length. 1864 */ 1865 static inline u8 pci_vpd_info_field_size(const u8 *info_field) 1866 { 1867 return info_field[2]; 1868 } 1869 1870 /** 1871 * pci_vpd_find_tag - Locates the Resource Data Type tag provided 1872 * @buf: Pointer to buffered vpd data 1873 * @off: The offset into the buffer at which to begin the search 1874 * @len: The length of the vpd buffer 1875 * @rdt: The Resource Data Type to search for 1876 * 1877 * Returns the index where the Resource Data Type was found or 1878 * -ENOENT otherwise. 1879 */ 1880 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); 1881 1882 /** 1883 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD 1884 * @buf: Pointer to buffered vpd data 1885 * @off: The offset into the buffer at which to begin the search 1886 * @len: The length of the buffer area, relative to off, in which to search 1887 * @kw: The keyword to search for 1888 * 1889 * Returns the index where the information field keyword was found or 1890 * -ENOENT otherwise. 1891 */ 1892 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, 1893 unsigned int len, const char *kw); 1894 1895 /* PCI <-> OF binding helpers */ 1896 #ifdef CONFIG_OF 1897 struct device_node; 1898 struct irq_domain; 1899 void pci_set_of_node(struct pci_dev *dev); 1900 void pci_release_of_node(struct pci_dev *dev); 1901 void pci_set_bus_of_node(struct pci_bus *bus); 1902 void pci_release_bus_of_node(struct pci_bus *bus); 1903 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 1904 1905 /* Arch may override this (weak) */ 1906 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 1907 1908 static inline struct device_node * 1909 pci_device_to_OF_node(const struct pci_dev *pdev) 1910 { 1911 return pdev ? pdev->dev.of_node : NULL; 1912 } 1913 1914 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 1915 { 1916 return bus ? bus->dev.of_node : NULL; 1917 } 1918 1919 #else /* CONFIG_OF */ 1920 static inline void pci_set_of_node(struct pci_dev *dev) { } 1921 static inline void pci_release_of_node(struct pci_dev *dev) { } 1922 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1923 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1924 static inline struct device_node * 1925 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 1926 static inline struct irq_domain * 1927 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 1928 #endif /* CONFIG_OF */ 1929 1930 #ifdef CONFIG_ACPI 1931 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 1932 1933 void 1934 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 1935 #else 1936 static inline struct irq_domain * 1937 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 1938 #endif 1939 1940 #ifdef CONFIG_EEH 1941 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 1942 { 1943 return pdev->dev.archdata.edev; 1944 } 1945 #endif 1946 1947 int pci_for_each_dma_alias(struct pci_dev *pdev, 1948 int (*fn)(struct pci_dev *pdev, 1949 u16 alias, void *data), void *data); 1950 1951 /* helper functions for operation of device flag */ 1952 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 1953 { 1954 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 1955 } 1956 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 1957 { 1958 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 1959 } 1960 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 1961 { 1962 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 1963 } 1964 1965 /** 1966 * pci_ari_enabled - query ARI forwarding status 1967 * @bus: the PCI bus 1968 * 1969 * Returns true if ARI forwarding is enabled. 1970 */ 1971 static inline bool pci_ari_enabled(struct pci_bus *bus) 1972 { 1973 return bus->self && bus->self->ari_enabled; 1974 } 1975 #endif /* LINUX_PCI_H */ 1976