1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PCI Endpoint *Controller* (EPC) header file 4 * 5 * Copyright (C) 2017 Texas Instruments 6 * Author: Kishon Vijay Abraham I <[email protected]> 7 */ 8 9 #ifndef __LINUX_PCI_EPC_H 10 #define __LINUX_PCI_EPC_H 11 12 #include <linux/pci-epf.h> 13 14 struct pci_epc; 15 16 enum pci_epc_interface_type { 17 UNKNOWN_INTERFACE = -1, 18 PRIMARY_INTERFACE, 19 SECONDARY_INTERFACE, 20 }; 21 22 enum pci_epc_irq_type { 23 PCI_EPC_IRQ_UNKNOWN, 24 PCI_EPC_IRQ_LEGACY, 25 PCI_EPC_IRQ_MSI, 26 PCI_EPC_IRQ_MSIX, 27 }; 28 29 static inline const char * 30 pci_epc_interface_string(enum pci_epc_interface_type type) 31 { 32 switch (type) { 33 case PRIMARY_INTERFACE: 34 return "primary"; 35 case SECONDARY_INTERFACE: 36 return "secondary"; 37 default: 38 return "UNKNOWN interface"; 39 } 40 } 41 42 /** 43 * struct pci_epc_ops - set of function pointers for performing EPC operations 44 * @write_header: ops to populate configuration space header 45 * @set_bar: ops to configure the BAR 46 * @clear_bar: ops to reset the BAR 47 * @map_addr: ops to map CPU address to PCI address 48 * @unmap_addr: ops to unmap CPU address and PCI address 49 * @set_msi: ops to set the requested number of MSI interrupts in the MSI 50 * capability register 51 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from 52 * the MSI capability register 53 * @set_msix: ops to set the requested number of MSI-X interrupts in the 54 * MSI-X capability register 55 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC 56 * from the MSI-X capability register 57 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt 58 * @map_msi_irq: ops to map physical address to MSI address and return MSI data 59 * @start: ops to start the PCI link 60 * @stop: ops to stop the PCI link 61 * @get_features: ops to get the features supported by the EPC 62 * @owner: the module owner containing the ops 63 */ 64 struct pci_epc_ops { 65 int (*write_header)(struct pci_epc *epc, u8 func_no, 66 struct pci_epf_header *hdr); 67 int (*set_bar)(struct pci_epc *epc, u8 func_no, 68 struct pci_epf_bar *epf_bar); 69 void (*clear_bar)(struct pci_epc *epc, u8 func_no, 70 struct pci_epf_bar *epf_bar); 71 int (*map_addr)(struct pci_epc *epc, u8 func_no, 72 phys_addr_t addr, u64 pci_addr, size_t size); 73 void (*unmap_addr)(struct pci_epc *epc, u8 func_no, 74 phys_addr_t addr); 75 int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts); 76 int (*get_msi)(struct pci_epc *epc, u8 func_no); 77 int (*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts, 78 enum pci_barno, u32 offset); 79 int (*get_msix)(struct pci_epc *epc, u8 func_no); 80 int (*raise_irq)(struct pci_epc *epc, u8 func_no, 81 enum pci_epc_irq_type type, u16 interrupt_num); 82 int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, 83 phys_addr_t phys_addr, u8 interrupt_num, 84 u32 entry_size, u32 *msi_data, 85 u32 *msi_addr_offset); 86 int (*start)(struct pci_epc *epc); 87 void (*stop)(struct pci_epc *epc); 88 const struct pci_epc_features* (*get_features)(struct pci_epc *epc, 89 u8 func_no); 90 struct module *owner; 91 }; 92 93 /** 94 * struct pci_epc_mem_window - address window of the endpoint controller 95 * @phys_base: physical base address of the PCI address window 96 * @size: the size of the PCI address window 97 * @page_size: size of each page 98 */ 99 struct pci_epc_mem_window { 100 phys_addr_t phys_base; 101 size_t size; 102 size_t page_size; 103 }; 104 105 /** 106 * struct pci_epc_mem - address space of the endpoint controller 107 * @window: address window of the endpoint controller 108 * @bitmap: bitmap to manage the PCI address space 109 * @pages: number of bits representing the address region 110 * @lock: mutex to protect bitmap 111 */ 112 struct pci_epc_mem { 113 struct pci_epc_mem_window window; 114 unsigned long *bitmap; 115 int pages; 116 /* mutex to protect against concurrent access for memory allocation*/ 117 struct mutex lock; 118 }; 119 120 /** 121 * struct pci_epc - represents the PCI EPC device 122 * @dev: PCI EPC device 123 * @pci_epf: list of endpoint functions present in this EPC device 124 * @ops: function pointers for performing endpoint operations 125 * @windows: array of address space of the endpoint controller 126 * @mem: first window of the endpoint controller, which corresponds to 127 * default address space of the endpoint controller supporting 128 * single window. 129 * @num_windows: number of windows supported by device 130 * @max_functions: max number of functions that can be configured in this EPC 131 * @group: configfs group representing the PCI EPC device 132 * @lock: mutex to protect pci_epc ops 133 * @function_num_map: bitmap to manage physical function number 134 * @notifier: used to notify EPF of any EPC events (like linkup) 135 */ 136 struct pci_epc { 137 struct device dev; 138 struct list_head pci_epf; 139 const struct pci_epc_ops *ops; 140 struct pci_epc_mem **windows; 141 struct pci_epc_mem *mem; 142 unsigned int num_windows; 143 u8 max_functions; 144 struct config_group *group; 145 /* mutex to protect against concurrent access of EP controller */ 146 struct mutex lock; 147 unsigned long function_num_map; 148 struct atomic_notifier_head notifier; 149 }; 150 151 /** 152 * struct pci_epc_features - features supported by a EPC device per function 153 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up 154 * @core_init_notifier: indicate cores that can notify about their availability 155 * for initialization 156 * @msi_capable: indicate if the endpoint function has MSI capability 157 * @msix_capable: indicate if the endpoint function has MSI-X capability 158 * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver 159 * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs 160 * @bar_fixed_size: Array specifying the size supported by each BAR 161 * @align: alignment size required for BAR buffer allocation 162 */ 163 struct pci_epc_features { 164 unsigned int linkup_notifier : 1; 165 unsigned int core_init_notifier : 1; 166 unsigned int msi_capable : 1; 167 unsigned int msix_capable : 1; 168 u8 reserved_bar; 169 u8 bar_fixed_64bit; 170 u64 bar_fixed_size[PCI_STD_NUM_BARS]; 171 size_t align; 172 }; 173 174 #define to_pci_epc(device) container_of((device), struct pci_epc, dev) 175 176 #define pci_epc_create(dev, ops) \ 177 __pci_epc_create((dev), (ops), THIS_MODULE) 178 #define devm_pci_epc_create(dev, ops) \ 179 __devm_pci_epc_create((dev), (ops), THIS_MODULE) 180 181 static inline void epc_set_drvdata(struct pci_epc *epc, void *data) 182 { 183 dev_set_drvdata(&epc->dev, data); 184 } 185 186 static inline void *epc_get_drvdata(struct pci_epc *epc) 187 { 188 return dev_get_drvdata(&epc->dev); 189 } 190 191 static inline int 192 pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb) 193 { 194 return atomic_notifier_chain_register(&epc->notifier, nb); 195 } 196 197 struct pci_epc * 198 __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, 199 struct module *owner); 200 struct pci_epc * 201 __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, 202 struct module *owner); 203 void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc); 204 void pci_epc_destroy(struct pci_epc *epc); 205 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, 206 enum pci_epc_interface_type type); 207 void pci_epc_linkup(struct pci_epc *epc); 208 void pci_epc_init_notify(struct pci_epc *epc); 209 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, 210 enum pci_epc_interface_type type); 211 int pci_epc_write_header(struct pci_epc *epc, u8 func_no, 212 struct pci_epf_header *hdr); 213 int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, 214 struct pci_epf_bar *epf_bar); 215 void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, 216 struct pci_epf_bar *epf_bar); 217 int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, 218 phys_addr_t phys_addr, 219 u64 pci_addr, size_t size); 220 void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, 221 phys_addr_t phys_addr); 222 int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts); 223 int pci_epc_get_msi(struct pci_epc *epc, u8 func_no); 224 int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts, 225 enum pci_barno, u32 offset); 226 int pci_epc_get_msix(struct pci_epc *epc, u8 func_no); 227 int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, 228 phys_addr_t phys_addr, u8 interrupt_num, 229 u32 entry_size, u32 *msi_data, u32 *msi_addr_offset); 230 int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, 231 enum pci_epc_irq_type type, u16 interrupt_num); 232 int pci_epc_start(struct pci_epc *epc); 233 void pci_epc_stop(struct pci_epc *epc); 234 const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, 235 u8 func_no); 236 enum pci_barno 237 pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); 238 enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features 239 *epc_features, enum pci_barno bar); 240 struct pci_epc *pci_epc_get(const char *epc_name); 241 void pci_epc_put(struct pci_epc *epc); 242 243 int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base, 244 size_t size, size_t page_size); 245 int pci_epc_multi_mem_init(struct pci_epc *epc, 246 struct pci_epc_mem_window *window, 247 unsigned int num_windows); 248 void pci_epc_mem_exit(struct pci_epc *epc); 249 void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, 250 phys_addr_t *phys_addr, size_t size); 251 void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, 252 void __iomem *virt_addr, size_t size); 253 #endif /* __LINUX_PCI_EPC_H */ 254