1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /** 3 * PCI Endpoint *Controller* (EPC) header file 4 * 5 * Copyright (C) 2017 Texas Instruments 6 * Author: Kishon Vijay Abraham I <[email protected]> 7 */ 8 9 #ifndef __LINUX_PCI_EPC_H 10 #define __LINUX_PCI_EPC_H 11 12 #include <linux/pci-epf.h> 13 14 struct pci_epc; 15 16 enum pci_epc_interface_type { 17 UNKNOWN_INTERFACE = -1, 18 PRIMARY_INTERFACE, 19 SECONDARY_INTERFACE, 20 }; 21 22 enum pci_epc_irq_type { 23 PCI_EPC_IRQ_UNKNOWN, 24 PCI_EPC_IRQ_LEGACY, 25 PCI_EPC_IRQ_MSI, 26 PCI_EPC_IRQ_MSIX, 27 }; 28 29 static inline const char * 30 pci_epc_interface_string(enum pci_epc_interface_type type) 31 { 32 switch (type) { 33 case PRIMARY_INTERFACE: 34 return "primary"; 35 case SECONDARY_INTERFACE: 36 return "secondary"; 37 default: 38 return "UNKNOWN interface"; 39 } 40 } 41 42 /** 43 * struct pci_epc_ops - set of function pointers for performing EPC operations 44 * @write_header: ops to populate configuration space header 45 * @set_bar: ops to configure the BAR 46 * @clear_bar: ops to reset the BAR 47 * @map_addr: ops to map CPU address to PCI address 48 * @unmap_addr: ops to unmap CPU address and PCI address 49 * @set_msi: ops to set the requested number of MSI interrupts in the MSI 50 * capability register 51 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from 52 * the MSI capability register 53 * @set_msix: ops to set the requested number of MSI-X interrupts in the 54 * MSI-X capability register 55 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC 56 * from the MSI-X capability register 57 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt 58 * @map_msi_irq: ops to map physical address to MSI address and return MSI data 59 * @start: ops to start the PCI link 60 * @stop: ops to stop the PCI link 61 * @owner: the module owner containing the ops 62 */ 63 struct pci_epc_ops { 64 int (*write_header)(struct pci_epc *epc, u8 func_no, 65 struct pci_epf_header *hdr); 66 int (*set_bar)(struct pci_epc *epc, u8 func_no, 67 struct pci_epf_bar *epf_bar); 68 void (*clear_bar)(struct pci_epc *epc, u8 func_no, 69 struct pci_epf_bar *epf_bar); 70 int (*map_addr)(struct pci_epc *epc, u8 func_no, 71 phys_addr_t addr, u64 pci_addr, size_t size); 72 void (*unmap_addr)(struct pci_epc *epc, u8 func_no, 73 phys_addr_t addr); 74 int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts); 75 int (*get_msi)(struct pci_epc *epc, u8 func_no); 76 int (*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts, 77 enum pci_barno, u32 offset); 78 int (*get_msix)(struct pci_epc *epc, u8 func_no); 79 int (*raise_irq)(struct pci_epc *epc, u8 func_no, 80 enum pci_epc_irq_type type, u16 interrupt_num); 81 int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, 82 phys_addr_t phys_addr, u8 interrupt_num, 83 u32 entry_size, u32 *msi_data, 84 u32 *msi_addr_offset); 85 int (*start)(struct pci_epc *epc); 86 void (*stop)(struct pci_epc *epc); 87 const struct pci_epc_features* (*get_features)(struct pci_epc *epc, 88 u8 func_no); 89 struct module *owner; 90 }; 91 92 /** 93 * struct pci_epc_mem_window - address window of the endpoint controller 94 * @phys_base: physical base address of the PCI address window 95 * @size: the size of the PCI address window 96 * @page_size: size of each page 97 */ 98 struct pci_epc_mem_window { 99 phys_addr_t phys_base; 100 size_t size; 101 size_t page_size; 102 }; 103 104 /** 105 * struct pci_epc_mem - address space of the endpoint controller 106 * @window: address window of the endpoint controller 107 * @bitmap: bitmap to manage the PCI address space 108 * @pages: number of bits representing the address region 109 * @lock: mutex to protect bitmap 110 */ 111 struct pci_epc_mem { 112 struct pci_epc_mem_window window; 113 unsigned long *bitmap; 114 int pages; 115 /* mutex to protect against concurrent access for memory allocation*/ 116 struct mutex lock; 117 }; 118 119 /** 120 * struct pci_epc - represents the PCI EPC device 121 * @dev: PCI EPC device 122 * @pci_epf: list of endpoint functions present in this EPC device 123 * @ops: function pointers for performing endpoint operations 124 * @windows: array of address space of the endpoint controller 125 * @mem: first window of the endpoint controller, which corresponds to 126 * default address space of the endpoint controller supporting 127 * single window. 128 * @num_windows: number of windows supported by device 129 * @max_functions: max number of functions that can be configured in this EPC 130 * @group: configfs group representing the PCI EPC device 131 * @lock: mutex to protect pci_epc ops 132 * @function_num_map: bitmap to manage physical function number 133 * @notifier: used to notify EPF of any EPC events (like linkup) 134 */ 135 struct pci_epc { 136 struct device dev; 137 struct list_head pci_epf; 138 const struct pci_epc_ops *ops; 139 struct pci_epc_mem **windows; 140 struct pci_epc_mem *mem; 141 unsigned int num_windows; 142 u8 max_functions; 143 struct config_group *group; 144 /* mutex to protect against concurrent access of EP controller */ 145 struct mutex lock; 146 unsigned long function_num_map; 147 struct atomic_notifier_head notifier; 148 }; 149 150 /** 151 * struct pci_epc_features - features supported by a EPC device per function 152 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up 153 * @msi_capable: indicate if the endpoint function has MSI capability 154 * @msix_capable: indicate if the endpoint function has MSI-X capability 155 * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver 156 * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs 157 * @bar_fixed_size: Array specifying the size supported by each BAR 158 * @align: alignment size required for BAR buffer allocation 159 */ 160 struct pci_epc_features { 161 unsigned int linkup_notifier : 1; 162 unsigned int core_init_notifier : 1; 163 unsigned int msi_capable : 1; 164 unsigned int msix_capable : 1; 165 u8 reserved_bar; 166 u8 bar_fixed_64bit; 167 u64 bar_fixed_size[PCI_STD_NUM_BARS]; 168 size_t align; 169 }; 170 171 #define to_pci_epc(device) container_of((device), struct pci_epc, dev) 172 173 #define pci_epc_create(dev, ops) \ 174 __pci_epc_create((dev), (ops), THIS_MODULE) 175 #define devm_pci_epc_create(dev, ops) \ 176 __devm_pci_epc_create((dev), (ops), THIS_MODULE) 177 178 static inline void epc_set_drvdata(struct pci_epc *epc, void *data) 179 { 180 dev_set_drvdata(&epc->dev, data); 181 } 182 183 static inline void *epc_get_drvdata(struct pci_epc *epc) 184 { 185 return dev_get_drvdata(&epc->dev); 186 } 187 188 static inline int 189 pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb) 190 { 191 return atomic_notifier_chain_register(&epc->notifier, nb); 192 } 193 194 struct pci_epc * 195 __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, 196 struct module *owner); 197 struct pci_epc * 198 __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, 199 struct module *owner); 200 void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc); 201 void pci_epc_destroy(struct pci_epc *epc); 202 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, 203 enum pci_epc_interface_type type); 204 void pci_epc_linkup(struct pci_epc *epc); 205 void pci_epc_init_notify(struct pci_epc *epc); 206 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, 207 enum pci_epc_interface_type type); 208 int pci_epc_write_header(struct pci_epc *epc, u8 func_no, 209 struct pci_epf_header *hdr); 210 int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, 211 struct pci_epf_bar *epf_bar); 212 void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, 213 struct pci_epf_bar *epf_bar); 214 int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, 215 phys_addr_t phys_addr, 216 u64 pci_addr, size_t size); 217 void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, 218 phys_addr_t phys_addr); 219 int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts); 220 int pci_epc_get_msi(struct pci_epc *epc, u8 func_no); 221 int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts, 222 enum pci_barno, u32 offset); 223 int pci_epc_get_msix(struct pci_epc *epc, u8 func_no); 224 int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, 225 phys_addr_t phys_addr, u8 interrupt_num, 226 u32 entry_size, u32 *msi_data, u32 *msi_addr_offset); 227 int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, 228 enum pci_epc_irq_type type, u16 interrupt_num); 229 int pci_epc_start(struct pci_epc *epc); 230 void pci_epc_stop(struct pci_epc *epc); 231 const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, 232 u8 func_no); 233 enum pci_barno 234 pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); 235 enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features 236 *epc_features, enum pci_barno bar); 237 struct pci_epc *pci_epc_get(const char *epc_name); 238 void pci_epc_put(struct pci_epc *epc); 239 240 int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base, 241 size_t size, size_t page_size); 242 int pci_epc_multi_mem_init(struct pci_epc *epc, 243 struct pci_epc_mem_window *window, 244 unsigned int num_windows); 245 void pci_epc_mem_exit(struct pci_epc *epc); 246 void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, 247 phys_addr_t *phys_addr, size_t size); 248 void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, 249 void __iomem *virt_addr, size_t size); 250 #endif /* __LINUX_PCI_EPC_H */ 251